A feedback-type adjustable bias ADC preamplifier circuit

Abstract

The application discloses a feedback type adjustable bias preamplifier circuit of an ADC, which can be used together with an existing fixed gain amplifier and a sigma-delta ADC to form a digital-to-analog conversion system with super high dynamic range. Compared with a conventional fixed gain amplifier + sigma-delta ADC digital-to-analog conversion system, the application adjusts the bias of an operational amplifier input in real time, ensures that the voltage entering the ADC is always in a linear amplification region, increases the signal amplification amplitude of the ADC front stage as a whole, enables greater signal dynamic range and lower ADC word length when the same signal-to-noise ratio and resolution requirements are reached, and thus reduces the area and power consumption of the system.

Description

Technical Field

[0001] This invention belongs to the field of signal amplification technology, and particularly relates to an adjustable bias amplifier circuit based on feedback. Background Technology

[0002] Analog-to-digital conversion (ADC) is an essential component of modern sensing systems. The design of the ADC, from signal amplification to digital-to-analog converter (DAC), significantly impacts both power consumption and performance. To improve the signal-to-noise ratio (SNR) of signal acquisition, sigma-delta ADCs typically employ high oversampling rates to compress low-frequency noise in the preceding stages. Simultaneously, to reduce power consumption, sigma-delta ADCs use discrete sampling. However, existing ADCs can only sample and quantize signals within a reference voltage range; signals outside this range are clipped. In the real world, many signals have dynamic ranges several times greater than the effective range. Therefore, optimizing and designing the ADC's pre-amplification stage is crucial for effectively detecting a wide range of signals without sacrificing detail resolution. Summary of the Invention

[0003] To address the shortcomings of existing ADC preamplifier circuits with low dynamic range, this invention provides a feedback-type adjustable bias amplifier circuit.

[0004] This invention solves the aforementioned technical problems by adding a feedback-type adjustable bias amplifier circuit between the traditional fixed-gain amplifier and the ADC. In this adjustable bias amplifier circuit, a reference level is set based on the amplifier's output voltage, and the circuit detects when the output voltage exceeds the reference level. Based on the out-of-limit condition, the adjustable capacitor switch array in the amplifier circuit is adjusted, causing a shift in the amplifier's common-mode input voltage, thereby adjusting the amplifier's output to within the allowable range of the ADC's input level. The adjustable bias amplifier circuit tracks and records the output level out-of-limit conditions and sends this information to the ADC to help the ADC reconstruct the original signal.

[0005] To address the above problems, this invention provides a feedback-type adjustable bias ADC preamplifier circuit, comprising: a control module, two adjustable capacitor switch arrays, an operational amplifier module, and an amplitude detection module; The control module is used for sampling, amplification state control and bias voltage setting. It receives voltage over-limit indication signal and over-limit polarity indication signal from the amplitude detection module, generates control signal to control the voltage configuration of the adjustable capacitor switch array, and outputs voltage signal range indication to the subsequent ADC. The adjustable capacitor switch array is used to receive control signals from the control module to dynamically adjust the input voltage bias of the operational amplifier module. The operational amplifier module is used to amplify the input signal and output it to the subsequent ADC. The input signal is a voltage bias. The amplitude detection module is used to determine whether the output voltage of the operational amplifier module is within the voltage range, and outputs an over-limit indication signal and an over-limit polarity indication signal.

[0006] Optionally, the voltage range (-V) th +V th When the output voltage of the operational amplifier module is greater than +V th When the over-limit indicator signal is 1, the over-limit indicator signal is 1; when the output voltage of the operational amplifier module is less than -V th When the limit is exceeded, the polarity indication signal is 0.

[0007] Optionally, the number of adjustable capacitor switch arrays is 2, namely adjustable capacitor switch array 1 and adjustable capacitor switch array 2. The input terminals of adjustable capacitor switch array 1 and adjustable capacitor switch array 2 are respectively connected to the control module. The output terminal of adjustable capacitor switch array 1 is connected to the positive input terminal of the operational amplifier module, and the output terminal of adjustable capacitor switch array 2 is connected to the negative input terminal of the operational amplifier module.

[0008] Optionally, the control module includes a control unit and a switch selection unit; The control unit receives the voltage over-limit indication signal F_over-limit and the over-limit polarity indication signal F_polarity from the amplitude detection module. Based on the voltage over-limit indication signal F_over-limit and the over-limit polarity indication signal F_polarity, it generates a voltage signal interval number S for the ADC, the switch selection unit, and the adjustable capacitor switch array, and sends the voltage signal interval number S to the subsequent ADC for signal reconstruction. The switch selection unit selects the first S capacitors of the adjustable capacitor switch array 1 and the first S capacitors of the adjustable capacitor switch array 2 to ground Vss when holding the voltage signal interval number S sent by the control unit. If S>0, the switch selection unit selects the first S capacitors of the adjustable capacitor switch array 1 to be connected to the positive voltage Vdd and the first S capacitors of the adjustable capacitor switch array 2 to be connected to ground Vss. This changes the input bias of the operational amplifier module and makes the output voltage of the operational amplifier module return to the input voltage range of the ADC. If S<0, the first S capacitors of the adjustable capacitor switch array 1 are connected to ground Vss and the first S capacitors of the adjustable capacitor switch array 2 are connected to the positive voltage Vdd.

[0009] Optionally, the operational amplifier module includes an operational amplifier and an op-amp bridging capacitor C. f Op-amp crossover capacitor C f One end of the pin is connected to the positive input terminal of the operational amplifier, and the negative input terminal of the operational amplifier is also connected to the holding switch En2. A capacitor C is connected across the operational amplifier. f The other end is connected to sampling switch En1 and holding switch En2 respectively.

[0010] Optionally, when the control module is in sampling mode, En1 is turned on, En2 is turned off, and the signal Vi+ passes through capacitor C. in Connect to the positive input terminal of the operational amplifier; the signal Vi- passes through capacitor C. in The negative input terminal of the operational amplifier is connected; the adjustable capacitor switch arrays 1 and 2 are connected to the positive and negative input terminals of the operational amplifier through the voltage signal interval S, and the operational amplifier operates in the feedback amplification state.

[0011] Optionally, when the control module is in the hold state, En2 is turned on, En1 is turned off, the output of the operational amplifier is short-circuited with the input, and the common-mode voltage V cm Through the operational amplifier and the capacitor C f The input is fed to the positive terminal of the operational amplifier, and the operational amplifier operates in a unity feedback state.

[0012] Optionally, all modules except the control module operate in a time-division strobe state.

[0013] Compared with existing technologies, the present invention has the following advantages: 1. The adjustable bias amplifier circuit for ADC provided by this invention detects the signal amplitude in real time and adjusts the bias to ensure that the signal entering the ADC is always within the allowable voltage range. Therefore, the circuit can amplify the signal further, avoiding clipping and saturation distortion, allowing the subsequent ADC to achieve the same resolution with a shorter word length, thereby reducing the area of ​​the subsequent ADC.

[0014] 2. The adjustable bias amplifier circuit of the ADC provided by the present invention includes sampling and holding switches that alternately select the signal and hold. This method avoids the non-ideality introduced by the feedback structure, selects a reasonable sampling frequency to reduce white noise aliasing caused by sampling, and can obtain a better signal-to-noise ratio.

[0015] 3. The adjustable bias amplifier circuit of the ADC provided by this invention uses a comparator to detect the difference between the output amplitude and the amplifier output swing threshold, and uses a feedback mechanism to shift the amplifier's input voltage to the center position. By reasonably setting the voltage threshold V... th This shifts the signal that was originally in the saturation region at the output end to the linear region, avoiding gain attenuation and amplitude distortion caused by saturation amplification. Attached Figure Description

[0016] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only one embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of signal processing in a typical application scenario according to an embodiment of the present invention; Figure 2 This is a circuit diagram of the overall circuit according to an embodiment of the present invention; Figure 3 This is a circuit diagram of an adjustable capacitor switch array according to an embodiment of the present invention. Detailed Implementation

[0018] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0020] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. Where the terms "first," "second," and "third" are used for descriptive purposes and to distinguish technical features, they should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the sequential relationship of the indicated technical features.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. The embodiments of this invention will now be described according to its overall structure.

[0022] like Figure 1 As shown, the feedback-type adjustable bias amplifier circuit of this invention is positioned between the fixed-gain amplifier circuit and the ADC circuit. The feedback-type adjustable bias amplifier circuit receives the amplified signal V from the fixed-gain amplifier circuit. i1 Additional amplification is performed, and the amplified signal V is output. i2 The signal range indicator S is given to the subsequent ADC circuit, and the ADC receives V.i2 After the signal interval indicator S, the signal is sampled and recovered, and the digital signal V is output. O The fixed-gain amplifier circuit has a gain of A1, the feedback amplifier circuit has a gain of A2, and the output gain is related to the input gain as follows: V i1 = V i0 A1; V i2 = V i1 A2+S V step Where V step V is the bias adjustment step size for the feedback amplifier circuit. step =V fs / n, V fs This refers to the rail-to-rail voltage of a feedback amplifier circuit, where n represents the total voltage V. fs The adjustable quantity within the range is a power of 2.

[0023] like Figure 2 As shown, the feedback-type adjustable bias ADC preamplifier circuit provided by the present invention includes: a control module, two adjustable capacitor switch arrays, an amplitude detection module, an operational amplifier module, and peripheral circuits.

[0024] The control module includes a control unit and a switch selection unit, which mainly performs sampling, amplification state control and bias voltage setting. The control unit receives the voltage over-limit indication signal and over-limit polarity indication signal from the amplitude detection module, and generates a control signal to control the input voltage of the adjustable capacitor switch array. At the same time, it outputs a voltage signal range indication to the subsequent ADC. The control unit enables the sampling switch En1 and the hold switch En2 in a time-division manner, switching the sampling and hold states of the feedback-adjustable bias ADC preamplifier circuit. This puts the feedback-adjustable bias ADC preamplifier circuit in a discontinuous amplification state, which helps control noise and reduce power consumption.

[0025] The adjustable capacitor switch array is used to receive control signals from the control module to dynamically adjust the input voltage bias of the operational amplifier module; The operational amplifier module is used to amplify the input signal and output it to the subsequent ADC. The input signal is a voltage bias. The amplitude detection module is used to determine whether the output voltage of the operational amplifier module is within the voltage range (-V). th +V th Within the range, it outputs an over-limit indication signal and an over-limit polarity indication signal. Specifically, when the output voltage of the operational amplifier module is greater than +V... th, the out-of-range indication signal is 1; when the output voltage of the operational amplification module is less than -V th , the out-of-range polarity indication signal is 0.

[0026] As an alternative embodiment, the number of adjustable capacitor switch arrays is 2, which are respectively a first adjustable capacitor switch array and a second adjustable capacitor switch array. The input ends of the first adjustable capacitor switch array and the second adjustable capacitor switch array are respectively connected to the control module, the output end of the first adjustable capacitor switch array is connected to the non-inverting input end of the operational amplifier of the operational amplification module, and the output end of the second adjustable capacitor switch array is connected to the inverting input end of the operational amplifier of the operational amplification module. The two adjustable capacitor switch arrays are used to dynamically adjust the pre-stage bias of the amplification circuit; both the first and second adjustable capacitor switch arrays adopt n capacitors with the same capacitance connected in parallel, and each capacitor C of the first adjustable capacitor switch array a has 3 options for the input end respectively: positive voltage pole Vdd, ground Vss, common-mode voltage Vcm, and the output end is connected to the non-inverting input end of the operational amplifier of the operational amplification module; each capacitor C of the second adjustable capacitor switch array a has 3 options for the input end respectively: positive voltage V dd , ground V ss , common-mode voltage V cm , and the output end is connected to the inverting input end of the operational amplifier of the operational amplification module. The circuit diagram of the adjustable capacitor switch array is shown in Figure 3 .

[0027] As an alternative embodiment, the operational amplifier and its accessory circuit are used to amplify the signal after bias addition.

[0028] Specifically, the operational amplification module comprises an operational amplifier and an operational amplifier cross-connected capacitor C f , one end of the operational amplifier cross-connected capacitor C f is connected to the positive input end of the operational amplifier, the negative input end of the operational amplifier is further connected to a holding switch En2, and the other end of the operational amplifier cross-connected capacitor C f is respectively connected to a sampling switch En1 and the holding switch En2.

[0029] As an alternative embodiment, the amplitude detection module is used to determine whether the output voltage of the operational amplification module is within the voltage interval (-V th , +V th ), and outputs an out-of-range indication signal and an out-of-range polarity indication signal (greater than +V th is positive, less than -V th is negative); for example, greater than +V th is 1, less than -V th is 0.

[0030] As an optional embodiment, the switch selection unit selects, based on the voltage signal interval S (assuming S>0) sent by the control unit, to connect the input terminals of the first S capacitors of the adjustable capacitor switch array 1 to V when in the holding state (En2=1). dd The input terminals of the first S capacitors of the adjustable capacitor switch array 2 are connected to V. ss This is to increase the input bias of the subsequent operational amplifier and reduce the input voltage range from the operational amplifier output to the ADC; if S < 0, then the input terminals of the first S capacitors of the adjustable capacitor switch array 1 are connected to V. ss The input terminals of the first S capacitors of the adjustable capacitor switch array 2 are connected to V. dd .

[0031] As an optional embodiment, the amplitude detection module uses an amplitude detection circuit based on a preset V. th The value is compared with the output voltage V of the operational amplifier module when En1=1. i2 Compared with the preset value V th If V i2 >V th Then the voltage over-limit indicator signal F will output high, and the polarity of F will be 1; if V i2 <-V th If F exceeds the limit, the output is high, and the polarity of F = 0; if |V i2 | <V th This indicates that the output is within the threshold, and Fover = 0. Based on the Fover and Fpolarity output range indication signal S, the control circuit feedback controls the adjustable capacitor switch arrays 1 and 2, causing the output Vover to... i2 Always maintain common-mode voltage V cm Nearby. The interval indicator signal S can be continuously added to or subtracted as the signal increases or decreases to ensure coverage of the input V. i1 The dynamic range.

[0032] like Figure 3 As shown, the internal capacitors of the adjustable capacitor switch array all have a capacitance value of Ca, and their connection method is closely related to the interval indicator S. When sampling switch En1 is active, all capacitors in adjustable switch arrays 1 and 2 have their input terminals connected to the common-mode voltage and their output terminals connected to the operational amplifier input. When switch En2 is active, if the interval indicator S is positive, i.e., V... i2 >V th One end of each of the S capacitors in the adjustable capacitor switch array 1 is connected to V. dd One end is connected to the positive input terminal of the operational amplifier; one end of each of the S capacitors in the adjustable capacitor switch array 2 is connected to V. ss One end is connected to the negative input terminal of the operational amplifier. The remaining capacitors in the switch array are all connected to V at one end. cm One end is connected to the input terminal of the operational amplifier. If S is negative, that is, V i2 <-V thIn the case of adjustable capacitor switch array 1, one end of each of the S capacitors is connected to Vss, and the other end is connected to the positive input terminal of the operational amplifier; in the case of adjustable capacitor switch array 2, one end of each of the S capacitors is connected to Vdd, and the other end is connected to the negative input terminal of the operational amplifier. The connections of the remaining capacitors remain unchanged.

[0033] Based on the law of charge conservation, the output and input have the following relationship during sampling (En=1): By connecting capacitor C in An external parallel adjustable capacitor switch array, with S Ca capacitors, can bring... The voltage deviation, thus at the previous sampling time V i2 (t-1) exceeds V th When, change the output voltage V at the next moment. i2 (t)= V i2 (t-1)-SV step This brings the signal back to near the common-mode voltage. The ADC combines the sampled output with the amplitude overshoot signal S from the preceding stage to reconstruct the input in the digital back-end, thus recovering the original output signal. This method allows the subsequent ADC to still provide good linearity even after the effective output swing significantly exceeds the reference voltage, ensuring that distortion caused by large input interference does not degrade the overall signal-to-noise ratio.

[0034] like Figure 2 As shown, the control module controls two adjustable capacitor switch arrays and a sample-and-hold switch. The sampling switch En1 and the holding switch En2 open in a time-sharing manner, controlling the sampling and amplification of the control circuit. When En1 is open, the amplitude detection circuit samples the signal, and a feedback capacitor C is connected to both ends of the operational amplifier. f The magnification is C. in / C f At this time, the input signal V i1+ V i1- Connected to capacitor C in Above, via C in Connected to the op-amp input; all capacitors at the inputs of adjustable capacitor switch arrays 1 and 2 are configured identically, with one end connected to V. cm The other end is connected to the op-amp input. After sampling, it enters hold mode, where En1 is off (En1=0) and En2 is on (En2=1). In hold mode, the operational amplifier is configured as a unity feedback amplifier. Capacitor C in The input terminal is connected to the common-mode input V. cm The output is connected to the input of the operational amplifier. The adjustable capacitor switch array, according to the signal interval indication S, makes the first S capacitors... a The capacitor input terminal is connected to V. dd / V ss The other end is connected to the input of the operational amplifier, and the remaining capacitor connections remain unchanged.

[0035] As an optional embodiment, with C in =5pF, C f Taking a 300fF op-amp as an example, this amplifier circuit can achieve an amplification of approximately 16 times. By setting the adjustable capacitor switch n=16, the adjustable capacitor switch can achieve ±16V... step The voltage range. V step = By adding the aforementioned feedback amplifier circuit, the subsequent ADC can absorb ±16V beyond 2Vth. step That is, 32 V step It can handle dynamic voltage changes within a certain range while maintaining the original signal-to-noise ratio and resolution.

[0036] Assuming the input signal has a minimum resolution of 4µV, a maximum signal amplitude of ±12mV, a reference voltage of 1.2V, and a fluctuation range of -1.2V to 1.2V, then the maximum value of the fixed gain amplification factor A1 is 100V / V. If only analog-to-digital conversion of the signal is required, then the system's requirement for the subsequent ADC is a word length... After adding the aforementioned feedback-type low-power high-gain circuit, the additional amplification A2 = 8 times, resulting in an overall amplification factor of 800V / V. i1 The input range is ±9.6V, set V th =0.6V, V step =0.5625V, then each adjustable capacitor switch array requires n=16 capacitor switches. At this time, the system's requirements for the subsequent ADC are reduced to 1 / 16 of the original signal length. The width of the subsequent ADC can be reduced by 4 bits.

[0037] The above description only discloses specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or modifications that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An ADC preamplifier circuit based on feedback-type adjustable bias, characterized in that, include: The system includes a control module, two adjustable capacitor switch arrays, an operational amplifier module, and an amplitude detection module. The control module is used for sampling, amplification state control and bias voltage setting. It receives voltage over-limit indication signal and over-limit polarity indication signal from the amplitude detection module, generates control signal to control the voltage configuration of the adjustable capacitor switch array, and outputs voltage signal range indication to the subsequent ADC. The adjustable capacitor switch array is used to receive control signals from the control module to dynamically adjust the input voltage bias of the operational amplifier module. The operational amplifier module is used to amplify the input signal and output it to the subsequent ADC. The input signal includes signal Vi+, signal Vi- and voltage bias. The amplitude detection module is used to determine whether the output voltage of the operational amplifier module is within the voltage range, and outputs an over-limit indication signal and an over-limit polarity indication signal. The number of adjustable capacitor switch arrays is 2, namely adjustable capacitor switch array 1 and adjustable capacitor switch array 2. The input terminals of adjustable capacitor switch array 1 and adjustable capacitor switch array 2 are respectively connected to the control module. The output terminal of adjustable capacitor switch array 1 is connected to the positive input terminal of the operational amplifier module, and the output terminal of adjustable capacitor switch array 2 is connected to the negative input terminal of the operational amplifier module. The control module includes a control unit and a switch selection unit; The control unit receives the voltage over-limit indication signal F_over-limit and the over-limit polarity indication signal F_polarity from the amplitude detection module. Based on the voltage over-limit indication signal F_over-limit and the over-limit polarity indication signal F_polarity, it generates a voltage signal interval number S for the ADC, the switch selection unit, and the adjustable capacitor switch array, and sends the voltage signal interval number S to the subsequent ADC for signal reconstruction. The switch selection unit selects the first S capacitors of the adjustable capacitor switch array 1 and the first S capacitors of the adjustable capacitor switch array 2 to ground Vss when holding the voltage signal interval number S sent by the control unit. If S>0, the switch selection unit selects the first S capacitors of the adjustable capacitor switch array 1 to be connected to the positive voltage Vdd and the first S capacitors of the adjustable capacitor switch array 2 to be connected to ground Vss. This changes the input bias of the operational amplifier module and makes the output voltage of the operational amplifier module return to the input voltage range of the ADC. If S<0, the first S capacitors of the adjustable capacitor switch array 1 are connected to ground Vss and the first S capacitors of the adjustable capacitor switch array 2 are connected to the positive voltage Vdd.

2. The feedback-type adjustable bias ADC preamplifier circuit according to claim 1, characterized in that, The voltage range (-V) th +V th When the output voltage of the operational amplifier module is greater than +V th When the over-limit indicator signal is 1, the over-limit indicator signal is 1; when the output voltage of the operational amplifier module is less than -V th When the limit is exceeded, the polarity indication signal is 0.

3. The feedback-type adjustable bias ADC preamplifier circuit according to claim 1, characterized in that, It also includes a sampling switch En1 and a hold switch En2. The sampling switch En1 and the hold switch En2 are electrically connected to the switch selection unit and the operational amplifier module, respectively. The control unit enables the sampling switch En1 and the hold switch En2 in a time-division manner to switch the sampling and hold states of the ADC preamplifier circuit, so that the ADC preamplifier circuit is in a discrete amplification state.

4. The feedback-type adjustable bias ADC preamplifier circuit according to claim 3, characterized in that, Both the adjustable capacitor switch arrays 1 and 2 are formed by connecting n capacitors with the same capacitance in parallel, and each capacitor C in the adjustable capacitor switch array 1 a has three options for the input terminal, which are respectively: positive voltage terminal Vdd, ground Vss, common-mode voltage Vcm, and all output terminals are connected to the non-inverting input terminal of the operational amplifier in the operational amplification module; each capacitor C in the adjustable capacitor switch array 2 a has three options for the input terminal, which are respectively: positive voltage V dd , ground V ss , common-mode voltage V cm , and all output terminals are connected to the inverting input terminal of the operational amplifier in the operational amplification module.

5. The feedback-type adjustable bias ADC preamplifier circuit according to claim 4, characterized in that: The operational amplifier module includes an operational amplifier and an operational amplifier bridging capacitor C. f Op-amp crossover capacitor C f One end of the pin is connected to the positive input terminal of the operational amplifier, and the negative input terminal of the operational amplifier is also connected to the holding switch En2. A capacitor C is connected across the operational amplifier. f The other end is connected to sampling switch En1 and holding switch En2 respectively.

6. The feedback-type adjustable bias ADC preamplifier circuit according to claim 5, characterized in that: When the control module is in sampling mode, En1 is on, En2 is off, and the signal Vi+ passes through capacitor C. in Connect to the positive input terminal of the operational amplifier; the signal Vi- passes through capacitor C. in The negative input terminal of the operational amplifier is connected; the adjustable capacitor switch arrays 1 and 2 are connected to the positive and negative input terminals of the operational amplifier through the voltage signal interval S, and the operational amplifier operates in the feedback amplification state.

7. The feedback-type adjustable bias ADC preamplifier circuit according to claim 5, characterized in that: When the control module is in hold state, En2 is on, En1 is off, the output and input of the operational amplifier are shorted, and the common-mode voltage V... cm Through the operational amplifier and the capacitor C f The input is fed to the positive terminal of the operational amplifier, and the operational amplifier operates in a unity feedback state.

8. The ADC preamplifier circuit according to claim 1, characterized in that: All modules except the control module operate in a time-division strobe state.

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