Mother substrate of array substrate and preparation method thereof, and preparation method of display panel

Abstract

The application provides a mother substrate of an array substrate and a preparation method of a display panel. The mother substrate of the array substrate comprises a substrate, a first metal layer, a first insulating layer and a second metal layer; the first metal layer is arranged on the substrate and comprises a connecting portion; the first insulating layer is located on a side of the first metal layer away from the substrate; the second metal layer is arranged on a side of the first insulating layer away from the substrate and comprises a second static electricity lead-out wire; the second static electricity lead-out wire has a first anti-interference notch; and the portions of the second static electricity lead-out wire located on both sides of the first anti-interference notch are electrically connected through the connecting portion. The mother substrate of the array substrate can avoid the pollution of the machine by the debris generated after the static electricity metal ring is scratched by the machine in the preparation process.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a motherboard for an array substrate and a method for preparing the same, as well as a method for preparing a display panel. Background Technology

[0002] Currently, organic light-emitting diodes (OLEDs) have received widespread attention and application due to their advantages such as high contrast, thinness, wide viewing angle, fast response speed, applicability to flexible panels, wide operating temperature range, and relatively simple structure and manufacturing process.

[0003] In the manufacturing process of OLED display panels, a metal layer is typically placed around the edge of the substrate to prevent damage from static electricity generated during the process. However, during panel manufacturing, interference from equipment can easily scratch the electrostatic protection metal layer, resulting in debris from the scratched metal layer contaminating the equipment. Summary of the Invention

[0004] The array substrate motherboard and its preparation method provided in this application, as well as the display panel preparation method, aim to solve the problem of residue contamination of the equipment after the equipment scratches the electrostatic protective metal layer during the existing display panel preparation process.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a mother plate for an array substrate; the mother plate for the array substrate includes:

[0006] Substrate;

[0007] A first metal layer is disposed on the substrate; the first metal layer includes a connecting portion;

[0008] A first insulating layer is located on the side of the first metal layer away from the substrate;

[0009] A second metal layer, located on the side of the first insulating layer away from the substrate, includes a second electrostatic lead; the second electrostatic lead has a first anti-interference notch;

[0010] The portion of the second electrostatic lead located on both sides of the first anti-interference gap is electrically connected through the connecting part.

[0011] The second electrostatic lead-out wire has two ends on both sides of the first anti-interference gap, and the two ends are electrically connected through the connecting part.

[0012] The first metal layer further includes a first electrostatic lead, which includes the connecting portion.

[0013] Preferably, the first electrostatic lead further includes an extension that is independent of the connecting portion; or, the first electrostatic lead includes an extension that includes the connecting portion.

[0014] The first electrostatic lead has a grounding end; and the second electrostatic lead is a non-closed loop with the first anti-interference notch.

[0015] Both the extension and the second electrostatic lead extend along the edge of the substrate.

[0016] The array substrate motherboard further includes a second insulating layer and a third metal layer; the third metal layer is disposed on the side of the second metal layer away from the first metal layer through the second insulating layer; the third metal layer includes a third electrostatic lead; the third electrostatic lead has a second anti-interference notch, the second anti-interference notch is located in the interference region; wherein the portion of the third electrostatic lead located on both sides of the second anti-interference notch is electrically connected through the first electrostatic lead.

[0017] To address the aforementioned technical problems, the second technical solution provided in this application is: a method for manufacturing a display panel, the method comprising:

[0018] A motherboard for an array substrate is provided; the motherboard for the array substrate is the motherboard for the array substrate involved in the above technical solution;

[0019] A light-emitting layer and an encapsulation layer are sequentially deposited on the motherboard of the array substrate to obtain the motherboard of the display panel;

[0020] Cut the motherboard of the display panel.

[0021] To address the aforementioned technical problems, the third technical solution provided in this application is: a method for preparing a mother plate of an array substrate, comprising:

[0022] A first metal layer is disposed on the substrate; the first metal layer includes a connecting portion;

[0023] A first insulating layer is disposed on the side of the first metal layer away from the substrate;

[0024] A second metal layer is disposed on the side of the first insulating layer away from the substrate; the second metal layer includes a second electrostatic lead; wherein the second electrostatic lead has a first anti-interference notch;

[0025] The portions of the second electrostatic lead located on both sides of the first anti-interference gap are electrically connected through the connecting part.

[0026] The step of forming a second metal layer on the side of the first insulating layer away from the substrate includes:

[0027] Patterning the second metal layer to form the second electrostatic lead; and removing the portion of the second electrostatic lead located in the interference region to form the first anti-interference gap; or

[0028] The patterned second metal layer is used to directly form the second electrostatic lead with the first anti-interference notch.

[0029] The step of forming a first metal layer on the substrate includes:

[0030] The first metal layer is patterned to form a first electrostatic lead, the first electrostatic lead including the connecting portion;

[0031] The step of electrically connecting the portions of the second electrostatic lead located on both sides of the first anti-interference notch via the first electrostatic lead further includes:

[0032] The two ends of the second electrostatic lead located on both sides of the first anti-interference notch are connected to the connection part through through holes.

[0033] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a motherboard for an array substrate and its fabrication method, as well as a method for fabricating a display panel. The motherboard of this array substrate includes a first metal layer comprising a first electrostatic lead-out line and a second metal layer comprising a second electrostatic lead-out line. This allows static electricity generated during the fabrication process of the display panel to be released and neutralized through the first and second electrostatic lead-out lines, achieving electrostatic protection for the display panel and preventing damage from static electricity generated during fabrication. Simultaneously, due to machine interference, the motherboard has an interference region. The second electrostatic lead-out line located in the interference region has a first anti-interference gap. By electrically connecting the portions of the second electrostatic lead-out line located on both sides of the first anti-interference gap through the first electrostatic lead-out line, the second electrostatic lead-out line can form a complete electrostatic discharge path through the electrical connection of the first electrostatic lead-out line. This not only achieves good electrostatic protection but also, the first anti-interference gap formed in the region where the second electrostatic lead-out line is located allows the second electrostatic lead-out line to effectively avoid the interference region and be unaffected by machine interference. This prevents residue from contaminating the machine after the second electrostatic lead-out line is scratched in the interference region due to machine interference. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0035] Figure 1 This is a top view of the motherboard of the array substrate provided in the first embodiment of this application;

[0036] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure along the CC direction;

[0037] Figure 3 This is a cross-sectional view of the mother plate of the array substrate provided in the second embodiment of this application;

[0038] Figure 4 This is a partial structural schematic diagram of the motherboard of the array substrate provided in the third embodiment of this company;

[0039] Figure 5 This is a cross-sectional view of the mother plate of the array substrate provided in the fourth embodiment of this application;

[0040] Figure 6 This is a cross-sectional view of the mother plate of the array substrate provided in the fifth embodiment of this application;

[0041] Figure 7 This is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of this application;

[0042] Figure 8 This is a flowchart illustrating step S1 provided in one embodiment of this application;

[0043] Figure 9 This is a flowchart illustrating step S1 provided in another embodiment of this application. Detailed Implementation

[0044] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0045] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0047] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0048] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] Please see Figure 1 and Figure 2 , Figure 1 This is a top view of the motherboard of the array substrate provided in the first embodiment of this application. Figure 2 yes Figure 1 A schematic cross-sectional view along the CC direction is provided. In this embodiment, a mother plate 1 for an array substrate is provided. After a light-emitting layer and an encapsulation layer are formed on the mother plate 1 of the array substrate, a mother plate for a display panel is obtained. Multiple display panels can be obtained by cutting the mother plate for the display panel. In this application, the display panel is an OLED display panel. The mother plate 1 of the array substrate includes a substrate 10, a first metal layer 20, a first insulating layer 30, and a second metal layer 40.

[0050] The substrate 10 is used to support and protect the circuit structure of the array substrate. The substrate 10 can be plate-shaped, and its shape and size can be set according to actual production needs; for example, the size, shape, and material of the substrate 10 of the driving substrate can be set according to factors such as the display area size and shape of the display panel. The substrate 10 can be a flexible substrate or a rigid substrate. Specifically, the substrate 10 can be an insulating material, such as glass, resin, or organic polymer materials; the substrate 10 can also be a metal material, on which an insulating layer is also required to avoid short circuits and other problems with other metal layers in the driving substrate.

[0051] The first metal layer 20 is disposed on the substrate 10. The first metal layer 20 includes a first electrostatic lead 21, which is used for electrostatic protection or electrostatic discharge during the fabrication of the display panel. For example, the first electrostatic lead 21 has a grounding terminal. In this embodiment, the first electrostatic lead 21 extends along the edge of the substrate 10. It should be noted that the extension of the first electrostatic lead 21 along the edge of the substrate 10 means that the overall extension trend of the first electrostatic lead 21 is along the edge of the substrate 10, rather than strictly making the first electrostatic lead 21 parallel to the edge of the substrate 10. During the manufacturing process, alignment marks or other structures or devices need to be set on the edge of the motherboard 1. Therefore, the first electrostatic lead 21 has multiple bends to avoid these alignment marks, but the overall outline still extends along the edge of the substrate 10.

[0052] The first insulating layer 30 is disposed on the side of the first metal layer 20 away from the substrate 10 to insulate the first metal layer 20, thereby preventing short circuits between the conductive structures of the first metal layer 20 and / or between the first metal layer 20 and adjacent conductive structure layers.

[0053] The second metal layer 40 is disposed on the side of the first insulating layer 30 away from the substrate 10, and the second metal layer 40 includes a second electrostatic lead 41. ， The second electrostatic lead 41 extends along the edge of the substrate 10. Similarly, "extending along the edge of the substrate 10" means that the overall extension trend of the second electrostatic lead 41 is along the edge of the substrate 10, rather than strictly making the second electrostatic lead 41 parallel to the edge of the substrate 10. During the manufacturing process, alignment marks or other structures or devices need to be set on the edge of the motherboard 1. Therefore, the second electrostatic lead 41 has multiple bends or protrusions to avoid these alignment marks, but its overall outline still extends along the edge of the substrate 10. Specifically, the second electrostatic lead 41 is a non-closed ring extending along the edge of the substrate 10 with a first anti-interference notch 417.

[0054] Specifically, during the manufacturing process of the display panel, interference from the equipment can scratch the electrostatic leads. Therefore, the motherboard 1 has an area where the electrostatic leads are scratched due to equipment interference, and this area is defined as the interference area 50. It is understandable that during the manufacturing process of the display panel, interference from the equipment can scratch the second electrostatic leads 41 in some areas. This can easily lead to some of the second electrostatic leads 41 located in the interference area being scratched, resulting in debris from the scratched second electrostatic leads 41 contaminating the equipment.

[0055] In this embodiment, the second electrostatic lead 41 having a first anti-interference gap 417 means that the second electrostatic lead 41 is disconnected in the interference region 50 to form the first anti-interference gap 417, thereby allowing the second electrostatic lead 41 to avoid the interference region 50. This effectively prevents the second electrostatic lead 41 from being scratched by the machine tool and avoids the residue generated after the second electrostatic lead 41 is scratched from contaminating the machine tool. It can be understood that as long as a portion of the second electrostatic lead 41 within the interference region 50 is removed, the residue generated after scratching can be reduced. Preferably, the second electrostatic lead 41 does not extend into the interference region 50, or there are no second electrostatic leads 41 in the interference region 50, that is, the portion of the second electrostatic lead 41 overlapping with the interference region 50 is completely removed to form the first anti-interference gap 417.

[0056] Furthermore, the portions of the second electrostatic lead 41 located on both sides of the first anti-interference gap 417 are electrically connected through the first electrostatic lead 21, so that the second electrostatic lead 41 forms a complete closed loop at the break point through the first electrostatic lead 21 located in the lower layer. This not only avoids the interference region 50, but also can be used for electrostatic protection in the fabrication of other structures in this layer and in subsequent processes, preventing electrostatic discharge generated during the process from damaging the display panel.

[0057] Specifically, the second electrostatic lead 41 forms two ends on both sides of the first anti-interference gap 417, namely the first end 411 and the second end 412. That is, the part of the second electrostatic lead 41 located on both sides of the first anti-interference gap 417 has the first end 411 and the second end 412 respectively, and the first end 411 and the second end 412 are electrically connected through the first electrostatic lead 21.

[0058] Specifically, such as Figure 2As shown, the first electrostatic lead 21 also includes a connecting portion 212, which is independent of the extension portion 211. The second electrostatic lead 41 is electrically connected to one end of the connecting portion 212 at its first end 411 through a first conductive hole 31, and the second electrostatic lead 41 is electrically connected to the other end of the connecting portion 212 at its second end 412 through a second conductive hole 32. This can be understood as follows: on opposite sides of the interference region 50, the second electrostatic lead 41 passes through the first conductive hole 31 at the first end 411 to the connecting part 212 below the first insulating layer 30, then crosses under the interference region 50 through the connecting part 212, and then passes through the second conductive hole 32 to the second end 412. This allows the second electrostatic lead 41 to completely avoid the interference region 50 and be unaffected by machine interference, effectively preventing the machine from being contaminated by debris generated after the second electrostatic lead 41 is scratched in the interference region 50 due to machine interference. At the same time, the first end 411 is electrically connected to the second end 412 through the connecting part 212, which can achieve a good electrostatic protection effect.

[0059] In this embodiment, the connecting portion 212 and the extension portion 211 are independent of each other; that is, the connecting portion 212 and the extension portion 211 are not connected and are two separate parts. The second electrostatic lead 41 and the extension portion 211 are not electrically connected and are independent of each other. In other embodiments, the connecting portion 212 may also be electrically connected to the extension portion 211, so that the second electrostatic lead 41 and the extension portion 211 form two three-dimensional electrostatic rings, increasing the electrostatic discharge path, thereby improving the electrostatic discharge rate and enhancing the electrostatic protection effect.

[0060] Please see Figure 3 , Figure 3 This is a cross-sectional view of the mother plate 1 of the array substrate provided in the second embodiment of this application. Unlike the first embodiment, in this embodiment, the first electrostatic lead 21 includes an extension 211, and the extension 211 includes a connecting portion 212, meaning the connecting portion 212 is a part of the extension 211. It can be understood that on opposite sides of the interference region 50, the second electrostatic lead 41, at its first end 411, passes through the first conductive hole 31 to the extension 211 below the first insulating layer 30, then crosses under the interference region 50 through the extension 211, and then passes through the second conductive hole 32 to the second end 412. This allows the second electrostatic lead 41 to completely avoid the interference region 50 and be unaffected by machine interference, thus achieving a good electrostatic protection effect. Simultaneously, by making the connecting portion 212 a part of the extension 211, the extension 211 and the second electrostatic lead 41 are connected, forming a three-dimensional electrostatic metal ring, increasing the path for electrostatic discharge and thus improving the electrostatic protection effect. Furthermore, by directly bridging the first end 411 and the second end 412 of the second electrostatic lead 41 through the existing extension 211, the step of setting the connecting part 212 can be eliminated, simplifying the process.

[0061] Please see Figure 4 , Figure 4 This is a partial structural schematic diagram of the mother plate of the array substrate provided in the third embodiment of this application. The structure of the mother plate of the array substrate provided in the third embodiment of this application is basically the same as that of the mother plate of the array substrate provided in the second embodiment of this application. The difference is that in the second embodiment, the second electrostatic lead 41 crosses the interference region 50 and breaks in the interference region 50 to form a first anti-interference gap 417; while in this embodiment, the second electrostatic lead 41 does not cross the interference region 50. That is, the portion of the second electrostatic lead 41 located on the side of the interference region 50 near the center of the mother plate 1 and the portion located in the interference region 50 are completely removed to form a third anti-interference gap 418. The second electrostatic lead 41 forms two ends on both sides of the third anti-interference gap 418, namely the third end 413 and the fourth end. 414; Similarly, the third end 413 and the fourth end 414 are bridged by the first electrostatic lead 21, specifically by the connecting part 212. The third end 413 and the fourth end 414 are electrically connected to the connecting part 212 through the third conductive hole 33 and the fourth conductive hole 34 located on the first insulating layer 30, respectively. This allows the second electrostatic lead 41 to not only avoid the positioning marks or other structures and devices at the edge of the motherboard 1 and achieve effective electrostatic protection, but also avoid the machine interference zone 50. This effectively prevents the machine from being contaminated by debris generated after the second electrostatic lead 41 is scratched in the interference zone 50 due to machine interference. It also reduces the routing length of the second electrostatic lead 41 and saves materials.

[0062] Please see Figure 5 , Figure 5 This is a cross-sectional view of the mother plate of the array substrate provided in the fourth embodiment of this application. In this embodiment, the mother plate 1 of the array substrate further includes a second insulating layer 60 and a third metal layer 70. The third metal layer 70 is disposed at intervals between the second insulating layer 60 and the side of the second metal layer 40 away from the first metal layer 20. The third metal layer 70 includes a third electrostatic lead 71, which extends along the edge of the substrate 10. The third electrostatic lead 71 can be electrically connected to the first electrostatic lead 21, thereby connecting the first electrostatic lead 21, the second electrostatic lead 41, and the third electrostatic lead 71 to form a multi-layered, three-dimensional electrostatic lead, increasing the path for electrostatic discharge, enabling better and faster dispersion of electrostatic charge, and further improving the effect of electrostatic protection.

[0063] Specifically, in this embodiment, similar to the second metal layer 40, the third electrostatic lead 71 is also disconnected at the interference region 50 to form a second anti-interference gap 713. The third electrostatic lead 71 has a fifth end 711 and a sixth end 712 on opposite sides of the second anti-interference gap 713. The fifth end 711 and the sixth end 712 can also be electrically connected by bridging the fifth conductive hole 61, the sixth conductive hole 62 and the second electrostatic lead 41, so that the third electrostatic lead 71 avoids the interference region 50, thereby avoiding machine interference that causes the third electrostatic lead 71 to be scratched and the resulting debris to contaminate the machine.

[0064] Please see Figure 6 , Figure 6 This is a cross-sectional view of the motherboard of the array substrate provided in the fifth embodiment of this application. In this embodiment, the third electrostatic lead 71 is electrically connected to the second electrostatic lead 41, thereby connecting the first electrostatic lead 21, the second electrostatic lead 41, and the third electrostatic lead 71 to form a multi-layered, three-dimensional electrostatic lead, which increases the path for electrostatic discharge, can better and faster disperse electrostatic charge, and further improve the effect of electrostatic protection.

[0065] Specifically, in this embodiment, the third electrostatic lead 71 has a fifth end 711 and a sixth end 712 on opposite sides of the second anti-interference notch 713. The fifth end 711 and the sixth end 712 can be electrically connected by bridging the seventh conductive hole 63, the eighth conductive hole 64 and the second electrostatic lead 41, so that the third electrostatic lead 71 avoids the interference region 50, thereby avoiding machine interference that causes the third electrostatic lead 71 to be scratched and the resulting debris to contaminate the machine.

[0066] In another embodiment (not shown), the third electrostatic lead 71 has multiple second anti-interference gaps 713 at the interference region 50. Each second anti-interference gap 713 has a fifth end 711 and a sixth end 712 on opposite sides. At least one second anti-interference gap 713 has its fifth end 711 and sixth end 712 on opposite sides electrically connected through a first electrostatic lead 21, and at least one second anti-interference gap 713 at different locations has its fifth end 711 and sixth end 712 on opposite sides electrically connected through a second electrostatic lead 41. That is, in this embodiment, the third electrostatic lead 71 is electrically connected to both the first electrostatic lead 21 and the second electrostatic lead 41. This allows for the formation of a multi-layered three-dimensional electrostatic metal ring, increasing the path for electrostatic discharge and enabling better and faster dispersion of electrostatic charges, further improving the electrostatic protection effect. At the same time, it avoids the interference region 50 and increases the design flexibility of the electrostatic lead.

[0067] In another embodiment (not shown), the second electrostatic lead 41 includes a non-closed loop and a second connecting portion. The fifth end 711 and the sixth end 712 of the third electrostatic lead 71 are electrically connected to the second connecting portion through through holes in the second insulating layer 60. This allows the third lead 71 to form a closed loop for electrostatic protection while avoiding the interference zone 50, preventing machine interference and scratches that could lead to debris contamination of the machine. Similar to the first electrostatic lead 21, the second connecting portion can be independent of or electrically connected to the non-closed loop, or it can be part of the non-closed loop, thus increasing the design flexibility of the electrostatic lead.

[0068] Furthermore, in the above embodiments, the widths of the first anti-interference notch 417, the second anti-interference notch 713, and the third anti-interference notch 418 are all greater than the width of the interference region 50. That is, the first end 411 and the second end 412, the third end 413 and the fourth end 414, and the fifth end 711 and the sixth end 712 are all spaced apart from the interference region 50, thereby enabling the second electrostatic lead 41 and the third electrostatic lead 71 to completely avoid interference from the machine tool, and ensuring the effectiveness of the bridging of the second electrostatic lead 41 and the third electrostatic lead 71 at the interference region 50.

[0069] In specific embodiments of this application, the first metal layer 20, the second metal layer 40, and the third metal layer 70 can be any metal layer in the display panel manufacturing process, especially in the driving circuit layer process of the motherboard 1 of the array substrate, and the number of metal layers is not limited to three, and may also include other metal layers. In one embodiment, the first metal layer 20 can be a gate metal layer, the second metal layer 40 can be a capacitor plate layer, the third metal layer 70 can be a source-drain metal layer, and other metal layers can be film layers containing signal lines such as power supply lines and reset signal lines.

[0070] In the above embodiments, the first electrostatic lead 21, the second electrostatic lead 41, and the third electrostatic lead 71 can be formed by metal layer patterning or mask deposition. In some embodiments, depending on actual production needs, the mother plate 1 of the array substrate may also include a fourth metal layer, a fifth metal layer, and other metal layers. An insulating layer is provided between adjacent metal layers. Each metal layer includes an electrostatic lead. Each electrostatic lead can avoid the interference region 50 by the sunken bridging method in the above embodiments, thereby avoiding the problem of machine interference causing the electrostatic lead to be scratched and the resulting debris to contaminate the machine.

[0071] Please see Figure 7 , Figure 7 This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application. In this embodiment, a method for manufacturing a display panel is provided, which includes the following steps:

[0072] S1: Motherboard 1 providing the array substrate.

[0073] S2: A light-emitting layer and an encapsulation layer are sequentially deposited on the motherboard 1 of the array substrate to obtain the motherboard of the display panel.

[0074] S3: Cut the motherboard for the display panel.

[0075] In step S1, the structure and function of the mother plate 1 of the array substrate are the same as or similar to the structure and function of the mother plate 1 of the array substrate involved in the above embodiment, and can achieve the same technical effect. For details, please refer to the above description, which will not be repeated here.

[0076] In step S2, the light-emitting layer can be an OLED light-emitting layer to fabricate an OLED display panel. An encapsulation layer is placed over the light-emitting layer to encapsulate it, preventing damage from external environmental interference and thus enabling the display function.

[0077] Please see Figure 8 , Figure 8 This is a schematic flowchart illustrating a method for fabricating the mother plate of an array substrate according to an embodiment of this application. In this embodiment, the method for fabricating the mother plate 1 of the array substrate specifically includes:

[0078] S11: Provides substrate 10.

[0079] S12: A first metal layer 20 is formed on the substrate 10; the first metal layer 20 includes a connecting portion 212.

[0080] S13: A first insulating layer 30 is disposed on the side of the first metal layer 20 away from the substrate 10.

[0081] S14: A second metal layer 40 is disposed on the side of the first insulating layer 30 away from the substrate 10; the second metal layer 40 includes a second electrostatic lead 41; wherein the second electrostatic lead 41 has a first anti-interference notch 417.

[0082] S15: The portions of the second electrostatic lead 41 located on both sides of the first anti-interference gap 417 are electrically connected via the connecting part 212.

[0083] In this embodiment, the specific structure and function of the substrate 10, the first metal layer 20, the first insulating layer 30 and the second metal layer 40 are the same as or similar to the structure and function of the substrate 10, the first metal layer 20, the first insulating layer 30 and the second metal layer 40 involved in the above embodiment, and can achieve the same technical effect. For details, please refer to the above description, which will not be repeated here.

[0084] In this embodiment, in the process of providing the motherboard 1 of the array substrate in the method for manufacturing the display panel, a connection portion 212 and a second electrostatic lead 41 are formed on the first metal layer 20 and the second metal layer 40 respectively through steps S12 and S14 to release static electricity generated during the manufacturing process and protect the array substrate from electrostatic damage. Further, through steps S12 and S15, the second electrostatic lead 41 passes under the interference region 50 via the first electrostatic lead 21 on opposite sides of the interference region 50, thereby allowing the second electrostatic lead 41 to completely avoid the interference region 50 and be unaffected by machine interference. This prevents the machine from being contaminated by debris generated after the second electrostatic lead 41 is scratched in the interference region 50 due to machine interference.

[0085] Specifically, in this embodiment, step S12 includes:

[0086] The patterned first metal layer 20 forms a first electrostatic lead 21, which includes a connecting portion 212.

[0087] In step S12, the first electrostatic lead 21 can be formed by patterning the first metal layer 20. The part of the first electrostatic lead 21 corresponding to the second electrostatic lead 41 in the interference region 50 serves as a connecting part 212. The first conductive hole 31 and the second conductive hole 32 are respectively provided on the first insulating layer 30 at the positions corresponding to the two ends of the connecting part 212. This allows the second electrostatic lead 41 to be electrically connected in the interference region 50 through the connecting part 212, so that the second electrostatic lead 41 avoids the interference region 50 and is not affected by machine interference. This avoids the machine from being contaminated by debris generated after the second electrostatic lead 41 is scratched in the interference region 50 due to machine interference.

[0088] In one embodiment, step S14 may specifically include:

[0089] S141: Patterning the second metal layer 40 forms the second electrostatic lead 41;

[0090] S142: Remove the portion of the second electrostatic lead 41 located in the interference region 50 to form the first anti-interference gap 417.

[0091] Specifically, the patterned second metal layer 40 can be patterned by photolithography to form the second electrostatic lead 41; the portion of the second electrostatic lead 41 located in the interference region 50 can be removed by laser scanning to remove the metal material of the second electrostatic lead 41 located in the interference region 50 to form the first anti-interference gap 417; by forming the second electrostatic lead 41 with the first anti-interference gap 417 in this way, the existing photomask can be used for photolithography, without the need to design and manufacture a new photomask, thereby saving production costs.

[0092] Alternatively, in another embodiment, step S14 may specifically include:

[0093] S143: The patterned second metal layer 40 directly forms a second electrostatic lead 41 with a first anti-interference notch 417.

[0094] Specifically, the pattern can be created using photolithography so that the second metal layer 40 forms a second electrostatic lead 41 with a first anti-interference gap 417 located in the interference region 50.

[0095] In this embodiment, the second electrostatic lead 41 is disconnected at the interference region 50 to form a first anti-interference notch 417. Two ends, a first end 411 and a second end 412, are formed on opposite sides of the first anti-interference notch 417. No metal layer is provided between the first end 411 and the second end 412, thereby preventing machine interference and the resulting debris from scratching the second electrostatic lead 41 in the interference region 50 and contaminating the machine. In this embodiment, a photomask matching the second electrostatic lead 41 with the first anti-interference notch 417 is used to perform photolithography on the second metal layer 40 to form the second electrostatic lead 41 with the first anti-interference notch 417. This method of forming the second electrostatic lead 41 reduces the process of removing some metal material from the second electrostatic lead 41 located in the interference region 50, shortens the preparation time, and thus improves preparation efficiency.

[0096] In this embodiment, step S15 specifically includes:

[0097] The two ends of the second electrostatic lead 41 located on both sides of the first anti-interference notch 417 are connected to the connecting part 212 through through holes.

[0098] Specifically, the first end 411 is electrically connected to the connecting part 212 through the first conductive hole 31, and the second end 412 is electrically connected to the connecting part 212 through the second conductive hole 32. The second electrostatic lead 41 passes under the interference region 50 through the connecting part 212 at the first end 411 and then wraps around to the second end 412, so that the second electrostatic lead 41 can completely avoid the interference region 50 and is not affected by machine interference. This avoids the machine from being contaminated by debris generated after the second electrostatic lead 41 is scratched in the interference region 50 due to machine interference. At the same time, the first end 411 is electrically connected to the second end 412 through the first connecting part 22, which can achieve a good electrostatic protection effect.

[0099] Specifically, the connecting portion 212 can be part of the extension portion 211. That is, the first end 411 and the second end 412 of the second electrostatic lead 41 on opposite sides of the interference region 50 can be bridged by a portion of the extension portion 211 below, thereby avoiding the interference region 50. Furthermore, by incorporating the extension portion 211 as part of the first electrostatic lead 21, the second electrostatic lead 41 and the first electrostatic lead 21 are electrically connected, forming a multi-layered three-dimensional electrostatic lead. Static electricity generated during the fabrication of the display panel can be released and neutralized through multiple paths, improving the rate of static electricity release and neutralization, avoiding static electricity accumulation, and thus enhancing the electrostatic protection effect.

[0100] Please see Figure 9 , Figure 9 This is a flowchart illustrating step S1 provided in another embodiment of this application. In one embodiment, the method for manufacturing the display panel further includes the following steps:

[0101] S16: On the side of the second metal layer 40 away from the first metal layer 20, a second insulating layer 60 and a third metal layer 70 are sequentially disposed; the third metal layer 70 includes a third electrostatic lead 71.

[0102] S17: Connect the third electrostatic lead 71 to the first electrostatic lead 21 and / or the second electrostatic lead 41.

[0103] In this embodiment, the third metal layer 70 is disposed at intervals on the side of the second metal layer 40 away from the first metal layer 20 through the second insulating layer 60. The third metal layer 70 includes a third electrostatic lead 71 extending along the edge of the substrate 10. The third electrostatic lead 71 is electrically connected to the second electrostatic lead 41 and / or the first electrostatic lead 21, thereby connecting the first electrostatic lead 21, the second electrostatic lead 41, and the third electrostatic lead 71 to form a multi-layered, three-dimensional electrostatic lead. The static electricity generated during the fabrication of the display panel can be released or neutralized through multiple paths, improving the rate of static electricity release or neutralization, avoiding static electricity accumulation, and thus improving the electrostatic protection effect.

[0104] Specifically, the structure and function of the third electrostatic lead 71 are the same as or similar to those of the third electrostatic lead 71 in the above embodiments, and can achieve the same technical effect. For details, please refer to the above description, which will not be repeated here.

[0105] In some embodiments, depending on actual production needs, the manufacturing method of the display panel may also include the fabrication of a fourth metal layer, a fifth metal layer, and other metal layers, and the setting of an insulating layer between adjacent metal layers. Each metal layer includes an electrostatic lead-out wire, and each electrostatic lead-out wire can avoid the interference region 50 through the bridging method in the above embodiments, thereby avoiding the problem of the electrostatic lead-out wire being scratched due to machine interference, and the problem of the residue generated after the scratch contaminating the machine.

[0106] It is easy to understand that, in the above embodiment, after the mother plate 1 of the array substrate is prepared, the first electrostatic lead 21, the second electrostatic lead 41, and the third electrostatic lead 71 can be cut and removed, that is, all the electrostatic leads of the mother plate 1 of the array substrate can be removed by cutting at once.

[0107] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A mother plate for an array substrate, characterized in that, include: Substrate; A first metal layer is disposed on the substrate; the first metal layer further includes a first electrostatic lead, the first electrostatic lead including a connection portion; the first electrostatic lead has a grounding terminal; A first insulating layer is located on the side of the first metal layer away from the substrate; A second metal layer, located on the side of the first insulating layer away from the substrate, includes a second electrostatic lead; the second electrostatic lead has a first anti-interference notch; The motherboard has an interference zone where the electrostatic lead wire is scratched due to machine interference; the second electrostatic lead wire is disconnected in the interference zone to form the first anti-interference gap, and the width of the first anti-interference gap is greater than the width of the interference zone; The portion of the second electrostatic lead located on both sides of the first anti-interference gap is electrically connected through the connecting part.

2. The mother plate of the array substrate according to claim 1, characterized in that, The second electrostatic lead has two ends on both sides of the first anti-interference notch, and the two ends are electrically connected through the connecting part.

3. The mother plate of the array substrate according to claim 1, characterized in that, The first electrostatic lead further includes an extension that is independent of the connecting portion; or, the first electrostatic lead includes an extension that includes the connecting portion.

4. The mother plate of the array substrate according to claim 3, characterized in that, The second electrostatic lead is a non-closed loop with the first anti-interference notch.

5. The mother plate of the array substrate according to claim 3, characterized in that, Both the extension and the second electrostatic lead extend along the edge of the substrate.

6. The mother plate of the array substrate according to claim 3, characterized in that, The motherboard of the array substrate further includes a second insulating layer and a third metal layer; the third metal layer is disposed at a distance from the first metal layer by the second insulating layer; the third metal layer includes a third electrostatic lead; the third electrostatic lead has a second anti-interference notch, the second anti-interference notch is located in the interference region; wherein, the portion of the third electrostatic lead located on both sides of the second anti-interference notch is electrically connected through the first electrostatic lead.

7. A method for manufacturing a display panel, characterized in that, include: A motherboard for an array substrate is provided; the motherboard for the array substrate is the motherboard for an array substrate as described in any one of claims 1-6; A light-emitting layer and an encapsulation layer are sequentially deposited on the motherboard of the array substrate to obtain the motherboard of the display panel; Cut the motherboard of the display panel.

8. A method for preparing a mother plate of an array substrate, characterized in that, include: Provide substrate; A first metal layer is disposed on the substrate; the first metal layer further includes a first electrostatic lead, the first electrostatic lead including a connection portion; the first electrostatic lead has a grounding terminal; A first insulating layer is disposed on the side of the first metal layer away from the substrate; A second metal layer is disposed on the side of the first insulating layer away from the substrate; the second metal layer includes a second electrostatic lead; wherein the second electrostatic lead has a first anti-interference notch; The motherboard has an interference zone where the electrostatic lead wire is scratched due to machine interference; the second electrostatic lead wire is disconnected in the interference zone to form the first anti-interference gap, and the width of the first anti-interference gap is greater than the width of the interference zone; The portions of the second electrostatic lead located on both sides of the first anti-interference gap are electrically connected through the connecting part.

9. The method for preparing the mother plate of the array substrate according to claim 8, characterized in that, The step of forming a second metal layer on the side of the first insulating layer away from the substrate includes: Patterning the second metal layer to form the second electrostatic lead; and removing the portion of the second electrostatic lead located in the interference region to form the first anti-interference gap; or The patterned second metal layer is used to directly form the second electrostatic lead with the first anti-interference notch.

10. The method for preparing the mother plate of the array substrate according to claim 8, characterized in that, The step of forming the first metal layer on the substrate includes: The first metal layer is patterned to form the first electrostatic lead-out line; The step of electrically connecting the portions of the second electrostatic lead wire located on both sides of the first anti-interference notch via the connecting part further includes: The two ends of the second electrostatic lead located on both sides of the first anti-interference notch are connected to the connection part through through holes.

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