Signed command stream and command execution

Abstract

Systems, methods, and computer-readable media for signing and executing graphics processing unit (GPU) commands are provided. In some examples, a method can include receiving, by a GPU, one or more commands, the one or more commands including one or more verification signatures generated using a processor, each of the one or more verification signatures including a first value generated based on the one or more commands; generating, by the GPU, one or more additional verification signatures associated with the one or more commands, wherein each of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determining, by the GPU, a validity of the one or more commands based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

Description

Technical Field

[0001] In summary, this disclosure relates to graphics processing systems, and more specifically, to signing and executing graphics processor command streams. Background Technology

[0002] Specialized processors, such as graphics processing units (GPUs), are increasingly used to perform specific operations in computer systems. For example, GPUs are highly efficient at manipulating computer graphics and image processing. For algorithms that process large blocks of data in parallel, the highly parallel architecture of GPUs makes them more efficient than many other processors. Therefore, GPUs are commonly used to process computer graphics and render graphical content for presentation on display devices. Furthermore, GPUs often work in conjunction with other processors, such as central processing units (CPUs), to execute computer applications more efficiently and offload certain processing tasks. In some examples, the CPU can send one or more command streams to the GPU, which can then execute them as part of a computer application performed by both the CPU and the GPU. Summary of the Invention

[0003] This document discloses systems, methods, and computer-readable media for signing and executing graphics processing unit (GPU) command streams. According to at least one example, a method for signing and executing GPU command streams is provided. An example method may include: receiving one or more commands by a graphics processing unit (GPU), said one or more commands including one or more verification signatures generated using a processor, each of said one or more verification signatures including a first value generated based on said one or more commands; generating one or more additional verification signatures associated with said one or more commands by said GPU, wherein each of said one or more additional verification signatures includes a second value generated by said GPU based on said one or more commands; and determining the validity of said one or more commands by said GPU based on a comparison of said one or more verification signatures and said one or more additional verification signatures.

[0004] According to at least some examples, an apparatus for signing and executing GPU command streams is provided. In one example, an example apparatus may include: a memory and one or more processors configured to: receive one or more commands via a graphics processing unit (GPU), the one or more commands including one or more verification signatures generated using the processor, each of the one or more verification signatures including a first value generated based on the one or more commands; generate one or more additional verification signatures associated with the one or more commands via the GPU, wherein each of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determine the validity of the one or more commands via the GPU based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

[0005] In another example, an example apparatus may include: a unit for receiving one or more commands via a graphics processing unit (GPU), the one or more commands including one or more verification signatures generated using a processor, each of the one or more verification signatures including a first value generated based on the one or more commands; a unit for generating one or more additional verification signatures associated with the one or more commands via the GPU, wherein each of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and a unit for determining the validity of the one or more commands via the GPU based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

[0006] According to at least one example, a non-transitory computer-readable medium is provided for signing and executing GPU command streams. One example non-transitory computer-readable medium may store instructions that, when executed by one or more processors, cause the one or more processors to: receive one or more commands via a graphics processing unit (GPU), the one or more commands including one or more verification signatures generated using the processor, each of the one or more verification signatures including a first value generated based on the one or more commands; generate one or more additional verification signatures associated with the one or more commands via the GPU, wherein each of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determine the validity of the one or more commands via the GPU based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

[0007] In some aspects, determining the validity of the one or more commands, as described in the methods, apparatus, and computer-readable media above, may include: determining that a first value associated with the one or more verification signatures matches a second value associated with the one or more additional verification signatures; and determining that the one or more commands are valid. In some examples, determining that the one or more commands are valid may result in (and / or include) at least one of the following: determining that the one or more commands are authorized to be executed by the GPU, determining the integrity of the one or more commands, and / or determining that the one or more commands do not contain unauthorized modifications.

[0008] In some aspects, the methods, apparatus, and computer-readable media described above may include: authorizing the execution of the one or more commands at the GPU based on the fact that the one or more commands are valid.

[0009] In some cases, determining the validity of the one or more commands may include: determining that the first value associated with the one or more verification signatures does not match a second value associated with the one or more additional verification signatures; and determining that the one or more commands are invalid. In some examples, determining that the one or more commands are invalid may result in (and / or include) at least one of the following: determining that the one or more commands are not authorized to be executed by the GPU and / or determining that the one or more commands include one or more unauthorized modifications.

[0010] In some aspects, the methods, apparatus, and computer-readable media described above may include: preventing the execution of the one or more commands at the GPU and / or the completion of the current execution of the one or more commands at the GPU based on the fact that the one or more commands are invalid.

[0011] In some examples, the one or more commands specify one or more operations to be performed by the GPU, and the validity of the one or more commands is determined during runtime execution of the one or more commands and / or the software application associated with the one or more commands.

[0012] In some cases, the first and second values ​​are generated based on one or more characteristics of the one or more commands. In some examples, the one or more characteristics may include: the number of commands, the number of commands of one or more types, the content of at least one of the one or more commands, and / or one or more indirect pointers included in the one or more commands. In some cases, the one or more indirect pointers may include one or more references to one or more additional commands.

[0013] In some aspects, the one or more verification signatures and the first value may be generated by a user-space device driver, a kernel-space driver, and / or a processor authorized to create and / or manipulate command streams. In some examples, the one or more additional verification signatures and the second value may be generated by a command processor associated with the GPU, a shader processor associated with the GPU, and / or a processor authorized to create and manipulate at least one operation of the command stream. In some cases, the validity of the one or more commands may be determined by the command processor and / or the shader processor.

[0014] In some examples, the one or more commands may include: a command stream, a shader program, a command referencing the shader program, and / or one or more pointers to one or more locations in memory associated with the one or more commands.

[0015] In some cases, the validity of the one or more commands may be determined during the runtime execution of the software application associated with the one or more commands and before the execution of the one or more commands and / or the completion of one or more operations associated with the one or more commands.

[0016] In some cases, the one or more verification signatures may include commands and / or instructions indicating that the execution of the one or more commands should be rejected when the one or more verification signatures are determined to be invalid.

[0017] In some cases, the aforementioned device may be and / or may include a mobile phone, a smart wearable device, a portable computer, a desktop computer, a server, and / or a camera system. In some cases, the aforementioned device may include an image sensor, a GPU, a central processing unit (CPU), and / or a display.

[0018] This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in isolation to define the scope of the claimed subject matter. This invention should be understood by referring to the appropriate portions of the entire specification, drawings, and claims.

[0019] The foregoing, as well as other features and embodiments, will become more apparent upon reference to the following description, claims, and drawings. Attached Figure Description

[0020] The following illustrative example of this application is described in detail with reference to the accompanying drawings:

[0021] Figure 1This is a block diagram illustrating an example image processing system according to some examples of the present disclosure;

[0022] Figure 2 This is a diagram illustrating example components of a graphics rendering system according to some examples of this disclosure;

[0023] Figure 3 This is a diagram illustrating an example system flow for implementing a signed command stream, based on some examples of this disclosure;

[0024] Figure 4A This is a diagram of an example system flow for compiling a shader program with a verified signature, based on some examples of this disclosure;

[0025] Figure 4B This is a diagram of an example system flow for verifying shader programs based on signature verification, based on some examples of this disclosure;

[0026] Figure 5 This is a flowchart illustrating an example of a method for signing and executing image processing unit commands, based on some examples of this disclosure;

[0027] Figure 6 An example computing device architecture is shown, representing some examples of what is presented in this disclosure. Detailed Implementation

[0028] Certain aspects and embodiments of this disclosure are provided below. As will be apparent to those skilled in the art, some of these aspects and embodiments can be applied independently, and some can be applied in combination. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of embodiments of this application. However, it will be apparent that various embodiments may be practiced without these specific details. The accompanying drawings and description are not intended to be limiting.

[0029] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of these exemplary embodiments will provide those skilled in the art with a feasible description for implementing the exemplary embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of this application as set forth in the appended claims.

[0030] A graphics processing unit (GPU) can execute commands generated by drivers and / or other computer components (e.g., within and / or separate from the GPU) to perform GPU operations, such as graphics rendering. In some cases, the drivers interacting with the GPU and the commands processed by the GPU may expose certain GPU information that users could exploit to tamper with GPU functionality, potentially negatively impacting the GPU's security, stability, and / or behavior. For example, if the GPU does not implement measures to protect the integrity of commands and / or information used by the GPU, users could potentially compromise GPU operations and information, implement unauthorized drivers and / or commands, tamper with GPU functionality, and / or otherwise alter GPU behavior.

[0031] In some cases, users may be able to analyze GPU data (e.g., groups, commands, operations, etc.) and reverse engineer the command stream executed by the GPU to write and implement drivers for generating commands that can be executed by the GPU. These commands can be configured to trigger GPU operations that can expose proprietary information and other information about the GPU, such as errata; modify GPU behavior; cause security and / or stability issues; and / or allow users unauthorized access to certain aspects of the GPU and / or its operations. In some examples, users may analyze GPU data (such as GPU groups) to reverse engineer the GPU command stream to generate GPU commands that manipulate the GPU to render proprietary information, expose hidden or inaccessible graphics content, and / or otherwise tamper with GPU operations. In some cases, users may be able to compromise GPU binaries (such as shader binaries) to manipulate GPU behavior.

[0032] For example, without GPU protection, a user might be able to perform runtime memory fetches to identify patterns in commands and shaders implemented by the GPU during a video game. The user could then potentially modify these patterns to control the opacity in the vertex shader. In this way, the user could possibly control the GPU to change rendered objects from opaque to transparent to see things and / or competitors behind the rendered objects, gaining an advantage during the video game.

[0033] The techniques disclosed herein can provide mechanisms for verifying the integrity of commands, shader programs, and / or other instructions implemented by a GPU. For example, the techniques disclosed herein can verify that commands, shader programs, and / or other instructions implemented by a GPU have not been compromised, tampered with, or altered. The techniques disclosed herein can also refuse and / or stop execution of any commands, shader programs, and / or other instructions that cannot be verified and / or determined to have been compromised, tampered with, or altered. The techniques disclosed herein can also obscure, hide, and / or protect command and / or shader program patterns to prevent others from reverse engineering and exploiting such patterns. In some examples, the techniques disclosed herein can implement signatures at arbitrary, pseudo-random, or other locations in the command stream, shader program, and / or other instructions to prevent others from reverse engineering the command stream, shader program, and / or other instructions and to verify the integrity of the command stream, shader program, and / or other instructions.

[0034] The following disclosure provides systems, apparatus (or devices), processes (or methods), and computer-readable media for signing and executing GPU command streams and software. The techniques described herein will be presented in the following disclosure. The discussion begins with a description of example systems, techniques, and methods for signing and executing GPU command streams and software, such as... Figures 1 to 4B As shown. This will be followed by a description of an example process for signing and executing GPU command streams and shader programs, as follows. Figure 5 As shown. The discussion concludes with a description of an example computing device architecture, which includes example hardware components suitable for signing and executing GPU command streams and software, such as... Figure 6 As shown. This disclosure now turns to Figure 1 .

[0035] Figure 1 This is a diagram illustrating an example computing system 100 that can be configured to implement one or more aspects of this disclosure. In some examples, the computing system 100 can sign and execute processor and / or computer program commands and command streams, as further described herein. For example, in some cases, the computing system 100 can sign and execute graphics processing unit (GPU) command streams to protect the command streams and prevent unauthorized reverse engineering of the command streams. In some examples, the computing system 100 can sign and execute computer graphics commands, such as shader commands. The computing system 100 can also perform any other computer processing tasks, such as data processing tasks, image processing tasks, and graphics rendering and / or manipulation, etc.

[0036] The computing system 100 may be part of one or more computing devices. In some examples, the computing system 100 may be part of electronic devices (or multiple electronic devices), such as a desktop computer, laptop or notebook computer, server, tablet computer, camera system (e.g., digital camera, IP camera, camcorder, security camera, etc.), telephone system (e.g., smartphone, cellular phone, conferencing system, etc.), embedded system, mobile phone, game console, display system, extended reality (XR) device (e.g., head-mounted display, smart glasses, etc.), or any other suitable electronic device.

[0037] exist Figure 1 In the example shown, computing system 100 includes one or more image sensors 102, one or more other sensors 104, one or more peripheral devices 106, storage device 108, memory 110, and computing component 120. In some implementations, one or more image sensors 102, one or more other sensors 104, one or more peripheral devices 106, storage device 108, memory 110, and computing component 120 may be part of the same computing device. For example, in some cases, one or more image sensors 102, one or more other sensors 104, one or more peripheral devices 106, storage device 108, memory 110, and computing component 120 may be integrated into smartphones, laptops, tablets, gaming systems, XR devices, servers, desktop computers, and / or any other computing device. However, in some implementations, one or more image sensors 102, one or more other sensors 104, one or more peripheral devices 106, storage device 108, memory 110, and computing component 120 may be part of two or more separate computing devices.

[0038] In some examples, one or more image sensors 102 may include any image and / or video sensor and / or camera device, such as a digital camera, camcorder, smartphone camera, camera device on an electronic device such as a television or computer, camera system, etc. In some cases, one or more image sensors 102 may be part of a camera or computing device, such as a digital camera, camcorder, IP camera, smartphone, smart TV, gaming system, etc. In some examples, one or more image sensors 102 may be part of a dual-camera assembly. One or more image sensors 102 may capture image and / or video content (e.g., raw image and / or video data), which may then be processed by computing component 120 to render, store, and / or manipulate the image and / or video content.

[0039] One or more other sensors 104 may include any sensor for detecting and / or measuring information such as light, sound, environmental conditions, objects, distance information, motion information, position information, velocity, etc. Non-limiting examples of sensors include LIDAR, gyroscope, accelerometer, magnetometer, radar, inertial measurement unit (IMU), temperature sensor, humidity sensor, sound sensor, light sensor, machine vision sensor, etc.

[0040] One or more peripheral devices 106 may include any device capable of receiving input and / or providing output. Non-limiting examples of peripheral devices may include displays, keyboards, pointing devices (e.g., computer mice, trackpoints, touchpads, touchscreens, joysticks, remote controls, input tracking devices, controllers, etc.), transceivers, microphones, speakers, screens, projectors, printers, scanners, network interfaces (e.g., wired and / or wireless communication interfaces, etc.), etc.

[0041] Storage device 108 can be any storage device used to store data (such as image data, video data, files, software, folders, content items, and / or any other type of digital data). Storage device 108 can store data from any component of computing system 100. For example, storage device 108 can store data or measurements (e.g., processing parameters, outputs, calculation results, states, etc.) from any of the following: one or more image sensors 102, one or more other sensors 104, one or more peripheral devices 106, memory 110, and computing component 120. In some examples, storage device 108 may include a buffer for storing data to be processed by computing component 120.

[0042] Memory 110 may include one or more volatile memories, non-volatile memories, and / or computer-readable storage media, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, solid-state memory, magnetic data media, optical storage media, etc. In some examples, memory 110 may include system memory or main memory.

[0043] In some implementations, computing component 120 may include a central processing unit (CPU) 122, a graphics processing unit (GPU) 124, a digital signal processor (DSP) 126, and / or an image signal processor (ISP) 128. In some cases, computing component 120 may include other circuitry or hardware, computer software, firmware, or any combination thereof to perform any of the various operations described herein. Computing component 120 can perform various operations, such as data processing operations, computer program execution and operation, image processing operations, computer vision, graphics rendering, extended reality (XR) (e.g., augmented reality, virtual reality, mixed reality, etc.), sensor processing, computer system operation, and / or any of the various operations described herein.

[0044] In some examples, computing component 120 can implement software application 130 of computing system 100. Software application 130 can include any software application and / or computer program. For example, software application 130 can include graphical user interface applications, video game applications, media applications (e.g., video playback / streaming applications, image rendering applications, etc.), XR applications, video and / or image editing applications, operating systems, virtualization systems (e.g., virtual machines, software containers, etc.), graphics rendering applications, two-dimensional (2D) and / or three-dimensional (3D) animation and rendering applications, simulation applications, decoding applications (e.g., encoding, decoding), applications for scientific computing, modeling applications, digital content creation applications, artificial intelligence applications, image processing applications, geometric computing applications, imaging applications, computer vision applications, etc.

[0045] Although computing system 100 is shown as including certain components, those skilled in the art will understand that computing system 100 may include more than [the specified components]. Figure 1 The components shown may include more or fewer components. For example, in some cases, the computing system 100 may also include a cache, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a modem, and / or other components. Figure 1 Other hardware or processing devices not shown in the diagram. See below for reference. Figure 6 Illustrative examples of computing devices and hardware components that can be implemented using computing system 100 are described.

[0046] Figure 2 This is a diagram illustrating example components of a graphics rendering system 200. In some cases, the graphics rendering system 200 may be implemented by a computing system 100. In this example, the graphics rendering system 200 includes a memory 110, a CPU 122, and a GPU 124.

[0047] CPU 122 can process instructions for execution within computing system 100. In some examples, CPU 122 can be configured to execute software application 130. Software application 130 may include software applications that implement one or more functions of GPU 124. In such examples, CPU 122 can be configured to execute software applications that implement one or more functions of GPU 124. For example, CPU 122 can be configured to execute software applications that include one or more instructions for GPU 124 to render graphics content (such as graphical user interfaces, video content, image content, animations, etc.).

[0048] CPU 122 may implement driver 202, which may generate one or more commands to implement instructions associated with software application 130 executed by CPU 122. In some examples, CPU 122 may use driver 202 to generate a command stream specifying operations to be performed by GPU 124. CPU 122 may send the command stream and / or compiled shader programs to GPU 124, and GPU 124 may perform operations associated with the command stream and / or compiled shader programs. In some examples, CPU 122 may (e.g., via driver 202) send instructions (e.g., compiled shader programs) to GPU 124 for execution by one or more shader processors 210 on GPU 124.

[0049] In some examples, driver 202 may implement application programming interface (API) functionality. For example, driver 202 may issue API calls to GPU 124 (and / or its components) and / or other components of computing system 100. In some cases, driver 202 may include one or more kernel-mode drivers. One or more kernel-mode drivers may execute software code in kernel mode. For example, one or more kernel-mode drivers may have full and / or unrestricted access to the underlying hardware, and may execute any CPU instruction and / or reference any memory address. In some examples, one or more kernel-mode drivers may perform lower-level functions, such as initializing hardware, managing memory, managing interrupts, etc. In some cases, driver 202 may also include one or more user-space drivers. One or more user-space drivers may be restricted from directly accessing the underlying hardware or referencing memory. One or more user-space drivers may alternatively delegate or rely on system APIs to access hardware or memory. In some examples, one or more user-space drivers may translate system APIs into commands to be executed.

[0050] Memory 110 may include one or more buffers 204 for storing data from CPU 122 and / or GPU 124. The one or more buffers 204 may include, for example, command buffers, ring buffers, and / or any other type of buffer. In some examples, the one or more buffers 204 may store one or more commands issued by driver 202 and / or CPU 122, one or more pointers to one or more commands issued by driver 202 and / or CPU 122 (and / or locations in memory where one or more commands are stored), one or more pointers to one or more indirect command buffers 218 (described further below) pointing to commands issued by driver 202 and / or CPU 122, data associated with memory access operations, data associated with the operation of one or more commands, etc. For example, the one or more buffers 204 may store a command stream specifying an operation performed by GPU 124 (e.g., via one or more shader processors 210 and / or command processors 214), the operational state of the command stream, and / or pointers to indirect buffers or to commands in memory and / or indirect buffers.

[0051] In some cases, one or more buffers 204 may store state data associated with the operations of the command stream (e.g., variables, intermediate results of operations, processing events, trace information, execution values, etc.). In some cases, one or more buffers 204 may allow the computing system 100 to store data associated with the command stream and / or the operations of the command stream (e.g., state, commands, memory access operation data, etc.) for fast access by the CPU 122 and / or GPU 124, and / or avoid persisting data in memory (e.g., memory 216) and / or memory 110 on the GPU 124.

[0052] GPU 124 can be configured to perform graphics rendering operations and / or graphics processing operations. In some examples, GPU 124 can be configured to perform general-purpose computing operations and / or other processing operations, such as image processing operations. Figure 2 In the example shown, GPU 124 includes shader system 208, command processor 214, and memory 216.

[0053] Shader system 208 may include one or more shader processors 210 and one or more shader programs 212 compiled by one or more of the drivers 202. The one or more shader processors 210 may perform shading operations to render graphical content. For example, the one or more shader processors 210 may perform geometry, vertex, pixel, and / or other shading operations. In some cases, the one or more shader processors 210 may include one or more components for performing associated operations, logic units for performing computations, registers, caches, memory, etc. The one or more shader programs 212 may include shading language programs compiled by one or more of the drivers 202. In some cases, the one or more shader programs 212 may include instructions (e.g., commands, logic, etc.) for associated shading operations performed by the one or more shader processors 210.

[0054] Command processor 214 can be configured to receive and process command streams from driver 202. In some examples, command processor 214 can be a stream processor configured to receive and process command streams from CPU 122 (e.g., from driver 202). In some cases, command processor 214 can schedule operations to be performed by GPU 124. For example, command processor 214 can schedule operations to be performed by one or more shader processors 210. In some cases, command processor 214 can determine when to schedule operations and / or which GPU resources to perform operations. In some examples, command processor 214 can receive command streams from driver 202 and schedule operations of the command streams for execution by one or more shader processors 210.

[0055] In some cases, command processor 214 may receive multiple command streams from driver 202. In some examples, command processor 214 may interrupt the operation of a command stream during execution of GPU 124 and initiate (e.g., start, restart, switch to, etc.) the operation of a different command stream. Command processor 214 may later restart the operation of the interrupted command stream. In some examples, command processor 214 may receive interrupts from driver 202 and / or CPU 122 to switch the operation of one command stream to another.

[0056] Command processor 214 may store data associated with operations of the command stream. In some cases, command processor 214 may store data on one or more buffers 204, memory 110, and / or memory 216 on GPU 124. For example, command processor 214 may store command streams, state associated with operations of the command stream, operation data, data associated with memory access operations, and / or other data on one or more buffers 204 and / or memory 216. In some examples, command processor 214 may process and / or schedule operations of commands in one or more indirect command buffers 218.

[0057] One or more indirect command buffers 218 may include commands and / or pointers to commands from one or more command streams received by command processor 214 from driver 202. For example, an indirect command buffer may include a set of pointers to commands from a command stream from driver 202. In some cases, pointers may reference commands in a command stream and / or locations in memory storing commands in the command stream. For example, an indirect command buffer may include a set of pointers to commands in a command stream. In some cases, each pointer may reference a location in memory (e.g., memory 216, one or more buffers 204, etc.) storing the command associated with that pointer and / or storing the state of an operation associated with that command. In some cases, command processor 214 may cache one or more indirect command buffers 218, retain one or more indirect command buffers 218 while processing commands in the indirect command buffers 218, and / or store one or more indirect command buffers 218 in memory 216.

[0058] In some cases, one or more buffers 204 may include pointers to one or more indirect command buffers 218, commands associated with one or more indirect command buffers 218, and / or the state of operations associated with commands in one or more indirect command buffers 218. In some examples, at least a portion of the data in one or more buffers 204 may correspond to data in one or more indirect command buffers 218. In some cases, indirect command buffers may include pointers to different indirect command buffers associated with different command streams.

[0059] For example, the first indirect command buffer may include a pointer to a second indirect command buffer, which is associated with a second command stream to be processed as part of the first command stream. Command processor 214 may initiate and / or process commands associated with the first command stream. During processing of commands in the first command stream, when command processor 214 reaches a pointer to the second indirect command buffer in the first indirect command buffer, command processor 214 may process the second command stream in the second indirect buffer associated with that pointer. When the operation on the second command stream is complete, command processor 214 may return to the first indirect buffer and process any remaining pointers (and / or associated commands).

[0060] To further illustrate, in one example, the first command stream may correspond to commands for drawing the car to be rendered, and the second command stream may correspond to commands for drawing the wheels of the car. In this example, the command processor 214 may sequentially access pointers and / or commands in the first indirect command buffer to initiate the operation of the first command stream for drawing the car. When the command processor 214 encounters a pointer to the second indirect command buffer, it may sequentially access pointers and / or commands in the second indirect command buffer to initiate the operation of the second command stream for drawing the wheels of the car. When the operation of the second command stream is complete, the command processor 214 may return to the first indirect command buffer to sequentially access any remaining pointers and / or commands and initiate any remaining operations for drawing the car.

[0061] In some cases, when command processor 214 processes a command stream, it may store data associated with the operations of that command stream. For example, command processor 214 may buffer data associated with memory access operations (e.g., read operations, write operations, etc.) and / or data associated with operations that depend on data in a specific memory location. In some cases, this can provide GPU 124 with fast access to the buffered data, prevent GPU 124 from generating the same data multiple times, and / or prevent GPU 124 from persisting data in memory 216 and / or memory 110 on GPU 124.

[0062] In some examples, operations in the command stream can access one or more locations in memory 216, memory 110, and / or one or more buffers 204. In some cases, the data associated with these operations may include indications of the contents of one or more locations in memory 216, memory 110, and / or one or more buffers 204 associated with these operations.

[0063] Memory 216 may include any graphics memory. In some examples, memory 216 may include one or more volatile memories, non-volatile memories, and / or computer-readable storage media, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc.

[0064] Figure 3 This is a diagram illustrating an example system flow 300 for implementing a signed command stream. In this example, driver 302 can represent a signal from... Figure 2 The driver 202 in the middle. The driver 302 can be associated with a software application from the software application 130.

[0065] Driver 302 can generate command streams 304 and 306 and send them to command processor 214. Command streams 304 and 306 can include commands specifying operations to be performed by GPU 124 and / or command processor 214. Figure 3 In this context, command stream 304 represents a command stream sent to command processor 214 and included in indirect command buffer (ICB) 310, and command stream 306 represents a command stream sent to command processor 214 and included in ICB 320. Although Figure 3 Two command streams and two ICBs are shown; however, it should be noted that other examples may include a single command stream and / or ICB, or two or more command streams and / or ICBs. Command streams 304 and 306 and ICBs 310 and 320 are non-limiting examples provided for illustrative purposes.

[0066] In some examples, commands in streams 304-306 and / or ICBs 310-320 may be encapsulated in packets. For example, a command may be the payload (or a portion of the payload) of a command stream and / or a packet in the corresponding ICB. In some cases, packets may have a specific structure defined by the programming model used. For example, a packet may have a header and payload defined by a specific programming model.

[0067] ICB 310 and ICB 320 can indicate from Figure 2 One or more indirect command buffers 218 in the indirect command buffer. ICB 310 may include commands (or pointers to commands) in command stream 304, and ICB 320 may include commands (or pointers to commands) in command stream 306. Figure 3In the example, ICB 310 also includes an indirect pointer 316 that references (e.g., points to) ICB 320. The indirect pointer 316 can reference ICB 320 to indicate that when command processor 214 reaches indirect pointer 316 as command processor 214 sequentially processes command stream 304 in ICB 310, command processor 214 should access and process command stream 306 in ICB 320. In other words, indirect pointer 316 can function similarly to a symbolic link, directing command processor 214 to ICB 320 when it reaches indirect pointer 316.

[0068] In this way, when command processor 214 reaches indirect pointer 316 within ICB 310, indirect pointer 316 can redirect command processor 214 to command stream 306 in ICB 320. Based on indirect pointer 316, command processor 214 can access ICB 320 and process command stream 306 within ICB 320. When command processor 214 finishes processing command stream 306 in ICB 320, command processor 214 can return to ICB 310 and continue executing the next command or pointer (if any) after indirect pointer 316. Figure 3 The example is a status command.

[0069] Command streams 304 and 306 may include signatures 312, 314, 322, and 324 generated by driver 302. For example, command stream 304 may include signatures 312 and 314 at different locations within command stream 304, and command stream 306 may include signatures 322 and 324 at different locations within command stream 306. Figure 3 The number of signatures shown is an illustrative example provided for explanation purposes. In other examples, command flows 304 and / or 306 may include more than [a certain number of signatures]. Figure 3 The more or fewer signatures shown.

[0070] Signatures 312, 314, 322, and 324 may include hash values ​​generated using a hash algorithm. Driver 302 and command processor 214 may know the hash algorithm and key used to generate signatures 312, 314, 322, and 324, allowing driver 302 and command processor 214 to independently generate and verify signatures 312, 314, 322, and 322. In some cases, other components of GPU 124 (such as one or more shader processors 210) may also know the hash algorithm and key used to generate signatures 312, 314, 322, and 324, to independently generate and verify signatures 312, 314, 322, and 324. Signatures 312, 314, 322, and 324 can provide security mechanisms for protecting the integrity of command streams 304 and 306 and the operation of GPU 124. For example, signatures 312, 314, 322, and 324 can provide levels of encryption, verification, and / or obfuscation to prevent others from reverse engineering and / or manipulating the command stream implemented by GPU 124 and associated software.

[0071] In some examples, signatures 312, 314, 322, 324 may include no-operation instructions or other instructions or commands indicating that command streams 304 and 306 should not be executed and / or accepted if signatures 312, 314, 322, 324 are not verified by command processor 214.

[0072] In some examples, driver 302 can generate signatures 312, 314, 322, and 324, and command processor 214 can verify signatures 312, 314, 322, and 324 when receiving, storing, processing, scheduling, and / or executing command streams 304 and 306. For example, command processor 214 can use the same hash algorithm to generate signatures based on command streams 304 and 306 received from driver 302. Command processor 214 can then compare the generated signatures with signatures 312, 314, 322, and 324 to verify that command streams 304 and 306 have not been manipulated (e.g., tampered with, corrupted, altered, intruded upon, etc.).

[0073] If command processor 214 fails to verify signatures 312, 314, 322, 324 (e.g., if the generated signatures do not match signatures 312, 314, 322, 324), command processor 214 may reject (e.g., abort, refuse, ignore, refuse to process / execute, etc.) command flows 304 and 306. In some examples, if command processor 214 fails to verify signatures 312, 314, 322, 324, command processor 214 may generate a fault (e.g., error, alarm, notification, fault event, etc.) that blocks (and / or stops) execution of command flows 304 and 306 and / or indicates that verification of signatures 312, 314, 322, 324 has failed. In some cases, command processor 214 may generate indications, alarms, notifications, etc., to notify driver 302, computing system 100, and / or user that signature verification has failed, which may indicate potential problems and / or malicious behavior. If command processor 214 is able to verify signatures 312, 314, 322, 324 (e.g., if the generated signature matches signatures 312, 314, 322, 324), then command processor 214 may allow execution and / or continue execution of command streams 304 and 306.

[0074] Driver 302 (and command processor 214 at verification time) can generate hash values ​​for signatures 312, 314, 322, and 324 based on one or more characteristics of command streams 304 and 306. For example, driver 302 can generate signatures for command streams based on: the size of the command stream (e.g., the number of commands or groups in the command stream), the number of indirect pointers in the command stream, one or more portions of the content of the command stream, the number of commands of a particular type (e.g., the number of draw commands, the number of status commands, the number of read commands, etc.), the number of command groups of a particular type (e.g., the number of draw, status, and / or other command groups), the content of one or more commands in the command stream (e.g., the content of draw and / or status commands, the content of every three commands, etc.), and / or any other characteristics of the command stream.

[0075] For example, when driver 302 generates command stream 304, it can track the number, type, pattern, characteristics, and / or content of commands (or a subset of these commands) it encounters. When driver 302 generates signature 312, driver 302 can know the number, type, pattern, characteristics, and / or content of commands (or some tracked commands) that driver 302 has encountered in command stream 304 before signature 312. Driver 302 can use any information from the number, type, pattern, characteristics, and / or content of the commands it encounters to generate signature 312. After generating signature 312, driver 302 can continue to track the number, type, pattern, characteristics, and / or content of commands in command stream 304. When generating signature 314, driver 302 can similarly use the tracked information to compute signature 314. Signature 314 can be generated based on information tracked before signing (e.g., including or excluding information tracked before signature 312). Driver 302 can similarly generate signatures 322 and 324 for command stream 306. In some cases, because command stream 304 references command stream 306 (e.g., via indirect pointer 316), driver 302 may optionally consider (e.g., use in calculating signatures 322 and 324) information traced from command stream 304 when generating signatures 322 and 324 for command stream 306, and / or vice versa.

[0076] In some examples, driver 302 may insert a signature into the command stream at one or more random, pseudo-random, and / or predetermined locations. For example, driver 302 may insert a signature into the command stream after every n commands, after every n kilobytes of data and / or space, after every n commands of a certain type, at one or more arbitrarily chosen locations, at one or more locations calculated as a factor of one or more characteristics of the command stream and / or as part of the content of the command stream (e.g., as a factor of one or more payloads in the command stream, the size of the command stream, the command pattern in the command stream, etc.), or at one or more locations calculated as a factor of one or more runtime conditions and / or any other characteristics used to calculate the location with a level of randomness.

[0077] By randomizing, obfuscating, and / or hiding the position of the signature in the command stream, driver 302 can prevent others from reverse engineering the signature and / or command stream based on patterns in the signature and / or command stream (or increase the difficulty for others to reverse engineer the signature and / or command stream based on patterns in the signature and / or command stream). For example, if a malicious user analyzes the command stream and detects that the signature is inserted at the same position in the command stream, the malicious user may be able to identify specific patterns about the signature and command stream and reverse engineer the signature based on the identified patterns. A malicious user may potentially reverse engineer the command stream, intrude (e.g., modify, tamper with, copy, corrupt, etc.) the command stream, intrude on the operation of GPU 124, and / or use information (e.g., command stream and / or signature information) for unauthorized and / or malicious actions.

[0078] Figure 4A This is a diagram illustrating an example system flow 400 for compiling a shader program with a verified signature. In this example, driver 402 can compile shader program 404 for execution by a shader processor (e.g., one or more shader processors 210). In some examples, shader program 404 may be stored in memory 216 for retrieval and execution by the shader processor. In other examples, shader program 404 may be stored in a different memory or buffer, such as memory 110 or one or more buffers 204.

[0079] Driver 402 can represent from Figure 2 The driver of driver 202 in the middle, and the shader program 404 can represent from the .... Figure 2 The shader program 404 is one or more shader programs 212 in the software application 130. The driver 402 may be associated with a software application from the software application 130. The shader program 404 may include a shader command stream and / or a shader instruction set specifying operations to be performed by the GPU 124 and / or the shader processor. In some cases, the shader program 404 may include an instruction set for the shader processor. In some examples, the instruction set may include a command stream. For example, each instruction in the instruction set may include a command, such as a shader command.

[0080] Shader program 404 may include signatures 408 and 410 generated by driver 402. For example, shader program 404 may include signatures 408 and 410 at different locations within shader program 404. Figure 4A The number of signatures shown is an illustrative example provided for explanatory purposes. In other examples, shader procedure 404 may include more than Figure 4A The number of signatures shown may be more or less.

[0081] Signatures 408 and 410 may include a hash value generated using a hash algorithm. Signatures 408 and 410 may provide security mechanisms to protect the integrity of the operation of shader program 404 and GPU 124. For example, signatures 408 and 410 may provide encryption, verification, and / or obfuscation levels to prevent others from reverse engineering and / or manipulating shader program 404.

[0082] In some examples, driver 402 may generate signatures 408 and 410, and command processor 214 and / or shader processor may verify signatures 408 and 410 when receiving, storing, processing, scheduling, and / or executing shader program 404. For example, command processor 214 and / or shader processor 210 may use the same hash algorithm to generate a signature based on shader program 404. Command processor 214 and / or shader processor 210 may then compare the generated signature with signatures 408 and 410 to verify that shader program 404 has not been manipulated (e.g., tampered with, corrupted, altered, intruded upon, etc.). If command processor 214 and / or shader processor 210 fails to verify signatures 408 and 410 (e.g., if the generated signature does not match signatures 408 and 410), command processor 214 and / or shader processor 210 may reject (e.g., abort, refuse, ignore, refuse to execute, etc.) shader program 404.

[0083] In some examples, signatures 408 and 410 may include no-operation instructions or other instructions or commands indicating that shader program 404 should not be executed and / or accepted if signatures 408 and 410 are not verified by shader processor 210 and / or command processor 214.

[0084] Driver 402 (and command processor 214 and / or shader processor at verification time) may generate hash values ​​for signatures 408 and 410 based on one or more characteristics of shader program 404. For example, driver 402 may generate a signature for shader program 404 (and / or one or more instructions and / or commands in shader program 404) based on: the size of shader program 404 (e.g., the number of instructions and / or commands in shader program 404), the number of indirect pointers in shader program 404, one or more portions of the contents of shader program 404, the number of commands of a particular type (e.g., draw, state, read, write, etc.), the number of command groups of a particular type (e.g., draw, state, etc.), the contents of one or more instructions and / or commands in shader program 404, and / or any other characteristics of shader program 404.

[0085] For example, when driver 402 generates shader program 404, it can track the number, type, pattern, characteristics, and / or content of commands (or a subset of those commands) it has encountered. When driver 402 generates signature 408, driver 402 can know the number, type, pattern, characteristics, and / or content of commands (or some tracked commands) encountered by driver 402 in shader program 404 prior to signature 408. Driver 402 can use any information from the number, type, pattern, characteristics, and / or content of the commands it has encountered to generate signature 408. After generating signature 408, driver 402 can continue to track the number, type, pattern, characteristics, and / or content of commands in shader program 404. When generating signature 410, driver 402 can similarly use the tracked information to compute signature 410. Signature 410 can be generated based on information tracked prior to signature 410 (e.g., including or excluding information tracked prior to signature 408).

[0086] In some examples, driver 402 may insert a signature at one or more random, pseudo-random, and / or predetermined locations in shader program 404. For example, driver 402 may insert a signature in shader program 404 after every n commands, after every n kilobytes of data and / or space, after every n commands of a certain type, at one or more arbitrarily chosen locations, at one or more locations calculated as a factor of one or more characteristics of shader program 404 and / or as part of the content of shader program 404 (e.g., as a factor of one or more commands in shader program 404, the size of shader program 404, the command pattern in shader program 404, etc.), at one or more locations calculated as a factor of one or more runtime conditions and / or any other characteristics used to calculate locations with a level of randomness.

[0087] By randomizing, obfuscating, and / or hiding the location of the signature in shader program 404, driver 402 can prevent others from reverse engineering the signature and / or shader program 404 based on patterns in the signature and / or shader program 404 (or increase the difficulty for others to reverse engineer the signature and / or shader program 404 based on patterns in the signature and / or shader program 404). For example, if a malicious user detects that the signature is inserted in the same location in the shader program, the malicious user may be able to identify specific patterns about the signature and shader program 404 and reverse engineer the signature based on the identified patterns. A malicious user may potentially reverse engineer shader program 404, compromise (e.g., modify, tamper with, copy, corrupt, etc.) shader program 404, compromise the operation of GPU 124, and / or use information (e.g., shader program 404 and / or signature information) for unauthorized and / or malicious acts.

[0088] Figure 4B This is a diagram illustrating an example system flow 420 for verifying a shader program based on a verified signature. In this example, driver 402 sends a command stream 422 to command processor 214. Command stream 422 may include commands instructing command processor 214 to schedule the execution of shader program 404 (e.g., and / or instructing shader processor 210 to execute shader program 404). In some examples, command stream 422 may include no-operation instructions or other instructions or commands indicating that shader program 404 should not be executed if signatures 408 and 410 in shader program 404 are not verified by command processor 214 and / or shader processor 210.

[0089] Command processor 214 may send command 424 to shader processor 210 to trigger shader processor 210 to execute shader program 404. In some cases, command 424 may include no-operation instructions or other instructions or commands as described above. In some examples, command 424 may include a pointer to a location in memory (e.g., memory 216) corresponding to shader program 404 (e.g., where shader program 404 is stored in memory). Shader processor 210 may retrieve shader program 404 from memory and verify signatures 408 and 410, as further described below. In some cases, command processor 214 may verify signatures 408 and 410 in shader program 404 before sending command 424 to shader processor 210, as described below with respect to shader processor 210.

[0090] To verify signatures 408 and 410, shader processor 210 (optionally, and command processor 214) can use a hash algorithm used by driver 402 to generate a signature based on shader program 404. As previously described, shader processor 210 (optionally, and command processor 214) can generate a signature based on one or more characteristics (and / or contents) of shader program 404. Shader processor 210 (optionally, and command processor 214) can then compare the generated signature with signatures 408 and 410 in shader program 404 to verify that shader program 404 has not been manipulated (e.g., tampered with, corrupted, altered, intruded upon, etc.).

[0091] If shader processor 210 (or command processor 214) fails to verify signatures 408 and 410 (e.g., if the generated signatures do not match signatures 408 and 410), shader processor 210 (or command processor 214) may refuse (e.g., abort, reject, ignore, refuse to execute, etc.) shader program 404. In some cases, shader processor 210 (or command processor 214) may generate indications, alerts, notifications, etc., to notify driver 402, computing system 100, and / or user that signature verification has failed, which may indicate potential problems and / or malicious behavior. If shader processor 210 (optionally, and command processor 214) is able to verify signatures 408 and 410 (e.g., if the generated signatures match signatures 408 and 410), shader processor 210 (and command processor 214) may allow execution of shader program 404 to begin, continue, and / or complete.

[0092] Having disclosed the example systems, technologies, and concepts, this disclosure now turns to... Figure 5 Example method 500 is shown. The steps outlined in this article are examples and can be implemented in any combination of them, including excluding, adding, or modifying certain steps.

[0093] At box 502, method 500 may include: receiving one or more commands (e.g., command stream 304, command stream 306, command stream 422, command 424) by a GPU (e.g., GPU 124), the one or more commands including one or more verification signatures (e.g., signatures 312, 314, 322, 324, 408, 410) generated using a processor (e.g., CPU 122). In some examples, each verification signature may include a first value generated based on one or more commands. In some cases, the first value may include a hash value generated based on a hash algorithm.

[0094] In some cases, a first value can be generated based on one or more characteristics of one or more commands. One or more characteristics may include, for example, but are not limited to: the number of commands in one or more commands, the number of commands of one or more types in one or more commands, the content of at least one command in one or more commands, the content of one or more indirect pointers included in one or more commands (e.g., indirect pointer 316), and / or the number of indirect pointers included in one or more commands (e.g., indirect pointer 316). In some examples, indirect pointers may include one or more references to one or more additional commands.

[0095] In some examples, one or more commands may specify one or more operations to be performed by the GPU (and / or one or more components of the GPU). For example, one or more commands may specify one or more shading and / or rendering operations to be performed by the GPU. In some examples, one or more commands may include command streams (e.g., command streams 304, 306, 422), shader programs (e.g., shader program 404), commands referencing shader programs (e.g., command 424), and / or one or more pointers to one or more locations in memory associated with one or more commands.

[0096] In some examples, one or more verification signatures may include no-operation instructions or commands indicating that one or more commands should not be executed and / or accepted if one or more verification signatures are not verified by the GPU (e.g., via a command processor, shader processor, and / or a processor authorized to create and manipulate at least one operation of the command stream). For example, in some cases, one or more verification signatures may include commands and / or instructions (e.g., no-operation instructions or other instructions or commands) indicating that one or more commands should not be executed and / or should be terminated if one or more verification signatures are invalid (and / or not verified as valid). In some examples, one or more commands may include a command stream comprising multiple commands.

[0097] In some cases, one or more verification signatures can be generated by a user-space device driver, a kernel-space driver, and / or a processor authorized to create and / or manipulate command streams. A kernel-space driver can include a kernel driver and / or a driver operating in kernel mode. In some examples, a kernel-space driver can execute software code in kernel mode and / or kernel space. For example, a kernel-space driver can have full and / or unrestricted access to the underlying hardware (e.g., GPU, memory, processor, etc.), can execute any processor instruction (e.g., any CPU instruction), and / or reference any memory address. In some examples, a kernel-space driver can perform lower-level functions such as hardware initialization, memory management, interrupt management, etc.

[0098] User-space drivers can include drivers that operate in user space and / or user-space mode. In some examples, user-space drivers may be restricted from directly accessing the underlying hardware or referencing memory. For example, a user-space driver may alternatively delegate or rely on system APIs to access hardware or memory. In some examples, a user-space driver may translate system APIs into commands to be executed.

[0099] At box 504, method 500 may include: generating one or more additional verification signatures associated with one or more commands by the GPU. In some examples, each verification signature may include a second value generated by the GPU based on one or more commands. In some cases, the second value may be generated based on one or more characteristics of one or more commands, as previously described. In some examples, the second value may include a hash value generated based on a hash algorithm. For example, the second value may include a hash value generated by hashing data corresponding to one or more characteristics of one or more commands (e.g., identifiers, descriptions, representations of one or more characteristics, etc.).

[0100] In some examples, one or more additional verification signatures may be generated by a command processor (e.g., command processor 214) associated with the GPU and / or a shader processor (e.g., shader processor 210) associated with the GPU.

[0101] At box 506, method 500 may include: determining the validity of one or more commands by the GPU based on a comparison of one or more verified signatures and one or more additional verified signatures. In some cases, the validity of one or more commands may be determined during runtime execution of one or more commands and / or the software application associated with one or more commands.

[0102] In some cases, the validity of one or more commands can be determined during the runtime execution of the software application associated with one or more commands and before the execution of one or more commands and / or the completion of one or more operations associated with one or more commands.

[0103] In some examples, determining the validity of one or more commands may include: determining that a first value associated with one or more verification signatures matches a second value associated with one or more additional verification signatures; and determining that one or more commands are valid. Based on the match between the first value associated with one or more verification signatures and the second value associated with one or more additional verification signatures, it can be determined that one or more commands are valid. In some aspects, method 500 may include: authorizing the execution of one or more commands at the GPU (e.g., initiation of execution, completion of execution, etc.) based on the validity of one or more commands.

[0104] In some cases, determining that one or more commands are valid can result in: determining that one or more commands are authorized to be executed by the GPU, determining the integrity of one or more commands, and / or determining that one or more commands do not contain unauthorized modifications. In some examples, a command can be authorized to be executed by the GPU if it is determined that it was generated (or matches commands generated by) the GPU manufacturer (or an entity authorized to generate commands for execution on the GPU), approved or pre-approved by the GPU manufacturer (or an entity authorized to generate commands for execution on the GPU), meets one or more authorization requirements (e.g., security requirements, stability requirements, verification requirements, developer requirements, source requirements, etc.), was generated from and / or obtained from a specific approved source, etc.

[0105] In some examples, command integrity may correspond to the trust level of the command's source (e.g., developer, GPU manufacturer, etc.), the command's reliability and / or security level and / or state, and a guarantee that the command has not been modified (e.g., corrupted, tampered with, intruded upon, etc.). In some examples, unauthorized modifications to the command may include modifications or intrusions made by an end user or unauthorized user (and / or unauthorized entity), modifications resulting from command corruption and / or destruction, accidental modifications to the command, etc.

[0106] In some cases, determining the validity of one or more commands may include: determining that a first value associated with one or more verification signatures does not match a second value associated with one or more additional verification signatures, and determining that one or more commands are invalid. In some examples, determining that one or more commands are invalid may result in determining that one or more commands are not authorized to be executed by the GPU and / or determining that one or more commands include one or more unauthorized modifications.

[0107] In some aspects, method 500 may include: preventing the execution of one or more commands at the GPU and / or the completion of the current execution of one or more commands at the GPU based on the fact that one or more commands are invalid. For example, when one or more commands are determined to be invalid, method 500 may prevent the execution of one or more commands, reject one or more commands, or terminate the execution of one or more commands.

[0108] In some examples, the validity of one or more commands can be determined by the command processor and / or shader processor. In some examples, one or more additional verification signatures can be generated by the command processor and / or shader processor.

[0109] In some examples, method 500 may be performed by one or more computing devices or apparatuses. In an illustrative example, method 500 may be performed by... Figure 1 The computing system 100 shown and / or having in Figure 6 The computing device architecture 600 shown is performed by one or more computing devices. In some cases, such a computing device or apparatus may include a processor, microprocessor, microcomputer, or other components of a device configured to perform the steps of method 500. In some examples, such a computing device or apparatus may include one or more sensors configured to capture image data. For example, the computing device may include a smartphone, head-mounted display, mobile device, camera, tablet computer, or other suitable device. In some examples, such a computing device or apparatus may include a camera configured to capture one or more images or videos. In some cases, such a computing device may include a display for displaying images. In some examples, one or more sensors and / or cameras are separate from the computing device, in which case the computing device receives the sensed data. Such a computing device may also include a network interface configured to transmit data.

[0110] Components of a computing device can be implemented in circuitry. For example, components may include and / or be implemented using electronic circuitry or other electronic hardware, which may include one or more programmable electronic circuits (e.g., a microprocessor, graphics processing unit (GPU), digital signal processor (DSP), central processing unit (CPU), and / or other suitable electronic circuitry), and / or may include computer software, firmware, or any combination thereof and / or be implemented using such software to perform the various operations described herein. A computing device may also include a display (as an example of an output device or other than an output device), a network interface configured to transmit and / or receive data, any combination thereof, and / or other components. The network interface may be configured to transmit and / or receive Internet Protocol (IP)-based data or other types of data.

[0111] Method 500 is illustrated as a logic flowchart, the operations of which represent a series of operations that can be implemented using hardware, computer instructions, or a combination thereof. In the context of computer instructions, the operations represent computer-executable instructions stored on one or more computer-readable storage media, which, when executed by one or more processors, perform the described operations. Typically, computer-executable instructions include routines, programs, objects, components, data structures, etc., that perform a specific function or implement a specific data type. The order in which the operations are described is not intended to be construed as limiting, and any number of the described operations can be combined in any order and / or in parallel to implement these processes.

[0112] Additionally, method 500 can be executed under the control of one or more computer systems configured with executable instructions, and can be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that executes jointly on one or more processors, implemented in hardware, or a combination thereof. As mentioned above, the code can be stored, for example, in the form of a computer program comprising multiple instructions executable by one or more processors on a computer-readable or machine-readable storage medium. The computer-readable or machine-readable storage medium can be non-transitory.

[0113] Figure 6 An example computing device architecture 600 is shown, illustrating an example computing device capable of implementing the various technologies described herein. For example, computing device architecture 600 can be implemented in… Figure 1At least some portions of the computing system 100 shown are illustrated. Components of the computing device architecture 600 are shown to be in electrical communication with each other using a connection 605 (such as a bus). The example computing device architecture 600 includes a processing unit (CPU or processor) 610 and a computing device connection 605 that couples various computing device components, including computing device memories 615 (e.g., read-only memory (ROM) 620 and random access memory (RAM) 625), to the processor 610.

[0114] The computing device architecture 600 may include a cache of high-speed memory, which may be directly connected to, close to, or integrated as part of the processor 610. The computing device architecture 600 may copy data from memory 615 and / or storage device 630 to cache 612 for fast access by the processor 610. In this way, the cache can provide performance improvements by preventing latency for the processor 610 while waiting for data. These and other modules may control or be configured to control the processor 610 to perform various operations. Other computing device memories 615 may also be available. Memory 615 may include various different types of memory with different performance characteristics.

[0115] Processor 610 may include any general-purpose processor as well as hardware and / or software services and / or components stored in storage device 630, configured to control processor 610 and dedicated processors in which software instructions are incorporated into the processor design. Processor 610 may be a self-contained system containing multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may be symmetric or asymmetric.

[0116] To enable user interaction with computing device architecture 600, input device 645 can represent any number of input mechanisms, such as a microphone for voice, a touchscreen for gesture or graphical input, a keyboard, a mouse, motion input, voice, etc. Output device 635 can also be one or more of a variety of output mechanisms known to those skilled in the art, such as a display, projector, television, speaker device. In some cases, multimodal computing devices can enable users to provide multiple types of input to communicate with computing device architecture 600. Communication interface 640 typically controls and manages user input and computing device output. There are no limitations on operation on any particular hardware configuration, and therefore, the basic features described here can be readily replaced by improved hardware or firmware configurations (as they are developed).

[0117] Storage device 630 is a non-volatile memory and may be a hard disk or other type of computer-readable medium that can store data accessible by a computer, such as magnetic tape, flash memory cards, solid-state storage devices, digital multifunction disks, magnetic tape cartridges, random access memory (RAM) 165, read-only memory (ROM) 620, and mixtures thereof. Storage device 630 may include software, firmware, and / or logic for controlling processor 610. Other hardware or software modules are contemplated. Storage device 630 may be connected to computing device connection 605. In one aspect, a hardware module performing a particular function may include a software component stored in a computer-readable medium connected to hardware components necessary to perform that function, such as processor 610, connection 605, output device 635, etc.

[0118] The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media capable of storing, containing, or carrying instructions and / or data. Computer-readable media can include non-transitory media in which data can be stored but excludes carrier waves and / or transient electronic signals propagating wirelessly or over a wired connection. Examples of non-transitory media include, but are not limited to, magnetic disks or magnetic tapes, optical storage media such as compact discs (CDs) or digital versatile discs (DVDs), flash memory, memory, or memory devices. Computer-readable media may have code and / or machine-executable instructions stored thereon, which may represent procedures, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or any combination of instructions, data structures, or program statements. A code segment can be coupled to another code segment or hardware circuitry by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., can be passed, forwarded, or sent via any suitable means, including memory sharing, messaging, token passing, network transmission, etc.

[0119] In some embodiments, computer-readable storage devices, media, and memories may include cables or wireless signals containing bit streams, etc. However, when referred to, non-transitory computer-readable storage media explicitly excludes media such as energy, carrier signals, electromagnetic waves, and the signals themselves.

[0120] Specific details are provided in the foregoing description to provide a thorough understanding of the embodiments and examples provided herein. However, those skilled in the art will understand that these embodiments can be practiced without these specific details. For clarity, in some instances, the techniques described herein may be presented as comprising individual functional blocks, including devices, device components, steps or routines in a software-embodied method, or a combination of hardware and software. Additional components may be used in addition to those shown in the figures and / or described herein. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure these embodiments with unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring these embodiments.

[0121] The various embodiments described above may be presented as processes or methods, depicted as flowcharts, schematic diagrams, data flow diagrams, structural diagrams, or block diagrams. While a flowchart may describe operations as a sequential process, many of these operations may be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. A process terminates upon completion of its operations, but may have additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subroutine, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0122] The processes and methods described in the examples above can be implemented using computer-executable instructions, which are stored in or otherwise made available from a computer-readable medium. Such instructions may include, for example, instructions or data that cause a general-purpose computer, special-purpose computer, or processing device to perform or otherwise configure it to perform a particular function or a particular set of functions. The portion of the computer resources used may be accessible via a network. Computer-executable instructions may be, for example, binary files, intermediate format instructions such as assembly language, firmware, or source code. Examples of computer-readable media that may be used to store instructions, information used, and / or information created during the methods according to the described examples include hard disks or optical disks, flash memory, USB devices with non-volatile memory, network storage devices, etc.

[0123] Devices implementing the processes and methods according to these disclosures may include hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof, and may employ any of a variety of form factors. When implemented using software, firmware, middleware, or microcode, program code or code segments (e.g., computer program products) for performing the necessary tasks may be stored in a computer-readable or machine-readable medium. A processor may perform the necessary tasks. Typical examples of form factors include laptop computers, smartphones, mobile phones, tablet devices, or other small form factor personal computers, personal digital assistants, rack-mount devices, standalone devices, etc. The functionality described herein may also be embodied in peripheral devices or plug-in cards. By further example, such functionality may also be implemented on a circuit board between different chips or different processes executed in a single device.

[0124] Instructions, media for transmitting such instructions, computing resources for executing them, and other structures for supporting such computing resources are example modules for providing the functionality described in this disclosure.

[0125] In the foregoing description, various aspects of this application have been described with reference to specific embodiments thereof; however, those skilled in the art will recognize that this application is not limited thereto. Therefore, although illustrative embodiments of this application have been described in detail herein, it should be understood that the inventive concept may be embodied and employed in other ways, and the appended claims are intended to be interpreted as including such variations, in addition to those limited by the prior art. Various features and aspects of the above-described applications may be used individually or in combination. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Therefore, the specification and drawings are to be considered illustrative rather than restrictive. For illustrative purposes, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in a different order than that described.

[0126] It will be understood by those skilled in the art that, without departing from the scope of this specification, the less than ("<") and greater than (">") symbols or terms used herein may be replaced by the less than or equal to ("≤") and greater than or equal to ("≥") symbols, respectively.

[0127] When a component is described as being “configured” to perform certain operations, such configuration can be achieved, for example, by designing a circuit or other hardware to perform the operation, programming a programmable circuit (e.g., a microprocessor or other suitable circuit) to perform the operation, or any combination thereof.

[0128] The phrase “coupled to” refers to any component that is physically connected directly or indirectly to another component, and / or any component that communicates directly or indirectly with another component (e.g., connected to another component via a wired or wireless connection and / or other suitable communication interface).

[0129] The language of a claim that states "at least one" and / or "one or more" in a set indicates that one or more members of that set (in any combination) satisfy the claim. For example, the language of a claim stating "at least one of A and B" or "at least one of A or B" means A, B, or A and B. In another example, the language of a claim stating "at least one of A, B, and C" or "at least one of A, B, or C" means A, B, C, or A and B, or A and C, or B and C, or A and B and C. The use of "at least one" and / or "one or more" in a language set does not limit the set to items listed in that set. For example, the language of a claim stating "at least one of A and B" or "at least one of A or B" may mean A, B, or A and B, and may additionally include items not listed in the set of A and B.

[0130] The various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, firmware, or a combination thereof. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps have been generally described above in relation to their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this application.

[0131] The techniques described herein can also be implemented using electronic hardware, computer software, firmware, or any combination thereof. Such techniques can be implemented in any of a variety of devices, such as general-purpose computers, mobile phones with wireless communication devices, or integrated circuit devices with multiple uses (including applications in mobile phones with wireless communication devices and other devices). Any feature described as a module or component can be implemented together in an integrated logic device, or separately as discrete but interoperable logic devices. If implemented in software, the techniques can be implemented at least in part by a computer-readable data storage medium comprising program code that, when executed, performs one or more of the methods, algorithms, and / or operations described above. The computer-readable data storage medium can form part of a computer program product, which may include packaging material. The computer-readable medium may include memory or data storage media, such as random access memory (RAM) (such as synchronous dynamic random access memory (SDRAM)), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic or optical data storage media, etc. Alternatively or concurrently, the technology may be implemented, at least in part, by a computer-readable communication medium (such as a propagating signal or wave) that carries or transmits program code in the form of instructions or data structures and can be accessed, read, and / or executed by a computer.

[0132] The program code can be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such processors can be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Therefore, as used herein, the term "processor" may refer to any of the foregoing structures, any combination of the foregoing structures, or any other structure or apparatus suitable for implementing the techniques described herein.

[0133] The illustrative aspects of this disclosure include:

[0134] Aspect 1: A method of processing at least one command, comprising: receiving one or more commands by a graphics processing unit (GPU), the one or more commands including one or more verification signatures generated using a processor, each of the one or more verification signatures including a first value generated based on the one or more commands; generating one or more additional verification signatures associated with the one or more commands by the GPU, wherein each of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determining the validity of the one or more commands by the GPU based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

[0135] Aspect 2: According to the method of aspect 1, wherein determining the validity of the one or more commands includes: determining that the first value associated with the one or more verification signatures matches a second value associated with the one or more additional verification signatures; and determining that the one or more commands are valid.

[0136] Aspect 3: According to the method of aspect 2, wherein determining that the one or more commands are valid results in at least one of the following: determining that the one or more commands are authorized to be executed by the GPU, determining the integrity of the one or more commands, and determining that the one or more commands do not include unauthorized modifications.

[0137] Aspect 4: The method according to any one of Aspects 2 or 3 further includes: authorizing the execution of the one or more commands at the GPU based on the fact that the one or more commands are valid.

[0138] Aspect 5: According to the method of aspect 1, wherein determining the validity of the one or more commands includes: determining that the first value associated with the one or more verification signatures does not match the second value associated with the one or more additional verification signatures; and determining that the one or more commands are invalid.

[0139] Aspect 6: According to the method of aspect 5, wherein determining that the one or more commands are invalid results in at least one of the following: determining that the one or more commands are not authorized to be executed by the GPU, and determining that the one or more commands include one or more unauthorized modifications.

[0140] Aspect 7: The method according to any one of Aspects 5 or 6 further includes: preventing at least one of the following based on the invalidity of the one or more commands: the execution of the one or more commands at the GPU, and the completion of the current execution of the one or more commands at the GPU.

[0141] Aspect 8: The method according to any one of Aspects 1 to 7, wherein the one or more commands specify one or more operations to be performed by the GPU, and wherein the validity of the one or more commands is determined during runtime execution of at least one of the one or more commands and the software application associated with the one or more commands.

[0142] Aspect 9: The method according to any one of Aspects 1 to 8, wherein at least one of the first value and the second value is generated based on one or more characteristics of the one or more commands, the one or more characteristics including at least one of the following: the number of commands, the number of commands of one or more types, the content of at least one of the one or more commands, and one or more indirect pointers included in the one or more commands, the one or more indirect pointers including one or more references to one or more additional commands.

[0143] Aspect 10: The method according to any one of Aspects 1 to 9, wherein the one or more verification signatures and the first value are generated by at least one of a user space device driver and a kernel space driver, and wherein the one or more additional verification signatures and the second value are generated by at least one of: a command processor associated with the GPU, a shader processor associated with the GPU, and a processor authorized to create command streams and manipulate at least one operation of the command streams.

[0144] Aspect 11: According to the method of aspect 10, the validity of the one or more commands is determined by at least one of the command processor and the shader processor.

[0145] Aspect 12: The method according to any one of aspects 1 to 11, wherein the one or more commands include at least one of the following: a command stream, a shader program, a command referencing the shader program, and one or more pointers to one or more locations in memory associated with the one or more commands.

[0146] Aspect 13: The method according to any one of Aspects 1 to 12, wherein the validity of the one or more commands is determined during runtime execution of the software application associated with the one or more commands and prior to at least one of the execution of the one or more commands and the completion of one or more operations associated with the one or more commands.

[0147] Aspect 14: The method according to any one of Aspects 1 to 13, wherein the one or more commands include a command stream comprising a plurality of commands, and the one or more verification signatures include at least one of a command and an instruction indicating that execution of the one or more commands should be rejected when the one or more verification signatures are determined to be invalid.

[0148] Aspect 15: An apparatus for processing at least one command, comprising: a memory; and one or more processors coupled to the memory, the one or more processors being configured to: receive one or more commands via a graphics processing unit (GPU), the one or more commands including one or more verification signatures generated using the processor, each of the one or more verification signatures including a first value generated based on the one or more commands; generate one or more additional verification signatures associated with the one or more commands via the GPU, wherein each of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determine the validity of the one or more commands via the GPU based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

[0149] Aspect 16: The apparatus according to aspect 15, wherein determining the validity of the one or more commands comprises: determining that a first value associated with the one or more verification signatures matches a second value associated with the one or more additional verification signatures; and determining that the one or more commands are valid.

[0150] Aspect 17: The apparatus according to aspect 16, wherein determining that the one or more commands are valid includes at least one of the following: determining that the one or more commands are authorized to be executed by the GPU, determining the integrity of the one or more commands, and determining that the one or more commands do not include unauthorized modifications.

[0151] Aspect 18: In the apparatus according to any one of Aspects 16 or 17, the one or more processors are configured to authorize the execution of the one or more commands at the GPU based on the fact that the one or more commands are valid.

[0152] Aspect 19: The apparatus according to aspect 15, wherein determining the validity of the one or more commands comprises: determining that the first value associated with the one or more verification signatures does not match the second value associated with the one or more additional verification signatures; and determining that the one or more commands are invalid.

[0153] Aspect 20: The apparatus according to aspect 19, wherein determining that the one or more commands are invalid includes at least one of the following: determining that the one or more commands are not authorized to be executed by the GPU, and determining that the one or more commands include one or more unauthorized modifications.

[0154] Aspect 21: In the apparatus according to any one of Aspects 19 or 20, the one or more processors are configured to prevent at least one of the following based on the invalidity of the one or more commands: the execution of the one or more commands at the GPU, and the completion of the current execution of the one or more commands at the GPU.

[0155] Aspect 22: An apparatus according to any one of aspects 15 to 21, wherein the one or more commands specify one or more operations to be performed by the GPU, and wherein the validity of the one or more commands is determined during runtime execution of at least one of the one or more commands and a software application associated with the one or more commands.

[0156] Aspect 23: The apparatus according to any one of aspects 15 to 22, wherein at least one of the first value and the second value is generated based on one or more characteristics of the one or more commands, the one or more characteristics including at least one of the following: the number of commands, the number of commands of one or more types, the content of at least one of the one or more commands, and one or more indirect pointers included in the one or more commands, the one or more indirect pointers including one or more references to one or more additional commands.

[0157] Aspect 24: An apparatus according to any one of aspects 15 to 23, wherein the one or more verification signatures and the first value are generated by at least one of: a user space device driver, a kernel space driver, and a processor authorized to create command streams and manipulate at least one operation in the command streams, and wherein the one or more additional verification signatures and the second value are generated by at least one of: a command processor associated with the GPU and a shader processor associated with the GPU.

[0158] Aspect 25: The apparatus according to aspect 24, wherein the validity of the one or more commands is determined by at least one of the command processor and the shader processor.

[0159] Aspect 26: An apparatus according to any one of aspects 15 to 25, wherein the one or more commands include at least one of the following: a command stream, a shader program, a command referencing the shader program, and one or more pointers to one or more locations in memory associated with the one or more commands.

[0160] Aspect 27: The apparatus according to any one of aspects 15 to 26, wherein the validity of the one or more commands is determined during the runtime execution of the software application associated with the one or more commands and prior to at least one of the execution of the one or more commands and the completion of one or more operations associated with the one or more commands.

[0161] Aspect 28: The apparatus according to any one of aspects 15 to 27, wherein the apparatus is a mobile device.

[0162] Aspect 29: The apparatus according to any one of aspects 15 to 28 includes the GPU and the display device.

[0163] Aspect 30: A non-transitory computer-readable medium having the instructions stored thereon, wherein when executed by one or more processors, the one or more processors cause the one or more processors to perform any one of aspects 1 to 29.

[0164] Aspect 31: An apparatus for processing at least one command, comprising one or more units for performing operations according to any one of aspects 1 to 29.

Claims

1. A method for processing at least one command, comprising: The graphics processing unit (GPU) receives multiple commands generated by an additional processor and a first verification signature, the multiple commands and the first verification signature being stored in a command buffer, the first verification signature being stored in the command buffer at a location calculated based on the multiple commands to obscure the location and prevent it from being identified, the first verification signature including a first value for verifying the integrity of the multiple commands, wherein the first value is generated based on a combination of the multiple commands; The GPU generates a second verification signature associated with the plurality of commands, wherein the second verification signature includes a second value generated by the GPU based on a combination of the plurality of commands; The validity of the plurality of commands is determined by the GPU based on a comparison of the first verification signature and the second verification signature, wherein the plurality of commands are determined to be valid if the first value associated with the first verification signature and the second value associated with the second verification signature match; and The GPU authorizes the execution of the plurality of commands at the GPU based on the determination that the plurality of commands are valid.

2. The method according to claim 1, wherein, If the first value associated with the first verification signature and the second value associated with the second verification signature do not match, then the plurality of commands are determined to be invalid; and Based on the fact that the plurality of commands are invalid, at least one of the following is prevented: the execution of the plurality of commands at the GPU, and the completion of the current execution of the plurality of commands at the GPU.

3. The method according to claim 1, wherein, The plurality of commands specify one or more operations to be performed by the GPU, and wherein the validity of the plurality of commands is determined during runtime execution of at least one of the plurality of commands and the software application associated with the plurality of commands.

4. The method according to claim 1, wherein, At least one of the first value and the second value is generated based on one or more characteristics of the plurality of commands, the one or more characteristics including at least one of the following: the number of commands, the number of commands of one or more types, the content of at least one of the plurality of commands, and one or more indirect pointers included in the plurality of commands, the one or more indirect pointers including one or more references to one or more additional commands.

5. The method according to claim 1, wherein, The first verification signature and the first value are generated by at least one of a user-space device driver and a kernel-space driver, and the second verification signature and the second value are generated by at least one of: a command processor associated with the GPU, a shader processor associated with the GPU, and a processor authorized to create command streams and manipulate at least one operation in the command streams.

6. The method according to claim 5, wherein, The validity of the plurality of commands is determined by at least one of the command processor and the shader processor.

7. The method according to claim 1, wherein, The plurality of commands includes at least one of the following: a command stream, a shader program, a command referencing the shader program, and one or more pointers to one or more locations in memory associated with the plurality of commands.

8. The method according to claim 1, wherein, The validity of the plurality of commands is determined during the runtime execution of the software application associated with the plurality of commands and prior to at least one of the execution of the plurality of commands and the completion of one or more operations associated with the plurality of commands.

9. An apparatus for processing at least one command, comprising: Memory; as well as One or more processors coupled to the memory, the one or more processors being configured to: The graphics processing unit (GPU) receives multiple commands generated by an additional processor and a first verification signature, the multiple commands and the first verification signature being stored in a command buffer, the first verification signature being stored in the command buffer at a location calculated based on the multiple commands to obscure the location and prevent it from being identified, the first verification signature including a first value for verifying the integrity of the multiple commands, wherein the first value is generated based on a combination of the multiple commands; The GPU generates a second verification signature associated with the plurality of commands, wherein the second verification signature includes a second value generated by the GPU based on a combination of the plurality of commands; The validity of the plurality of commands is determined by the GPU based on a comparison of the first verification signature and the second verification signature, wherein the plurality of commands are determined to be valid if the first value associated with the first verification signature and the second value associated with the second verification signature match; and The GPU authorizes the execution of the plurality of commands at the GPU based on the determination that the plurality of commands are valid.

10. The apparatus according to claim 9, wherein, If the first value associated with the first verification signature and the second value associated with the second verification signature do not match, the plurality of commands are determined to be invalid, wherein the one or more processors are configured to: Based on the fact that the plurality of commands are invalid, at least one of the following is prevented: the execution of the plurality of commands at the GPU, and the completion of the current execution of the plurality of commands at the GPU.

11. The apparatus according to claim 9, wherein, The plurality of commands specify one or more operations to be performed by the GPU, and wherein the validity of the plurality of commands is determined during runtime execution of at least one of the plurality of commands and the software application associated with the plurality of commands.

12. The apparatus according to claim 9, wherein, At least one of the first value and the second value is generated based on one or more characteristics of the plurality of commands, the one or more characteristics including at least one of the following: the number of commands, the number of commands of one or more types, the content of at least one of the plurality of commands, and one or more indirect pointers included in the plurality of commands, the one or more indirect pointers including one or more references to one or more additional commands.

13. The apparatus according to claim 9, wherein, The first verification signature and the first value are generated by at least one of the following: a user space device driver, a kernel space driver, and a processor authorized to create command streams and manipulate at least one operation in the command streams, and wherein the second verification signature and the second value are generated by at least one of the following: a command processor associated with the GPU, and a shader processor associated with the GPU.

14. The apparatus according to claim 13, wherein, The validity of the plurality of commands is determined by at least one of the command processor and the shader processor.

15. The apparatus according to claim 9, wherein, The plurality of commands includes at least one of the following: a command stream, a shader program, a command referencing the shader program, and one or more pointers to one or more locations in memory associated with the plurality of commands.

16. The apparatus according to claim 9, wherein, The validity of the plurality of commands is determined during the runtime execution of the software application associated with the plurality of commands and prior to at least one of the execution of the plurality of commands and the completion of one or more operations associated with the plurality of commands.

17. The apparatus according to claim 9, wherein, The device is a mobile device.

18. The apparatus of claim 9, comprising the GPU and the display device.

19. A non-transitory computer-readable medium having instructions stored thereon, the instructions causing the one or more processors, when executed, to perform the following operations: The graphics processing unit (GPU) receives multiple commands generated using a separate processor and a first verification signature. The multiple commands and the first verification signature are stored in a command buffer. The first verification signature is stored in the command buffer at a location calculated based on the multiple commands to obscure the location and prevent it from being identified. The first verification signature includes a first value for verifying the integrity of the multiple commands. The first value is generated based on a combination of the multiple commands; The GPU generates a second verification signature associated with the plurality of commands, wherein the second verification signature includes a second value generated by the GPU based on a combination of the plurality of commands; The validity of the plurality of commands is determined by the GPU based on a comparison of the first verification signature and the second verification signature, wherein the plurality of commands are determined to be valid if the first value associated with the first verification signature and the second value associated with the second verification signature match; and The GPU authorizes the execution of the plurality of commands at the GPU based on the determination that the plurality of commands are valid.

20. The non-transitory computer-readable medium according to claim 19, wherein, If the first value associated with the first verification signature and the second value associated with the second verification signature do not match, the plurality of commands are determined to be invalid, wherein the instructions, when executed by the one or more processors, cause the one or more processors to perform the following operations: Based on the fact that the plurality of commands are invalid, at least one of the following is prevented: the execution of the plurality of commands at the GPU, and the completion of the current execution of the plurality of commands at the GPU.

21. The non-transitory computer-readable medium according to claim 19, wherein, The plurality of commands specify one or more operations to be performed by the GPU, and wherein the validity of the plurality of commands is determined during runtime execution of at least one of the plurality of commands and the software application associated with the plurality of commands.

22. The non-transitory computer-readable medium according to claim 19, wherein, At least one of the first value and the second value is generated based on one or more characteristics of the plurality of commands, the one or more characteristics including at least one of the following: the number of commands, the number of commands of one or more types, the content of at least one of the plurality of commands, and one or more indirect pointers included in the plurality of commands, the one or more indirect pointers including one or more references to one or more additional commands.

23. The non-transitory computer-readable medium according to claim 19, wherein, The first verification signature and the first value are generated by at least one of a user-space device driver and a kernel-space driver, and the second verification signature and the second value are generated by at least one of: a command processor associated with the GPU, a shader processor associated with the GPU, and a processor authorized to create command streams and manipulate at least one operation in the command streams.

24. The non-transitory computer-readable medium according to claim 23, wherein, The validity of the plurality of commands is determined by at least one of the command processor and the shader processor.

25. The non-transitory computer-readable medium according to claim 19, wherein, The plurality of commands includes at least one of the following: a command stream, a shader program, a command referencing the shader program, and one or more pointers to one or more locations in memory associated with the plurality of commands.

26. The non-transitory computer-readable medium according to claim 19, wherein, The validity of the plurality of commands is determined during the runtime execution of the software application associated with the plurality of commands and prior to at least one of the execution of the plurality of commands and the completion of one or more operations associated with the plurality of commands.

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