CIM cell circuit and CIM bitcell array circuit employing capacitive storage circuit

Abstract

A CIM bitcell circuit that employs a capacitive storage circuit to store binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bitcell circuit, thereby reducing the area increase caused by adding a CIM bitcell array circuit to an IC. The CIM bitcell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage that indicates a binary product resulting from a logic AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit can include a capacitor and a read access switch or transistor. The CIM bitcell circuit includes a write access switch for coupling a write bit voltage to the capacitive storage circuit. In a CIM bitcell array circuit, the product voltages are summed in a MAC operation.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 067,205, filed October 9, 2020, entitled “COMPUTE-IN-MEMORY (CIM) CELLCIRCUITS EMPLOYING CAPACITIVE STORAGE CIRCUITS FOR REDUCED AREA AND CIM BITCELL ARRAY CIRCUITS”, which is incorporated herein by reference in its entirety. Technical Field

[0003] The field of this disclosure generally relates to compute-in-memory (CIM) arrays in circuits used for high-speed parallel data processing, such as neural networks. Background Technology

[0004] Machine learning is an example of artificial intelligence (AI). In the initial learning phase, a computer configured with machine learning receives a set of known input data and performs an evaluation of that input data. The evaluation of the input data can include thousands of computations, where individual inputs are weighted based on weight data stored in the computer's memory. Indications of the correctness of the evaluation are provided as feedback, and the computer modifies the stored weight data in response to this feedback. The computer uses the modified weight data to evaluate new data. The more feedback received, the more accurate the evaluation becomes.

[0005] In a conventional computer, each computation requires transferring input and weight data from memory, and then generating output data that is transferred back to memory. When a computer attempts to perform many computations in parallel, data transfer bottlenecks between the processing circuitry and memory can cause data shortages in the processing circuitry, which prolongs execution time and increases power consumption.

[0006] In an alternative approach, dedicated processing circuitry in a computer can perform numerous multiplication and accumulation operations in parallel. These operations can be efficiently implemented using a neural network framework composed of arrays of nodes organized in a structure similar to brain synapses. Each of these processing nodes performs a multiplication-accumulation (MAC) operation, where each input is multiplied by its corresponding weight data and the resulting products are summed. Figure 1 This is a diagram of node 100 of a neural network configured to perform MAC operations. Node 100 receives a set of inputs X0-X... M Each input is multiplied by a weight value W0-W M One corresponding to each of the following. Weight values ​​W0-W MBased on feedback from previous calculations, and over time, the accuracy of calculations with respect to specific types of input data is improved. The product of multiplications is the corresponding product P0-P. M Product P0-P M The sums are added together to generate a total sum SUM, and node 100 generates the output OUT of the function AF (e.g., activation function) as the sum SUM.

[0007] Computation in Memory (CIM) arrays have been developed to implement nodes in neural network frameworks that perform MAC operations on a single binary number and reduce data transfer bottlenecks, resulting in faster result generation. A CIM array stores bits of binary weight data within its bit cells and also performs multiplication operations between the weight data and the input data. Multiplication of a single binary value can be implemented as a logical AND operation (e.g., AND or Not AND (NAND)). Each CIM bit cell includes circuitry for storing the weight data bits and performing the multiplication. When a neural network incorporating a CIM array is used in processing circuitry to reduce data bottlenecks, the increase in processing speed comes at the cost of increased integrated circuit (IC) area occupied by the CIM bit cell circuitry. Summary of the Invention

[0008] The aspects disclosed herein include computation-in-memory (CIM) bit cell circuits employing capacitive storage circuitry to reduce area. CIM bit cell array circuits employing CIM bit cell circuitry and methods for operating such CIM bit cell array circuits are also disclosed. Compared to individual computations performing MAC operations in a conventional processor, parallel execution of multiple multiply-accumulate (MAC) operations in a neural network using CIM bit cell array circuitry reduces execution time; however, the area occupied by the CIM bit cell array circuitry increases the size of the integrated circuit (IC). Six-transistor (6T) static random access memory (SRAM) bit cell circuitry has previously been used in CIM bit cell circuitry. In an exemplary aspect, a CIM bit cell circuitry employing capacitive storage circuitry to store binary weight data as a voltage occupies half or less of the area of ​​a 6T SRAM CIM bit cell circuitry, thereby reducing the area increase caused by adding CIM bit cell array circuitry to the IC. The capacitive storage circuitry is configured to store binary weight data in a capacitor and generate a product voltage indicating the binary product produced by a logical AND-based operation of the stored binary weight data and an activation signal. The CIM bit cell circuitry includes a write access switch configured to couple a write bit voltage to a capacitive storage circuit. The capacitive storage circuitry is configured to store binary weighted data as charge based on the write bit voltage and generate a product voltage at the read bit output based on the stored binary weighted data and an activation signal. In this example, the capacitive storage circuitry may include a capacitor and a read access switch or transistor.

[0009] In this regard, in one aspect, a CIM bit cell circuit is disclosed. The CIM bit cell circuit includes a write access switch. The write access switch includes an input terminal coupled to a write bit input. The write access switch also includes a control terminal coupled to a write word input. The write access switch also includes an output terminal. The write access switch is configured to couple the write bit input to the output terminal in response to a write word voltage supplied to the write word input. The CIM bit cell circuit also includes a capacitive storage circuit. The capacitive storage circuit includes a first port coupled to the output terminal of the write access switch. The capacitive storage circuit also includes a second port coupled to a read bit output. The capacitive storage circuit is configured to store weight data based on a write bit voltage supplied to the write bit input in response to a write word voltage supplied to the write word input. The capacitive storage circuit is also configured to generate a product voltage on the read bit output based on an activation signal and the stored weight data.

[0010] In another aspect, a CIM bit cell array circuit is disclosed. The CIM bit cell array circuit includes an array of CIM bit cell circuits. The CIM bit cell circuit array further includes multiple rows of CIM bit cell circuits and multiple columns of CIM bit cell circuits. Each row includes a corresponding activation line and a corresponding write word line, the corresponding activation line being coupled to the activation input of each CIM bit cell circuit in the row, and the corresponding write word line being coupled to the write word input of each CIM bit cell circuit in the row. Each column includes a corresponding write bit line and a corresponding read bit line, the corresponding write bit line being coupled to the write bit input of each CIM bit cell circuit in the column, and the corresponding read bit line being coupled to the read bit output of each CIM bit cell circuit in the column. Each CIM bit cell circuit includes a write access switch. The write access switch includes an input terminal coupled to the write bit input. The write access switch also includes a control terminal coupled to the write word input. The write access switch also includes an output terminal. Each CIM bit cell circuit also includes capacitive storage circuitry. The capacitive storage circuit includes a first port coupled to the output terminal of a write access switch. The capacitive storage circuit also includes a second port. The capacitive storage circuit is configured to store weighted data based on a write bit voltage provided on the write bit line in response to a write word voltage provided to the write word line. The capacitive storage circuit is also configured to generate a product voltage on the read bit output based on an activation signal on the activation line and the stored weighted data. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a processing node in a neural network used to perform the multiply-accumulate (MAC) operation;

[0012] Figure 2A This is a schematic diagram of an exemplary compute in memory (CIM) bit cell circuit in a three-transistor (3T) memory. The CIM bit cell circuit includes an N-type metal-oxide-semiconductor (MOS) field-effect transistor (MOSFET) and an NMOS read access transistor in a capacitive storage circuit, and generates a logical product (AND-based operation) of input data bits and weighted data bits stored in the capacitive storage circuit.

[0013] Figure 2B It is shown Figure 2A The truth table of the logical multiplication (based on AND) operation of the binary weight data and activation signal stored in the 3T CIM bit cell circuit;

[0014] Figure 3This is a schematic diagram of an exemplary 3T CIM bit cell circuit, which includes a P-type MOS (PMOS) FET (MOSFET) and a PMOS read access transistor circuit in a capacitive storage circuit.

[0015] Figure 4 This is a schematic diagram of an exemplary dual-transistor (2T) single-capacitor (1C) (2T1C) CIM bit cell circuit, which includes a parallel-plate capacitor and an NMOS read access transistor in a capacitive storage circuit.

[0016] Figure 5 This is a schematic diagram of an exemplary 2T1C CIM bit cell circuit, which includes a parallel-plate capacitor and a PMOS read access transistor in a capacitive storage circuit.

[0017] Figure 6 This is a schematic diagram of a 2×2 array of multiple 3T CIM bit cell circuits in Figure 2, and a summing circuit is included in each column of the 2×2 array;

[0018] Figure 7A This is a schematic diagram of an exemplary 2T CIM bit cell circuit based on a dynamic random access memory (DRAM) bit circuit, which includes a P-type MOSFET and a PMOS read access transistor in a capacitive storage circuit.

[0019] Figure 7B It is shown Figure 7A The truth table for the operation of the 2T CIM bit cell circuit;

[0020] Figure 8A This is a schematic diagram of an exemplary 2T CIM bit cell circuit, which includes an N-type MOSFET and an NMOS read access transistor in a capacitive storage circuit.

[0021] Figure 8B It is shown Figure 8A The truth table for the operation of the 2T CIM bit cell circuit;

[0022] Figure 9 Figure 8 shows a schematic diagram of a 2×2 array of multiple 2T CIM bit cell circuits, each of which includes a summing circuit in each column of the 2×2 array.

[0023] Figure 10 It integrates, for example Figure 6 and Figure 9 The block diagram of the integrated circuit for the CIM bit cell array circuit shown; and

[0024] Figure 11 This is a block diagram of an exemplary processor-based system, which includes components as disclosed in any aspect herein. Figure 5 The CIM bit cell array circuit shown in Figures 7-8 includes a capacitive storage circuit for each CIM bit cell, configured to store weight data and generate a logical product (AND-based operation) of the input data bits and the stored weight data. Figure 6 and Figure 9 As shown in any of them. Detailed Implementation

[0025] Several exemplary aspects of this disclosure are now described with reference to the accompanying drawings. The term “exemplary” as used herein means “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to the others.

[0026] The aspects disclosed herein include computation-in-memory (CIM) bit cell circuits employing capacitive storage circuitry to reduce area. CIM bit cell array circuits employing CIM bit cell circuitry and methods for operating such CIM bit cell array circuits are also disclosed. Compared to individual computations performing MAC operations in a conventional processor, parallel execution of multiple multiply-accumulate (MAC) operations in a neural network using CIM bit cell array circuitry reduces execution time; however, the area occupied by the CIM bit cell array circuitry increases the size of the integrated circuit (IC). Six-transistor (6T) static random access memory (SRAM) bit cell circuitry has previously been used in CIM bit cell circuitry. In an exemplary aspect, a CIM bit cell circuitry employing capacitive storage circuitry to store binary weight data as a voltage occupies half or less of the area of ​​a 6T SRAM CIM bit cell circuitry, thereby reducing the area increase caused by adding CIM bit cell array circuitry to the IC. The capacitive storage circuitry is configured to store binary weight data in a capacitor and generate a product voltage indicating the binary product produced by a logical AND-based operation of the stored binary weight data and an activation signal. The CIM bit cell circuitry includes a write access switch configured to couple a write bit voltage to a capacitive storage circuit. The capacitive storage circuitry is configured to store binary weighted data as charge based on the write bit voltage and generate a product voltage at the read bit output based on the stored binary weighted data and an activation signal. In this example, the capacitive storage circuitry may include a capacitor and a read access switch or transistor.

[0027] Figure 2AThis is a schematic diagram of a first exemplary CIM bit cell circuit 200 for MAC operations. The CIM bit cell circuit 200 employs capacitive charge-based data storage and performs binary multiplication in half or less the area of ​​a 6T SRAM-based CIM bit cell. The CIM bit cell circuit 200 includes a write access switch 202 controlled to program a capacitive storage circuit 204 with binary weight data 206. The CIM bit cell circuit 200 receives an activation signal 208 at an activation input 210 to control the generation of product data 212. Product data 212 is the result of a binary multiplication (e.g., a logical AND-based operation) of the activation signal 208 and the binary weight data 206. Product data 212 is indicated by a product voltage 214 generated on a read bit output 216.

[0028] The capacitive storage circuit 204 stores binary weighted data 206 as charge based on a write bit voltage 218. The write bit voltage 218 is provided at the write bit input 220 and, in response to a write word voltage 222 received at the write word input 224, is provided to the capacitive storage circuit 204 via a write access switch 202. In this respect, the write access switch 202 includes an input terminal 226 coupled to the write bit input 220, a control terminal 228 coupled to the write word input 224, and an output terminal 230 coupled to a first port 232 of the capacitive storage circuit 204. The input terminal 226 is electrically coupled to the output terminal 230 to provide the write bit voltage 218 to the first port 232 of the capacitive storage circuit 204 in response to the write word voltage 222 provided at the control terminal 228.

[0029] In one example, the write bit voltage 218 could be the power supply voltage V that indicates the binary weight data 206 is a binary "1". DD Alternatively, it could be the ground voltage V indicating that the binary weight data 206 is a binary "0". SS Alternatively, the ground voltage V SS It can indicate a binary "1", and the power supply voltage V DD The binary value "0" can be indicated. The binary value of the activation signal 208 on the activation input 210 can be indicated in the same way as the binary weight data 206. The CIM bit cell circuit 200 generates a product voltage 214 to indicate the binary product of the logical AND operation of the binary weight data 206 and the activation signal 208. The capacitive storage circuit 204 generates the product voltage 214 through a second port 234 coupled to the read bit output 216. The CIM bit cell circuit 200 can also be configured to generate the product voltage 214 as the product of a logical AND operation.

[0030] exist Figure 2AIn the example, the write access switch 202 is an N-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (N-type MOSFET) 236. The source / drain 238 of the NFET 236 is the input terminal 226 of the write access switch 202, and the drain / source 240 of the NFET 236 is the output terminal 230. The gate 242 of the NFET 236 is the control terminal 228. In an alternative example, the write access switch 202 may be implemented as a P-type MOSFET (PFET). Generally, depending on the implementation, the source / drain mentioned herein may be used as either the source or drain of the FET, and drain / source refers to the other of the drain or source of the FET. The access switch 202 may also be implemented as a bipolar junction transistor (BJT), a microelectromechanical system (MEMS) device, or other switching technology. In such an alternative, the input terminal 226, output terminal 230, and control terminal 228 of the write access switch 202 are implemented by appropriate terminals of such a device, and the control terminal 228 can be activated by different signals, voltages, and / or currents to electrically couple the write bit input 220 to the first port 232 of the capacitive storage circuit 204.

[0031] The capacitive storage circuit 204 includes a capacitor 244 for storing binary weighted data 206 and a read access switch 246 for generating a product voltage 214. The capacitor 244 includes a first terminal 248 coupled to a first port 232. The capacitor 244 also includes a second terminal 250 coupled to an input terminal 252 of the read access switch 246. The output terminal 254 of the read access switch 246 is coupled to a second port 234 of the capacitive storage circuit 204, and the control terminal 256 of the read access switch 246 is coupled to an activation input 210 of the CIM bit cell circuit 200.

[0032] exist Figure 2A In the example, NFET 258 is configured as capacitor 244. The gate 260 of NFET 258 is the first terminal 248 of capacitor 244. The source / drain 262 and drain / source 264 of NFET 258 are electrically shorted to each other and are also coupled to the second terminal 250 of capacitor 244.

[0033] To write binary weighted data 206 for MAC operations into the CIM bit cell circuit 200, the write access switch 202 is turned on by the write word voltage 222 supplied to the write word input 224, and the activated write access switch 202 passes the write bit voltage 218 supplied to the write bit input 220 to the gate 260. In the CIM bit cell circuit 200, the write word voltage 222 is responsive to the power supply voltage V. DDThe NFET 236 of the write access switch 202 is turned on (e.g., to conduct between source / drain 238 and drain / source 240). The write bit voltage 218 charges the gate 260 to a voltage level indicating that the binary weighted data 206 is "0" or "1". The charge on the gate 260 is reflected at the second terminal 250 of the capacitor 244. In order to read the product data 212 from the CIM bit cell circuit 200, the activation signal 208 provided on the activation input 210 turns on the read access switch 246, and the product voltage 214 is generated on the read bit output 216. In response to the write word voltage 222 being the supply voltage V... DD The read access switch 246 is turned on (e.g., to conduct between source / drain 238 and drain / source 240). At this point, the read access switch 246 can be an NFET 266 or other type of electrical switch. After reading the product data 212 from the capacitive storage circuit 204, the charge representing the binary weight data 206 remains on the capacitor 244. Therefore, the read operation for reading the product data 212 is non-destructive.

[0034] The NFET 258, which serves as capacitor 244, is charged based on the write bit voltage 218, but leakage current in the NFET 258 allows the charge to dissipate slowly over time. Therefore, in order to maintain the charge on the NFET 258 to avoid losing the binary weight data 206 written to the CIM bit cell circuit 200, the charge on the capacitor 244 can be dynamically (e.g., periodically or occasionally) refreshed by providing the same write bit voltage 218 to the write bit input 220 and activating the write access switch 202 by providing the write word voltage 222 to the write word input 224.

[0035] Furthermore, the read access switch 246 can be activated to read the product data 212 on the read bit output 216 simultaneously (e.g., at the same time) as the charge on the capacitor 244 is refreshed. In this respect, the refresh operation does not conflict with the reading of the product data 212 from the CIM bit cell circuit 200, eliminating the need for control logic and the possibility of processing delays due to conflicts.

[0036] Refer to truth table 270. Figure 2B As shown, the product data 212 will only have a binary value of "1" if both the binary weight data 206 and the activation signal 208 have a binary value of "1". Otherwise, the product data 212 will have a binary value of "0". Therefore, the CIM bit cell circuit 200 performs a binary multiplication of the stored binary weight data 206 and the activation signal 208 to produce the product data 212.

[0037] The write access switch 202 is also implemented by an NFET 266. Therefore, the CIM bit cell circuit 200 comprises only three (3) transistors (i.e., the write access switch 202, capacitor 244, and read access switch 246), all of which are NFETs in this example. The three NFETs of the CIM bit cell circuit 200 occupy approximately half the area of ​​the 6T SRAM bit cell circuit previously used in CIM circuits. Due to charge leakage stored in capacitor 244, the capacitively stored binary weight data 206 requires periodic refreshing, but the 50% area reduction of the SRAM-based circuit is an acceptable trade-off for IC designers constantly seeking to reduce IC area. Compared to neural network processing circuits formed by 6T SRAM bit cell circuits, the use of… Figure 2A The use of multiple CIM bit cell circuits 200 as an IC for neural network processing circuits will result in a smaller size increase, which reduces the cost of the IC.

[0038] Furthermore, the CIM bit cell circuit 200 (where the electrical components are MOSFETs) can be manufactured without the need for a special process that would require embedded dynamic random access memory (DRAM) on an IC with MOSFET-based logic circuitry. Thus, a smaller area CIM processing circuit is provided without additional processing steps.

[0039] As mentioned above, Figure 2A The write access switch 202 and the capacitive storage circuit 204 both use N-type MOSFETs (i.e., NFET 236 and NFET 258, respectively). Figure 3 A schematic diagram of an alternative CIM bit cell circuit 300 is shown. The CIM bit cell circuit 300 employs capacitive charge-based data storage and performs binary multiplication in half or less the area of ​​a 6T SRAM-based CIM bit cell. The CIM bit cell circuit 300 includes a write access switch 302 for controlling the programming of the capacitive storage circuit 304. The CIM bit cell circuit 300 is operationally similar to... Figure 2A The CIM bit cell circuit 300 is the same as that of the CIM bit cell circuit 200, except that the write word voltage 306 is provided to the write word input 308 to turn on the write access switch 302. In the CIM bit cell circuit 300, the write access switch 302 is a P-type MOSFET (PFET) 310, which is powered by a ground voltage V. SS The write word voltage is 306 for activation, which is related to Figure 2A The power supply voltage V provided to the write word input 224 is... DDConversely, write access switch 302 couples write bit input 312 to a first port 314 of capacitive storage circuit 304 in response to write word voltage 306 on write word input 308. First port 314 of capacitive storage circuit 304 is coupled to a first terminal 316 of PFET 318, which serves as capacitor 320. In capacitive storage circuit 304, the source / drain 322 and drain / source 324 of PFET 318 are coupled to the first terminal 316, and the gate 326 of PFET 318 is coupled to a second terminal 328. Capacitor 320 is electrically charged to store binary weighted data 330 based on write bit voltage 332 provided on write bit input 312.

[0040] In response to the activation signal 338 on the activation input 340, the read access switch 334 in the capacitive storage circuit 304 couples the second terminal 328 of the capacitor 320 to the second port 336 of the capacitive storage circuit 304. The activation input 340 is coupled to the control terminal 342 of the read access switch 334. The second port 336 is further coupled to the read bit output 344. The read access switch 334 is connected to... Figure 2A The NFET 266 corresponds to the NFET 346. The product data 348 generated on the read bit output 344 is the binary result of the logical AND of the binary weight data 330 and the activation signal 338.

[0041] In another example, Figure 4 A schematic diagram of a CIM bit cell circuit 400 is shown. The CIM bit cell circuit 400 employs capacitive charge-based data storage and performs binary multiplication in half or less the area of ​​a 6T SRAM-based CIM bit cell. The CIM bit cell circuit 400 includes a write access switch 402 for controlling the programming of the capacitive storage circuit 404. The operation of the CIM bit cell circuit 400 is related to... Figure 2A The operation is the same as that of the CIM bit cell circuit 200. That is, the CIM bit cell circuit 400 stores binary weight data 406, which is based on the write bit voltage 408 on the write bit input 410 in response to the write word voltage 412 on the write word input 414. In addition, the product data 416 is generated by a logical AND operation between the binary weight data 406 and the activation signal 418 on the activation input 420.

[0042] The CIM bit cell circuit 400 is structurally equivalent to the CIM bit cell circuit 200, except that the capacitive storage circuit 404 is replaced by a capacitor 422. Figure 2AThe NFET 258 is used in the capacitive storage circuit 204. The CIM bit cell circuit 400 is functionally equivalent to the CIM bit cell circuit 200. The capacitor 422 stores the binary weight data 406. The write access switch 402 and the read access switch 424 can be NFETs 426 and 428, respectively, which correspond to... Figure 2A The NFETs 236 and 266 are used in this process. Capacitor 422 can be a parallel-plate capacitor or other types of capacitor formed in a front-end line (FEOL) or back-end line (BEOL) process. Alternatively, the CIM bit cell circuit 400 according to this disclosure can include another capacitor structure besides the parallel-plate capacitor 422.

[0043] In another example, a schematic diagram of the CIM bit unit circuit 500 is shown below. Figure 5 As shown. The CIM bit cell circuit 500 also employs capacitive charge-based data storage in half or less the area of ​​a 6T SRAM-based CIM bit cell. The CIM bit cell circuit 500 includes a write access switch 502 for controlling the programming of the capacitive storage circuit 504. The operation of the CIM bit cell circuit 500 is similar to... Figure 3 The operation is the same as that of the CIM bit cell circuit 300. That is, the CIM bit cell circuit 500 stores binary weight data 506, which is based on the write bit voltage 508 provided on the write bit input 510 in response to the write word voltage 512 provided on the write word input 514. The product data 516 is generated by a logical AND operation between the binary weight data 506 and the activation signal 518 provided on the activation input 520. The CIM bit cell circuit 500 is structurally equivalent to the CIM bit cell circuit 300, except that the capacitive storage circuit 504 is replaced by a capacitor 522. Figure 3 The PFET 318 is used in the capacitive storage circuit 304. The capacitor 522 can be a parallel-plate capacitor formed in a FEOL or BEOL process, or other types of capacitors. Figure 3 Similar to the PFET 310 in the write access switch 302, the write access switch 502 includes a PFET 524, which is activated by a write word voltage 512 (e.g., when the switch is closed), which is the ground voltage V supplied to the write word input 514. SS .

[0044] Figure 6 This is a schematic diagram of the CIM bit cell array circuit (CIM array circuit) 600, which consists of CIM bit cell circuits 602(0,0)-602(1,1) (collectively referred to as CIM bit cell circuit 602). The CIM bit cell circuit 602 in the CIM array circuit 600 is... Figure 2AThe CIM bit unit circuit 200 in the middle, and Figure 2A The labels shown are referenced in all references to the features of the CIM bit cell circuit 602. Therefore, each CIM bit cell circuit 602 includes an activation input 210, a write bit input 220, a write word input 224, and a read bit output 216. Each CIM bit cell circuit 602 stores binary weight data 206, such as... Figure 2A As shown.

[0045] The CIM array circuit 600 includes a row R0 with CIM bit cell circuits 602(0,0) and 602(0,1) and a row R1 with CIM bit cell circuits 602(1,0) and 602(1,1). The CIM array circuit 600 also includes a column C0 with CIM bit cell circuits 602(0,0) and 602(1,0) and a column C1 with CIM bit cell circuits 602(0,1) and 602(1,1). As further described below, in response to a write operation, binary weight data 206 corresponding to each activation signal 208 is stored in the CIM bit cell circuit 602 prior to multiplication. The product data 212 of the multiplication from each CIM bit cell circuit 602 in column C0 or C1 is summed to complete the "accumulation" portion of the MAC operation.

[0046] refer to Figure 6 The structural details of the CIM array circuit 600 are described. Rows R0 and R1 of the CIM array circuit 600 include corresponding activation lines 604(0) and 604(1) and corresponding write word lines 606(0) and 606(1). Activation line 604(0) is coupled to the activation input 210 of each CIM bit cell circuit 602 in row R0, and activation line 604(1) is coupled to the activation input 210 of each CIM bit cell circuit 602 in column R1. Write word line 606(0) is coupled to the write word input 224 of each CIM bit cell circuit 602 in row R0, and write word line 608(1) is coupled to the write word output 224 of each CIM bit cell circuit 602 in column R1.

[0047] Columns C0 and C1 include corresponding write bit lines 608(0) and 608(1) and corresponding read bit lines 610(0) and 610(1). Write bit line 608(0) is coupled to the write bit input 220 of each CIM bit cell circuit 602 in column C0, and write bit line 608(1) is coupled to the write bit input 220 of each CIM bit cell circuit 602 in column C1. Read bit line 610(0) is coupled to the read bit output 216 of each CIM bit cell circuit 602 in column C0, and read bit line 610(1) is coupled to the read bit output 216 of each CIM bit cell circuit 602 in column C1.

[0048] The CIM array circuit 600 includes summing circuits 612(0) and 612(1) respectively coupled to read bit lines 610(0) and 610(1). During a read operation, product data 212 from each CIM bit cell circuit 602 in column C0 is accumulated on read bit line 610(0). Specifically, a product voltage 214 indicating the multiplication result in each of the CIM bit cell circuits 602(0,0) and 602(1,0) is provided to read bit line 610(0). Each CIM bit cell circuit 602 in the column that generates product data 212 as a binary "1" contributes to charging read bit line 610(0), which increases the voltage of read bit line 610(0) as follows. For one of the CIM bit cell circuits 602 in column C0 that generates product data 212 as a binary "1", the voltage on read bit line 610(0) can be determined according to the following equation:

[0049] V RBL =V gg (C gg / (C gg +C RBL )),

[0050] in:

[0051] V RBL =Voltage generated to read bit line 610(0)

[0052] V gg = The voltage across the capacitor (e.g., 244) in the capacitive storage circuit 204 provided by the write bit voltage 218

[0053] C gg = The capacitance of capacitor 244 in capacitive storage circuit 204

[0054] C RBL =Read the capacitor of bit line 610(0)

[0055] The summing circuit 612(0) may include, for example, a sense amplifier or an analog-to-digital converter (ADC), which adjusts according to voltage V. RBL The sum of the number of “1”s charging the read bit line 610(O) in indicator column C0 is 614 (“O”). Similarly, the summing circuit 612(1) generates the sum of the number of “1”s charging the read bit line 610(1) in indicator column C1, 614 (“1”). In this way, the CIM array circuit 600 performs the multiplication and accumulation of the MAC operation of the neural network.

[0056] The capacitance C of capacitor 244 in capacitive storage circuit 204 gg In comparison, the capacitor C of the read bit line 610(0)RBL It is very small. Therefore, charging the read bit line 610(0) to the product voltage 214 does not discharge the capacitor 244, so the binary weight data 206 remains on the capacitor 244 after the product data 212 is read. Therefore, the read operation of the CIM bit cell circuit 602 in the CIM array 600 is called a non-destructive read operation.

[0057] Figure 7 is a schematic diagram of an exemplary CIM bit cell circuit 700 for performing binary multiplication in a MAC operation in a neural network (not shown). The CIM bit cell circuit 700 includes a write access switch 702 for programming a capacitive storage circuit 704 with binary weight data 706. Figure 2A and Figures 3-5 In the example shown, the CIM bit cell circuit 700 receives an activation signal 708 at the activation input 710. The product data 712 of the activation signal 708 and the binary multiplication (e.g., a logical AND operation) of the binary weight data 706 is generated as the product voltage 714 on the read bit output 716.

[0058] In response to a write word voltage 722 on write word input 724, write access switch 702 couples write bit input 718 to a first port 720 of capacitive storage circuit 704. The first port 720 of capacitive storage circuit 704 is coupled to a first terminal 726 of capacitor 728. Capacitor 728 is charged to store binary weighted data 706 based on the write bit voltage 730 provided on write bit input 718.

[0059] The capacitive storage circuit 204 includes both a capacitor 244 and a read / access switch 246. Figure 2A Unlike the CIM bit cell circuit 200, the capacitive storage circuit 704 of the CIM bit cell circuit 700 uses only a capacitor 728, namely an NFET 732. The first terminal 726 of the capacitor 728 is the gate 734 of the NFET 732. The NFET 732 includes source / drain 738A and drain / drain 738B. Here, unlike source / drain 262 and drain / drain 264, where source / drain 738A and drain / drain 738B are coupled together, source / drain 738A is coupled to the activation input 710, and drain / drain 738B is coupled to the read bit output 716. The product data 712 generated on the read bit output 716 is the binary result of the logical AND of binary weight data 706 and the activation signal 708 provided on the activation input 710. Specifically, in response to the binary weight data 706 being a binary "1", in the case of NFET 732, the activation input 710 is coupled to the read bit output 716, and the product data 712 takes the value of the activation signal 708.

[0060] The write access switch 702 in Figure 7 is also an NFET 740. Therefore, with Figure 2A The three-transistor (3T) CIM bit unit circuit 200 or Figure 4 Compared to the CIM bit cell circuit 400 with two transistors (2T) and a single capacitor (1C), the CIM bit cell circuit 700 is capable of performing multiplication operations, such as... Figure 2A The CIM bit cell circuit 200 includes only two transistors (732 and 740). In this respect, the area occupied by the CIM bit cell circuit 700 is less than half the area occupied by the previous CIM bit cell using 6T SRAM. Truth table 750 illustrates the AND-based operations of the CIM bit cell circuit 700, which are related to... Figure 2B The truth table 270 is the same.

[0061] In another example, Figure 8 is a schematic diagram of an exemplary CIM bit cell circuit 800 for binary multiplication, which includes a write access switch 802 for programming a capacitive storage circuit 804 with binary weight data 806 based on a write bit voltage 808 provided at a write bit input 810. Like the CIM bit cell circuit 700 of Figure 7, the CIM bit cell circuit 800 is a 2T circuit. The CIM bit cell circuit 800 receives an activation signal 812 at an activation input 814 to read product data 816. The product data 816 is the product of the activation signal 812 and the binary weight data 806 (e.g., a logical AND operation). The product data 816 is generated as a product voltage 818 at a read bit output 820.

[0062] Compared to the CIM bit cell circuit 700, the write access switch 802 uses a PFET 822 to couple the write bit input 810 to a first port 824 of the capacitive storage circuit 804 in response to a write word voltage 826 on the write word input 828. The first port 824 of the capacitive storage circuit 804 is coupled to a first terminal 830 of a capacitor 832 provided by a PFET 834. The first terminal 830 is the gate 836 of the PFET 834. The capacitor 832 is charged to store binary weighted data 806 based on the write bit voltage 808 provided on the write bit input 810. The write access switch 802 provided by the PFET 822 responds to the write word voltage 826 as a ground voltage V. SS (For example, 0 volts) The write bit input 810 is coupled to the first port 824 of the capacitive storage circuit 804, and the ground voltage is opposite in polarity to the write word voltage 722 provided to the write word input 724 in FIG. 7.

[0063] In addition, in response to the binary weight data 806, the ground voltage V SS In the capacitive storage circuit 804, the PFET 834 couples the activation input 814 to the read bit output 820. At this point, the polarity of the binary weight data 806 stored in the CIM bit cell circuit 800 must be opposite to that of the binary weight data 706 in the CIM bit cell circuit 700 to turn on the PFET 834. Therefore, the binary weight data 806 of the CIM bit cell circuit 800 has the opposite polarity to the binary weight data 706 in Figure 7. The truth table 850 in Figure 8 illustrates the logical AND-based operation of the CIM bit cell circuit 800. The truth table 850 shows that the product data 816 is a logical AND of the activation signal 812, and also shows the reciprocal of the binary weight data 806 (in parentheses). Similar to the CIM bit cell circuit 700, the CIM bit cell circuit 800 occupies less than half the area occupied by the previous CIM bit cell using 6T SRAM.

[0064] Figure 9 This is a schematic diagram of a CIM bit cell array circuit (CIM array circuit) 900 comprising CIM bit cell circuits 902(0,0)-902(1,1) (collectively referred to as CIM bit cell circuits 902). The CIM bit cell circuits 902 in the CIM array circuit 900 are the CIM bit cell circuits 700 shown in Figure 7, and the labels in Figure 7 refer to the features of the CIM bit cell circuits 902. Therefore, each CIM bit cell circuit 902 includes an activation input 710, a write bit input 718, a write word input 724, and a read bit output 716. Each CIM bit cell circuit 902 stores binary weight data 706, as shown in Figure 7.

[0065] The CIM array circuit 900 includes a row R0 with CIM bit cell circuits 902 (0,0) and 902 (0,1) and a row R1 with CIM bit cell circuits 902 (1,0) and 902 (1,1). The CIM array circuit 900 also includes a column C0 with CIM bit cell circuits 902 (0,0) and 902 (1,0) and a column C1 with CIM bit cell circuits 902 (0,1) and 902 (1,1). As further described below, in response to a write operation, binary weight data 706 corresponding to each activation signal 708 is stored in the CIM bit cell circuit 902 prior to multiplication. The product data 712 of the multiplication from each CIM bit cell circuit 902 in column C0 or C1 is summed to complete the "accumulation" portion of the MAC operation.

[0066] Rows R0 and R1 include activation lines 904(0) and 904(1) coupled to the activation input 710 of the CIM bit cell circuit 902 in the corresponding row. Rows R0 and R1 also include write word lines 906(0) and 906(1) coupled to the write word input 724 of the CIM bit cell circuit 902 in the corresponding row. Columns C0 and C1 include write bit lines 908(0) and 908(1) coupled to the write bit input 718 of the CIM bit cell circuit 902 in the corresponding column. Columns C0 and C1 also include read bit lines 910(0) and 910(1) coupled to the read bit output 716 of the CIM bit cell circuit 902 in the corresponding column.

[0067] Write binary weight data 706 into CIM bit unit circuit 902, and write binary weight data 206 as described above. Figure 6 The same as the CIM bit cell circuit 602 in the CIM array circuit 600. However, due to Figure 2A The structural differences between the capacitive storage circuit 204 in Figure 2 and the capacitive memory circuit 704 in Figure 7 are that the operation of reading the product data 712 from the corresponding CIM bit cell circuit 902 is different from reading the CIM bit cell circuit 602 in the CIM array circuit 600.

[0068] Columns C0 and C1 include summing circuits 912(0) and 912(1), which are used to determine how much binary weighted data 706 with a binary value of "1" is being stored in the CIM bit cell circuit 902 of one of the columns C0 and C1 of the CIM array circuit 900. An activation signal 708 is provided on activation line 904(0) to generate a product voltage 714 on the read bit output 716 of a specific one of the CIM bit cell circuits 902. In the case of CIM bit cell circuits 700 and 800, the activation signal 708 is the power supply voltage V. DD or ground voltage V SS And not based on the above regarding Figure 6The charge-sharing equation is discussed. Therefore, a read operation is performed sequentially for each CIM bit cell circuit 902 in, for example, column C0. The summing circuit 912(0) in column C0 senses the product voltage 714 at the time corresponding to each read operation to determine whether the binary weight data 706 stored in the CIM bit cell circuit 902 is a binary "1" or "0", and adds the number of "1s" sensed in that column. Therefore, an additional trade-off for the area reduction provided by the array formed by the CIM bit cell circuits 700 (such as CIM array circuit 900) is that more cycles are required to read the product data 712 from all CIM bit cell circuits 902 in the column, which increases the execution time of the MAC operation. As in CIM array circuit 600, the read operation in CIM array circuit 900 is non-destructive, the binary weight data 706 needs to be refreshed periodically or occasionally, and a particular CIM bit cell circuit 902 can be refreshed at the same time (e.g., simultaneously) as the product data 712 is read in a read operation.

[0069] Figure 10 An exemplary wireless communication device 1000 is shown, including a radio frequency (RF) component 1002, wherein one or more RF components 1002 may be in the form of an IC, and any RF component 1002 may include a CIM bit cell array circuit, such as Figure 6 and Figure 9 As shown in any of them, the CIM bit cell array circuit includes a CIM bit cell circuit according to any aspect disclosed herein, which provides capacitive charge-based data storage and performs binary multiplication in half or less of the area of ​​a 6T SRAM bit cell circuit, such as Figure 2A , Figures 3-5 As shown in any of Figures 7 and 8. As an example, the wireless communication device 1000 may include any of the aforementioned devices or be incorporated into any of the aforementioned devices. Figure 10 As shown, the wireless communication device 1000 includes a transceiver 1004 and a data processor 1006. The data processor 1006 may include memory for storing data and program code. The transceiver 1004 includes a transmitter 1008 and a receiver 1010 supporting bidirectional communication. Typically, the wireless communication device 1000 may include any number of transmitters 1008 and / or receivers 1010 for any number of communication systems and frequency bands. All or part of the transceiver 1004 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0070] Transmitter 1008 or receiver 1010 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, for receiver 1010, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 10 In the wireless communication device 1000, the transmitter 1008 and the receiver 1010 are implemented using a direct conversion architecture.

[0071] In the transmission path, the data processor 1006 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1008. In the exemplary wireless communication device 1000, the data processor 1006 includes digital-to-analog converters (DACs) 1012(1) and 1012(2) for converting the digital signals generated by the data processor 1006 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0072] Within transmitter 1008, low-pass filters 1014(1) and 1014(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1016(1) and 1016(2) amplify the signals from low-pass filters 1014(1) and 1014(2), respectively, and provide I and Q baseband signals. Upconverter 1018 upconverts the I and Q baseband signals using I and Q transmission (TX) local oscillator (LO) signals from TX LO signal generator 1022 via mixers 1020(1) and 1020(2) to provide upconverted signal 1024. Filter 1026 filters upconverted signal 1024 to remove unwanted signals caused by upconversion and noise in the receiving band. Power amplifier (PA) 1028 amplifies the up-converted signal 1024 from filter 1026 to obtain the desired output power level and provides a transmission RF signal. The transmission RF signal is routed through duplexer or switch 1030 and transmitted via antenna 1032.

[0073] In the receiving path, antenna 1032 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1030 and provided to low-noise amplifier (LNA) 1034. Duplexer or switch 1030 is designed to operate at a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1034 and filtered by filter 1036 to obtain the desired RF input signal. Downconversion mixers 1038(1) and 1038(2) mix the output of filter 1036 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1040 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1042(1) and 1042(2) and further filtered by low-pass filters 1044(1) and 1044(2) to obtain I and Q analog input signals, which are provided to data processor 1006. In this example, data processor 1006 includes ADCs 1046(1) and 1046(2) for converting the analog input signals into digital signals for further processing by data processor 1006.

[0074] exist Figure 10 In the wireless communication device 1000, a TX LO signal generator 1022 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1040 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1048 receives timing information from a data processor 1006 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1022. Similarly, an RXILL circuit 1050 receives timing information from a data processor 1006 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1040.

[0075] The wireless communication device 1000 can be located in or integrated into any of the aforementioned processor-based devices, each of which includes a CIM bit cell array circuit, such as... Figure 6 and Figure 9 As shown in any of them, the CIM bit cell array circuit includes a CIM bit cell circuit according to any aspect disclosed herein, which provides capacitive charge-based data storage and performs binary multiplication in half or less of the area of ​​a 6T SRAM bit cell circuit, such as Figure 2A , Figures 3-5As shown in any of Figures 7 and 8. Examples (but not limited to) include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), displays, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multi-rotor helicopters.

[0076] On this point, Figure 11 An example of a processor-based system 1100 is shown, which includes a CIM bit cell array circuit, such as Figure 6 and Figure 9 As shown in any of them, the CIM bit cell array circuit includes a CIM bit cell circuit according to any aspect disclosed herein, which provides capacitive charge-based data storage and performs binary multiplication in half or less of the area of ​​a 6TSRAM bit cell circuit, such as Figure 2A , Figures 3-5 As shown in any of Figures 7 and 8. In this example, the processor-based system 1100 includes one or more central processing unit (CPU) units 1102, which may also be referred to as CPUs or processor cores, each CPU 1102 including one or more processors 1104. The CPU(s) 1102 may have a cache memory 1106 coupled to the processor(s) 1104 for fast access to temporarily stored data. As an example, the processor(s) 1104 may include an SRAM bit cell array according to any aspect disclosed herein, the SRAM bit cell array including a minimized inactive bit cell region, a minimized inactive array region, and gate contacts overlapping with the active region of the memory circuitry to reduce the array length, such as Figure 4 As shown in any of Figures 8. Multiple CPUs 1102 are coupled to system bus 1108 and can interconnect master and slave devices included in the processor-based system 1100. It is well known that the multiple CPUs 1102 communicate with these other devices by exchanging address, control, and data information on system bus 1108. For example, as an example of a slave device, the multiple CPUs 1102 can transmit bus transaction requests to memory controller 1110. Although... Figure 11It is not shown in the figure, but multiple system buses 1108 can be provided, each of which constitutes a different structure.

[0077] Other master and slave devices can be connected to system bus 1108. For example... Figure 11 As shown, as an example, these devices may include a memory system 1112 (which includes a memory controller 1110 and one or more memory arrays 1114), one or more input devices 1116, one or more output devices 1118, one or more network interface devices 1120, and one or more display controllers 1122. Each of the memory system 1112, one or more input devices 1116, one or more output devices 1118, one or more network interface devices 1120, and one or more display controllers 1122 may include CIM bit cell array circuitry, such as... Figure 6 and Figure 9 As shown in any of them, the CIM bit cell array circuit includes a CIM bit cell circuit according to any aspect disclosed herein, which provides capacitive charge-based data storage and performs binary multiplication in half or less of the area of ​​a 6T SRAM bit cell circuit, such as Figure 2A , Figures 3-5 As shown in any of Figures 7 and 8. Multiple input devices 1116 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Multiple output devices 1118 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Multiple network interface devices 1120 may be any device configured to allow data exchange with network 1124. Network 1124 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetexts. TM Networks and the Internet. Multiple network interface devices 1120 can be configured to support any type of communication protocol required.

[0078] The CPU 1102 can also be configured to access the display controller 1122 via the system bus 1108 to control information sent to one or more displays 1126. The display controller 1122 sends information to be displayed to the displays 1126 via one or more video processors 1128, which process the information to be displayed into a format suitable for the displays 1126. The displays 1126 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. The display controller 1122, the displays 1126, and / or the video processors 1128 can include CIM bit cell array circuitry, such as... Figure 6 and Figure 9 As shown in any of them, the CIM bit cell array circuit includes a CIM bit cell circuit according to any aspect disclosed herein, which provides capacitive charge-based data storage and performs binary multiplication in half or less of the area of ​​a 6T SRAM bit cell circuit, such as Figure 2A , Figures 3-5 As shown in any of Figures 7 and 8.

[0079] Those skilled in the art will further recognize that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0080] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0081] The aspects disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0082] It should also be noted that the operational steps described in any exemplary aspect herein are for illustrative and discussion purposes only. The described operations can be performed in many different sequences than those shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0083] The prior description of this disclosure is provided to enable those skilled in the art to make or use it. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory-based CIM bit-cell circuit, comprising: Write access switches, including: The input terminal is coupled to the write bit input; The control terminal is coupled to the write word input; and Output terminals; The write access switch is configured to couple the write bit input to the output terminal in response to a write word voltage supplied to the write word input; and Capacitive storage circuit, including: The first port is coupled to the output terminal of the write access switch; The second port is coupled to the read bit output; and Metal-oxide-semiconductor (MOS) field-effect transistor (FET) in: The first port of the capacitive storage circuit is coupled to the gate of the MOSFET; The second port of the capacitive storage circuit includes the source / drain of the MOSFET coupled to the read bit output; The MOSFET further includes a third port, the third port including a drain / source coupled to the active input; and The capacitive storage circuit is configured as follows: Storing weighted data based on write bit voltage, which is provided on the write bit input in response to the write word voltage provided to the write word input; and A product voltage is generated on the read bit output based on the activation signal and the stored weight data.

2. The CIM bit cell circuit according to claim 1, wherein the MOSFET further comprises a P-type FET (PFET).

3. The CIM bit cell circuit according to claim 1, wherein the MOSFET further comprises an N-type FET (NFET).

4. The CIM bit cell circuit according to claim 1, wherein the write access switch comprises a transistor.

5. The CIM bit cell circuit according to claim 1, wherein the write access switch comprises a P-type field-effect transistor (PFET).

6. The CIM bit cell circuit according to claim 1, wherein the write access switch comprises an N-type field-effect transistor (NFET).

7. The CIM bit cell circuit of claim 1, wherein the capacitive storage circuit is further configured to couple the activation input to the read bit output.

8. A memory-based CIM bit cell array circuit, comprising a CIM bit cell circuit array, wherein the CIM bit cell circuit array includes multiple rows of CIM bit cell circuits and multiple columns of CIM bit cell circuits, wherein: Each of the multiple rows includes a corresponding activation line and a corresponding write word line. The corresponding activation line is coupled to the activation input of each CIM bit cell circuit in the row, and the corresponding write word line is coupled to the write word input of each CIM bit cell circuit in the row. Each of the multiple columns includes a corresponding write bit line and a corresponding read bit line. The corresponding write bit line is coupled to the write bit input of each CIM bit cell circuit in the column, and the corresponding read bit line is coupled to the read bit output of each CIM bit cell circuit in the column. and Each CIM bit unit circuit in the CIM bit unit circuit includes: Write access switches, including: The input terminal is coupled to the write bit input; Control terminal, coupled to the write word input; and Output terminals; and Capacitive storage circuit, including: The first port is coupled to the output terminal of the write access switch; The second port is coupled to the read bit output; and Metal-oxide-semiconductor (MOS) field-effect transistor (FET) in: The first port of the capacitive storage circuit is coupled to the gate of the MOSFET; The second port of the capacitive storage circuit includes the source / drain of the MOSFET coupled to the read bit output; The MOSFET further includes a third port, the third port including a drain / source coupled to the active input; and The capacitive storage circuit is configured as follows: Storing weighted data based on write bit voltage, which is provided on the write bit input in response to the write word voltage provided to the write word input; and A product voltage is generated on the read bit output based on the activation signal and the stored weight data.

9. The CIM bit array circuit of claim 8, wherein the capacitive storage circuit is further configured to couple the activation input to the read bit output.

10. The CIM bit cell array circuit according to claim 8 is further configured as follows: In response to: The write bit line in the first column of the multi-column CIM bit cell circuit provides the write bit voltage; and The write word line in the first row of the multi-row CIM bit cell circuit provides the write word voltage. The weighted data based on the write bit voltage is stored in the capacitive storage circuit of the CIM bit cell circuit in the first column of the multiple columns and the first row of the multiple rows.

11. The CIM bit array circuit according to claim 8 is further configured as follows: Based on the weight data in the capacitive storage circuit of the CIM bit cell circuit stored in the second column of the multiple columns, and the activation signal on the activation line in the multiple rows, a total read voltage is generated on the read bit line of the second column; and A summation circuit generates a sum that indicates the read sum voltage, wherein the summation includes an analog signal or a digital signal.

12. The CIM bit array circuit according to claim 8 is integrated into an integrated circuit IC.

13. The CIM bit array circuit of claim 8 is integrated into a device selected from: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a display; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; a motor vehicle; a vehicle component; an avionics system; an unmanned aerial vehicle (UAV); and a multi-rotor helicopter.

Images