Dram with fast random row refresh for row hammer mitigation

Abstract

A DRAM memory controller is provided that identifies a tag command that points to a given row in a DRAM. If a threshold probability is satisfied in response to identifying the tag command, the DRAM memory controller commands the DRAM to refresh an adjacent row in the DRAM. The adjacent row can be adjacent to the given row or a most recently closed row.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Nonprovisional Patent Application No. 17 / 445,220, filed August 17, 2021, and U.S. Provisional Patent Application No. 63 / 105,621, filed October 26, 2020, each of which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to DRAM memory controllers, and more specifically to DRAM memory controllers with fast random row refresh to mitigate data interference induced by row hammering. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is denser and therefore cheaper per unit of memory storage compared to Static Random Access Memory (SRAM). Therefore, modern integrated circuits such as Systems-on-a-Chip (SoCs) typically include DRAM memory controllers, allowing access to the DRAM integrated circuits for data storage. While DRAM is thus a common memory architecture, DRAM bit cells do not store data as robustly as SRAM bit cells. SRAM bit cells use a pair of cross-coupled inverters to store their bits. These cross-coupled inverters are powered and can therefore be called active devices. However, DRAM bit cells store their bits as charge on a passive capacitor. The capacitor constantly leaks charge, causing DRAM bit cells to be periodically refreshed or their stored bits to become corrupted.

[0005] Although DRAM uses periodic refresh cycles to protect its data, the passive nature of its bit cells makes it susceptible to interference compared to SRAM. DRAM bit cells are arranged in rows sharing a common word line. To access a row, the word line voltage is asserted, allowing the bit cells in that row to receive write or read operations. Assertions on the word line of a row can induce leakage from bit cells in neighboring rows. Therefore, repeated assertions on the word line of a given row before the refresh cycle of neighboring rows can corrupt the stored bits in bit cells of neighboring rows. This interference is commonly referred to as "row hammering." To mitigate row hammering, it is proposed to include a counter in the DRAM for each row, which counts accesses to that row and is reset when the row is refreshed. If the count reaches a threshold, the DRAM performs a refresh on the affected row. Alternatively, the counter can be located in the memory controller, rather than in the DRAM. However, counter-based methods for row hammering mitigation can be cumbersome due to the number of counters required. Summary of the Invention

[0006] A memory controller for dynamic random access memory (DRAM) is provided, the memory controller comprising: logic circuitry configured to identify a tag command pointing to a given row in the DRAM; a probability engine configured to determine whether a threshold probability is satisfied in response to the identification of the tag command; and a command generator configured to signal the DRAM to refresh at least one row other than the given row in response to the satisfaction of the threshold probability.

[0007] A method for a DRAM memory controller is provided, the method comprising: identifying a tag command pointing to a given row in DRAM; determining, in response to identifying the tag command, whether the tag command is associated with a threshold probability; and issuing a command to refresh adjacent rows in DRAM in response to the threshold probability being met.

[0008] A memory controller for DRAM is provided, the memory controller comprising: a command queue configured to queue a plurality of commands destined for DRAM to form a command queue; a first pipeline configured to pipette the command queue to form a plurality of pipette commands; logic circuitry configured to identify a flag command among the plurality of pipette commands; a probability engine configured to determine whether a threshold probability is satisfied in response to identifying a flag command; and a command generator configured to modify commands among the plurality of pipette commands in response to the satisfaction of the threshold probability to form modified commands, the modified commands being commands destined for DRAM that refresh one or more rows.

[0009] These and other advantageous features can be better understood through the following detailed description. Attached Figure Description

[0010] Figure 1 This is a diagram of an example DRAM memory array.

[0011] Figure 2 The illustration shows a memory controller with row hammer mitigation according to a first aspect of the present disclosure.

[0012] Figure 3 The illustration shows a memory controller with row hammer mitigation according to a second aspect of the present disclosure.

[0013] Figure 4 The figure illustrates a memory controller with row hammer mitigation according to a third aspect of this disclosure.

[0014] Figure 5 This is a flowchart of an example operation method of a memory controller with row hammer mitigation according to one aspect of this disclosure.

[0015] Figure 6The illustrations show some example electronic systems including a memory controller according to one aspect of this disclosure.

[0016] The embodiments and advantages of this disclosure are best understood by referring to the following detailed description. It should be recognized that similar reference numerals are used to identify similar elements illustrated in one or more of the accompanying drawings. Detailed Implementation

[0017] To provide a better understanding of the innovative row hammer refresh management disclosed in this article, we will first refer to... Figure 1 The example DRAM array 100 is discussed. DRAM array 100 includes multiple (N) rows of bit cells ranging from row 1 to row N. For clarity, in... Figure 1 Only the first three rows and the last two rows are shown. Row 1 and row N have only one adjacent or neighboring row. The remaining rows will have two neighboring rows. For example, row 2 in array 100 is adjacent to rows 1 and 3. Each row is accessed through a corresponding word line. Therefore, there is a word line W1 for row 1, a word line W2 for row 2, a word line W3 for row 3, and so on, such that there is a word line WN-1 for row (N-1) and a word line WN for row N.

[0018] As defined herein, a row is considered open when its word line voltage is asserted. Generally, this assertion involves charging the word line of the accessed row from ground to the supply voltage, but other voltages may be used in alternative implementations. Row access can occur in response to an activation command, commonly abbreviated as ACT, as defined by the Joint Electronic Equipment Committee (JEDEC). With the word line open, data in the accessed row can be read (read operation) or modified (write operation). The word line is then turned off (e.g., discharged to ground) in response to a JEDEC precharge command, commonly abbreviated as PRE.

[0019] As previously discussed, DRAM rows are periodically refreshed due to leakage from the capacitors of each bit cell from the storage bit cell. Refreshing involves both activation and precharge. Activation occurs so that the contents of the row can be sensed by a corresponding set of sense amplifiers. The sense amplifiers latch the sensed bits so that these sensed bits can be rewritten to the refreshed row during a subsequent precharge period. However, this refresh takes time and may not be possible to perform it simultaneously for more than one row in any given array.

[0020] In an array of DRAM rows, a refresh is applied to only one row, causing all rows to be refreshed over multiple refresh cycles. Because the sense amplifier is occupied during refresh, the memory array cannot be written to or read from during a refresh cycle. Therefore, the refresh of any given row must be time-spaced according to the refresh rate so that the memory array can be used during read and write operations. However, the refresh rate cannot be too slow, causing bit cells to lose their stored bits due to leakage. Given this refresh rate, there are time periods during which a row must hold its data without being refreshed. During this time between refreshes of a given row, adjacent rows can be repeatedly accessed. For example, suppose row 2 in array 100 is repeatedly accessed before refreshing row 1 or row 3. This repeated assertion of word line W2 can cause parasitic assertions of word lines W1 and / or W3. Then, due to the partial assertion of the corresponding word line of row 1 or row 2, the bit cells in row 1 or row 2 may suffer excessive leakage, corrupting their stored data. As previously discussed, this data interference is called row hammering.

[0021] A DRAM memory controller that mitigates row hammering data interference is disclosed. To distinguish this advantageous DRAM memory controller from conventional DRAM memory controllers, the DRAM memory controller disclosed herein is referred to as a row hammering-mitigated DRAM memory controller. Similar to any DRAM memory controller, the row hammering-mitigated memory controller translates memory access requests into a series of commands to its associated DRAM, such as commands related to read and write operations. As previously discussed, two example commands are PRE and ACT. Other types of commands exist in the JEDEC standard, such as Read Commands with Automatic Precharge (RDA) or Write Commands with Automatic Precharge (WDA). Therefore, various types of JEDEC commands exist: PRE, ACT, RDA, WDA, etc. To mitigate the damage to stored data caused by row hammering, this document designates one type of command as a flagging command. As used herein, a flagging command refers to a command that triggers the row hammering-mitigated memory controller to perform an evaluation of whether a refresh neighbor command should be generated. A refresh neighbor command can be abbreviated as an RFN command. An RFN command points to a row in the DRAM memory array (referred to herein as an RFN row). When received at DRAM, DRAM refreshes one or more adjacent rows adjacent to the RFN row, as will be further explained herein. In some embodiments, the tagging command may be an existing JEDEC command. Such a tagging command is referred to herein as an unmodified tagging command. In other embodiments, the tagging command may be a modified form of an existing JEDEC command. Such a tagging command is referred to herein as a modified tagging command.

[0022] A discussion will now be provided of a row hammer mitigation DRAM memory controller applicable to both modified and unmodified tagging command implementations. In this regard, the term "tag command" should be understood as applicable to both implementations unless otherwise specified as modified or unmodified. To provide enhanced row hammer mitigation, the row hammer mitigation DRAM memory controller responds to an identifier-to-tag command with a threshold probability by generating an RFN command. Note that row refreshes in DRAM consume power and can slow down DRAM operation. Therefore, it is not desirable to generate an RFN command on every identifier-to-tag command. In that case, the probability of generating an RFN command in response to an identifier-to-tag command would be 100%. Therefore, in response to an identifier-to-tag command, the row hammer mitigation memory controller generates an RFN command only with a threshold probability. The content constituting the threshold probability depends on the DRAM design and implementation, but this document may assume a "threshold probability" of less than 50%. Note that the choice of threshold probability involves a trade-off between the row hammer mitigation provided by generating the RFN command and the reduction in DRAM power consumption and speed caused by the additional row refresh operation.

[0023] exist Figure 2 Example hammer-relief DRAM memory controller 200 is shown. Controller 200 receives memory access requests, which can also be represented as commands. When a set of commands is received in command queue 205, controller 200 stores that set of commands. The number of commands stored in command queue 205 can vary depending on specific design requirements. For illustrative purposes, command queue 205 is shown as storing sixteen commands ranging from command zero (cmd0) to command fifteen (cmd15), but it will be appreciated that in alternative implementations, fewer or more commands may be stored in command queue 205. Arbitrator 210 selects commands from command queue 205 based on command priority. Final command generator 225 converts the selected commands from arbitrator 210 into DRAM commands for DRAM (not shown). Generally, the DRAM commands generated by final command generator 225 will depend on the DRAM architecture, while the commands processed by command queue 205 and arbitrator 210 are typically independent of the DRAM implementation.

[0024] Those skilled in the art of DRAM memory controllers will recognize that known DRAM memory controllers include some form of command queue, arbitrator, and final command generator. In this respect, command queue 205, arbitrator 210, and final command generator 225 can function in a conventional manner in some embodiments regarding the processing of unmarked commands. However, depending on the type of memory access request being translated, some of the commands will be marked commands. Row hammer mitigator 220 in memory controller 200 may include logic circuitry 240 that identifies the presence of marked commands among the commands being presented to command queue 205. For each instance of a marked command, such as that identified by logic circuitry 240, row hammer mitigator 220 uses probability engine 245 to determine whether a threshold probability is met. A particularly advantageous implementation of this probability engine 245 is generated using random number generator 235 and counter 230. Random number generator 235 generates an integer random number M ranging from 0 to a maximum count (m_max) value. Then, for each consecutive marked command identified, counter 230 increments the count starting from zero (or from some non-zero positive integer). For example, suppose logic circuit 240 identifies the first instance of a tag command. Counter 230 is then initialized to begin counting additional instances of the tag command. Once the count reaches M, probability engine 245 triggers final command generator 225 to insert an RFN command into the DRAM command stream sent to the DRAM, and triggers random number generator 235 to generate a new random number M. Thus, the threshold probability is satisfied by counting the Mth tag command. Non-tag commands and tag commands that do not meet the threshold probability are also passed through controller 200 and become the final command issued to the DRAM by final command generator 225. However, only tag commands that meet the threshold probability trigger an RFN command that is sent to the DRAM. Note that even in implementations where the RFN command is a modified tag command, the trigger tag command (in this example, the Mth tag command counted by counter 230) and the RFN command are two different commands. However, in some implementations, the trigger tag command and the RFN command can be combined to form a single DRAM command.

[0025] According to this disclosure, numerous modifications can be made to the controller 200 to provide line hammering mitigation. Figure 3Another example memory controller 300 is shown. Command queue 205 and arbitrator 210 are as discussed for memory controller 200. Arbitrated commands from arbitrator 210 can be pipelined in pipeline 305 before being passed through timing check circuitry 330 to become DRAM commands as generated by final command generator 335. These DRAM commands may or may not include flag updates. In controller 300, in addition to row hammer mitigator 320 processing DRAM commands issued by final command generator 335, row hammer mitigator 320 can function as discussed for row hammer mitigator 220. If a DRAM command 335 from final command generator 335 meets a threshold probability, row hammer mitigator 320 signals final command generator 335 to insert an RFN command. For example, final command generator 335 can assert flags in the DRAM command to perform an RFN command insertion. Note that the outgoing DRAM commands from the final command generator 335 to the DRAM remain unchanged; therefore, RFN commands will be issued as subsequent DRAM commands compared to DRAM commands that meet a threshold probability determined by the row hammer reliever 320. Since the row hammer reliever 320 can handle commands targeting different groups in the DRAM, control from the row hammer reliever 320 can be pipelined via pipeline 325 to ensure proper scheduling of each group of commands. Timing check circuitry 330 processes the last issued DRAM command from the final command generator 335 to determine how much time or delay should elapse before issuing another DRAM command. If the last issued DRAM command is an RFN command, timing check circuitry 330 can increase this delay to give the DRAM sufficient time to refresh adjacent rows.

[0026] exist Figure 4 Another example memory controller 400 is shown. The command first-in-first-out (FIFO) 405 operates as discussed with respect to command queue 205. Commands from FIFO 405 are pipelined in pipeline 410. Row hammer defragmenter 415 includes an ACT counter to count instances of ACT commands. If the ACT command count satisfies a random number m as discussed with respect to row hammer defragmenter 220, row hammer defragmenter 415 processes the ACT command to become an ACT RFN command. Such an ACT RFN command can be a modified or unmodified flagged command. In an alternative implementation, the row hammer defragmenter can be stateless, such that no counting is performed. For example, based on the ACT command identified in the queue from pipeline 410, row hammer defragmenter 415 can simply generate a random number. If the random number satisfies a threshold probability, then the ACT command is converted into an ACT RFN command.

[0027] We will now begin with a discussion of the modified and unmodified implementations of the tagging command, and will now discuss the modified and unmodified implementations of the tagging command in more detail.

[0028] Line hammering mitigation using modified marker commands

[0029] The modified tagging command can be a modification of an existing JEDEC command to include an RFN field. The RFN field has a true / false state depending on whether a threshold probability is met. For example, the regular PRE command can be modified to include an RFN field to form the tag specified herein as PRE. RFN Example of a modified tagging command. Due to the low probability of generating RFN commands, most PRE... RFN The command will be used as a regular PRE command with its RFN field set to false. However, if a threshold probability is met, the RFN field will be set to true, making PRE... RFN The command is also used as the RFN command. As previously discussed, adjacent rows refreshed in DRAM are neighbors of the RFN row. For the modified tag command implementation, the RFN row corresponds to the row addressed by the modified tag command before the RFN field is set to true. Therefore, PRE RFN The RFN line of the command is in response to PRE. RFN The command is executed on the row that is being precharged in DRAM. If the RFN field is false, DRAM will respond to the PRE command as it would for a regular PRE command. RFN The command responds by precharging the same row that will be precharged by the corresponding regular PRE command. However, if the RFN field is true, the DRAM precharges the PRE not only by precharging the addressed row but also by refreshing the two adjacent rows of that RFN row. RFN The command is responded to. In other implementations, the DRAM precharges the addressed row and also refreshes only one adjacent row among the adjacent rows. RFN The command responds, as will be explained further in this article.

[0030] Another example of a modified tagging command can be formed by modifying the ACT command to include the RFN field, instead of modifying the PRE command. The line hammering reliever 415 can generate such a modified ACT command. The modified ACT command can be specified herein as ACT. RFN As with PRE RFN The examples discussed mostly involve ACTs. RFN Commands will be processed normally, leaving their RFN field false. However, if a threshold probability is met, the RFN field is set to true. In this case, ACT RFNThe command is used not only as an ACT command but also as an RFN command, causing the DRAM to be triggered to refresh the ACT. RFN The command activates one or more adjacent rows of the RFN row.

[0031] Note that PRE commands can be integrated with read or write commands. For example, in the JEDEC standard, a read command with automatic precharge is represented as a Read Automatic Precharge (RDA) command. Similarly, a Write Automatic Precharge command is abbreviated as WDA. A Write Mask Automatic Precharge command is abbreviated as WMA. Therefore, these automatic precharge commands inherently include PRE commands as part of their execution. (See also: PRE...) RFN The standard (existing) automatic precharge command discussed in the command can be modified to include the RFN field to become a modified automatic precharge command.

[0032] Line hammering mitigation using unmodified marker commands

[0033] In this implementation, the tagging command is a regular JEDEC command. In the unmodified tagging command implementation, the RFN command is a completely new command from the JEDEC standard. The unmodified tagging command can be any type of regular JEDEC command, such as the ACT command, PRE command, etc. The row hammer mitigator discussed herein can respond to an unmodified tagging command by inserting the RFN command as one of the DRAM commands issued to the DRAM. As is possible with modified tagging commands, note that the RFN row can then be decoupled from the row addressed by the unmodified tagging command. In some implementations, the RFN row can actually be the same row as the row addressed by the unmodified tagging command. However, in other implementations, the RFN row can instead be the most recently closed row (e.g., the most recently closed row, the second most recently closed row, etc.). The DRAM will then refresh the two (or only one) neighbors of the most recently closed row in response to receiving the RFN command.

[0034] Regardless of whether the marking command is modified or unmodified, the resulting RFN command can trigger a refresh of two adjacent rows of the RFN row, or a refresh of only one adjacent row. The implementation method for triggering a refresh of two adjacent rows will be discussed first, followed by the implementation method for refreshing only one adjacent row.

[0035] Refresh two adjacent rows

[0036] Depending on whether the flag command is modified or not, the RFN command that triggers a refresh of two adjacent rows can take several forms. For example, a modified flag command could be PRE as discussed earlier. RFN Command or ACT RFNCommand. In the implementation of refreshing two adjacent rows, PRE RFN The command triggers a refresh of the two adjacent rows of the row being precharged. Similarly, ACT RFN The command triggers a refresh of the two adjacent rows of the currently active row.

[0037] In the unmodified implementation of the tagging command, one implementation of the new RFN command can be designated as RFN. PREV This is because it instructs the DRAM to refresh the rows adjacent to the most recently closed row. Whether this most recently closed row is the most recently closed row, the second most recently closed row, etc., depends on the implementation. Therefore, there is no connection with RFN. PREV Associated parameters. Another new RFN command can be specified as an RFN issued before the ACT command or after the PRE command. ROW RFN PREV and RFN ROW The command can be issued after the automatic precharge command. RFN ROW The command includes the line address of the RFN line. Response to RFN ROW Command, DRAM refresh as by RFN ROW The line address in the command identifies the adjacent line of the RFN line.

[0038] Refresh only one adjacent row

[0039] Referring again to array 100, note that adjacent rows (such as row 3 above row 2) can be considered to the left of row 2. Conversely, row 1 can be considered to the right of row 2. All remaining rows, except row 1 and row N, will similarly have left and right row neighbors. In the single-adjacent-row refresh implementation, whether the left or right adjacent row is to be refreshed in response to the RFN command can be determined by a register in row hammering relief 220. This register toggles between two values ​​(e.g., between 0 and 1) whenever a threshold probability is met. One value (e.g., 0) can be assigned to select the left adjacent row, and the remaining value (e.g., 1) can be assigned to select the right adjacent row. The example RFN command above can be modified accordingly. For example, the modified flag command could be a modified PRE command. The existing PRE command from the JEDEC standard is modified to include two additional bits. One bit indicates that the adjacent row should be refreshed (or not refreshed), and the other bit indicates whether it is a left or right adjacent row. Similarly, the ACT command can be modified in the same way. In addition, the RDA, WDA, and WMA commands can be modified to include these two parameter fields.

[0040] Alternatively, the RFN discussed earlier can be modified. PREVThe command includes a left / right field, which identifies whether the left-adjacent row or the right-adjacent row is to be flushed. The DRAM will then flush the rows adjacent to the most recently closed row accordingly. Similarly, the RFN discussed earlier... ROW The command can be modified to include a left / right field in addition to the row address. The DRAM will then refresh the appropriate adjacent rows based on the row address.

[0041] Manual refresh

[0042] In the previous example, the DRAM identifies adjacent rows because it knows the location of the RFN row. In the manual refresh alternative, the row(s) to be refreshed are identified by the memory controller. To manually identify these adjacent rows, the memory controller can use a DRAM row proximity function. For example, the memory controller can access the mode register (MR register) in the DRAM, or it can use reserved bits in the existing MR to identify the DRAM row proximity function. The DRAM row proximity function describes how the logical address of a row maps to the physical row. The row proximity function depends on the DRAM implementation. In one example, the row proximity function F(X) equals X / 2. In another example, F(X) equals X XOR(RIGHT_SHIFT((X AND 0x8),1)OR(RIGHT_SHIFT(X AND 0x8),2))). It will be appreciated that the row proximity function therefore depends on the DRAM manufacturer's design. To implement manual refresh, it is assumed that the marking command satisfies a threshold probability. In this example, the RFN row can be considered to have an address identified by the variable ROW. The memory controller can then issue a refresh of the adjacent row using the ACT command and the PRE command. For example, the ACT command would point to ACT(F(ROW+ / -1)). In this way, one or two adjacent rows can be refreshed consecutively. If only the left adjacent row needs to be refreshed, the ACT command will be directed to ACT(F(ROW-1)). Similarly, if only the right adjacent row needs to be refreshed, the ACT command will be directed to ACT(F(ROW+1)).

[0043] exist Figure 5 The diagram illustrates the process flow in the row hammer defragmenter 220. In step 500, when a marking command enters the command queue being processed by the memory controller, circuitry such as logic circuitry in the row hammer defragmenter determines whether a marking command has been identified. If no marking command has been identified, the process returns to step 500 until a marking command is identified. If a marking command has been identified, in step 505, a probability engine, such as a counter and random number generator discussed previously, determines whether a threshold probability is met. If the threshold probability is not met, the process returns to step 500. However, if the threshold probability is met in step 505, an RFN command is issued in step 510.

[0044] The memory controller disclosed herein can be advantageously incorporated into any suitable mobile device or electronic system. For example, such as Figure 6 As shown, the cellular phone 600, laptop computer 605, and tablet PC 610 can all include a DRAM memory controller according to this disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, can also be configured with a memory controller constructed according to this disclosure.

[0045] This disclosure will now be outlined in the following example terms:

[0046] Clause 1. A memory controller for dynamic random access memory (DRAM), comprising:

[0047] Logic circuitry configured to identify a tag command pointing to a given row in the DRAM;

[0048] A probability engine, configured to determine whether a threshold probability is met in response to an identifier for the tag command; and

[0049] A command generator configured to command the DRAM to refresh one or more rows other than the given row in response to the satisfaction of the threshold probability.

[0050] Clause 2. The memory controller according to Clause 1 further includes:

[0051] A command queue, wherein the logic circuitry is further configured to identify the tagged command from a plurality of commands presented to the command queue.

[0052] Clause 3. The memory controller as described in Clause 2 further includes:

[0053] An arbitrator is used to arbitrate commands from the command queue.

[0054] Clause 4. A memory controller according to any one of Clauses 1-3, wherein the one or more rows comprise a pair of rows.

[0055] Clause 5. The memory controller according to Clause 4, wherein the marking command is a command to precharge the given row, and wherein the pair of rows is a pair of adjacent rows of the given row, the probability engine is further configured to assert a refresh field in the marking command in response to the satisfaction of the threshold probability, to command the DRAM to refresh the pair of adjacent rows.

[0056] Clause 6. The memory controller according to Clause 4, wherein the marking command is a command to activate the given row, and wherein the pair of rows is a pair of adjacent rows of the given row, the probability engine is further configured to assert a refresh field in the marking command in response to the satisfaction of the threshold probability, to command the DRAM to refresh both of the pair of adjacent rows.

[0057] Clause 7. The memory controller according to Clause 4, wherein the pair of rows is a pair of adjacent rows of the most recently closed rows, and the probability engine is further configured to issue a refresh adjacent row (RFN) command in response to the satisfaction of the threshold probability to command the DRAM to refresh the pair of adjacent rows.

[0058] Clause 8. The memory controller as described in Clause 7, wherein the RFN command includes a row address field.

[0059] Clause 9. A memory controller according to any one of Clauses 1-3, wherein the given row in the DRAM is adjacent to a first adjacent row and adjacent to a second adjacent row, and wherein the probability engine is further configured to command to refresh only the first adjacent row or only the second adjacent row in response to the satisfaction of the threshold probability.

[0060] Clause 10. The memory controller according to Clause 9, wherein the probability engine is further configured to issue a precharge command having a row left or right field to command only the first adjacent row or the second adjacent row to be refreshed.

[0061] Clause 11. The memory controller according to Clause 9, wherein the probability engine is further configured to issue an activation command with a row left or right field to command only the first adjacent row or the second adjacent row to be refreshed.

[0062] Clause 12. The memory controller according to Clause 9, wherein the probability engine is further configured to issue a refresh adjacent row (RFN) command with a row left or right field to command only the first adjacent row or the second adjacent row to be refreshed.

[0063] Clause 13. The memory controller as described in Clause 12, wherein the RFN command includes a row address field having the address of the given row.

[0064] Clause 14. A memory controller pursuant to any one of Clauses 1-13, wherein the marking command is a Joint Electronic Equipment Committee (JEDEC) command.

[0065] Clause 15. A method for a DRAM memory controller, comprising:

[0066] A marker command that points to a given row in DRAM;

[0067] In response to the tagging command, determine whether the tagging command is associated with a threshold probability; and

[0068] In response to the threshold probability being met, a command is issued to refresh adjacent rows in the DRAM.

[0069] Clause 16. The method according to Clause 15, wherein issuing the command to the DRAM includes modifying the tag command.

[0070] Clause 17. The method according to Clause 16, wherein the marking command is a precharge command for the given row, and wherein modifying the marking command includes asserting a refresh field in the precharge command.

[0071] Clause 18. The method according to Clause 17, wherein the assertion of the refresh field commands the DRAM to refresh a pair of adjacent rows of the given row.

[0072] Clause 19. The method according to Clause 17, wherein the assertion of the refresh field commands the DRAM to refresh only one adjacent row of the given row.

[0073] Clause 20. The method according to Clause 16, wherein the marking command is an activation command for the given row, and wherein modifying the marking command includes asserting a refresh field in the activation command.

[0074] Clause 21. The method according to Clause 20, wherein the assertion of the refresh field commands the DRAM to refresh a pair of adjacent rows of the given row.

[0075] Clause 22. The method according to Clause 17, wherein the assertion of the refresh field commands the DRAM to refresh only one adjacent row of the given row.

[0076] Clause 23. The method according to Clause 15, wherein issuing the command to refresh the adjacent row to the DRAM comprises: issuing a command separate from the marking command.

[0077] Clause 24. The method according to Clause 15, wherein issuing the command includes: mapping the address of the given row via a row proximity function to identify the physical location of the adjacent row in the DRAM.

[0078] Clause 25. A memory controller for dynamic random access memory (DRAM), comprising:

[0079] A command queue, configured to queue multiple commands destined for the DRAM to form a command queue;

[0080] A first pipeline is configured to pipeline the command queue to form a plurality of pipelined commands;

[0081] A logic circuit configured to identify a marker command among the plurality of pipeline commands;

[0082] A probability engine, configured to determine whether a threshold probability is met in response to an identifier for the tag command; and

[0083] A command generator is configured to modify one of the plurality of pipelined commands in response to the satisfaction of the threshold probability to form a modified command, the modified command being a command to refresh one or more rows of the DRAM.

[0084] Clause 26. The memory controller pursuant to Clause 25 further includes:

[0085] A second pipeline for the modified commands.

[0086] Clause 27. The memory controller according to any one of Clauses 25-26 further includes timing checking circuitry configured to check the timing of the plurality of pipeline commands.

[0087] Clause 28. The memory controller according to any one of Clauses 25-27, wherein the plurality of pipeline commands comprises a plurality of JEDEC commands.

[0088] Clause 29. The memory controller according to any one of Clauses 25-28, wherein the command generator is further configured to assert flags in the modified command.

[0089] 30. The memory controller according to any one of clauses 25-29, wherein the command queue includes a first-in-first-out (FIFO) buffer.

[0090] It will be appreciated that many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices of this disclosure without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments described herein (as they are only by way of some examples), but rather should be fully proportionate to the scope of the appended claims and their functional equivalents.

Claims

1. A memory controller for dynamic random access memory (DRAM), comprising: Logic circuitry configured to identify a tag command pointing to a given row in the DRAM; A probability engine is configured to generate random integer numbers and increment the count for each subsequent identifier of the tagging command; as well as A command generator is configured to command the DRAM to refresh one or more rows other than the given row once the count reaches the integer random number, wherein the one or more rows are adjacent to the given row or the most recently closed row.

2. The memory controller according to claim 1, further comprising: A command queue, wherein the logic circuitry is further configured to identify the tagged command from a plurality of commands presented to the command queue.

3. The memory controller according to claim 2, further comprising: An arbitrator is used to arbitrate commands from the command queue.

4. The memory controller of claim 1, wherein the one or more rows comprise a pair of rows.

5. The memory controller of claim 4, wherein the marking command is a command to precharge the given row, and wherein the pair of rows is a pair of adjacent rows of the given row, the probability engine is further configured to assert the refresh field in the marking command once the count reaches the integer random number, so as to command the DRAM to refresh the pair of adjacent rows.

6. The memory controller of claim 4, wherein the marking command is a command to activate the given row, and wherein the pair of rows is a pair of adjacent rows of the given row, the probability engine is further configured to assert the refresh field in the marking command once the count reaches the integer random number, so as to command the DRAM to refresh the pair of adjacent rows.

7. The memory controller of claim 4, wherein the pair of rows is a pair of adjacent rows of the most recently closed rows, and the probability engine is further configured to issue a refresh adjacent rows RFN command to command the DRAM to refresh the pair of adjacent rows once the count reaches the integer random number.

8. The memory controller of claim 7, wherein the RFN command includes a row address field.

9. The memory controller of claim 1, wherein the given row in the DRAM is adjacent to a first adjacent row and adjacent to a second adjacent row, and wherein the probability engine is further configured to command only the first adjacent row or only the second adjacent row to be refreshed once the count reaches the integer random number.

10. The memory controller of claim 9, wherein the probability engine is further configured to issue a precharge command having a row left or right field to command only the first adjacent row or the second adjacent row to be refreshed.

11. The memory controller of claim 9, wherein the probability engine is further configured to issue an activation command having a row left or right field to command only the first adjacent row or the second adjacent row to be refreshed.

12. The memory controller of claim 9, wherein the probability engine is further configured to issue a refresh adjacent row RFN command having a row left or right field to command only the first adjacent row or the second adjacent row to be refreshed.

13. The memory controller of claim 12, wherein the RFN command includes a row address field having the address of the given row.

14. The memory controller of claim 1, wherein the marking command is a Joint Electronic Device Engineering Committee (JEDEC) command.

15. A method for a DRAM memory controller, comprising: A marker command that points to a given row in DRAM; Generate random integers; The count is incremented each time the tagging command is subsequently identified; as well as Once the count reaches the integer random number, a command is issued to the DRAM to refresh adjacent rows in the DRAM.

16. The method of claim 15, wherein issuing the command to the DRAM includes modifying the tag command.

17. The method of claim 16, wherein the marking command is a precharge command for the given row, and wherein modifying the marking command includes asserting a refresh field in the precharge command.

18. The method of claim 17, wherein the assertion of the refresh field in the precharge command instructs the DRAM to refresh a pair of adjacent rows of the given row.

19. The method of claim 17, wherein the assertion of the refresh field in the precharge command instructs the DRAM to refresh only one adjacent row of the given row.

20. The method of claim 16, wherein the marking command is an activation command for the given row, and wherein modifying the marking command includes asserting a refresh field in the activation command.

21. The method of claim 20, wherein the assertion of the refresh field in the activation command instructs the DRAM to refresh a pair of adjacent rows of the given row.

22. The method of claim 17, wherein the assertion in the refresh field of the precharge command instructs the DRAM to refresh only one adjacent row of the given row.

23. The method of claim 15, wherein issuing the command to refresh the adjacent rows in the DRAM comprises: Issue a command separate from the marked command.

24. The method of claim 15, wherein issuing the command comprises: The address of the given row is mapped using a row proximity function to identify the physical location of the adjacent row in the DRAM.

25. A memory controller for dynamic random access memory (DRAM), comprising: A command queue, configured to queue multiple commands destined for the DRAM to form a command queue; A first pipeline is configured to pipeline the command queue to form a plurality of pipelined commands; A logic circuit configured to identify a marker command among the plurality of pipeline commands; A probability engine is configured to generate random integer numbers and increment the count for each subsequent identifier of the tagging command; as well as A command generator is configured to modify one of the plurality of pipelined commands to form a modified command once the count reaches the integer random number. The modified command is a command that goes to the DRAM and refreshes one or more rows.

26. The memory controller of claim 25, further comprising: A second pipeline for the modified commands.

27. The memory controller of claim 25, further comprising timing check circuitry configured to check the timing of the plurality of pipelined commands.

28. The memory controller of claim 25, wherein the plurality of pipeline commands comprises a plurality of JEDEC commands.

29. The memory controller of claim 25, wherein the command generator is further configured to assert flags in the modified command.

30. The memory controller of claim 25, wherein the command queue includes a first-in-first-out (FIFO) buffer.

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