Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, a source region provided on the body region in a manner separated from the drift region and having the first conductivity type, and a contact region provided on the body region and having the second conductivity type, a plurality of gate trenches provided on the first main surface, the plurality of gate trenches being defined by a side surface reaching the drift region through the source region and the body region and a bottom surface connected to the side surface, and extending in a first direction parallel to the first main surface, the contact region being continuous with one first gate trench of the plurality of gate trenches from both sides in a second direction perpendicular to the first direction, and being separated from a second gate trench adjacent to the first gate trench in the second direction.

Description

Technical Field

[0001] This disclosure relates to a silicon carbide semiconductor device.

[0002] This application claims priority based on Japanese Application No. 2020-213691, filed on December 23, 2020, and invokes all the contents of the said Japanese application. Background Technology

[0003] As one type of silicon carbide semiconductor device, a trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is disclosed in which a contact region connected to the body region is discontinuously arranged along the gate trench inside the contact hole formed in the interlayer insulating film (for example, Patent Document 1).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2012-23291 Summary of the Invention

[0007] The silicon carbide semiconductor device disclosed herein includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: a drift region having a first conductivity type; a body region disposed on the drift region having a second conductivity type different from the first conductivity type; a source region disposed on the body region in a manner separated from the drift region and having the first conductivity type; and a contact region disposed on the body region and having the second conductivity type. A plurality of gate trenches are disposed on the first main surface. The plurality of gate trenches are defined by a side surface extending through the source region and the body region to the drift region and a bottom surface connected to the side surface, and extend in a first direction parallel to the first main surface. The contact region is connected from both sides to a first gate trench of the plurality of gate trenches in a second direction perpendicular to the first direction, and is separated from a second gate trench adjacent to the first gate trench in the second direction. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the relationship between the interlayer insulating film, the source region, and the contact region in a silicon carbide semiconductor device according to the embodiments.

[0009] Figure 2 This is a cross-sectional view (1) showing the structure of the silicon carbide semiconductor device according to the embodiment.

[0010] Figure 3 This is a cross-sectional view (2) showing the structure of the silicon carbide semiconductor device involved in the embodiment.

[0011] Figure 4 This is a cross-sectional view (1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0012] Figure 5 This is a cross-sectional view (2) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0013] Figure 6 This is a cross-sectional view (3) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0014] Figure 7 This is a cross-sectional view (4) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0015] Figure 8 This is a cross-sectional view (5) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0016] Figure 9 This is a cross-sectional view (6) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0017] Figure 10 This is a cross-sectional view (7) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0018] Figure 11 This is a cross-sectional view (8) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0019] Figure 12 This is a cross-sectional view (9) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0020] Figure 13 This is a diagram illustrating the relationship between the source region and the contact region in a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0021] Figure 14 This is a diagram illustrating the relationship between the gate trench, source region, and contact region in the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0022] Figure 15 This is a diagram illustrating the relationship between the interlayer insulating film, the source region, and the contact region in the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0023] Figure 16This is a diagram illustrating the relationship between the source region and the contact region when a pattern position shift occurs during the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0024] Figure 17 This is a diagram illustrating the relationship between the interlayer insulating film, the source region, and the contact region when a pattern position shift occurs during the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0025] Figure 18 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment that produces a positional offset of the pattern. Detailed Implementation

[0026] [The technical problem this disclosure aims to solve]

[0027] In existing MOSFETs with intermittently arranged contact areas, the uniformity of temperature distribution during operation tends to decrease. This is because the current between the source and drain flows through the source region but not through the contact region, easily causing temperature unevenness. Furthermore, when the contact area is positioned inside the contact hole, if the pattern position is misaligned during manufacturing, the contact area will be insufficient, leading to changes in characteristics.

[0028] The purpose of this disclosure is to provide a silicon carbide semiconductor device that can improve the uniformity of temperature distribution during operation.

[0029] [The Effects of This Disclosure]

[0030] According to this disclosure, the uniformity of temperature distribution during operation can be improved.

[0031] The following describes the implementation method.

[0032] [Description of embodiments of this disclosure]

[0033] First, embodiments of this disclosure will be described. In the following description, the same or corresponding elements will be labeled with the same reference numerals, and their descriptions will not be repeated. In the crystallographic descriptions in this specification, individual crystal directions are represented by [], groups of crystal directions by <>, individual faces by (), and groups of faces by {}. Furthermore, while crystallographic indices are negative and are typically represented by adding a "-" (hyphen) before the number, in this specification, a negative sign is added before the number.

[0034] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: a drift region having a first conductivity type; a body region disposed on the drift region having a second conductivity type different from the first conductivity type; a source region disposed on the body region in a manner separated from the drift region and having the first conductivity type; and a contact region disposed on the body region and having the second conductivity type. A plurality of gate trenches are disposed on the first main surface. The plurality of gate trenches are defined by a side surface extending through the source region and the body region to the drift region and a bottom surface connected to the side surface, and extend in a first direction parallel to the first main surface. The contact region is connected from both sides to a first gate trench of the plurality of gate trenches in a second direction perpendicular to the first direction, and is separated from a second gate trench adjacent to the first gate trench in the second direction.

[0035] The contact region is connected to the first gate trench and separated from the second gate trench. When the contact region is connected to both the first and second gate trenches, the source region is divided by the contact region in the first direction. During conduction, the source region becomes a conducting region, and the contact region becomes a non-conducting region; therefore, in this case, the conducting region in the first direction is divided by the non-conducting region. In contrast, in the silicon carbide semiconductor device according to this embodiment, a source region exists between the second gate trench and the contact region, and the source region is continuous in the first direction. Therefore, according to the silicon carbide semiconductor device according to this embodiment, a continuous conducting region in the first direction can be ensured. Furthermore, although heat is generated due to the flowing current, the uniformity of heat generation and temperature distribution can be improved because the conducting region is continuous in the first direction. Moreover, since the contact region is connected to the first gate trench from both sides in the second direction, even if a positional shift of the pattern occurs during the formation of the contact region, the total area of ​​the contact region can remain constant. Therefore, stable characteristics can be obtained even if a positional shift of the contact region occurs.

[0036] [2] Alternatively, in [1], the plurality of gate trenches are arranged in the second direction at a first pitch, and the dimension of the contact region in the second direction is more than 0.90 times and less than 1.10 times the first pitch. In this case, it is easy to impart a potential to the body region through the contact region, and it is easy to allow sufficient current to flow through the source region.

[0037] [3] Alternatively, in [1] or [2], a plurality of the contact regions are arranged along the first gate trench in the first direction. In this case, it is easy to improve the uniformity of temperature distribution.

[0038] [4] Alternatively, in [1] to [3], the source region is continuous in the first direction between the first gate trench and the second gate trench. In this case, a large current can easily flow.

[0039] [5] Alternatively, in [1] to [4], the plurality of contact regions are arranged in the second direction at intervals of one of the plurality of gate trenches. In this case, it is easy to flow a large current and easy to impart a potential to the body region through the contact regions.

[0040] [6] Alternatively, in [1] to [5], the plurality of contact areas are arranged in an inclined lattice pattern relative to the first direction and the second direction. In this case, it is easy for a large current to flow and easy to impart a potential to the body region through the contact areas.

[0041] [7] Alternatively, in [1] to [6], the sidewalls of the gate trench may include {0-33-8} surfaces or {11-20} surfaces. In this case, good mobility can be obtained on the sidewalls of the gate trench, and the channel resistance can be reduced.

[0042] [Implementation of this disclosure]

[0043] Embodiments of this disclosure relate to so-called vertical MOSFETs (silicon carbide semiconductor devices). Figure 1 This is a diagram illustrating the relationship between the interlayer insulating film, the source region, and the contact region in a silicon carbide semiconductor device according to the embodiments. Figure 2 as well as Figure 3 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. Figure 1 This is equivalent to a top view showing the configuration of the gate trench, source region, and contact region in the first main surface of a silicon carbide substrate. Figure 2 Equivalent to along Figure 1 A cross-sectional view of line II-II in the diagram. Figure 3 Equivalent to along Figure 1 A cross-sectional view of line III-III in the diagram.

[0044] like Figures 1-3As shown, the MOSFET 100 involved in this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 located on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are, for example, made of polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains, for example, a donor (n-type impurity) such as nitrogen (N) and has an n-type (first conductivity type).

[0045] The first main surface 1 is the {0001} surface or the surface inclined at an angle of less than 8° to the deviation direction. Preferably, the first main surface 1 is the (000-1) surface or the surface inclined at an angle of less than 8° to the deviation direction. The deviation direction can be, for example, the <11-20> direction or the <1-100> direction. The deviation angle can be, for example, more than 1° or more than 2°. The deviation angle can be less than 6° or less than 4°.

[0046] The silicon carbide epitaxial layer 40 mainly has a drift region 11, a bulk region 12, a source region 13, and a contact region 18.

[0047] Drift region 11 is n-type, for example, by adding donors such as nitrogen or phosphorus (P). Preferably, the addition of donors to drift region 11 is not performed by ion implantation, but by impurity addition during the epitaxial growth of drift region 11. Preferably, the donor concentration of drift region 11 is lower than the donor concentration of the silicon carbide single-crystal substrate 50. The donor concentration of drift region 11 is preferably 1 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 For example, 8×10 15 cm -3 about.

[0048] Body region 12 is disposed on drift region 11. Body region 12 has p-type (second conductivity type) characteristics by adding acceptors (p-type impurities) such as aluminum (Al). The acceptor concentration of body region 12 is, for example, 1 × 10⁻⁶. 18 cm -3 about.

[0049] The source region 13 is disposed on the body region 12, separated from the drift region 11 by the body region 12. The source region 13 is n-type, for example, by adding donors such as nitrogen or phosphorus. The source region 13 constitutes the first principal surface 1. The donor concentration of the source region 13 is, for example, 1 × 10⁻⁶. 19 cm-3 about.

[0050] Contact region 18 is p-type by adding acceptors such as aluminum. Contact region 18 forms the first principal surface 1. Contact region 18 penetrates the source region 13 and is connected to the bulk region 12. The acceptor concentration of contact region 18 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 the following.

[0051] A plurality of gate trenches 5 are provided on a first main surface 1. The gate trenches 5 extend, for example, in a first direction parallel to the first main surface 1, and the plurality of gate trenches 5 are arranged in a second direction parallel to the first main surface 1 and orthogonal to the first direction. Each gate trench 5 has a bottom surface 4 formed by a drift region 11. Each gate trench 5 has a side surface 3 that penetrates the contact region 18, the source region 13, and the body region 12 and is connected to the bottom surface 4. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 relative to the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 can also be, for example, 50° or more. The angle θ1 can also be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane or a {11-20} plane. The {0-33-8} plane and the {11-20} plane are crystal planes from which excellent mobility can be obtained.

[0052] Multiple contact regions 18 are arranged along the gate trench 5 in a first direction. Each contact region 18 is connected from both sides to one of the gate trenches 5 in a second direction. If the gate trench 5 connected to the contact region 18 is designated as the first gate trench, and the gate trench 5 adjacent to the first gate trench in the second direction is designated as the second gate trench, then the contact region 18 is separated from the second gate trench. A source region 13 may also exist between the contact region 18 and the second gate trench. The source region 13 may also be continuous in the first direction between the first gate trench and the second gate trench. The multiple contact regions 18 may also be arranged every other one of the multiple gate trenches 5 in the second direction. The multiple contact regions 18 may also be arranged in an inclined grid pattern relative to the first and second directions.

[0053] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is, for example, made of a material containing silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 on the bottom surface 4. The gate insulating film 81 is in contact with the contact region 18, the source region 13, the body region 12, and the drift region 11 on the side surface 3, respectively. The gate insulating film 81 may also be in contact with the source region 13 on the first main surface 1.

[0054] The gate electrode 82 is disposed on the gate insulating film 81. The gate electrode 82 is, for example, made of polysilicon (Poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5.

[0055] The interlayer insulating film 83 is configured to be in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60.

[0056] Contact holes 90 are formed at constant intervals in a second direction on the interlayer insulating film 83 and the gate insulating film 81. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in a first direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0057] The source electrode 60 is connected to the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62 disposed within a contact hole 90. The contact electrode 61 is connected to the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of, for example, a material containing nickel silicide (NiSi). The contact electrode 61 may also be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is ohmically bonded to the source region 13 and the contact region 18. The source wiring 62 covers the upper and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is connected to the contact electrode 61. The source wiring 62 is made of, for example, a material containing Al.

[0058] The drain electrode 70 is connected to the second main surface 2. The drain electrode 70 is connected to the silicon carbide single-crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is, for example, made of a material containing NiSi. The drain electrode 70 may also be made of a material containing Ti, Al, or Si. The drain electrode 70 is ohmically bonded to the silicon carbide single-crystal substrate 50.

[0059] It should be noted that the concentrations of acceptors and donors in the aforementioned impurity regions can be determined, for example, using a scanning capacitance microscope (SCM) or by secondary ion mass spectrometry (SIMS).

[0060] Next, the manufacturing method of the MOSFET 100 according to the embodiment will be described. Figures 4 to 12 This is a cross-sectional view showing a method for manufacturing the MOSFET 100 according to an embodiment. Figures 4 to 12 Show Figure 2 The changes in the cross-section shown. Figure 13 This is a diagram illustrating the relationship between the source region 13 and the contact region 18 in the manufacturing method of the MOSFET 100 according to the embodiment. Figure 14 This is a diagram showing the relationship between the gate trench 5, the source region 13, and the contact region 18 in the manufacturing method of the MOSFET 100 according to the embodiment. Figure 15 This is a diagram illustrating the relationship between the interlayer insulating film 83, the source region 13, and the contact region 18 in the manufacturing method of the MOSFET 100 according to the embodiment.

[0061] First, such as Figure 4 as well as Figure 13 As shown, a drift region 11 is formed on a silicon carbide single-crystal substrate 50 by epitaxial growth. This epitaxial growth can be performed by chemical vapor deposition (CVD), which uses, for example, a mixture of silane (SiH4) and propane (C3H8) as the feed gas and hydrogen (H2) as the carrier gas. Additionally, nitrogen (N) or phosphorus (P) is preferably introduced as a donor. Next, a body region 12 on the drift region 11 and a source region 13 on the body region 12 are formed. Specifically, ion implantation is performed on the upper surface of the drift region 11. In the ion implantation for forming the body region 12, an acceptor such as aluminum (Al) is implanted. In the ion implantation for forming the source region 13, a donor such as phosphorus (P) is implanted. Thus, a silicon carbide substrate 10 having a drift region 11, a body region 12, and a source region 13 is formed. It should be noted that epitaxial growth with the addition of impurities can also be used instead of ion implantation. Next, contact region 18 is formed by ion implantation. For example... Figure 13 As shown, the contact region 18 is formed in an island shape, intersecting with the region forming the gate trench 5. Next, an activation heat treatment is performed to activate the impurities added by ion implantation. The temperature of this heat treatment is preferably 1500°C or higher and 1900°C or lower, for example, around 1700°C. The heat treatment time is, for example, around 30 minutes. The atmosphere for the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere. The silicon carbide substrate 10 is prepared as described above.

[0062] Next, as Figure 5 As shown, a mask 9 is formed on a silicon carbide substrate 10, the mask 9 having an opening that partially exposes the source region 13 and the contact region 18. The opening is formed corresponding to the position of the gate trench 5. As the mask 9, for example, a silicon oxide film formed by thermal oxidation can be used.

[0063] Next, as Figure 6As shown, in the opening of mask 9, a portion of the source region 13, contact region 18, body region 12, and drift region 11 are removed by etching. As an etching method, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE, can be used. Specifically, ICP-RIE using SF6 or a mixture of SF6 and O2 as the reactive gas can be used. Through such etching, a recess 5A with an inner surface 3A that is substantially perpendicular to the main surface of the silicon carbide single-crystal substrate 50 can be formed in the region where the gate trench 5 is to be formed.

[0064] Next, the silicon carbide substrate 10 is etched using mask 9. Specifically, the silicon carbide substrate 10 is thermally etched on the inner surface 3A of the recess 5A. Thermal etching can be performed, for example, by heating the silicon carbide substrate 10 in an atmosphere containing a reactive gas having at least one halogen atom. The at least one halogen atom contains at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere can be, for example, Cl2, BCl3, SF6, or CF4. For example, a mixture of chlorine and oxygen is used as the reactive gas, and thermal etching is performed at a heat treatment temperature of, for example, 700°C or higher and 1000°C or lower. It should be noted that the reactive gas may contain a carrier gas in addition to chlorine and oxygen. For example, nitrogen (N2), argon, helium, etc., can be used as the carrier gas. Furthermore, as described above, when the heat treatment temperature is set to 700°C or higher and 1000°C or lower, the etching rate of SiC is, for example, approximately 70 μm / hour. In addition, in this case, the mask 9 made of silicon oxide has a very high selectivity relative to SiC, so it is not actually etched during the etching of SiC.

[0065] like Figure 7 as well as Figure 14 As shown, a gate trench 5 having a side surface 3 and a bottom surface 4 is formed on the silicon carbide substrate 10 by the above-described thermal etching. When forming the gate trench 5, the silicon carbide substrate 10 is etched from the opening of the mask 9 by side etching, as indicated by arrow SE. Furthermore, during thermal etching, a {0-33-8} surface is automatically formed on the side surface 3.

[0066] Next, as Figure 8As shown, a gate insulating film 81 is formed by removing the mask 9 from the first main surface 1. For example, a gate insulating film 81 is formed by thermally oxidizing a silicon carbide substrate 10, which is in contact with the source region 13, the body region 12, the drift region 11, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere, for example, at a temperature of 1300°C or higher and 1400°C or lower. This forms the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4. It should be noted that, strictly speaking, when the gate insulating film 81 is formed by thermal oxidation, a portion of the silicon carbide substrate 10 enters the gate insulating film 81. Therefore, in subsequent processing, the first main surface 1, the side surface 3, and the bottom surface 4 slightly shift towards the interface between the thermally oxidized gate insulating film 81 and the silicon carbide substrate 10.

[0067] Next, the silicon carbide substrate 10 can be heat-treated (NO annealing) in a nitric oxide (NO) atmosphere. In NO annealing, the silicon carbide substrate 10 is held, for example, at a temperature above 1100°C and below 1400°C for about 1 hour. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the channel mobility can be improved by suppressing the formation of interface states in the interface region.

[0068] Next, as Figure 9 As shown, a gate electrode 82 is formed. The gate electrode 82 is formed on a gate insulating film 81. The gate electrode 82 is formed, for example, by low-pressure chemical vapor deposition (LP-CVD). The gate electrode 82 is formed facing each of the source region 13, the body region 12, and the drift region 11.

[0069] Next, as Figure 10 As shown, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed in such a way that it covers the gate electrode 82 and is in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by chemical vapor deposition. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A portion of the interlayer insulating film 83 may also be formed inside the gate trench 5.

[0070] Next, as Figure 11 as well as Figure 15 As shown, contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 by etching. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0071] Next, a metal film (not shown) for a contact electrode 61, which is in contact with the source region 13 and the contact region 18, is formed on the first main surface 1. The metal film for the contact electrode 61 is formed, for example, by sputtering. The metal film for the contact electrode 61 is made of, for example, a Ni-containing material. Next, a metal film (not shown) for a drain electrode 70, which is in contact with the silicon carbide single-crystal substrate 50, is formed on the second main surface 2. The metal film for the drain electrode 70 is formed, for example, by sputtering. The metal film for the drain electrode 70 is made of, for example, a Ni-containing material.

[0072] Next, alloying annealing is performed. The metal film for contact electrode 61 and the metal film for drain electrode 70 are held at a temperature of 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a portion of the metal film for contact electrode 61 and at least a portion of the metal film for drain electrode 70 react with silicon contained in the silicon carbide substrate 10 to form a silicide. This forms a contact electrode 61 that is ohmically bonded to the source region 13 and the contact region 18, and a drain electrode 70 that is ohmically bonded to the silicon carbide single crystal substrate 50. The contact electrode 61 may also be made of a material containing Ti, Al, or Si. The drain electrode 70 may also be made of a material containing Ti, Al, or Si.

[0073] Next, as Figure 12 As shown, source wiring 62 is formed. Specifically, source wiring 62 is formed covering contact electrode 61 and interlayer insulating film 83. Source wiring 62 is formed, for example, by film deposition based on sputtering and RIE. Source wiring 62 is made of, for example, an aluminum-containing material. In this way, a source electrode 60 having contact electrode 61 and source wiring 62 is formed.

[0074] Thus, the MOSFET 100 involved in the implementation method is completed.

[0075] In the MOSFET 100 of this embodiment, when turned on, current flows between the source electrode 60 and the drain electrode 70, but this current flows through the source region 13 and not through the contact region 18. That is, the source region 13 becomes a conducting region, and the contact region 18 becomes a non-conducting region. The contact region 18 is connected to a gate trench 5 and separated from adjacent gate trenches 5. Therefore, a source region 13 exists between the adjacent gate trenches 5 and the contact region 18, and the source region 13 is continuous in the first direction. When the contact region 18 is connected to two gate trenches 5, the source region 13 is divided by the contact region 18 in the first direction. Therefore, according to this embodiment, a continuous conducting region in the first direction can be ensured. In addition, although heat is generated due to the flowing current, since the conducting region is continuous in the first direction, the uniformity of heat generation and the uniformity of temperature distribution can be improved.

[0076] Furthermore, since the contact area 18 is connected to a gate trench 5 from both sides in the second direction, as will be explained below, even if a positional offset of the pattern occurs when the contact area 18 is formed, the total area of ​​the contact area 18 exposed in the contact hole 90 can remain constant. Figures 16-18 This is a diagram showing the MOSFET100 when the positional offset of the pattern is generated. Figure 16 This is a diagram showing the relationship between the source region 13 and the contact region 18 when a pattern position offset occurs in the manufacturing method of the MOSFET 100 according to the embodiment. Figure 17 This is a diagram showing the relationship between the interlayer insulating film 83, the source region 13, and the contact region 18 when a pattern position offset occurs in the manufacturing method of the MOSFET 100 according to the embodiment. Figure 18 This is a cross-sectional view showing the structure of the MOSFET 100 involved in the embodiment that produces a positional offset of the pattern.

[0077] Here, as Figure 16 As shown, due to the positional offset of the pattern, the contact area 18 is formed offset in the second direction. In this case, in the MOSFET 100 manufactured by performing the processing described above, as... Figure 17 as well as Figure 18 As shown, positional offset still occurred in each contact area 18. However, the total area of ​​the contact areas 18 exposed by each contact hole 90 is significantly larger than the area without positional offset (see reference). Figure 15 The total area is the same. Therefore, even if the position of the contact area 18 is offset, it is difficult to cause changes in characteristics, and stable characteristics can be obtained.

[0078] In addition, in this embodiment, multiple contact areas 18 are arranged along the gate trench 5 in the first direction, thereby easily improving the uniformity of temperature distribution.

[0079] By making the source region 13 continuous in the first direction, a wider conduction region can be ensured, making it easier for current to flow over a wider range. That is, it is easier for large currents to flow.

[0080] Multiple contact regions 18 are arranged in the second direction at intervals of one of the multiple gate trenches 5, thereby facilitating the flow of large currents and facilitating the assignment of potentials to the body region 12 from the source electrode 60.

[0081] By arranging multiple contact areas 18 in an inclined grid pattern relative to the first and second directions, it is easy to carry large currents and easy to impart potential to the body region 12 from the source electrode 60.

[0082] It should be noted that, as Figure 1As shown, multiple gate trenches 5 are arranged in the second direction with a first pitch P. The dimension L of the contact region 18 in the second direction is preferably 0.90 times or more and 1.10 times or less of the first pitch P, more preferably 0.92 times or more and 1.08 times or less. If the dimension L is less than 0.90 times the first pitch P, the contact region 18 becomes too small, and it may be difficult to adequately impart potential to the body region 12. If the dimension L exceeds 1.10 times the first pitch P, the contact region 18 becomes too large, and in the event of pattern offset, the contact region 18 may come into contact with two adjacent gate trenches 5. If the contact region 18 comes into contact with two adjacent gate trenches 5, the conductive area in the first direction is divided by the non-conductive area, which may reduce the uniformity of heat generation and the uniformity of temperature distribution.

[0083] The embodiments have been described in detail above, but are not limited to specific embodiments. Various modifications and alterations are possible within the scope of the claims.

[0084] Explanation of reference numerals in the attached figures

[0085] 1 First main surface; 2 Second main surface; 3 Side surface; 3A Inner surface; 4 Bottom surface; 5 Gate trench; 5A Recess; 9 Mask; 10 Silicon carbide substrate; 11 Drift region; 12 Body region; 13 Source region; 18 Contact region; 40 Silicon carbide epitaxial layer; 50 Silicon carbide single crystal substrate; 60 Source electrode; 61 Contact electrode; 62 Source wiring; 70 Drain electrode; 81 Gate insulating film; 82 Gate electrode; 83 Interlayer insulating film; 90 Contact hole; 100 MOSFET.

Claims

1. A silicon carbide semiconductor device comprising a silicon carbide substrate, the silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: The drift region has a first conductivity type; The body region, disposed on the drift region, has a second conductivity type different from the first conductivity type; The source region is disposed on the body region in a manner separated from the drift region, and has the first conductivity type; as well as A contact area is disposed on the body region and has the second conductivity type. A plurality of gate trenches are provided on the first main surface. The plurality of gate trenches are defined by a side surface that extends through the source region and the body region to the drift region and a bottom surface connected to the side surface, and extend in a first direction parallel to the first main surface. The contact area is connected from both sides to a first gate trench of the plurality of gate trenches in a second direction perpendicular to the first direction, and is separated from a second gate trench adjacent to the first gate trench in the second direction. The plurality of gate trenches are arranged at a first pitch in the second direction. The dimension of the contact area in the second direction is more than 0.90 times and less than 1.10 times the first pitch. Between the first gate trench and the second gate trench, the source region is continuous in the first direction.

2. The silicon carbide semiconductor device according to claim 1, wherein, The plurality of contact regions are arranged along the first gate trench in the first direction.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The plurality of contact regions are arranged in the second direction every other one of the plurality of gate trenches.

4. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The plurality of contact areas are arranged in an inclined grid pattern relative to the first direction and the second direction.

5. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The sidewalls of the gate trench include a {0-33-8} surface or a {11-20} surface.

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