Method and apparatus for loading timing parameters of off-chip memory, electronic device and medium

Abstract

Embodiments of the present application disclose a timing parameter loading method and device for off-chip memory, electronic equipment and medium. The method comprises: determining a device type of the off-chip memory on a single board chip through a secondary program loader running in an on-chip memory in the single board chip; reading and writing adapted device timing parameters into the on-chip memory in the single board chip according to the device type of the off-chip memory on the single board chip; and initializing the off-chip memory on the single board chip by using the device timing parameters in the on-chip memory in the single board chip, so as to start a kernel by using the initialized off-chip memory. The technical scheme of the embodiments of the present application dynamically loads the appropriate off-chip memory device timing parameters in the secondary program loader running stage to complete the off-chip memory device initialization scheme, realizes that one set of software version is compatible with a plurality of off-chip memory devices, and realizes software version downward compatibility.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer application technology, and in particular to a method, apparatus, electronic device and medium for loading timing parameters of off-chip memory. Background Technology

[0002] By launching numerous products with different hardware forms but similar software business, we highlight product differentiation. At the same time, in order to reduce the overall software maintenance cost, we will follow the principle of making one software version compatible with as many hardware models as possible.

[0003] Because Linux provides the DTB mechanism and Windows provides the ACPI mechanism to ensure that the operating system can dynamically identify hardware attributes during runtime, the rules mentioned above will work normally in most device replacement scenarios. However, if the replacement is an external memory (such as a DDR device) connected to the chip, and the timing parameters of the replacement memory and the replaced memory are very different, then it is impossible to use the same set of timing parameters. This will necessitate the release of two embedded software versions, increasing the overall software maintenance cost. Summary of the Invention

[0004] This invention provides a method, apparatus, electronic device, and medium for loading timing parameters of off-chip memory, so as to achieve the goal of one set of software being compatible with multiple off-chip memory devices.

[0005] In a first aspect, embodiments of the present invention provide a method for loading timing parameters of off-chip memory, the method comprising:

[0006] The device type of the external memory on the single-board chip is determined by a secondary program loader running on the on-chip memory of the single-board chip.

[0007] Based on the device type of the external memory on the single-board chip, read the appropriate device timing parameters and write them into the on-chip memory of the single-board chip;

[0008] The device timing parameters in the on-chip memory of the single-board chip are used to initialize the off-chip memory on the single-board chip so that the initialized off-chip memory can be used for kernel boot.

[0009] Secondly, embodiments of the present invention also provide a timing parameter loading device for off-chip memory, the device comprising:

[0010] The device type determination module is used to determine the device type of the external memory on the single-board chip by using a secondary program loader running on the on-chip memory of the single-board chip.

[0011] The timing parameter reading module is used to read the appropriate device timing parameters based on the device type of the external memory on the single-board chip and write them into the on-chip memory of the single-board chip.

[0012] The off-chip memory initialization module is used to initialize the off-chip memory on the single-board chip using the device timing parameters in the on-chip memory of the single-board chip, so as to use the initialized off-chip memory for kernel boot.

[0013] Thirdly, this invention also provides an electronic device, comprising:

[0014] One or more processors;

[0015] Storage device for storing one or more programs;

[0016] The one or more programs are executed by the one or more processors, causing the one or more processors to implement the timing parameter loading method for off-chip memory as provided in any embodiment of the present invention.

[0017] Fourthly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the timing parameter loading method for off-chip memory as provided in any embodiment of the present invention.

[0018] This invention discloses a method, apparatus, electronic device, and medium for loading timing parameters of off-chip memory. The method includes: determining the device type of the off-chip memory on a single-board chip using a secondary program loader running on the on-chip memory; reading appropriate device timing parameters based on the device type of the off-chip memory and writing them into the on-chip memory of the single-board chip; initializing the off-chip memory on the single-board chip using the device timing parameters in the on-chip memory of the single-board chip, and then using the initialized off-chip memory for kernel boot. By employing the technical solution of this invention, a scheme for dynamically loading appropriate DDR timing parameters to complete DDR initialization during the SPL runtime phase is implemented, achieving software version compatibility with multiple DDR hardware and backward compatibility of the software version.

[0019] The above description of the invention is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0020] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0021] Figure 1 This is a flowchart of a timing parameter loading method for off-chip memory provided in Embodiment 1 of the present invention;

[0022] Figure 2A This is a flowchart of a timing parameter loading method for off-chip memory provided in Embodiment 2 of the present invention;

[0023] Figure 2B This is a flowchart of an embedded system startup provided in Embodiment 2 of the present invention;

[0024] Figure 3A This is a flowchart of a timing parameter loading method for off-chip memory provided in Embodiment 3 of the present invention;

[0025] Figure 3B This is a schematic diagram of a system power-on structure provided in Embodiment 3 of the present invention;

[0026] Figure 4 This is a structural diagram of a timing parameter loading device for off-chip memory provided in Embodiment 4 of the present invention;

[0027] Figure 5 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of the present invention. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention and not the entire structure.

[0029] Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations (or steps) may be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations may be rearranged. The process may be terminated when its operation is completed, but may also have additional steps not included in the figures. The process may correspond to a method, function, procedure, subroutine, subroutine, etc.

[0030] Traditional embedded software reads DDR timing parameters from a fixed address in Flash and saves them to on-chip SRAM. It then uses these parameters to initialize the DDR hardware. However, it cannot use DTB or ACPI mechanisms for dynamic identification at runtime because DDR initialization occurs during the early startup phase of the chip, before U-Boot and Linux are running. If the DDR device on the board is replaced, a software version adapted to the new DDR timing parameters must be rewritten and flashed. To address the issue of new software versions due to DDR device replacement, a dynamic DDR parameter identification and loading scheme is proposed for the SPL stage (before U-Boot startup), enabling a single software version to be compatible with multiple types of DDR.

[0031] The timing parameter loading method, apparatus, electronic device, and medium for off-chip memory provided in the embodiments of the present invention will be described in detail below through various embodiments.

[0032] Example 1

[0033] Figure 1 This is a flowchart of a timing parameter loading method for off-chip memory according to Embodiment 1 of the present invention. This embodiment is applicable to situations where timing parameters of off-chip memory are loaded. This method can be executed by an off-chip memory timing parameter loading device, which can be implemented in software and / or hardware and can be integrated into any electronic device with network communication capabilities. Figure 1 As shown, the timing parameter loading method for off-chip memory provided in Embodiment 1 of the present invention may include the following steps:

[0034] S110. The device type of the external memory on the single-board chip is determined by the secondary program loader running on the on-chip memory of the single-board chip.

[0035] Among them, a single-board chip can refer to a silicon wafer containing integrated circuits. It is very small and is usually part of a computer or other electronic device. For example, a system-on-chip (SoC) is an integrated circuit with a specific purpose, which contains a complete system and all the embedded software.

[0036] On-chip memory can refer to a non-physical, storage-functional memory, such as DRAM, FIFO, and SRAM. Static Random Access Memory (SRAM) is a type of memory that retains its data as long as it is powered on, but the data is lost when the power supply is cut off.

[0037] A secondary program loader (SPL) can refer to a program responsible for detecting the ROM and hardware, locating the system boot partition, and loading other parts of the ROM. For example, an SPL might be a program that initializes the DDR hardware and reads the U-Boot program into the DDR.

[0038] External memory can refer to storage devices with physical form, such as Double Data Rate SDRAM (DDR), memory modules, and TF cards. The hardware type of DDR corresponds one-to-one with the resistance values ​​of the voltage divider resistors in the circuit. By reading the resistance values ​​of the voltage divider resistors in the circuit, the device type of external memory on the single-board chip can be determined. DDR hardware types include, but are not limited to, DDR1, DDR2, DDR3, and DDR4.

[0039] In this embodiment of the invention, the device type of the external memory on the single-board chip is determined by running a secondary program loader on the on-chip memory of the single-board chip and reading the voltage division value of the voltage divider resistor in the external memory type differentiation circuit.

[0040] S120. Based on the device type of the external memory on the single-board chip, read the appropriate device timing parameters and write them into the on-chip memory of the single-board chip.

[0041] Timing parameters refer to the relative position between the data signal and its reference clock signal, ensuring that the data remains stable near the rising or falling edge of the clock, so that the data can be effectively read. For example, DDR timing parameters include, but are not limited to, CL (CAS latency), tRC, tRRD, tFAW, tCCD, tRPRE, tRPST, tWTR, tWR, tRCD, etc.

[0042] Based on the resistance values ​​of the voltage divider resistors in the circuit, the device type of the external memory on the single-board chip is determined. From multiple timing parameters, a timing parameter matching the device type of the external memory is found. The matching timing parameter is read and written into the on-chip memory of the single-board chip.

[0043] S130. The device timing parameters in the on-chip memory of the single-board chip are used to initialize the off-chip memory on the single-board chip so as to use the initialized off-chip memory for kernel startup.

[0044] Initialization can refer to initializing the external memory on the single-board chip using the device timing parameters of the on-chip memory. For example, based on the device type of the external memory on the single-board chip, an appropriate voltage is output to power the external memory. The device timing parameters of the on-chip memory in the single-board chip are used to initialize the external memory on the single-board chip, and the initialized external memory is used to start the kernel.

[0045] This invention provides a method for loading timing parameters for off-chip memory. A secondary program loader running on the on-chip memory of a single-board chip determines the device type of the off-chip memory based on the voltage division values ​​of the voltage divider resistors in the circuit. Based on the device type of the off-chip memory, timing parameters matching the device type are found, and the appropriate device timing parameters are read and written to the on-chip memory of the single-board chip. The device timing parameters in the on-chip memory are then used to initialize the off-chip memory, enabling kernel startup using the initialized off-chip memory. This invention's solution, which dynamically loads appropriate DDR timing parameters during the SPL runtime phase to complete DDR initialization, achieves software version compatibility with multiple DDR hardware types, thus enabling backward compatibility of the software version.

[0046] Example 2

[0047] Figure 2A This is a flowchart of a timing parameter loading method for off-chip memory provided in Embodiment 2 of the present invention. This embodiment is an optimization based on the above embodiments, and the embodiments of the present invention can be combined with various optional solutions in one or more of the above embodiments. For example... Figure 2A As shown, the timing parameter loading method for off-chip memory provided in this embodiment of the invention may include the following steps:

[0048] S210. The device type of the external memory on the single-board chip is determined by the secondary program loader running on the on-chip memory of the single-board chip.

[0049] S220. From the multiple device timing parameters pre-stored in the non-volatile storage medium associated with the single-board chip, find the device timing parameters that match the device type of the off-chip memory on the single-board chip.

[0050] Non-volatile storage media (Flash) can refer to storage media used to store executable code, variables, and other transient data. For example, a non-volatile storage medium reads a secondary program loader into static random-access memory (SRAM) and transfers program control to the secondary program loader.

[0051] The non-volatile storage media associated with the single-board chip include, but are not limited to, the first non-volatile storage media inherent on the single-board chip and the second non-volatile storage media added to the single-board chip for backing up device timing parameters; the first non-volatile storage media has a higher usage priority than the second non-volatile storage media.

[0052] The first non-volatile storage medium can refer to flash memory (Flash EPROM), which allows for multiple erasures or writes during operation and is non-volatile; the second non-volatile storage medium can refer to electrically erasable programmable read-only memory (EEPROM), which is a storage chip that does not lose data after power failure.

[0053] The parameters include, but are not limited to, detailed DDR timing parameters such as CL (CAS latency), tRC, tRRD, tFAW, tCCD, tRPRE, tRPST, tWTR, tWR, and tRCD; DDR power supply voltage values; and DDR manufacturer information, which are not essential for startup and are used for problem localization.

[0054] The single-board chip in this embodiment of the invention is no longer limited to the replacement of DDR devices with the same timing parameters. The software version can be backward compatible. With proper planning during the product development stage, it can be ensured that a sufficient variety of DDR timing parameters can be incorporated into the same software version, thereby increasing the reliability of device supply and improving procurement bargaining power.

[0055] S230: Read the timing parameters of the adapted device and write them into the on-chip memory of the single-board chip.

[0056] in, Figure 2B This is a flowchart of an embedded system startup provided in Embodiment 2 of the present invention, such as... Figure 2B As shown, SPL first initializes the chip ADC controller, reads the resistor voltage divider value, determines the DDR hardware type on the current board based on the voltage value, and reads the parameters from the appropriate Flash address and saves them to the on-chip SRAM.

[0057] In one optional embodiment of the present invention, the step of reading the adapted device timing parameters and writing them into the on-chip memory of the single-board chip may further include:

[0058] When reading and writing the adapted device timing parameters from the second non-volatile storage medium, the monitoring program of the single-board chip is started, waiting for the new program image to be passed in;

[0059] The new program image is received via the serial port or universal serial bus of the single-board chip, and after writing is completed, the new program image is flashed into the first non-volatile storage medium inherent on the single-board chip; the new program image is the same as the program image in the first non-volatile storage medium inherent on the single-board chip that has image corruption.

[0060] The newly received program image can be directly written to the on-chip external memory of the single-board chip for kernel booting; or, the new program image, which has been re-flushed onto the first non-volatile storage medium inherent on the single-board chip, can be written to the on-chip external memory of the single-board chip for kernel booting.

[0061] If the DDR parameters are read from the primary partition, it proves that the Flash image is not damaged. SPL then reads the kernel bootloader (such as U-Boot) from the Flash and saves it to the DDR, and then transfers program control to U-Boot. U-Boot completes the remaining initialization work and boots the kernel.

[0062] If the DDR parameter table is read from EEPROM, it indicates that the flash image is corrupted. In this case, the backup parameters are used to complete the DDR hardware initialization, ensuring sufficient memory is available for device recovery (rewriting the flash image). The specific process is as follows: When SPL detects that the device is booting from the DDR parameters in EEPROM, it starts a serial port or USB monitoring program, waiting for the user to send a new program image, and sets a timeout period. If no upgrade connection is initiated before the timeout expires, the device automatically restarts; otherwise, it receives upgrade data from the serial port or USB while simultaneously writing it to the DDR. After writing is complete, the entire image is flashed into the Flash. This function greatly simplifies device recovery, eliminating the need for a dedicated programmer.

[0063] S240. The device timing parameters in the on-chip memory of the single-board chip are used to initialize the off-chip memory on the single-board chip so as to use the initialized off-chip memory for kernel boot.

[0064] This invention provides a method for loading timing parameters of off-chip memory. The method involves using a secondary program loader running on the on-chip memory of a single-board chip to determine the device type of the off-chip memory; reading the voltage divider value of the voltage divider resistor in the off-chip memory type differentiation circuit; the off-chip memory type differentiation circuit includes voltage divider resistors connected to the analog-to-digital converter port or I / O port of the single-board chip; determining the device type of the off-chip memory based on the read voltage divider value; and initializing the off-chip memory using the device timing parameters of the on-chip memory to boot the kernel using the initialized off-chip memory. This invention's technical solution, based on a dynamic DDR parameter differentiation scheme, extends a software image backup scheme. It utilizes EEPROM to additionally back up DDR parameters, enabling the SPL program to continue initializing DDR and monitor the serial port or USB for rapid recovery even after DDR parameter partition corruption due to power outages or other abnormal situations during the upgrade process. This eliminates the need for a dedicated flash programmer, achieving software compatibility with multiple off-chip memory devices.

[0065] Example 3

[0066] Figure 3A This is a flowchart of a timing parameter loading method for off-chip memory provided in Embodiment 3 of the present invention. This embodiment is an optimization based on the above embodiments, and the embodiments of the present invention can be combined with various optional solutions in one or more of the above embodiments. Figure 3A As shown, the timing parameter loading method for off-chip memory provided in this embodiment of the invention may include the following steps:

[0067] S310. The device type of the external memory on the single-board chip is determined by the secondary program loader running on the on-chip memory of the single-board chip.

[0068] Among them, determining the device type of the on-chip external memory of the single-board chip includes:

[0069] Read the voltage division value of the voltage divider resistor in the off-chip memory type differentiation circuit; the off-chip memory type differentiation circuit includes a voltage divider resistor connected to the analog-to-digital conversion port or I / O port of the single-board chip;

[0070] Based on the read resistor voltage divider values, determine the device type of the on-chip external memory on the single-board chip;

[0071] In the external memory type differentiation circuit, the resistance value of the voltage divider resistor is adapted to the change of the device type of the external memory on the single-board chip.

[0072] Specifically, by running the secondary program loader on the on-chip memory of the single-board chip, the voltage division value of the voltage divider resistor in the external memory type differentiation circuit is read, thereby determining the device type of the external memory on the single-board chip.

[0073] In one alternative, Figure 3B This is a schematic diagram of a system power-on structure provided in Embodiment 3 of the present invention, as shown below. Figure 3B As shown, upon system power-up, the single-board chip (SOC) is reset, and a program (BOOTROM) stored at a fixed address within the chip begins execution. The BOOTROM initializes the on-chip SRAM, reads the second program loader (SPL) from non-volatile storage into the SRAM, and transfers program control to the SPL. The SPL first initializes the chip's ADC controller, reads the resistor divider values, and determines the DDR hardware type on the current single-board board based on the voltage values. The BOOTROM is a program stored on-chip before the chip leaves the factory; it is the first program executed after the chip powers on and resets. Its main function is to initialize the on-chip SRAM and read the SPL program from Flash into the SRAM.

[0074] Among them, there is a DDR type differentiation circuit, such as two resistors dividing the voltage and connecting to the chip's ADC input or a set of IO pins as board type differentiation pins; a DDR power supply voltage regulation control circuit, which does not power on the DDR by default when the hardware is powered on and reset, and is controlled by the software after startup; for different DDR devices, the current DDR hardware information is told to the software by adjusting the resistance value of the voltage divider resistor; an external EEPROM is added to the main chip to back up the DDR parameters once more.

[0075] This invention uses a DDR type differentiation circuit to provide the basis for software to differentiate DDR parameters. The differentiation methods listed in this solution are all hardware methods, and the specific methods are not limited. The backup DDR parameter partition ensures that the parameters can still be read from the backup partition after the main chip's DDR parameters are damaged, and ensures that SPL has sufficient memory for image repair.

[0076] S320: Based on the device type of the external memory on the single-board chip, read the appropriate device timing parameters and write them into the on-chip memory of the single-board chip.

[0077] S330: Based on the device type of the external memory on the single-board chip, output an appropriate voltage to power the external memory.

[0078] Specifically, the device type of the external memory is determined based on the resistance value of the voltage divider resistor in the circuit; the appropriate voltage is determined based on the device type of the external memory on the single-board chip, and the external memory is powered accordingly.

[0079] Optionally, an adapted voltage can be output to the off-chip memory on the single-board chip via an off-chip memory power supply regulation control circuit associated with the single-board chip.

[0080] In this embodiment of the invention, SPL controls the DDR power supply voltage regulation control circuit to output a suitable voltage to power the DDR according to the DDR hardware type, and then initializes the DDR hardware according to the DDR timing parameters in SRAM, thus achieving the goal of one software being compatible with multiple DDR hardware.

[0081] S340. After powering on the external memory on the single-board chip, the device timing parameters written to the on-chip memory of the single-board chip are used to initialize the external memory on the single-board chip.

[0082] This invention provides a method for loading timing parameters of off-chip memory. By reading the voltage divider values ​​of the voltage divider resistors in the off-chip memory type differentiation circuit, the device type of the off-chip memory on the single-board chip is determined. A DDR parameter partition is backed up, ensuring that parameters can still be read from the backup partition even if the main chip's DDR parameters are damaged, guaranteeing that the SPL has sufficient memory for image repair. Based on the device type of the off-chip memory on the single-board chip, suitable device timing parameters are read and written to the on-chip memory of the single-board chip. Based on the device type of the off-chip memory on the single-board chip, a suitable voltage is output to the off-chip memory to power it. Then, the DDR hardware is initialized according to the DDR timing parameters in the SRAM, achieving software compatibility with multiple DDR hardware types. After powering the off-chip memory on the single-board chip, the device timing parameters written to the on-chip memory of the single-board chip are used to initialize the off-chip memory, achieving software version compatibility with multiple DDR hardware types and backward compatibility.

[0083] Example 4

[0084] Figure 4 This is a structural diagram of a timing parameter loading device for off-chip memory provided in Embodiment 4 of the present invention. This embodiment is applicable to situations where timing parameters are loaded for off-chip memory. The device can be implemented in software and / or hardware and can be integrated into any electronic device with network communication capabilities. Figure 4 As shown, the timing parameter loading device for off-chip memory provided in this embodiment of the invention may include the following: a device type determination module 410, a timing parameter reading module 420, and an off-chip memory initialization module 430; wherein:

[0085] Device type determination module 410 is used to determine the device type of the external memory on the single board chip by using a secondary program loader running on the on-chip memory of the single board chip.

[0086] Timing parameter reading module 420 is used to read the appropriate device timing parameters and write them into the on-chip memory of the single board chip according to the device type of the external memory on the single board chip.

[0087] The off-chip memory initialization module 430 is used to initialize the off-chip memory on the single-board chip using the device timing parameters in the on-chip memory of the single-board chip, so as to use the initialized off-chip memory for kernel boot.

[0088] Based on the above embodiments, optionally, determining the device type of the on-chip external memory of the single-board chip includes:

[0089] Read the voltage division value of the voltage divider resistor in the off-chip memory type differentiation circuit; the off-chip memory type differentiation circuit includes a voltage divider resistor connected to the analog-to-digital conversion port or I / O port of the single-board chip;

[0090] Based on the read resistor voltage divider values, determine the device type of the off-chip memory on the single-board chip;

[0091] In the circuit that distinguishes the type of external memory, the resistance value of the voltage divider resistor is adapted to change as the device type of the external memory on the single-board chip changes.

[0092] Based on the above embodiments, optionally, the timing parameter reading module 420 includes:

[0093] Find the device timing parameters that match the device type of the off-chip memory on the single board chip from the multiple device timing parameters pre-stored in the non-volatile storage medium associated with the single board chip.

[0094] Read the timing parameters of the compatible device and write them into the on-chip memory of the single-board chip.

[0095] Based on the above embodiments, optionally, the non-volatile storage medium associated with the single-board chip includes a first non-volatile storage medium inherent on the single-board chip and a second non-volatile storage medium added on the single-board chip for backing up device timing parameters; the first non-volatile storage medium has a higher usage priority than the second non-volatile storage medium.

[0096] Based on the above embodiments, optionally, the off-chip memory initialization module 430 includes:

[0097] Based on the device type of the external memory on the single-board chip, an appropriate voltage is output to the external memory on the single-board chip to supply power to the external memory;

[0098] After powering on the external memory on the single-board chip, the device timing parameters written to the on-chip memory of the single-board chip are used to initialize the external memory on the single-board chip.

[0099] Optionally, based on the above embodiments, the step of outputting an adapted voltage to the on-chip external memory of the single-board chip includes:

[0100] The off-chip memory power supply regulation control circuit associated with the single-board chip outputs an adapted voltage to the off-chip memory on the single-board chip.

[0101] Optionally, based on the above embodiments, the method further includes:

[0102] When reading and writing the adapted device timing parameters from the second non-volatile storage medium, the monitoring program of the single-board chip is started, waiting for the new program image to be passed in;

[0103] The new program image is received via the serial port or universal serial bus of the single-board chip, and after writing is completed, the new program image is flashed into the first non-volatile storage medium inherent on the single-board chip; the new program image is the same as the program image in the first non-volatile storage medium inherent on the single-board chip that has image corruption.

[0104] The newly received program image can be directly written to the on-chip external memory of the single-board chip for kernel booting; or, the new program image, which has been re-flushed onto the first non-volatile storage medium inherent on the single-board chip, can be written to the on-chip external memory of the single-board chip for kernel booting.

[0105] The timing parameter loading device for off-chip memory provided in the embodiments of the present invention can execute the timing parameter loading method for off-chip memory provided in any of the embodiments of the present invention, and has the corresponding functions and beneficial effects of executing the timing parameter loading method for off-chip memory. For technical details not described in detail in the above embodiments, please refer to the timing parameter loading method for off-chip memory provided in any of the embodiments of this application.

[0106] Example 5

[0107] Figure 5 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of the present invention. Figure 5 The structure shown in this embodiment of the invention includes an electronic device comprising one or more processors 510 and a storage device 520; the processors 510 in this electronic device may be one or more. Figure 5 Taking a processor 510 as an example; storage device 520 is used to store one or more programs; the one or more programs are executed by the one or more processors 510, so that the one or more processors 510 implement the timing parameter loading method of off-chip memory as described in any one embodiment of the present invention.

[0108] The electronic device may also include an input device 530 and an output device 540.

[0109] The processor 510, storage device 520, input device 530, and output device 540 in this electronic device can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0110] The storage device 520 in this electronic device serves as a computer-readable storage medium, capable of storing one or more programs. These programs can be software programs, computer-executable programs, or modules, such as the program instructions / modules corresponding to the timing parameter loading method for off-chip memory provided in this embodiment of the invention. The processor 510 executes various functional applications and data processing of the electronic device by running the software programs, instructions, and modules stored in the storage device 520, thereby implementing the timing parameter loading method for off-chip memory in the above method embodiment.

[0111] Storage device 520 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device, etc. Furthermore, storage device 520 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, storage device 520 may further include memory remotely located relative to processor 510, and this remote memory may be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] Input device 530 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the electronic device. Output device 540 may include display devices such as a display screen.

[0113] Furthermore, when one or more programs included in the aforementioned electronic device are executed by one or more processors 510, the programs perform the following operations:

[0114] The device type of the external memory on the single-board chip is determined by a secondary program loader running on the on-chip memory of the single-board chip.

[0115] Based on the device type of the external memory on the single-board chip, read the appropriate device timing parameters and write them into the on-chip memory of the single-board chip;

[0116] The device timing parameters in the on-chip memory of the single-board chip are used to initialize the off-chip memory on the single-board chip so that the initialized off-chip memory can be used for kernel boot.

[0117] Of course, those skilled in the art will understand that when one or more programs included in the above-mentioned electronic device are executed by one or more processors 510, the programs can also perform related operations in the timing parameter loading method of off-chip memory provided in any embodiment of the present invention.

[0118] Example 6

[0119] Embodiment 6 of the present invention provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the program is used to execute a timing parameter loading method for off-chip memory. The method includes:

[0120] The device type of the external memory on the single-board chip is determined by a secondary program loader running on the on-chip memory of the single-board chip.

[0121] Based on the device type of the external memory on the single-board chip, read the appropriate device timing parameters and write them into the on-chip memory of the single-board chip;

[0122] The device timing parameters in the on-chip memory of the single-board chip are used to initialize the off-chip memory on the single-board chip so that the initialized off-chip memory can be used for kernel boot.

[0123] Optionally, when the program is executed by the processor, it can also be used to execute the timing parameter loading method for off-chip memory provided in any embodiment of the present invention.

[0124] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable CD-ROM, optical storage device, magnetic storage device, or any suitable combination thereof. A computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0125] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in connection with an instruction execution system, apparatus, or device.

[0126] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0127] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0128] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0129] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for loading timing parameters of off-chip memory, characterized in that, The method includes: The secondary program loader running on the on-chip memory of the single-board chip reads the voltage division value of the voltage divider resistor in the external memory type differentiation circuit, and determines the device type of the external memory on the single-board chip based on the read voltage division value; wherein, the external memory type differentiation circuit includes a voltage divider resistor connected to the analog-to-digital conversion port or I / O port of the single-board chip, and the resistance value of the voltage divider resistor in the external memory type differentiation circuit is adapted to change as the device type of the external memory on the single-board chip changes; From the multiple device timing parameters pre-stored in the non-volatile storage medium associated with the single-board chip, find the device timing parameters that match the device type of the external memory on the single-board chip, read the matching device timing parameters and write them into the on-chip memory of the single-board chip. The device timing parameters in the on-chip memory of the single-board chip are used to initialize the off-chip memory on the single-board chip so that the initialized off-chip memory can be used for kernel boot.

2. The method according to claim 1, characterized in that, The non-volatile storage medium associated with the single-board chip includes a first non-volatile storage medium inherent on the single-board chip and a second non-volatile storage medium added to the single-board chip for backing up device timing parameters; The first non-volatile storage medium has a higher priority in use than the second non-volatile storage medium.

3. The method according to claim 1, characterized in that, The on-chip external memory of the single-board chip is initialized using the device timing parameters in the on-chip memory of the single-board chip, including: Based on the device type of the external memory on the single-board chip, an appropriate voltage is output to the external memory on the single-board chip to supply power to the external memory; After powering on the external memory on the single-board chip, the device timing parameters written to the on-chip memory of the single-board chip are used to initialize the external memory on the single-board chip.

4. The method according to claim 3, characterized in that, Outputting an adapted voltage to the on-chip external memory of the single-board chip, including: The off-chip memory power supply regulation control circuit associated with the single-board chip outputs an adapted voltage to the off-chip memory on the single-board chip.

5. The method according to claim 2, characterized in that, The method further includes: When reading and writing the adapted device timing parameters from the second non-volatile storage medium, the monitoring program of the single-board chip is started, waiting for the new program image to be passed in; The new program image is received via the serial port or universal serial bus of the single-board chip, and after writing is completed, the new program image is flashed into the first non-volatile storage medium inherent on the single-board chip; the new program image is the same as the program image in the first non-volatile storage medium inherent on the single-board chip that has image corruption. The newly received program image can be directly written to the on-chip external memory of the single-board chip for kernel booting; or, the new program image, which has been re-flushed onto the first non-volatile storage medium inherent on the single-board chip, can be written to the on-chip external memory of the single-board chip for kernel booting.

6. A timing parameter loading device for off-chip memory, characterized in that, The device includes: The device type determination module is used to read the voltage division value of the voltage divider resistor in the external memory type differentiation circuit through a secondary program loader running on the on-chip memory of the single-board chip, and determine the device type of the external memory on the single-board chip based on the read voltage division value; wherein, the external memory type differentiation circuit includes a voltage divider resistor connected to the analog-to-digital conversion port or I / O port of the single-board chip, and the resistance value of the voltage divider resistor in the external memory type differentiation circuit is adapted to change as the device type of the external memory on the single-board chip changes; The timing parameter reading module is used to search for device timing parameters that are compatible with the device type of the external memory on the single board chip from multiple device timing parameters pre-stored in the non-volatile storage medium associated with the single board chip, read the compatible device timing parameters and write them into the on-chip memory of the single board chip. The off-chip memory initialization module is used to initialize the off-chip memory on the single-board chip using the device timing parameters in the on-chip memory of the single-board chip, so as to use the initialized off-chip memory for kernel boot.

7. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the timing parameter loading method for off-chip memory as described in any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the timing parameter loading method for off-chip memory as described in any one of claims 1-5.

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