Display device

Abstract

Disclosed are display devices. The display devices include active stages each including a scan output circuit that outputs a scan clock signal to a first output terminal when a voltage at a first node is at a logic high level and a carry output circuit that outputs a carry clock signal to a second output terminal when the voltage at the first node is at the logic high level. The scan output circuit and the carry output circuit output an off-level scan signal and an off-level carry signal to the first output terminal and the second output terminal, respectively, when a voltage at a second node or a carry signal is at a logic high level. Intervals between pulses of the carry clock signal generated during one frame period are the same, and at least two of the intervals between pulses of the scan clock signal generated during one frame period are different from each other.

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