Apparatus and methods for 1t and 2t memory cell architectures

Abstract

Apparatus and methods for 1T and 2T memory cell architectures. A memory array includes a word line having both 1T and 2T portions. In the 1T portion, each sense amplifier is coupled to one memory cell along the word line. In the 2T portion, sense amplifiers are each coupled to more than one memory cell along the word line. For example, each sense amplifier in the 2T portion can be coupled to two bit lines, each of which intersects a memory cell along the word line. In some embodiments, the 2T portion can store a count value representing a count of accesses to the word line.

Description

Technical Field

[0001] This disclosure relates to devices and methods for 1T and 2T memory cell architectures. Background Technology

[0002] Information can be stored on memory cells of a memory device. Memory cells can be organized at the intersection of word lines (rows) and bit lines (columns). During access operations, word lines can be activated, and data can be read from memory cells along the bit lines to a sensing amplifier that detects the information stored in the memory cells. In some applications, it may be useful to change the timing of operation of certain memory cells along word lines. Summary of the Invention

[0003] One aspect of this disclosure relates to a device comprising: a word line coupled to a first memory cell, a second memory cell, and a third memory cell; a first sense amplifier coupled to the first memory cell; and a second sense amplifier coupled to the second memory cell and the third memory cell.

[0004] Another aspect of this disclosure relates to a device comprising: a word line coupled to a plurality of memory cells, the plurality of memory cells including a first plurality of memory cells and a second plurality of memory cells; and a plurality of sense amplifiers, including a first plurality of sense amplifiers and a second plurality of sense amplifiers, wherein each of the first plurality of sense amplifiers is coupled to one of the first plurality of memory cells, and wherein each of the second plurality of sense amplifiers is coupled to two of the second plurality of memory cells.

[0005] Another aspect of this disclosure relates to a device comprising: a word line coupled to a plurality of memory cells; a first sense amplifier section including a first plurality of sense amplifiers; a second sense amplifier section including a second plurality of sense amplifiers; a first portion of the first and second plurality of sense amplifiers configured to be activated by a first column select signal, wherein each of the first portions of the first and second plurality of sense amplifiers is coupled to one of the plurality of memory cells coupled to the word line; and a second portion of the first plurality of sense amplifiers configured to be activated by a second column select signal, wherein each of the second portions of the first plurality of sense amplifiers is coupled to more than one of the plurality of memory cells coupled to the word line. Attached Figure Description

[0006] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2This is a block diagram of a memory cell array according to an embodiment of the present disclosure.

[0008] Figure 3 This is a block diagram of a refresh address control circuit according to an embodiment of the present disclosure.

[0009] Figure 4 This is a schematic diagram of a memory array according to some embodiments of the present disclosure.

[0010] Figure 5 This is a schematic diagram of a memory array according to some embodiments of the present disclosure.

[0011] Figure 6 This is a schematic diagram of a memory array according to some embodiments of the present disclosure.

[0012] Figure 7 This is a schematic diagram of a memory array according to some embodiments of the present disclosure.

[0013] Figures 8A-8B This is an example layout of a sense amplifier according to some embodiments of the present disclosure.

[0014] Figure 9A and 9B These are example layouts and timing diagrams of memory arrays according to some embodiments of the present disclosure.

[0015] Figure 10A and 10B These are example layouts and timing diagrams of memory arrays according to some embodiments of the present disclosure. Detailed Implementation

[0016] The following description of certain embodiments is exemplary in nature only and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form part of this document and illustrate specific embodiments in which the described systems and methods can be practiced by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, certain features will not be described in detail where they are obvious to those skilled in the art, so as not to obscure the description of the embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is limited only by the appended claims.

[0017] Information in a memory array can be accessed via one or more access operations, such as read or write operations. During a read operation, a word line is activated, and data is read from the memory cells along the word line along the bit lines coupled to those corresponding memory cells. A sense amplifier coupled to the bit line detects whether the voltage along the bit line indicates logic high or logic low and drives the voltage along the bit line to the appropriate voltage level. One or more bit lines can then be coupled to the corresponding input / output (I / O) lines to read the voltage on the bit lines. Similarly, during a write operation, a bit line can be coupled to an I / O line, and a sense amplifier can provide the data along the bit line to be written to the memory cell. The memory takes some time to access the memory cell along a given word line. In some applications, it may be useful for different memory cells to have different access speeds. One of the limiting factors determining access speed can be the time spent sensing the relatively small voltage generated by the charge stored in a single memory cell.

[0018] This disclosure relates to apparatus, systems, and methods for 1T and 2T memory cell architectures. A given word line may have a plurality of memory cells along it, comprising a first portion and a second portion of the memory cells. Along the first portion, each memory cell may be coupled to a separate sense amplifier along a corresponding bit line, which may be referred to as a 1T architecture. In the second portion, each sense amplifier is coupled to more than one memory cell (e.g., each sense amplifier may have two bit lines coupled to it together in a shorted manner), which may be referred to as a 2T architecture. 2T may have increased access speed compared to 1T architecture because both memory cells store the same logic value and therefore both contribute charge to the voltage read by the sense amplifier.

[0019] An example application of this architecture is a memory where the access count associated with each row is stored in the memory cells of that row. Repeated accesses to a word line of memory (e.g., a "row hammer" attack) can cause an increased rate of memory degradation in memory cells of nearby word lines. To mitigate this problem, the memory can store the access count associated with that row along designated counter memory cells along each row. Because those counter memory cells must undergo a read-modify-write cycle with each access operation (e.g., to read the count, update the count, and then write the updated count back to the counter memory cell), it can be useful for those counter memory cells to operate at a faster timing than the memory cells along the rest of the word line. Accordingly, the counter memory cells can use a 2T architecture, while the rest of the memory cells along the word line can use a 1T architecture.

[0020] Although the term 2T is used herein, and although embodiments may be described with respect to arrangements in which two memory cells are coupled together to store the same bits, it should be understood that in other embodiments, two or more memory cells may be coupled together in a 2T region. For example, in some embodiments, three memory cells may exist, each with its bit lines shorted together.

[0021] Figure 1 This is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0022] Semiconductor device 100 includes memory array 118. Memory array 118 is shown as containing multiple memory banks. Figure 1 In one embodiment, memory array 118 is shown as comprising eight memory banks BANK0 to BANK7. In other embodiments, memory array 118 may comprise more or fewer memory banks. Each memory bank comprises multiple word lines WL (rows), multiple bit lines BL (columns), and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. Some memory cells MC along the word lines may be 2T memory cells 126. 2T memory cells 126 may be similar to other memory cells in memory array 118 (e.g., 1T memory cells), except that 2T memory cells 126 are organized such that pairs of memory cells are coupled together to store the same bit. For example, two memory cells in 2T region 126 may have bit lines shorted together. Other arrangements connecting memory cells in 2T region 126 may be used in other exemplary embodiments. This document, for example, in... Figure 4-8B The example layout of 2T zone 126 is described in the text.

[0023] Memory device 100 may use 2T region 126 to store a count value XCount associated with the number of accesses to word lines. For example, memory cells along 2T region 126 may be used to store bits of the number XCount, and memory cells along 2T region 126 may be counter memory cells. For example, if the number XCount is an N-bit binary number, there may be 2N memory cells shorted together along 2T region 126 to store N bits. The data bus associated with 2T memory region 126 may be coupled to refresh address control circuitry 116. In some embodiments, the data bus associated with counter memory cells 126 may be decoupled from the data bus that couples other memory cells to I / O circuitry 122.

[0024] The selection of word line WL is performed by row decoder 108, and the selection of bit line BL is performed by column decoder 110. Figure 1In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit line BL is coupled to a corresponding sense amplifier (SAMP). Read data from bit line BL is amplified by the sense amplifier SAMP and passed to read / write amplifier 120 via complementary local data line (LIOT / B), transmission gate (TG), and complementary master data line (MIOT / B). Conversely, write data output from read / write amplifier 120 is passed to the sense amplifier SAMP via complementary master data line MIOT / B, transmission gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL. Information can generally be read from and written to 2T memory cell 126 in a similar manner. In embodiments where the 2T memory cell stores a count value XCount, data in the 2T memory cell 126 is read and written by refresh address control circuitry 116.

[0025] The semiconductor device 100 may employ multiple external terminals, including: a command and address (C / A) terminal coupled to the command and address bus to receive commands and addresses; a CS signal clock terminal for receiving clock CK and / CK; a data terminal DQ for providing data; and a power supply terminal for receiving supply potentials VDD, VSS, VDDQ and VSSQ.

[0026] An external clock CK and / or CK is supplied to the clock terminal of input circuit 112. The external clocks may be complementary. Input circuit 112 generates an internal clock ICLK based on the CK and / or CK clocks. The ICLK clock is provided to command decoder 110 and to internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. An internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits contained in input / output circuit 122, for example, to a data receiver to time the reception of written data.

[0027] A memory address can be supplied to the C / A terminal. The memory address supplied to the C / A terminal is passed to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD, which indicates a bank in the memory array 118 containing the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD used to indicate the memory cell to be accessed.

[0028] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0029] Device 100 can receive access commands as row activation commands ACT. When the row activation command ACT is received, the row activation command ACT is supplied to the memory address BADD and the row address XADD in a timely manner.

[0030] Device 100 can receive access commands as read commands. When a read command is received, a read command is supplied in a timely manner for the bank address BADD and column address YADD to read read data from the memory cells in memory array 118 corresponding to row address XADD and column address YADD. The read command is received by command decoder 106, which provides an internal command such that the read data from memory array 118 is provided to read / write amplifier 120. The read data is output to the outside via input / output circuitry 122 from data terminal DQ. The access count XCount stored in the 2T memory cell 126 of the row associated with row address XADD is read to refresh address control circuitry 116, and the updated value XCount' of the access count is written back to the 2T memory cell 126 of row XADD.

[0031] Device 100 can receive access commands as write commands. When a write command is received and is supplied to the bank address BADD and column address YADD in a timely manner, write data supplied to the data terminal DQ is written to the memory cells in the memory array 118 corresponding to the row and column addresses. The write command is received by command decoder 106, which provides an internal command causing the write data to be received by the data receiver in input / output circuit 122. A write clock can also be provided to an external clock terminal for timing the data receiver in input / output circuit 122 to receive the write data. The write data is supplied to read / write amplifier 120 via input / output circuit 122 and from read / write amplifier 120 to memory array 118 for writing into memory cells MC. Similar to the read operation described above, the access count Xcount stored in the 2T memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value Xcount' of the access count is written back to the 2T memory cell 126 of the row XADD.

[0032] The device 100 may also receive commands that cause it to perform an automatic refresh operation. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating an automatic refresh command. In some embodiments, the automatic refresh command may be externally issued to the memory device 100. In some embodiments, the automatic refresh command may be periodically generated by a component of the device. In some embodiments, the refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF may be activated once immediately after the command input, and thereafter may be activated cyclically at desired internal timings. Therefore, the refresh operation may continue automatically. A self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to the IDLE state.

[0033] The refresh signal AREF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which refreshes the word line WL indicated by the refresh row address RXADD. The refresh address control circuit 116 can control the timing of the refresh operation and can generate and provide the refresh address RXADD. The refresh address control circuit 116 can be controlled to change the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address), or can operate based on internal logic.

[0034] The refresh address control circuit 116 can selectively output a target refresh address (e.g., the victim address) or an automatic refresh address (or auto-refresh address) as the refresh address RXADD. The automatic refresh address can be a series of addresses provided based on the activation of the automatic refresh signal AREF. The refresh address control circuit 116 can cycle through the series of automatic refresh addresses at a rate determined by AREF. In some embodiments, the sequence of automatic refresh addresses may include all addresses in the memory bank 118. In some embodiments, the automatic refresh signal AREF can be issued at a certain frequency, causing most or all addresses in the memory bank 118 to be refreshed within a certain cycle, said cycle being based on the expected rate of information decay in the memory cell MC.

[0035] The refresh address control circuit 116 can also determine the target refresh address (e.g., the victim address corresponding to the victim row) based on the access patterns of nearby addresses in the memory array 118 (e.g., the attacker address associated with the attacker row). The refresh address control circuit 116 can monitor accesses to different word lines WL of the memory bank. When the row decoder 108 sends an access command to a specific row, the information of the 2T memory cells 126 along that row can be read into the refresh address control circuit 116 as an access count Xcount. The refresh address control circuit 116 can determine the access count of the row based on the value stored in the 2T memory cells 126 of the accessed row.

[0036] The refresh address control circuit 116 can determine whether an accessed row is an aggressor row based on access counts from the 2T memory cell 126. If the current row is not an aggressor row, the access count value can be changed, and the refresh address control circuit can then write the new value of the access count back to the counter memory cell 126 of the accessed row. If the refresh address control circuit 116 determines that the accessed row is an aggressor, the refresh address control circuit 116 can use the row address XADD of the accessed row to determine one or more victim row addresses and provide them as refresh address RXADD as part of the target refresh operation. When an accessed row is determined to be an aggressor, the access count Xcount associated with the row can be reset (e.g., to a minimum value, such as 0). In some embodiments, the refresh address control circuit 116 can queue (e.g., in a register) the identified aggressor addresses for later use in the target refresh operation.

[0037] The refresh address RXADD can be timed based on the timing of the refresh signal AREF. The refresh address control circuit 116 may have time slots corresponding to the timing of AREF, and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the target refresh address may be published in a time slot that would otherwise be assigned to an auto-refresh address (e.g., "stolen"). In some embodiments, certain time slots may be reserved for the target refresh address, and the refresh address control circuit 116 may determine whether to provide the target refresh address, not provide an address during the time slot, or instead provide an auto-refresh address during the time slot.

[0038] The target refresh address can be based on the access characteristics of the row address XADD received from the address decoder 104 over time. For example, the access characteristics can be determined based on the value of the access count Xcount stored in the 2T memory cell 126. The refresh address control circuit 116 can use different methods to calculate the target refresh address based on the row address XADD identified as an attacker address based on the access count. For example, the refresh address control circuit 116 can determine whether a given row is an attacker address, and then calculate and provide the address of the victim address corresponding to the attacker address as the target refresh address. In some embodiments, more than one victim address may correspond to a given attacker address. In this case, the refresh address control circuit can queue multiple target refresh addresses and sequentially provide the multiple target refresh addresses when it determines that a target refresh address should be provided. The refresh address control circuit 116 can provide the target refresh address immediately, or it can queue the target refresh addresses to provide them at a later time (e.g., in the next time slot available for target refresh).

[0039] Power supply potentials VDD and VSS are supplied to the power supply terminals. These potentials VDD and VSS are then supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifier SAMP included in the memory array 118, and internal potential VPERI is used in many peripheral circuit blocks.

[0040] Supply potentials VDDQ and VSSQ are also supplied to the power supply terminals. These supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of this disclosure, the supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the supply potentials VDD and VSS supplied to the power supply terminals. The supply potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0041] Figure 2 This is a block diagram of a memory cell array according to an embodiment of the present disclosure. The memory cell array 200 may represent, for example... Figure 1 This is an exemplary portion of a memory array, such as memory array 118. Memory cell array 200 includes multiple word lines WL (rows) and bit lines BL (columns). Row drivers 234 are coupled to rows. For example, multiple memory cells MC, such as instance memory cell 230, are located at the intersection of rows and columns. A portion of the memory cells along a given word line may be configured using a 2T architecture, for example, in 2T region 226, while the remainder of the memory cells along the word line uses a 1T architecture. Memory array 200 includes several sense amplifiers 232 and 233. Sense amplifiers 232 and 233 may be generally similar to each other, except that sense amplifier 232 is coupled to bit lines in the 1T region, while sense amplifier 233 is coupled to bit lines in the 2T region 226.

[0042] Each memory cell MC can store information. In some embodiments, the information can be stored as binary code, and each memory cell MC in the 1T area can store one bit, while each pair of memory cells MC in the 2T area 226 can store one bit, which can be at a logic high or logic low level. Example memory cell 230 illustrates a specific embodiment that can be used to store information bits in some embodiments. Other types of memory cells can be used in other embodiments. In example memory cell 230, a capacitive element stores the information bit as a charge. A first charge level can represent a logic high level, and a second charge level can represent a logic low level. One node of the capacitive element is coupled to a reference voltage (e.g., VSS). The other node of the capacitive element is coupled to a switch. In example memory cell 230, a transistor is used to implement the switch. The sensing node of the switch (e.g., the gate of the transistor) is coupled to a word line. The voltage along the word line can be set by the row driver 234 to close the switch in the memory cell MC, thereby coupling the capacitive element (or other bit storage element) to the associated bit line BL to access the word line WL.

[0043] Sensing amplifiers 232 and 233 can read or write the value of an information bit along bit line BL (or, in 2T region 226, a bit line) to a memory cell MC (or memory cell) at the accessed word line WL. Sensing amplifiers 232 / 233 can (e.g., by amplifying a voltage) convert the signal along the bit line into a signal 'readable' by other elements of the memory device. The bit line can be coupled to input / output circuitry (e.g., via a corresponding column selection switch) via a corresponding column selection switch. Figure 1 The input / output circuit 122), wherein the column selection switch can be a column selection transistor activated by the column selection signal CS. Figure 2 In the instance view, six bit lines are shown: four "normal" bit lines accessed by the corresponding column select signals CS1 to CS4, and two bit lines in area 226 of 2T accessed by a single column select signal CSx. Accordingly, Figure 2 Each word line stores a total of 5 bits. It should be understood that... Figure 2 It is a simplified view and can use more (or fewer) memory cells, and / or different ratios of normal memory cells to 2T memory cells.

[0044] During an instance read operation, when accessing word line WL, memory cell MC can provide its charge to coupled bit line BL, which can cause a change in voltage and / or current along bit line BL. Sensing amplifier 232 can determine the logic level of accessed memory cell MC based on the resulting voltage and / or current along bit line BL, and can provide a signal corresponding to the logic level to input / output circuitry via column select transistor.

[0045] During a write operation, sense amplifier 232 may receive from input / output circuitry a signal indicating the logic level to be written to the accessed memory cell. Sensing amplifier 232 may provide a voltage and / or current along a coupled bit line BL (e.g., along a bit line with an active column select transistor) corresponding to the logic level to be written. The voltage and / or current along bit line BL may charge capacitive elements at the intersection of the bit line and the accessed word line to a charge level associated with the logic level being written. In this way, by specifying the row to be accessed and the bit line from which data is recorded (and / or to which data is written), a specific memory cell MC can be accessed during one or more operations of the memory device.

[0046] During an instance refresh operation (target or auto refresh), the word line WL to be refreshed can be read, and then the logic value read from each memory cell along the word line can be written back to the same memory cell. In this way, the charge level in the refreshed memory cell MC can be restored to the complete value associated with the logic level stored in the memory cell.

[0047] Some memory cells along each of the word lines can be configured as 2T memory cells 226. 2T memory cells 226 can be substantially similar to other 1T memory cells of the memory array 200. In some embodiments, 2T memory cells 226 can be physically identical to other memory cells MC. However, not every sense amplifier 232 is coupled to a single memory cell; in the 2T region, each sense amplifier 233 is coupled to multiple memory cells (e.g., a pair of memory cells). For example, bit lines BL in the 2T region... A and BL B They can be shorted together and coupled to a single sensing amplifier 233.

[0048] In some embodiments, the 2T memory cells 226 may be organized along specific bit lines and specific sense amplifiers of the memory array 200. Therefore, memory access to the 2T region can be controlled based on which bit lines and sense amplifiers are accessed. Similarly, the timing of access to the 2T region 226 may be controlled by control signals issued to the bit lines (e.g., B1A and BLB) and sense amplifier 233 of the 2T region. In some embodiments, the 2T memory cells 226 may be located along one end of the memory array 200. For example, if there are a certain number n 2T memory cells 226 along each word line, the 2T memory cells 226 may be the first n memory cells of the word line or the last n memory cells of the word line.

[0049] For the sake of clarity, Figure 2 Only a small number of word lines (WL) and bit lines (BL) (and their corresponding memory cells (MC)) are shown in this disclosure. More word lines (WL) and bit lines (BL) can be provided in the memory arrays disclosed herein. Similarly, Figure 2 Only a single pair of 2T bit lines of the counter memory cell 226 is shown. However, each word line WL may have several 2T memory cells 226. For example, there may be 16 or 32 2T memory cells (e.g., for storing 8 or 16 bits) along each word line. More or fewer 2T memory cells may be used in other embodiments. In some embodiments, the 2T memory cells 226 may be located together in an adjacency region. In some embodiments, the 2T memory cells 226 may be distributed along the word line, and 1T memory cells may be located between sets of 2T memory cells.

[0050] Figure 3 This is a block diagram of a refresh address control circuit according to an embodiment of the present disclosure. Figure 3 This illustrates an example embodiment of how memory can utilize word lines containing both 1T and 2T memory cells. Specifically, in... Figure 3 In one embodiment, the 2T memory cell is used as a counter memory cell 326 to store a count value associated with the number of accesses to the word line. Figure 3 This is just one example application, and in other example embodiments, the 2T memory cell can be used for other purposes.

[0051] In some embodiments, the refresh address control circuit 316 can be implemented Figure 1 The refresh address control circuit 316 is shown. Some internal components and signals of the refresh address control circuit 316 are shown to illustrate its operation. Dotted lines are shown around the refresh address control circuit 316, the row decoder 308, and the memory array 318 to indicate that in some embodiments, each of the components within the dotted lines may correspond to a specific memory bank, and these components may be repeated for each memory bank. In some embodiments, the components shown within the dotted lines may be associated with each memory bank. Therefore, multiple refresh address control circuits 316 and row decoders 308 may exist. For simplicity, only components for a single memory bank will be described.

[0052] The DRAM interface 340 can provide one or more signals to the address refresh control circuit 316 and the row decoder 308, which in turn (together with a column decoder not shown) can perform access operations on the memory array 318. The refresh address control circuit 316 may include an RHR status control 342, an intruder address register 344, a refresh address generator 350, a counter 346, and a threshold comparator 348. The counter 346 may be coupled to a counter memory cell 326 in the memory array 318.

[0053] When a row of memory array 318 is accessed, the value of the counter memory cell 326 along said row is read into counter 346. For example, several 2T memory cells can store bits of the binary number representing the count value. For example, if the number is a 16-bit number, then 32 2T memory cells can store the value.

[0054] Counter 346 can determine the access count value for the row based on the value read from counter memory unit 326. Counter 346 may be a counting control circuit that manages the count value stored in counter memory unit 326 (e.g., by reading the original data in counter memory unit 326 as a value, writing a new value to counter memory unit 326, etc.). Counter 346 can provide the count value to threshold comparator 348, which can determine whether the count value exceeds a threshold (e.g., whether the value is greater than the threshold). If the value does not exceed the threshold (e.g., if the value is less than or equal to the threshold), the counter can increment the count value and write the incremented count back to counter memory unit 326. If the value does exceed the threshold, the current address XADD can be determined to be the attacker address. If the current address XADD is the attacker address, a signal Agg can be provided to attacker address register 344, which can record (e.g., latch) the current value of row address XADD. If the count value exceeds the threshold, counter 346 can reset the count value by writing the initial count value (e.g., 0) back to counter memory unit 326.

[0055] RHR status controller 342 can provide the signal RHR to indicate that a target refresh operation should occur, such as a row hammer refresh (e.g., a refresh of a victim row corresponding to an identified attacker row). RHR status controller 342 can also provide an internal refresh signal IREF to indicate that an automatic refresh operation should occur. In response to RHR activation, attacker address register 344 can provide attacker address HitXADD, and refresh address generator 350 can provide refresh address RXADD, which can be one or more victim addresses associated with HitXADD. In response to IREF, refresh address generator 350 can provide an automatic refresh address as refresh address RXADD. Row decoder 308 can perform a refresh operation in response to refresh address RXADD and row hammer refresh signal RHR. Row decoder 308 can perform an automatic refresh operation based on refresh address RXADD and internal refresh signal IREF.

[0056] DRAM interface 340 may represent one or more components that provide signals to components of a memory bank. In some embodiments, DRAM interface 340 may represent a device coupled to a semiconductor memory device (e.g., Figure 1 The memory controller of the device 100). In some embodiments, the DRAM interface 340 may represent, for example, Figure 1The DRAM interface 340 includes components such as command address input circuit 102, address decoder 104, and / or command decoder 106. The DRAM interface 340 provides a row address XADD, an auto-refresh signal AREF, an activation signal ACT, and a precharge signal Pre. The auto-refresh signal AREF can be a periodic signal indicating when an auto-refresh operation will occur. The activation signal ACT can be provided to activate a given memory bank. The precharge signal Pre can be provided to precharge a given memory bank. The row address XADD can be a signal specifying one or more particular word lines of the memory array 318, and can be a signal containing multiple bits (which can be transmitted serially or in parallel).

[0057] Counter 346 and threshold comparator 348 work together to determine whether the access count for the row associated with the current row address XADD exceeds a threshold. When a given word line is accessed, the value stored in each of the counter memory cells 326 along the word line is read into counter 346, which interprets the value of counter memory cell 326 as access count XCount. Counter 346 interprets memory cell 326 by determining the value of access count XCount based on bits stored in counter memory cell 326. Threshold comparator 348 compares the value of access count XCount with a threshold. In some embodiments, the threshold value may be a programmable value. If the count value exceeds the threshold value, threshold comparator 348 provides a signal Agg. If the count value does not exceed the threshold, counter 346 increments the count value and writes the incremented value back to counter memory cell 326. If the count value does exceed the threshold, counter 346 resets the access count value to a minimum value and writes the reset value back to counter memory cell 326.

[0058] In some embodiments, if the accessed row remains active for a period of time, counter 346 may also increment the access count. Counter 346 may be coupled to a timer (e.g., an oscillator) that periodically activates a timing signal. After incrementing the access count when a row is accessed, counter 346 may increment the access count again whenever the timing signal is activated. In some embodiments, the access count may be compared to a threshold again whenever the timing signal is activated. In instance timing, counter 346 may increment the accessed row every 100-200 ns of its continued access. Other timing may be used in other instances. In embodiments with a timer, refresh address control circuitry 316 may use additional logic to monitor the activation of memory array 318 to prevent information loss (e.g., refresh address control circuitry 316 may ensure sufficient time to increment the access count before updating the value).

[0059] In some embodiments, counter 346 can directly determine whether the access count value exceeds a threshold, and the threshold comparator 348 can be omitted. For example, the counter can have a maximum value, and as it increments after reaching the maximum value, counter 346 can "roll" back to a minimum value. Counter 346 can provide a signal Agg in response to the rolling. Furthermore, since the counter value is reset to the minimum value, the rolled-back value of the counter can be written back to counter memory unit 326 to reset the counter memory unit after the signal Agg marks the accessed line as the intruder address.

[0060] In some embodiments, counter 346 and threshold comparator 348 may be physically close to memory array 318, such that the counter bus XCount is relatively short compared to other buses entering and exiting memory array 318. When comparator 348 or counter 346 determines that the value of XCount exceeds a threshold, signal Agg may be sent to intruder address register 344 (and / or other components of address refresh control circuitry 316). In some embodiments, counter 346 and comparator 348 may be closer to memory array 318 than other components of refresh address control circuitry 316 (e.g., RHR status control 342, intruder address register 344, and / or refresh address generator 350). In some embodiments, counter 346 and threshold comparator 348 may be circuitry local to memory array 318, while other components of refresh address control circuitry 316 may be bank-level circuitry. In some embodiments, only signal Agg needs to run to bank-level circuitry, which reduces the area and power required for the XCount bus.

[0061] The aggressor address register 344 may store one or more row addresses that have been identified as aggressor addresses based on their access counts. In response to a command signal Agg from a threshold comparator 348, the aggressor address register 344 may store the currently accessed row address XADD. The aggressor address register 344 may provide the stored address as a matching address HitXADD to a refresh address generator 350, which may calculate one or more victim addresses associated with the matching address HitXADD. In some embodiments, the aggressor address register 344 may be a latch circuit storing a single address. In some embodiments, the aggressor address register 344 may be a buffer storing multiple addresses and providing a first stored address as the matching address HitXADD. The aggressor address register 344 may switch to the next address in the register after the victim row associated with the first address has been refreshed.

[0062] RHR state controller 342 may receive an auto-refresh signal AREF and provide a row hammer refresh signal RHR. The auto-refresh signal AREF may be generated periodically and may be used to control the timing of refresh operations. The memory device may perform a series of auto-refresh operations to periodically refresh rows of the memory device. The RHR signal may be generated to indicate that the device should refresh a specific target row (e.g., the victim row) rather than an address from an auto-refresh address sequence. The RHR state controller 342 may use internal logic to provide the RHR signal. In some embodiments, the RHR state controller 342 may provide the RHR signal based on a specific number of AREF activations (e.g., every 4 activations of AREF). The RHR state controller 342 may also provide an internal refresh signal IREF, which may indicate that an auto-refresh operation should occur. In some embodiments, the signals RHR and IREF may be generated such that they are not both active at the same time (e.g., neither is both at a high logic level at the same time).

[0063] The refresh address generator 350 can receive a row hammer refresh signal RHR and a matching address HitXADD. The matching address HitXADD can represent an aggressor row. The refresh address generator 350 can determine the location of one or more victim rows based on the matching address HitXADD and provide said location as a refresh address RXADD. In some embodiments, victim rows can include rows that are physically adjacent to aggressor rows (e.g., HitXADD+1 and HitXADD-1). In some embodiments, victim rows can also include rows that are physically adjacent to physically adjacent rows of aggressor rows (e.g., HitXADD+2 and HitXADD-2). Other relationships between victim rows and identified aggressor rows can be used in other instances.

[0064] The refresh address generator 350 can determine the value of the refresh address RXADD based on the row hammer refresh signal RHR and the internal auto-refresh signal IREF. In some embodiments, when the IREF signal is active, the refresh address generator 350 can provide one of the auto-refresh address sequences. When the RHR signal is active, the refresh address generator 350 can provide a target refresh address, such as a victim address, as the refresh address RXADD.

[0065] The row decoder 308 can perform one or more operations on the memory array 318 based on received signals and addresses. For example, in response to the activation signal ACT and the row address XADD (and IREF and RHR being at low logic levels), the row decoder 308 directs one or more access operations (e.g., read operations) to the specified row address XADD. In response to the RHR signal being active, the row decoder 308 can refresh the refresh address RXADD. In some embodiments, the counter 346 can increment the access count stored in the counter memory cell 326 in response to a refresh operation on a given row. In some embodiments, the counter 346 can increment the access count without responding to a refresh operation.

[0066] Figure 4-7 This section showcases various example layouts of memory cell arrays containing 2T architecture regions. Each of these layouts represents a portion of a memory cell array containing representative sections of both the 1T and 2T regions, similar to... Figure 2 Array 200. Figure 4-7 Each view may only show a portion of the memory cell array, and the memory cell array may contain more or fewer memory cells, word lines, bit lines, etc. For example, Figure 4-7 Each view can show only a portion of the 2T area, and can use a larger (or smaller) number of memory cells within the 2T area. Because Figure 4-7 Each of these can contain many components that are roughly similar to each other, so for the sake of brevity, some details may only be described once. For example, they may only be described relative to... Figure 4 Describe the layout of the normal (e.g., 1T) area. However, it should be understood that the details of the normal area may also apply to other areas. Figure 5-7 Each of them.

[0067] Similarly, it should be understood that variations described with respect to one embodiment are equally applicable to other embodiments. For example, Figure 4-8B Each of these illustrates a memory layout in which each column select signal CS activates eight sense amplifiers (or four in a 2T zone), and two CS signals can be activated to read 16 bits of data (or fewer bits if a 2T zone is activated). However, relative to Figure 4-8B The described embodiments may also select more or fewer bits per CS signal.

[0068] Figure 4 This is a schematic diagram of a memory array according to some embodiments of the present disclosure. The memory array 400 may be included in some embodiments. Figure 1 In the memory array 118, and / or may be Figure 2 An implementation scheme for the memory array 200.

[0069] Memory array 400 includes a normal region 402 and a 2T region 450. Word lines, such as instance word line 406, may extend from the normal region 402 to the 2T region 450 and may be coupled to memory cells in both regions. In some embodiments, the normal region 402 may contain a different number of memory cells than the 2T region 450. For example, the normal region 402 may have more memory cells than the 2T region 450. In some embodiments, 8, 16, 32, or more or fewer memory cells may be in the 2T region 450.

[0070] exist Figure 4 In this embodiment, the 2T region 450 comprises both a 2T portion 452 and a 1T portion 454. Each portion 452 and 454 is activated by corresponding column select signals CSA and CSB. In the 2T portion, each sense amplifier is coupled to two adjacent bit lines and, via those bit lines, to two adjacent memory cells. Accordingly, when signal CSA is active, four sense amplifiers are activated to read 4 bits of information from 4 pairs of bit lines (and four pairs of memory cells). If only signal CSA is activated, 4 bits are read. If both CSA and CSB are activated, a total of 12 bits are read (e.g., in contrast to 16 bits in the case where both CS signals are activated in normal region 402).

[0071] Normal region 402 contains a plurality of memory cells 404. Each memory cell contains a capacitive element that stores charge. The amount of charge stored indicates a logic value stored in the memory cell. A transistor having a gate coupled to a word line has a node coupled to the bit line and the capacitive element. Accordingly, when a word line is selected and activated, the voltage on the word line couples the capacitive element to the bit line, which changes the voltage along the bit line. For example, a higher voltage (e.g., more charge on the capacitive element) may indicate logic high, while a lower voltage may indicate logic low.

[0072] The memory layout includes sense amplifier regions 410 and 412. Each sense amplifier region contains a set 414 of sense amplifiers. In a normal memory region 402, each sense amplifier is coupled to a pair of bit lines, each of which is coupled to a memory cell along a different word line. For example, each sense amplifier may be coupled to first and second word lines along first and second bit lines, which are adjacent to each other. A column select signal can activate the sense amplifiers in both sense amplifier regions 410 and 412, which are coupled to the bit lines coupled to the memory cells along the word lines. Those sense amplifiers may then be coupled to I / O lines.

[0073] During an instance read operation in normal region 402, word line 406 can be activated, and column select signals CS0 and CS1 can be provided. Each of the column select signals activates four sense amplifiers in sense amplifier regions 410 and 412. Every other memory cell along the activated word line 406 is coupled to a sense amplifier in one of regions 410 or 412. Each sense amplifier can be coupled to an active memory cell (e.g., along active word line 410) and an inactive memory cell (e.g., along an adjacent unselected word line). The active memory cell provides a voltage representing the stored logic value, while the bit line coupled to the inactive memory cell provides a reference voltage. Sensing amplifier 414 senses the difference between the voltage of the bit line coupled to the active memory cell and the reference voltage, and generates an output based on the sensed difference. Accordingly, by activating CS0, eight bits are read from eight memory cells along the word line, wherein the bits are read alternately by sense amplifier regions 410 and 412. Similarly, by activating CS1, another eight bits are read, for a total of 16 bits.

[0074] The 2T region 450 may have components generally similar to those of the normal region 402, such as memory cells 404 and sense amplifiers 414. Similarly, the 2T region 450 may be configured with sense amplifier regions 410 and 412. However, in the 2T region 450, particularly in the 2T portion 452, each sense amplifier 414 is coupled to two bit lines, which are coupled to adjacent memory cells along the same word line. Accordingly, the two memory cells coupled to the sense amplifiers can store the same information because the two memory cells are coupled to the same word line. Consequently, when the word line is activated (e.g., as part of a read or write operation) and a signal CSA is provided, each sense amplifier simultaneously provides (or receives) information from both active memory cells.

[0075] The 2T section 452 can use differential signal storage. The sense amplifier 414 may have a differential architecture with two inputs. However, unlike the normal region 402 (or 1T section 454) where each sense amplifier is coupled to an active bit line and a reference bit line, each sense amplifier 414 in the 2T section 452 is coupled to two bit lines, each of which is coupled to an active memory cell. During an instance write operation, the sense amplifier 414 may receive a voltage representing an information bit. The sense amplifier 414 drives the first bit line to the voltage representing the value of the bit and drives the second bit line to the voltage representing the logic complement of the value of the bit. For example, if the sense amplifier receives a voltage representing a logic high, the first bit line is driven high and the second bit line is driven low. The two active memory cells may then capture and store these values. Accordingly, while the two memory cells may store a single information bit, each memory cell may store complementary information bits. This increases the speed at which the sense amplifier can detect the stored bit, because instead of comparing the read value with a reference value, the sense amplifier is comparing the “true” voltage with its logic complement, which will result in a larger voltage difference (e.g., since the reference voltage is roughly halfway between logic high and logic low voltages).

[0076] During the instance read operation, word line 406 is activated. Signals CSA and CSB are available. In 1T section 454, as previously described relative to normal section 402, sense amplifiers in SA sections 410 and 412 are activated, and 8 bits are read from eight memory cells along a portion of word line 406 in 1T section 454. The activated sense amplifiers are labeled by box 460. In 2T section 452, signal CSA activates sense amplifiers in both sense amplifier sections 410 and 412; however, the sense amplifier in section 410 is not coupled to the active word line, and therefore its output is considered invalid and discarded. The sense amplifiers in section 412 are each coupled to bit lines coupled to a corresponding pair of adjacent memory cells along the activated word line. Because these memory cells store differential signals, one bit line is filled with the "true" value, and the other line is filled with its logical complement, thus allowing the sense amplifiers to read the bit values. Accordingly, four bits are read from section 412 in 2T section 452, for a total of 12 bits.

[0077] Figure 5 This is a schematic diagram of a memory array according to some embodiments of the present disclosure. The memory array 500 may be included in some embodiments. Figure 1 In the memory array 118, and / or may be Figure 2 An implementation scheme for the memory array 200.

[0078] The memory array 500 includes 2T regions 550, wherein each sense amplifier is coupled to a pair of memory cells along the same word line, and wherein a column select signal activates a single sense amplifier region in each segment of the 2T region 550. Accordingly, the 2T region 550 can store and read 8 bits from four bits in each segment 552 and 554.

[0079] Memory array 500 includes a 1T region 402. The 1T region 402 can be roughly similar to the previous one. Figure 4 The 1T region is described, and therefore, for the sake of brevity, the features and components already described will not be described again. Example selected word line 406 can extend from 1T region 402 into 2T region 450 and can be coupled to memory cells in both regions.

[0080] Similar to Figure 4 The 2T portion 452 of the 2T region 550, in which each sense amplifier is coupled to a pair of adjacent bit lines, which in turn are coupled to adjacent memory cells along a single word line. Accordingly, the paired memory cells store differential signals. Because the 2T region 550 contains multiple 2T portions (e.g., with...), Figure 4 The regions 450 form a contrast, so each region can alternate the word lines to which the sense amplifier region is coupled. For example, in the first region 552, the sense amplifier region can be coupled to memory cells along word lines shown above the sense amplifier region, while in the second region 554, the sense amplifier region can be coupled to memory cells along word lines shown below the sense amplifier region. In other words, example word line 406 is coupled to the sense amplifier in region 412 of region 552 (but not to the sense amplifier in region 410) and to the sense amplifier in region 510 of region 554 (but not to the sense amplifier in region 412).

[0081] and Figure 4 Compared to the 2T zone 450, in Figure 5 In section 550 of the 2T array, the column selection signal alternates between activating the sense amplifier regions in the first section 552 and the second section 554. This causes a single CS signal to activate every other sense amplifier region. For example, the signal CSA can activate the sense amplifier region 412 in section 552 but not the sense amplifier region 410. Similarly, the signal CSB can activate the sense amplifier region 410 in section 552 but not region 410 in section 554, and can activate region 412 in section 554, and so on, thus alternating word-by-word.

[0082] During an instance read operation, word line 406 can be activated, and every other column select signal CS can be activated in zone 550 of 2T. For example, column select signals CSA and CSC (not shown) can be activated. This activates zones such as those shown in boxes 560 and 562. Accordingly, a total of 8 bits can be read (from each of the four bits in zones 552 and 554).

[0083] Figure 6 This is a schematic diagram of a memory array according to some embodiments of the present disclosure. The memory array 500 may be included in some embodiments. Figure 1 In the memory array 118, and / or may be Figure 2 An implementation scheme for the memory array 200.

[0084] Memory array 600 includes a 1T region 402. The 1T region 402 can be roughly similar to the previous one. Figure 4 The 1T region is described, and therefore, for the sake of brevity, the features and components already described will not be described again. Example selected word line 406 can extend from 1T region 402 into 2T region 450 and can be coupled to memory cells in both regions.

[0085] The memory array 600 includes 2T regions 650, where each sense amplifier is coupled to two non-adjacent bit lines intersecting with (non-adjacent) memory cells along the same word line. Similar to... Figure 5 2T area 550, in Figure 6 In the 2T region 650, each column select signal activates four sense amplifiers coupled to two memory cells, for a total of four bits stored differentially in eight memory cells. However, in the memory array 600, a different layout is used, which utilizes both sense amplifier regions 410 and 412 in each of the portions 652 and 654.

[0086] Taking sense amplifier region 410 as an example, a first sense amplifier 656 is coupled to a memory cell coupled to word line 610 and to a memory cell along adjacent word line 612. Sensing amplifier 656 and other similar sense amplifiers are indicated by dotted lines to indicate that they are not in use (e.g., they may not be coupled to I / O lines, and / or signals along their I / O lines may be ignored). In some embodiments, dotted-line sense amplifiers may still be used (e.g., to operate serially and increase operating speed), but the dotted-line amplifiers may not have separate outputs.

[0087] Adjacent to sense amplifier 656 is sense amplifier 658. Sense amplifier 658 has a first input coupled to a memory cell along word line 406, the same memory cell coupled to amplifier 656. Sense amplifier 658 also has a second input coupled to a memory cell not adjacent to the memory cell coupled to the first input. For example, two memory cells coupled to sense amplifier 658 may be separated by memory cells coupled to sense amplifiers in sense amplifier region 412.

[0088] Accordingly, during an instance read operation, the column select signal CSA can be activated, and sense amplifier regions 410 and 412 are activated. In each region, two of the four sense amplifiers are activated (e.g., 658) and coupled to the I / O line, with a total of four bits stored differentially in eight memory cells in section 652.

[0089] Figure 7 This is a schematic diagram of a memory array according to some embodiments of the present disclosure. The memory array 500 may be included in some embodiments. Figure 1 In the memory array 118, and / or may be Figure 2 An implementation scheme for the memory array 200.

[0090] Memory array 600 includes a 1T region 402. The 1T region 402 can be roughly similar to the previous one. Figure 4 The 1T region is described, and therefore, for the sake of brevity, the features and components already described will not be described again. Example selected word line 406 can extend from 1T region 402 into 2T region 450 and can be coupled to memory cells in both regions.

[0091] The memory array 700 can be broadly similar to Figure 6 The memory array 600, however, in the memory array 700, in the 2T region 750, each column select signal activates a sense amplifier corresponding to 8 bits of information, the same as each column select signal in the normal region 402. Accordingly, each column select signal in the 2T region 752 can activate 8 sense amplifiers in each sense amplifier region (e.g., 410 and 412), four of which are coupled to I / O lines, and each activated CS signal and activated word line corresponds to a total of four bits from each SA region. Therefore, each activated CS signal in the 2T region 752 provides the same number of bits of information as each activated CS signal in the normal region 402.

[0092] Figures 8A-8B This is an example layout of a sense amplifier according to some embodiments of the present disclosure. Sensing amplifiers 802 and 804 represent those that can be used as... Figure 2 Sensing amplifier 232, Figure 4-7 414 Figure 6 656 and 658, and / or Figure 7 Examples of 756 and 758 sense amplifiers. Specifically, Figure 8A and 8B The display can be, for example Figure 6 and 7 Examples of implementations include instance layouts for coupling sensing amplifiers to memory cells, wherein each pair of sensing amplifiers in the sensing amplifier region is used to sense data from a pair of memory cells.

[0093] Each sense amplifier may include a pair of cross-coupled inverters, with the input of each inverter serving as one of the inputs of the sense amplifier. Each sense amplifier includes two pairs of p-type and n-type transistors coupled between high and low voltages (e.g., VDD and VSS) representing high and low logic levels. A node between each pair is coupled to the gate of the other pair. Each node serves as one of the inputs of the sense amplifier, and one node is also coupled to an I / O line (e.g., via a transistor acting as a switch, which can be activated by a CS signal).

[0094] Figure 8A The demonstrations can be implemented separately. Figure 6 Transistors 656 and 658 and / or Figure 7 The transistors 756 and 758 are sense amplifiers 802 and 804. In this embodiment, sense amplifier 802 remains decoupled, while sense amplifier 804 is coupled to a pair of memory cells.

[0095] Figure 8B The demonstrations can be implemented separately. Figure 6 Transistors 656 and 658 and / or Figure 7 The transistors 756 and 758 are used in sense amplifiers 802 and 804. In this embodiment, the two sense amplifiers are coupled together, and both are active to sense and amplify the voltages entering and exiting the memory cells. The first input of sense amplifier 802 is coupled to the second input and the first bit line of sense amplifier 804, while the second input of sense amplifier 802 is coupled to the first input and the second bit line of sense amplifier 804.

[0096] Figure 9A and 9B These are example layouts and timing diagrams of memory arrays according to some embodiments of the present disclosure. The memory array 900a may be, in some embodiments,... Figure 1 memory array 100 and / or Figure 4 The implementation scheme of 400. Timing diagram 900b shows the timing of an instance of operation in memory array 900a.

[0097] The memory array 900a is organized into a plurality of memory pads 904, each containing a plurality of word lines and bit lines. Each memory pad 904 has associated logic organized in a region 908 between regions 904. For example, a sense amplifier may be located in the logic region 908. A global logic region 902 contains various circuits, such as global input / output circuits coupled to the memory pads 904.

[0098] In memory array 900a, memory pad 904 may contain only a 1T memory cell architecture (e.g., memory pad 904 may represent...). Figure 4-7 (Normal area 402). Meanwhile, the additional memory pad 906 contains only a 2T memory cell architecture. Accordingly, the 2T memory cells in the additional memory pad 906 can be activated separately from the 1T memory cells in the other memory pads 904. In some embodiments, the additional memory pad 906 may be located at one end of a word line. In other embodiments, the additional memory pad 906 may be located in other locations.

[0099] Timing diagram 900b illustrates an example of access operation timing. Waveform CSn represents the column select signal in normal memory pad 904 (e.g., Figure 4-7 The timing of CS0 or CS1 in the extra memory pad 906. The waveform CSx represents the bit line (e.g., in the extra memory pad 906) Figure 4-7 The activation of the CSA or CSB. Because the memory cells in pad 904 and additional pad 908 can be operated independently, access operations such as read and write can be performed in parallel in memory pads 904 and 908.

[0100] For example, if the memory cells in the additional pad 908 are used to store a count value, the column signal CSx may need to remain active for a sufficiently long time to change the count value for a sustained read operation and subsequently for a write operation. As can be seen from timing diagram 900b, because the memory cells can be accessed in parallel, the column signal CSx can be activated before the normal zone signal CSn. This allows the column signals CSn and CSx to become inactive at approximately the same time, thus allowing the time tWR defined in this specification to elapse before another access operation can be performed.

[0101] Figure 10A and 10B These are example layouts and timing diagrams of memory arrays according to some embodiments of this disclosure. The memory array 1000a may be, in some embodiments,... Figure 1 memory array 100 and / or Figure 4 The implementation scheme of 400. Timing diagram 1000b shows the timing of an instance of operation in memory array 1000a. Because Figure 10A and 10B They are roughly similar to Figure 9A and9B Therefore, for the sake of simplicity, it will not be relative to Figures 10A-10B Repetition is similar to relative Figure 9A and 9B The description of the components and operations.

[0102] The memory array 1000a is organized into a plurality of memory pads 1004, each containing a plurality of word lines and bit lines. Each memory pad 1004 has associated logic organized in a region 1008 between regions 1004. For example, a sense amplifier may be located in the logic region 1008. A global logic region 1002 contains various circuits, such as global input / output circuits coupled to the memory pads 1004.

[0103] The memory array 1000a includes a column select signal 1006 (generally referred to here as CSx) located in pad 1004 (e.g. Figure 4-7 The sense amplifier in the 2T region activated by the CSA or CSB, the pad also includes a 1T coupled and... Figure 10A Other column selection signals not shown in the view (e.g., Figure 4-7 The sense amplifier operates on either CS0 or CS1. Accordingly, each memory pad 1004 may include both 1T and 2T architectures. In an embodiment where the 2T memory cells are used to store count values, the count values ​​may be distributed across multiple pads 1004.

[0104] Timing diagram 1000b shows that the normal column select signal CSn and the 2T column select signal CSx are provided sequentially. Correspondingly, when signal CSn becomes inactive, signal CSx can become active. However, the 2T memory cells accessed when signal CSx is active may require a short recovery time after the access operation. Therefore, the access time of CSx and tWR required by the CSx sense amplifier can be equal to or less than the tWR required by the CSn access operation. Accordingly, accessing the 2T memory cells does not increase the total time used for the access operation.

[0105] In some embodiments of this disclosure, a targeted refresh of one or more victim word lines associated with an accessed word line may be performed based on comparing an access count to a threshold. For example, if the access count is greater than a threshold, the accessed word line may be identified as an aggressor word line. Refreshing may be performed in response to the access count of the accessed word line being greater than a threshold (e.g., in...). Figure 3 Intruder address register 344 or Figure 4 In section 444, the address associated with the fetch line is latched. The address refresh control circuitry (e.g., ...) Figure 1 The refresh address control circuit 116 or Figure 3(316) can instruct that a target refresh operation should be performed at a timing based on a memory-based automatic refresh signal. When the target refresh operation is performed, the refresh address control circuitry can calculate the address associated with one or more victim word lines that are associated with the attacker address retrieved from the latch. In some embodiments, these victim lines may be adjacent to the accessed word lines. The victim word lines can then be refreshed. In this way, the memory device can count accesses to word lines of the memory device, identify certain word lines as attacker word lines based on the access count, and perform a target refresh of the victim word lines associated with the identified attacker word lines.

[0106] It should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed between separate means or parts of means of a system, apparatus, or method according to the invention.

[0107] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Thus, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device for memory operations, comprising: Word lines, which are coupled to the first memory cell, the second memory cell, and the third memory cell; A first sensing amplifier, which is coupled to the first memory cell; A second sensing amplifier is coupled to the second memory cell and the third memory cell; as well as A counter circuit coupled to the second sense amplifier, wherein the counter circuit is configured to adjust the count values ​​partially stored in the second memory cell and the third memory cell based on access to the word line.

2. The device of claim 1, further comprising a refresh control circuit configured to store the address associated with the word line as an intruder address based on the count value exceeding a threshold.

3. The device of claim 1, wherein the second memory cell and the third memory cell are adjacent to each other.

4. The device according to claim 1, wherein the second memory cell and the third memory cell are not adjacent to each other.

5. The device of claim 1, further comprising a third sensing amplifier coupled to the second memory cell and the third memory cell.

6. The device of claim 1, wherein the word line is further coupled to a fourth memory cell and a fifth memory cell. The device further includes a third sensing amplifier coupled to the fourth memory cell and the fifth memory cell. The second sensing amplifier is located in the first sensing amplifier region, and the third sensing amplifier is located in the second sensing amplifier region.

7. The device of claim 1, wherein the second sensing amplifier includes a first input coupled to the second memory cell and a second input coupled to the third memory cell.

8. A device for memory operations, comprising: A word line coupled to a plurality of memory cells, the plurality of memory cells including a first plurality of memory cells and a second plurality of memory cells, wherein the second plurality of memory cells are configured to store a count value associated with the number of accesses to the word line; as well as Multiple sensing amplifiers, including a first plurality of sensing amplifiers and a second plurality of sensing amplifiers, Each of the first plurality of sensing amplifiers is coupled to one of the first plurality of memory cells, and each of the second plurality of sensing amplifiers is coupled to two of the second plurality of memory cells.

9. The device of claim 8, wherein each of the second plurality of sensing amplifiers is configured to sense bits differentially in the two of the second plurality of memory cells.

10. The device of claim 8, wherein each of the second plurality of sense amplifiers is coupled to two non-adjacent memory cells of the second plurality of memory cells.

11. The device of claim 8, wherein the second plurality of memory cells are located in a different pad than the first plurality of memory cells.

12. The device of claim 8, wherein the second plurality of memory cells are located in the same pad as the first plurality of memory cells.

13. A device for memory operations, comprising: Word lines, which are coupled to multiple memory cells; A first sensing amplifier section, which includes a first plurality of sensing amplifiers; The second sensing amplifier section includes a second plurality of sensing amplifiers; First portions of the first and second plurality of sense amplifiers are configured to be activated by a first column selection signal, wherein each of the first portions of the first and second plurality of sense amplifiers is coupled to one of the plurality of memory cells coupled to the word line; as well as A second portion of the first plurality of sense amplifiers is configured to be activated by a second column select signal, wherein each of the second portions of the first plurality of sense amplifiers is coupled to more than one of the plurality of memory cells coupled to the word line.

14. The device of claim 13, wherein the first portion of the first and second plurality of sense amplifiers is configured to provide a first number of bits in response to the first column select signal, wherein the second portion of the first plurality of sense amplifiers is configured to provide a second number of bits in response to the first column select signal, and wherein the second number is less than the first number.

15. The device of claim 13, wherein the first portion of the first and second plurality of sense amplifiers is configured to provide a first number of bits in response to the first column select signal, wherein the second portion of the first plurality of sense amplifiers is configured to provide a second number of bits in response to the first column select signal, and wherein the second number is the same as the first number.

16. The device of claim 13, wherein a second portion of the second plurality of sense amplifiers is configured to be activated by a third column select signal, and wherein each of the second portions of the second plurality of sense amplifiers is coupled to one or more memory cells along a second word line.

17. The device of claim 13, wherein the second portion of the first plurality of sense amplifiers further comprises an additional sense amplifier not activated by the second column selection signal.

18. The device of claim 13, wherein each of the second portions of the first plurality of sense amplifiers is configured to differentially store bits in a first and a second of the plurality of memory cells.

Images