Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same, the method of forming the semiconductor device includes forming a first dummy gate structure over a first region of a substrate and a second dummy gate structure over a second region of the substrate, the first and second regions of the substrate having a first composition, the first composition having a first etch rate; implanting the first region of the substrate with dopants laterally adjacent to the first dummy gate structure, wherein after the implanting the first region, the first region has a second composition, the second composition having a second etch rate, the second etch rate being different than the first etch rate; etching a first recess in the first region of the substrate having the second composition and etching a second recess in the second region having the first composition; and epitaxially growing a first source / drain region in the first recess and a second source / drain region in the second recess.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for their fabrication. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements on the substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to some embodiments disclosed herein, a method of forming a semiconductor device includes the following steps: forming a first dummy gate structure over a first region of a substrate and forming a second dummy gate structure over a second region of the substrate, wherein the first region and the second region of the substrate have a first composite and the first composite has a first etch rate; laterally implanting a plurality of dopants into the first region of the substrate adjacent to the first dummy gate structure, wherein after implanting the first region, the first region has a second composite and the second composite has a second etch rate different from the first etch rate; etching a first recess in the first region of the substrate having the second composite and etching a second recess in the second region having the first composite; and epitaxially growing a first source / drain region in the first recess and epitaxially growing a second source / drain region in the second recess.

[0005] According to some embodiments disclosed herein, a method of forming a semiconductor device includes the following steps: forming a first gate structure over a first semiconductor region and forming a first isolation region adjacent to the first semiconductor region; forming a second gate structure over a second semiconductor region and forming a second isolation region adjacent to the second semiconductor region; forming a patterned mask layer having an opening, wherein the opening exposes a plurality of exposed portions of the first semiconductor region, the first gate structure, and the first isolation region, wherein the second semiconductor region, the second gate structure, and the second isolation region adjacent to the second gate structure remain covered by the patterned mask layer. The process involves: implanting a dopant into the plurality of exposed portions of the first semiconductor region, the first gate structure, and the first isolation region, wherein the exposed portion of the first isolation region has a first concentration profile of the dopant extending from an upper surface of the first isolation region to a semiconductor substrate, wherein the first concentration profile has a raised shape; removing the patterned mask layer; etching the exposed portion of the first semiconductor region to form a first recess in the first semiconductor region and a second recess in the second semiconductor region; and forming a first source / drain region in the first recess and a second source / drain region in the second recess.

[0006] According to some embodiments of this disclosure, a semiconductor device includes a first region and a second region. The first region includes: a plurality of first gate electrodes having a first spacing; and a first epitaxial region disposed within a substrate and between the plurality of first gate electrodes, the first epitaxial region having a first depth below a top surface of the substrate. The second region includes: a plurality of second gate electrodes having a second spacing greater than the first spacing; and a second epitaxial region disposed within the substrate and between the plurality of second gate electrodes, the second epitaxial region having a second depth below the top surface of the substrate, the first depth being between 95% and 105% of the second depth. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 The illustration shows an example of a FinFET in three-dimensional view according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7, Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 19A and Figure 19B A cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments;

[0010] Figure 20A , Figure 20B , Figure 20C , Figure 20D and Figure 20E The illustration shows an example of an intermediate stage presented in three dimensions according to some embodiments.

[0011] [Symbol Explanation]

[0012] 50:Substrate

[0013] 50N: N-type region

[0014] 50P: P-type area

[0015] 51: Divider

[0016] 52: Fins

[0017] 52A: First fin

[0018] 52B: Second fin

[0019] 52C: Third fin

[0020] 54: Insulating materials

[0021] 56: Shallow trench isolation zone

[0022] 58: Passage Area

[0023] 60: Dummy dielectric layer

[0024] 62: Dummy gate layer

[0025] 64: Masking layer

[0026] 72: Dummy gate

[0027] 74: Mask

[0028] 80: Gate sealing spacer

[0029] 82: Source / Drain Region

[0030] 82C: Third epitaxial source / drain region

[0031] 86: Gate spacer

[0032] 87: Contact Etching Termination Layer (CESL)

[0033] 88: Interlayer Dielectric (ILD)

[0034] 89: District

[0035] 90: concave part

[0036] 92: Gate dielectric layer

[0037] 94: Gate electrode

[0038] 94A: Lining layer

[0039] 94B: Power Function Tuning Layer

[0040] 94C: Filler material

[0041] 96: Gate mask

[0042] 106: Gate electrode

[0043] 108: Interlayer Dielectric (ILD)

[0044] 110: Gate contact

[0045] 112: Source / Drain Contact

[0046] 120: First planting cover

[0047] 124: Planting layer

[0048] 130: Source / drain recess

[0049] 130A: First source / drain recess

[0050] 130B: Second source / drain recess

[0051] 200A: Zone 1

[0052] 200B: Second Zone

[0053] 200C: Zone 3

[0054] 251: Separator

[0055] 300: Planting Beam

[0056] D1: Depth

[0057] D2: Depth

[0058] D3: Depth

[0059] P0: Undoped profile

[0060] P1: First outline

[0061] P2: Second outline

[0062] P3: Third outline

[0063] θ: Inclination angle

[0064] Φ: Angle of twist Detailed Implementation

[0065] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0066] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element or feature(s). Spatial relative terms are intended to cover different orientations of the device in its use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0067] The disclosed embodiments relate to the fabrication of a semiconductor device. The semiconductor device may include transistors, such as FinFETs. The formation of the transistor may include: forming a dummy gate structure, forming source / drain regions on opposite sides of the dummy gate structure, and replacing portions of the dummy gate structure with a gate dielectric layer and a gate electrode. According to some embodiments, recesses are etched into portions of the semiconductor substrate on opposite sides of the dummy gate structure, and epitaxial source / drain regions are grown in said recesses. After the etching process, a first region of the semiconductor substrate (e.g., containing multiple dummy gate structures) is implanted with a dopant, while a second region (e.g., also containing multiple dummy gate structures) is masked. After the implantation process, the mask is removed to etch recesses in both the first and second regions of the semiconductor substrate. The implantation of the dopant modifies the composite and thus modifies various material properties of the semiconductor in the first region. Therefore, the doped semiconductor substrate in the first region is converted into a doped material with a different etch rate (e.g., a faster etch rate) compared to the material of the undoped semiconductor substrate in the second region. However, due to one or more characteristic differences between the first and second regions (e.g., small and large pitch respectively), the semiconductor substrate can be etched at similar rates (or to similar depths) in both the first and second regions. Furthermore, the epitaxial source / drain regions grown in the first and second regions can have similar depths, shapes, and sizes. Additionally, the source / drain regions can exhibit greater consistency across the first and second regions, thereby improving the yield, performance, and reliability of the finished semiconductor device.

[0068] Figure 1 The illustration shows an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET includes fins 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fins 52 project over and from adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or to a semiconductor substrate including the isolation regions. Additionally, although the fins 52 are illustrated as a single continuous material with respect to the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this case, fins 52 refer to the portion extending between adjacent isolation regions 56.

[0069] The gate dielectric layer 92 is along the sidewall of the fin 52 and above the top surface, and the gate electrode 94 is above the gate dielectric layer 92. The source / drain regions 82 are disposed on opposite sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. Figure 1Further illustrations are provided for reference cross sections used in subsequent figures. Cross section AA is along the longitudinal axis of the gate electrode 94 and is, for example, perpendicular to the current flow direction between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52, and is, for example, in the current flow direction between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, these reference cross sections are referred to in subsequent figures.

[0070] Some embodiments discussed herein are described in the context of FinFETs formed using a post-gate process. In some embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices such as planar FETs, nanostructured field-effect transistors (NSFETs) (e.g., nanosheets, nanowires, all-around gates, or the like), or the like.

[0071] Figures 2 to 19B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 The illustration is in Figure 1 The reference cross-section AA shown in the middle diagram includes multiple fins / FinFETs. Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A Along in Figure 1 The reference cross-section AA shown in the middle diagram is illustrated, and Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 17C , Figure 18B and Figure 19B It is along the diagram at Figure 1 The diagram shows a similar cross-section BB, except for multiple fins / FinFETs. Figure 10C , Figure 10D , Figure 11C , Figure 11D , Figure 12C, Figure 12D , Figure 13C and Figure 13D It is along Figure 1 The reference cross-section CC diagram shown in the middle figure shows multiple fins / FinFETs.

[0072] exist Figure 2 In this embodiment, a substrate 50 is disposed. The substrate 50 may be a semiconductor substrate, such as a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., by p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0073] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as illustrated by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0074] exist Figure 3 In this embodiment, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 are formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or similar combinations thereof. The etching process can be anisotropic.

[0075] Fin 52 can be patterned by any suitable method. For example, fin 52 can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography and self-alignment processes to allow patterns to be generated that have, for example, smaller spacing compared to patterns otherwise obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. In some embodiments, a mask (or other layer) may be retained on fin 52.

[0076] exist Figure 4 In this embodiment, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide, nitride, or combination thereof, such as silicon oxide, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-type material deposition and post-curing in a remote plasma system to convert the insulating material 54 into another material, such as an oxide), or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide comprising a dopant material (e.g., nitrogen). For example, silicon oxide (e.g., silicon oxynitride) or silicon nitride may be formed by an FCVD process. Once the insulating material is formed, an annealing process (e.g., in an oxygen environment) may be performed. In this embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may be formed first along the surface of the substrate 50 and the fins 52. Subsequently, filler materials such as those discussed above may be formed on top of the liner.

[0077] exist Figure 5In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, a combination thereof, or the like, may be used. The planarization process exposes the fin 52 such that the top surfaces of the fin 52 and the insulating material 54 are flush after the planarization process is completed. In embodiments where a mask is held on the fin 52, the planarization process may expose or remove the mask such that the top surface of the mask or the fin 52 and the insulating material 54 are flush after the planarization process is completed.

[0078] exist Figure 6 In this process, insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in the n-type region 50N and p-type region 50P protrude from between adjacent STI regions 56. Furthermore, the top surface of the STI region 56, as illustrated, may have a flat surface, a raised surface, a recessed surface (such as a dish shape), or a combination thereof. The top surface of the STI region 56 may be formed as flat, raised, and / or recessed by appropriate etching. The STI region 56 may be recessed using acceptable etching processes, such as processes that are selective for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fins 52). For example, oxide removal using, for example, diluted hydrofluoric acid (dHF) may be used.

[0079] about Figures 2 to 6 The described process is only one example of how fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepic structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, heteroepic structures can be used for fin 52. For example, Figure 5The fins 52 may be recessed, and a material different from the fins 52 may be epitaxially grown over the recessed fins 52. In such embodiments, the fins 52 comprise recessed material and epitaxial growth material disposed over the recessed material. In even other embodiments, a dielectric layer may be formed above the top surface of the substrate 50, and trenches may be etched through the dielectric layer. Heterogeneous epitaxial structures may then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxial growth material may be doped in situ during growth (e.g., by n-type or p-type impurities), which may eliminate previous and / or subsequent implantation, although in-situ and implantation doping may be used together.

[0080] Furthermore, it is advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., a PMOS region) in the n-type region 50N (e.g., an NMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si... x Ge 1-x (where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, or the like. For example, materials that can be used to form group III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0081] In addition, Figure 6 In this embodiment, appropriate wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-type well may be formed in an n-type region 50N, and an N-type well may be formed in a p-type region 50P. In some embodiments, a P-type well or an N-type well may be formed in both the n-type region 50N and the p-type region 50P.

[0082] In embodiments with different well types, different implantation steps for the n-type region 50N and p-type region 50P can be achieved using photoresist or other masks (not shown). For example, photoresist can be formed over the fins 52 and STI region 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using spin coating technology and can be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, and the plurality of n-type impurities are in groups of 10 or less. 18 cm -3 Such as in about 10 16cm -3 With about 10 18 cm -3 The photoresist is implanted in the zone at a concentration between these values. After implantation, the photoresist is removed using an acceptable ashing process.

[0083] After implanting n-type impurities in the p-type region 50P, photoresist is formed in the p-type region 50P above the fin 52 and the STI region 56. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating technology and can be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like, and the plurality of impurities is equal to or less than 10. 18 cm -3 Such as in about 10 16 cm -3 With about 10 18 cm -3 The photoresist is applied in the zone at a concentration between these values. After application, the photoresist can be removed, for example, by an acceptable ashing process.

[0084] Following the implantation of the n-type region 50N and the p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be doped in situ during growth, which may eliminate implantation, although in-situ and implantation doping may be used together.

[0085] exist Figure 7In this configuration, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a masking layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60 and then planarized, for example, by CMP. The masking layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material and may be selected from the group consisting of: amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 62 may be made of other materials with high etch selectivity for etching self-isolation regions, such as STI region 56, and / or dummy dielectric layer 60. The mask layer 64 may include one or more layers, such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over n-type region 50N and p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown covering only fin 52. In some embodiments, the dummy dielectric layer 60 may be deposited such that it covers STI region 56, extending over STI region and between dummy gate layer 62 and STI region 56.

[0086] Figures 8A to 19B The illustration shows various additional steps in the apparatus used to manufacture the embodiment. Figures 8A to 19B The diagram illustrates the characteristics of either the n-type region 50N or the p-type region 50P. For example, the diagram shows... Figures 8A to 19B The structure described herein is applicable to both n-type region 50N and p-type region 50P. Differences (if any) in the structures of n-type region 50N and p-type region 50P will be described in text accompanying each figure.

[0087] exist Figure 8A and Figure 8B In the middle, mask layer 64 (see Figure 7The mask 74 can be patterned using acceptable optical lithography and etching techniques. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using acceptable etching techniques to form the dummy gate 72. The dummy gate 72 covers the respective channel regions 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from the adjacent dummy gates. The dummy gate 72 may also have a longitudinal direction that is generally perpendicular to the longitudinal direction of the respective epitaxial fin 52.

[0088] In addition, Figure 8A and Figure 8B In this configuration, a gate sealing spacer 80 may be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. The gate sealing spacer 80 may be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0089] After forming the gate sealing spacer 80, placement for the lightly doped source / drain (LDD) region (not explicitly illustrated) can be performed. In embodiments with different device types, similar to the above... Figure 6 As described in the previous section, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the exposed fin 52 in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the p-type region 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the exposed fin 52 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities described above, and the p-type impurity can be any of the p-type impurities described above. The lightly doped source / drain regions may have a depth of approximately 10 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0090] exist Figure 9A and Figure 9BIn this configuration, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or similar materials. According to some embodiments, the anisotropic etching can further remove portions of the dummy dielectric layer 60 disposed above the fin 52 and laterally adjacent to the gate spacer 86. In some embodiments (not shown), these portions of the dummy dielectric layer 60 can be removed in a subsequent etching process. The dummy gate 72, mask 74, dummy dielectric layer 60, gate sealing spacer 80, and gate spacer 86 can be collectively referred to as the "dummy gate structure".

[0091] Please note that the above disclosure broadly describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different sequences of steps can be employed (e.g., gate seal spacer 80 may not be etched before the formation of gate spacer 86, resulting in an "L-shaped" gate seal spacer), spacers can be formed and removed, and / or similar. Furthermore, n-type and p-type devices can be formed using different structures and steps. For example, the LDD region of an n-type device can be formed before the formation of gate seal spacer 80, while the LDD region of a p-type device can be formed after the formation of gate seal spacer 80.

[0092] Figures 10A to 13D The illustration shows various steps in forming the epitaxial source / drain region 82 of the embodiment device. Specifically, a first implantation mask 120 is formed above the structure (see [reference]). Figures 10A to 10D In the first region 200A of the structure, the fins 52 are implanted with dopants to modify their material properties, while the fins 52 in other regions of the structure are shielded (see [link to relevant documentation]). Figures 11A to 11F The source / drain recess 130 is etched into the fin 52 of the first region 200A and other regions (see [reference]). Figures 12A to 12D Furthermore, the epitaxial source / drain region 82 is formed in the source / drain recess 130 (see [reference]). Figures 13A to 13D Please note that the implantation process performed in the first region 200A may include a portion of the p-type region 50P, a portion of the n-type region 50N, or a portion of both. Additionally, regions 200A / B / C may each include a single continuous region or multiple discrete (e.g., non-continuous) regions of the substrate 50.

[0093] exist Figures 10A to 10DIn this structure, a first implanted mask 120 is formed and patterned to expose a first region 200A while covering a second region 200B and a third region 200C. The first implanted mask 120 may include a photoresist and / or other masks (not shown separately) and may be formed similarly in combination with other processes as described above. For example, the photoresist of the first implanted mask 120 may be formed using a spin-coating technique and may be patterned using an acceptable optical lithography technique.

[0094] See details Figure 10B Separator 251 is provided to separately illustrate the first region 200A, the second region 200B, and the third region 200C. Note that some of the dummy gate structures illustrated in the first region 200A (e.g., each including a dummy gate 72, a mask 74, a dummy dielectric layer 60, a gate sealing spacer 80, and a gate spacer 86) may not be the same dummy gate structures partially illustrated in the second region 200B and the third region 200C. Furthermore, each of regions 200A / B / C may be physically separable from one or both of the other regions, and any number of dummy gate structures or other device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed within or between regions 200A / B / C. Similarly, in Figure 10A In the diagram, the dummy gate structure is used to represent the identity as being located separately in the second region 200B or the third region 200C.

[0095] For illustrative purposes, the first region 200A and the third region 200C illustrate regions with relatively high density and small spacing between adjacent features (e.g., dummy gate 72), and the second region 200B illustrates a region with relatively low density and large spacing between adjacent features (e.g., dummy gate 72). While the materials of the first fin 52A, the second fin 52B, and the third fin 52C may be the same, the first fin 52A in the first region 200A and the third fin 52C in the third region 52C can be attributed to the higher pattern density in the first region 200A and the third region 200C, which etches at a slower rate than the second fin 52B in the second region 200B, thereby confining the exposure of the etchant to the first fin 52A and the third fin 52C. For example, the first region 200A may have a small spacing, the second region 200B may have a large spacing, and the third region 200C may have a small spacing similar to that in the first region 200A. For example, each of the spacings can range from greater than 0 nm to 60 nm.

[0096] As will be discussed in more detail below, the first fin 52A in the first region 200A is implanted with dopant to increase the etching rate of the first fin 52A compared to the etching rate of the second fin 52B. By increasing the etching rate of the material of the first fin 52A in the first region 200A compared to the etching rate of the material of the second fin 52B in the second region, the depth of the recesses etched in the first fin 52A and the second fin 52A can be controlled to have similar depths. The third fin 52C in the third region 200C is not implanted, and the third region 200C can have a high density / small pitch similar to the first region 200A. Therefore, the third fin 52C will be etched at a lower rate than the first fin 52A, thereby creating recesses with a smaller depth compared to the recesses in the first fin 52A. Therefore, by selectively controlling the implanted areas, the depth of the recesses can be controlled, thereby allowing greater control over the operating characteristics of individual transistors.

[0097] Figure 10C The diagram shows the cross-section of the first fin 52A and the STI region 56 within the first zone 200A, and... Figure 10D The diagram shows a cross-section of the second fin 52B and the STI region 56 within the second region 200B. As shown, a first fin cover 120 is formed above the second fin 52B within the second region 200B (and above the third fin 52C in the third region 200C), while the first fin 52A in the first region 200A remains exposed.

[0098] exist Figures 11A to 11F In this structure, the implantation layer 124 is formed above the structure by performing an implantation process to implant dopant into the first region 52A of the first region 200A, while the second fins 52B and the third fins 52C of the second region 200B and the third region 200C are covered by the first implantation mask 120. In some embodiments, the exposed upper portion of the first fin 52A is converted into the implantation layer 124 by the dopant from the implantation process. Note that the fin 52 herein may be described as "doped" or "undoped" with respect to the dopant from the implantation process (e.g., ...). Figures 11A to 11F ), and although any other type of doping, such as n-type or p-type impurities described above and below, is doped (see, for example) Figure 6 , Figure 8A and Figure 8B ).

[0099] As a result of the implantation process, the upper portion of the first fin 52A (e.g., including the implantation layer 124) will have modified material properties (e.g., modified concentration profile) compared to the material properties of the second fin 52B and the third fin 52C in the second region 200B and the third region 200C (see example). Figures 12A to 12DFor example, the implant layer 124 may extend into the first fin 52A to a depth ranging from greater than 0 nm to 60 nm (e.g., the thickness of the implant layer 124). According to some embodiments, a portion of the implant layer 124 may be additionally formed above the outer surface (e.g., the upper and / or side surfaces) of the first fin 52A, such as... Figure 11E As shown in the diagram.

[0100] According to some embodiments, the implantation process may be an ion implantation process that implants an ion dopant into the first fin 52A of the first region 200A, although any suitable process may be used. The dopant may include nitrogen, argon, silicon, germanium, the like, or combinations thereof. For example, although not specifically illustrated, one or more precursors such as nitrogen, ammonia, argon, silane, germane, or combinations thereof may be sourced from, such as a storage tank or a facility that independently prepares and delivers the material to the plasma generator. In some embodiments, the dopant is different from the n-type and p-type impurities used to form the LDD regions as discussed above. In some embodiments, the dopant may include the same material as used in the STI region 56, such as silicon or a dopant material (e.g., nitrogen). The implantation process may be performed at a temperature ranging from -150°C to 450°C and at a frequency ranging from 10... -6 Up to 2×10 -5 The process is performed under pressure. In some embodiments, the implantation process is followed by an annealing process at a temperature ranging from 400°C to 1200°C to repair excessive damage and / or other features that receive dopants in the first fin 52A.

[0101] Dopants can be used in energies ranging from 1 kEV to 30 kEV and in frequencies ranging from 10... 14 atoms / cm 3 Up to 10 16 atoms / cm 3 The dose concentration is accelerated to the structure (e.g., located within the treatment chamber). At least 1 kEv and / or 10 kEv are used respectively. 14 atoms / cm 3 The energy and dose concentration allowed the dopant to penetrate sufficiently deep and at a sufficiently high concentration into the first fin 52A to adequately modify the composite and material properties. This was achieved using no more than 30 kEv and / or 10 kEv respectively. 16 atoms / cm 3 The energy and dose concentration ensure that the dopant penetrates into the first fin 52A to a sufficiently shallow depth or at a sufficient concentration to prevent or minimize any damage to other nearby features (e.g., dummy gate structure, STI region 56, and substrate 50), while adequately modifying the composite and material properties of the first fin 52A.

[0102] As illustrated, in addition to the dopant being implanted into the first fin 52A of the exposed first region 200A to form the implantation layer 124, the implantation layer 124 may further form structures such as the exposed STI region 56, dummy gate structures (e.g., mask 74, gate sealing spacer 80, and gate spacer 86), and the upper portion of other exposed features of the first implantation mask 120. Due to material properties, such as differences in feature density, the implantation layer 124 may form with varying thicknesses (e.g., depths) in the mask 74 and STI region 56 compared to the first fin 52A discussed above. For example, the implantation layer 124 in the STI region 56 (e.g., having a lower density compared to the fin 52) may reach a thickness (e.g., depth) of up to 80 nm or the entire depth in the STI region 56. Furthermore, the implantation layer 124 in the mask 74 may have a thickness (e.g., depth) ranging from greater than 0 nm to 200 nm in the mask 74.

[0103] Although the implantation layer 124 is illustrated as being formed in the upper portion of exposed features (e.g., the first fin 52A, mask 74, gate sealing spacer 80, gate spacer 86, and first implantation mask 120), varying amounts of dopant can further penetrate those features. As discussed above, compared to materials with higher density such as semiconductors and / or metals, the dopant can extend further through materials with lower density, such as dielectric materials. For example, the implantation layer 124 can extend entirely through the STI region 56 and, in some embodiments, partially extend into the underside of the substrate 50.

[0104] Figure 11E The diagram is similar to Figure 11C The cross-sectional view of one of the first fins 52A in the first zone 200A after the installation process. Figure 11F Provides a dopant concentration profile corresponding to the depth through the STI region 56 and into the substrate 50. Note that the illustrated embodiment shows that the implanted layer 124 is formed through the entire STI region 56 and partially extends into the underlying portion of the fin 52.

[0105] Figure 11FThree exemplary dopant concentration profiles (e.g., first profile P1, second profile P2, and third profile P3) of the STI region 56 in the first region 200A after the implantation process are provided for comparison with exemplary undoped concentration profiles (e.g., undoped profile P0) of the STI region 56 in the second region 200B and the third region 200C, which have not yet received dopant from the implantation process. The exemplary dopant concentration profiles represent the dopant concentration from the top surface of the STI region 56 to a depth that completely passes through the STI region 56 and partially extends into the substrate 50. Note that the concentration y-axis is plotted logarithmically, while the depth x-axis is plotted linearly. However, regardless of whether the concentration y-axis is plotted logarithmically or linearly, the three exemplary concentration profiles may have curved shapes (e.g., convex shapes), such as Gaussian curves.

[0106] For example, the illustrated dopant concentration profiles P1 / P2 / P3 illustrate an instance where the first region 200A receives nitrogen-ion dopant during the implantation process, and where the STI region 56 has been formed from nitrogen-doped silicon oxide. The dopant concentration profiles P1 / P2 / P3 after the implantation process indicate that the dopant concentration may tend to follow a Gaussian curve through the STI region 56 (e.g., with peaks in the block portions of the STI region 56) and may stop at or near the boundary between the STI region 56 and the substrate 50. In contrast, the doped concentration profile P0 may tend to be linear through the STI region 56 (e.g., flat as shown). As illustrated, the three dopant concentration profiles P1 / P2 / P3 and the undoped concentration profile P0 may exhibit a downward sloping profile through the underlying portion of the substrate 50, which may contain small (e.g., trace amounts) of one or more chemicals used as dopant. In some embodiments, the illustrated dopant concentration profiles P1 / P2 / P3 can be applied to the same dopant (e.g., nitrogen or silicon) used in the implantation process, which is pre-formed in the STI region 56. In some embodiments, the illustrated dopant concentration profiles P1 / P2 / P3 can be applied to different dopants (e.g., argon or germanium) that can be used to form the STI region 56. Furthermore, the dopant concentration profiles P1 / P2 / P3 can illustrate the total concentration of more than one dopant. In some embodiments, the dopant concentration in the STI region 56 can reach a range of 10. 20 atoms / cm 3 Up to 10 21 atoms / cm 3 The peak dopant concentration. Furthermore, the dopant can be directly applied below the STI region 56 to a depth of up to 5 nm within the substrate 50.

[0107] According to some embodiments, the implantation process can be performed at various points in the manufacturing process. For example, the formation of the first implantation mask 120 and the implantation process can be performed after the deposition of the gate spacer 86 material but before patterning to form the gate spacer 86. Thus, dopants from the implantation process can pass through and be implanted along the upper surface of the first fin 52A within the exposed portions of the gate spacer 86 and the dummy dielectric layer 60.

[0108] In some instances, the formation of the implantation mask 120 and the implantation process can be performed prior to the patterning of the dummy dielectric layer 60. Therefore, dopants from the implantation process can pass through and be implanted along the surface of the first fin 52A within the exposed portion of the material of the dummy dielectric layer 60.

[0109] Figures 12A to 12D The illustration shows etched fins 52 to form source / drain recesses 130, followed by the formation of epitaxial source / drain regions 82 within the source / drain recesses 130. In some embodiments, the first implantation mask 120 may be removed by a suitable method after the implantation process. For example, photoresist may be removed using an acceptable ashing process. After removing the first implantation mask 120, the p-type region 50P may be masked to etch the source / drain recesses 130 and epitaxially grow the epitaxial source / drain regions 82 in the n-type region 50N. Similarly, the n-type region 50N may be masked to etch the source / drain recesses 130 and epitaxially grow the epitaxial source / drain regions 82 in the p-type region 50P. Nevertheless, any suitable method and sequence of steps may be used. As discussed above, features in either the n-type region 50N or the p-type region 50P are illustrated in the figures, and differences (if any) in the structure or process of the n-type region 50N and the p-type region 50P may be described in the accompanying text. For example, the source / drain recess 130 may be formed using one or more etching processes. In some embodiments, the etching process may include any acceptable wet or dry etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or similar combinations thereof. The etching process may include anisotropic etching, isotropic etching, or combinations thereof.

[0110] In some embodiments, the p-type region 50P may include several portions of a first region 200A, a second region 200B, a third region 200C, or combinations thereof. Similarly, the n-type region 50N may include different portions of the first region 200A, the second region 200B, the third region 200C, or combinations thereof. Therefore, the etching process in the p-type region 50P may etch some portions of the first fin 52A that receive etchant from the implantation process and some portions of the second fin 52B and / or the third fin 52C that do not receive dopant from the etching process. Therefore, the etching process in the n-type region 50N may etch other portions of the first fin 52A that receive etchant from the implantation process and other portions of the second fin 52B and / or the third fin 52C that do not receive dopant from the etching process.

[0111] According to some embodiments, the first region 200A may have a first characteristic that affects the etching rate of the first fin 52A, such as a relatively high pattern density between high features of the structure (e.g., features may be relatively closely spaced relative to each other). Furthermore, the second region 200B may have a second characteristic that affects the etching rate of the second fin 52B, such as a relatively low pattern density (e.g., features may be relatively far spaced relative to each other). Additionally, as mentioned above, the third region 200C, similar to the first region 200A, may have the first characteristic (e.g., high pattern density).

[0112] According to some embodiments, a first characteristic (e.g., high pattern density) of the first region 200A and the third region 200C may specifically refer to a relatively small spacing between the dummy gate structures. Furthermore, a second characteristic (e.g., low pattern density) of the second region 200B may specifically refer to a relatively large spacing between the dummy gate structures. For example, the spacing between the dummy gate structures in the first region 200A and the third region 200C may be 100 nm or less, and the spacing between the dummy gate structures in the second region 200B may be 100 nm or more. As mentioned above, the first region 200A and the third region 200C may include several portions of the p-type region 50P (e.g., subsequently including a PFET) and several portions of the n-type region 50N (e.g., subsequently including an NFET). Similarly, the second region 200B may include other portions of the p-type region 50P and the n-type region 50N.

[0113] Differences in spacing (e.g., pattern density) as described above can take into account the etching rate of fin 52 when forming the source / drain recess 130 (see [link]). Figures 12A to 12D For example, in the absence of a planting process (see...). Figures 11A to 11FIn this case, the pattern loading effect will tend to cause the material in the low pattern density region (e.g., the second region 200B) to be etched at a faster rate than the material in the high pattern density region (e.g., the first region 200A and / or the third region 200C). Specifically, the pattern density difference allows the etchant to reach the second fin 52B in the second region 200B more easily than the first fin 52A in the first region 200A and the third fin 52C in the third region 200C.

[0114] According to some embodiments, the formation of the implanted layer 124 by the implantation process increases the etching rate of the material of the first fin 52A to compensate for the aforementioned pattern loading effect. Specifically, the material of the implanted layer 124 (e.g., the upper portion of the first fin 52A) has a higher etching rate than the undoped materials of the second fin 52B and the third fin 52C. Therefore, etching the first fin 52A and the second fin 52B (simultaneously) can form the first source / drain recess 130A and the second source / drain recess 130B to the same or similar desired depth at the same or nearly the same time. Furthermore, etching the second fin 52B stops before the recess becomes too deep, thereby preventing leakage current from the epitaxial source / drain region 82 from subsequently forming therein.

[0115] The first source / drain recess 130A in the first region 200A may have a depth D1, and the second source / drain recess 130B in the second region 200B may have a depth D2, wherein each of depths D1 / D2 may range from greater than 0 nm to 60 nm. In some embodiments, depth D1 ranges from 95% to 105% of depth D2.

[0116] According to some embodiments, as discussed above, similar to the first fin 52A corresponding to the dummy gate structure in the first region 200A, the third region 200C (e.g., shaded during the placement process) may include a third fin 52C with a small pitch corresponding to the dummy gate structure. This is attributed to the shading during the placement process (see [link to documentation]). Figures 11A to 11F The third fin 52C does not receive dopants and therefore does not form the implantation layer 124, and thus does not experience an increase in the etch rate of the material of the third fin 52C. Therefore, the third source / drain recess 130C may have a depth less than depths D1 and D2, such as a depth D3 ranging from greater than 0 nm to 50 nm (e.g., less than depths D1 / D2) and ranging from 80% to 90% of depths D1 and / or D2.

[0117] As discussed above, the implantation layer 124 increases the etching rate of the first fin 52A. In some embodiments, the implantation layer 124 reduces the etching rate of the first fin 52A. Dopant may include boron, boron fluoride (e.g., BF2), or the like. For example, the first region 200A and the third region 200C may each have a lower pattern density (e.g., a larger pitch), and the second region 200B may have a higher pattern density (e.g., a smaller pitch). For example, the pitch of the dummy gate structures in the first region 200A and the third region 200C may be 100 nm or more, and the pitch of the dummy gate structures in the second region 200B may be 100 nm or less. Similarly, as described above, the second region 200B and the third region 200C may be masked to perform the implantation process on the first region 200A. However, the dopants and parameters used in the implantation process can be selected to form implantation layer 124 to reduce the etching rate of the first fin 52A material compared to the undoped fin 52B / 52C material. Therefore, in subsequent etching processes, the first source / drain recess 130A can have the same or similar depth as the second source / drain recess 130B. For example, the second source / drain recess 130B can have a depth ranging from 95% to 105% of the depth of the first source / drain recess 130A. Furthermore, the third source / drain recess 130C (e.g., located in a third region 200C, which has a large spacing and is masked during the implantation process) can have a depth greater than the depths of the first source / drain recess 130A and the second source / drain recess 130B. Therefore, the third epitaxial source / drain region 82C formed as described below (see...) Figures 13A to 13D It can have a size larger than that of the first epitaxial source / drain region 82A and the second epitaxial source / drain region 82B.

[0118] exist Figures 13A to 13DIn the fin 52, epitaxial source / drain regions 82 are formed in the source / drain recesses 130. For example, a first epitaxial source / drain region 82A, a second epitaxial source / drain region 82B, and a third epitaxial source / drain region 82C are formed in the first source / drain regions 130A, 130B, and 130C of the first fin 52A, the second fin 52B, and the third fin 52C, respectively. The epitaxial source / drain regions 82 are formed in the fin 52 such that a dummy gate structure (e.g., a dummy gate 72) can be disposed between several adjacent pairs of epitaxial source / drain regions 82. The epitaxial source / drain regions 82 extend into the fin 52 and can also penetrate the fin 52. In some embodiments, the gate spacer 86 is used to separate the epitaxial source / drain region 82 from the dummy gate 72 by an appropriate lateral distance, such that the epitaxial source / drain region 82 is not short-circuited to the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain region 82 may be selected to apply stress to the respective channel regions 58, thereby improving performance.

[0119] As discussed above, the epitaxial source / drain region 82 in the n-type region 50N may be formed, while the p-type region 50P is masked. The epitaxial source / drain region 82 in the n-type region 50N is epitaxially grown in the source / drain recess 130. The epitaxial source / drain region 82 may include any acceptable material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N may include a material that applies tensile stress to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 82 in the n-type region 50N may have a surface raised from the individual surface of the fin 52 and may have facets.

[0120] As discussed above, the epitaxial source / drain region 82 in the p-type region 50P can be formed, while the n-type region 50P is shielded. The epitaxial source / drain region 82 in the p-type region 50P is epitaxially grown in the source / drain recess 130. The epitaxial source / drain region 82 can include any acceptable material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P can include a material that applies compressive stress to the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 82 in the p-type region 50P can have surfaces raised from the individual surfaces of the fin 52 and can have facets.

[0121] As discussed above, each of the first region 200A, the second region 200B, and the third region 200C may include several portions of the n-type region 50N and the p-type region 50P. Therefore, the epitaxial source / drain region 82 in the p-type region 50P can be formed simultaneously in all three regions 200A, 200B, and 200C, while the n-type region 50N is shielded. Similarly, the epitaxial source / drain region 82 in the n-type region 50N can be formed simultaneously in all three regions 200A, 200B, and 200C, while the p-type region 50P is shielded.

[0122] As illustrated, due to the formation of source / drain recesses 130A / 130B with similar depths D1 / D2, the first epitaxial source / drain region 82A can be formed to a substantially the same size as the second epitaxial source / drain region 82B. Furthermore, due to the formation of a third source / drain recess 130C with a shallower D3, the third epitaxial source / drain region 82C can be formed to a smaller size compared to the first epitaxial source / drain region 82A and the second epitaxial source / drain region 82B.

[0123] Similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing, the epitaxial source / drain regions 82 and / or fins 52 can be implanted with impurities (e.g., n-type or p-type doping). The source / drain regions may have a density of approximately 10 19 cm -3 With about 10 21 cm -3 The impurity concentrations between these values. The n-type and / or p-type impurities in the source / drain regions may be any of those previously discussed and may differ from the dopants used in the implantation process (see [link to relevant documentation]). Figures 11A to 11F In some embodiments, the epitaxial source / drain 82 may be in-situ doped during growth.

[0124] Figure 13C and Figure 13D The diagram shows a cross-sectional view of the epitaxial source / drain region 82 formed above the fin 52 in any or all of the three regions 200A / 200B / 200C. For example, Figure 13C and Figure 13D Any of these can correspond to the epitaxial source / drain regions 82, which have been formed in a first fin 52A that receives dopant from the implantation process or in a second region 52B and a third region 52C that do not receive dopant from the implantation process. As a result of the epitaxial process used to form the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 82 has facets that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, such as by Figure 13CAs illustrated. In some embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, as shown by... Figure 13D As illustrated. In some of the illustrated embodiments, gate spacers 86 are formed to cover a portion of the sidewalls of the fin 52, which extend over the STI region 56, thereby blocking epitaxial growth. In some embodiments, the spacer etching used to form the gate spacers 86 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 56.

[0125] about Figures 9A to 13D The described process is just one example of how epitaxial source / drain regions 82 can be formed. In some embodiments (not shown), a second implantation process similar to the implantation process described above can be performed on, for example, the fourth region. For example, after forming the first implantation mask 120 and performing the first implantation process, the first implantation mask 120 can be removed, a second implantation mask can be formed over the fifth region, and the second implantation process can be performed on the exposed fourth region. Note that the exposed fourth region (e.g., receiving the second implantation process) can be different from the first region 200A (e.g., receiving the first implantation process). Alternatively, the fourth region can partially or entirely overlap with the first region 200A. Therefore, some or all of the fins 52 can receive different implantations compared to other fins in the fins 52. Furthermore or alternatively, some of the fins 52 can receive multiple implantations, while other fins in the fins 52 can receive only one implantation or no implantation. The above steps can be performed for any number of implantation processes, regardless of whether the same, similar, or varying parameters and dopants are used for each implantation process. For example, any of the dopants, implantation energy, dose concentration, and implantation angle may differ between the first implantation process and any subsequent implantation process.

[0126] In some embodiments with multiple implantations, during the second implantation, the exposed fourth region may include a portion or all of the first region 200A and / or a portion or all of the second region 200B. The second implantation process may then be performed on the exposed fins 52 in the fourth region using the same or similar dopant and process parameters as the first implantation process. For example, the second implantation process may be designed to provide a lower doping level than the first implantation process. Therefore, some fins 52 may receive two implantations (e.g., a first highest dopant concentration), some fins 52 may receive only a first implantation (e.g., a second highest dopant concentration), some fins 52 may receive only a second implantation (e.g., a third highest dopant concentration), and some fins 52 may not receive any of the implantations. Alternatively, the first and second implantation processes may use different dopant and / or process parameters to provide a greater variety of material properties modifications to the three groups of fins 52 receiving one or two implantations.

[0127] In some embodiments with multiple implantations, a first implantation process can increase the etching rate of the material of the first fin 52A, while a second implantation process can decrease the etching rate of the material of the fin 52 in the fourth region. Note that in this embodiment, there may be no overlap between the first region 200A and the fourth region, and therefore, no fin 52 receives both the first and second implantations. Alternatively, the first implantation process can decrease the etching rate of the material of the first fin 52A, while the second implantation process can increase the etching rate of the material of the fin 52 in the fourth region.

[0128] Additionally, in some embodiments with multiple implants, a second implantation process can be performed without first removing the first implantation mask 120 after the first implantation. In some such embodiments, a second implantation mask can be formed over the first implantation mask 120 and patterned to expose a portion of the first region 200A. Note that the second implantation mask can be formed in conjunction with the first implantation mask 120 as described above or similarly by any suitable method. Thus, some of the first fins 52A will receive two implants, the other fins in the first fins 52A will receive only the first implantation, and the second fins 52B and the third fin 52C will not receive implants. The second implantation process can be performed using the same or similar process parameters and dopants as the first implantation process, as described above.

[0129] Please note that other combinations of process parameters and dopants described in conjunction with one or more implantation processes may be used and are intended to be within the scope of this disclosure. Furthermore, one or more implantation processes and the formation of epitaxial source / drain regions 82 may be formed in the p-type region 50P, while the entire n-type region 50N is masked. Similarly, one or more other implantation processes and the formation of epitaxial source / drain regions 82 may be formed in the n-type region 50N, while the entire p-type region 50P is masked.

[0130] Figures 14A to 19B The diagram illustrates subsequent steps in the manufacture of a semiconductor device. Note that each diagram may illustrate features of any of the three regions 200A / 200B / 200C unless otherwise stated.

[0131] exist Figure 14A and Figure 14B In the middle, the first interlayer dielectric (ILD) 88 is deposited on Figure 10A and Figure 10BAbove the structure shown in the diagram. The first ILD 88 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, the mask 74, and the spacer 86. The CESL 87 may comprise a dielectric material having an etch rate lower than that of the material covering the first ILD 88, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0132] exist Figure 15A and Figure 15B In this process, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72, and several portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed via the first ILD 88. In some embodiments, the mask 74 can be maintained while the planarization process has made the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0133] exist Figure 16A and Figure 16BIn this process, the dummy gate 72 and the mask 74 (if present) are removed in one or more etching steps, resulting in the formation of the recess 90. Several portions of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and remains in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases that selectively etch the dummy gate 72 with little or no etching of the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or overlaps with the channel region 58 of the respective fin 52. Each channel region 58 is disposed between several adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric layer 60 can then be optionally removed after the dummy gate 72 is removed.

[0134] exist Figure 17A and Figure 17B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 17C Illustration Figure 17B A detailed view of region 89. A gate dielectric layer 92, one or more layers are deposited in the recess 90, on the top surface and sidewalls of, for example, the fin 52, and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 comprises one or more dielectric layers, such as silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layer 92 comprises a silicon oxide interface layer formed by thermal or chemical oxidation, and a layer of high-k dielectric material, such as metal oxide or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where several portions of the dummy dielectric layer 60 are held in the recess 90, the gate dielectric layer 92 comprises the material of the dummy dielectric layer 60 (e.g., SiO2).

[0135] Gate electrodes 94 are deposited over the gate dielectric layer 92 and fill the remaining portion of the recess 90. Gate electrodes 94 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 94 is illustrated... Figure 17B However, the gate electrode 94 may include any number of liner layers 94A, any number of work function tuning layers 94B, and filler material 94C, such as... Figure 17C As illustrated, after filling the recess 90, a planarization process, such as CMP, can be performed to remove additional portions of the material of the gate dielectric layer 92 and the gate electrode 94, which are located above the top surface of the ILD 88. The remaining portions of the material of the gate electrode 94 and the gate dielectric layer 92 thus form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as the “gate stack”. The gate and the gate stack can extend along the sidewalls of the channel region 58 of the fin 52.

[0136] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by a unique process, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed by a unique process, such that the gate electrode 94 can be made of different materials. Various masking steps can be used to mask and expose appropriate areas when using unique processes.

[0137] In 18A and Figure 18B In this configuration, a gate mask 96 is formed over a gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94), and the gate mask may be disposed between opposing portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack such that the recess is formed directly over the gate stack and between opposing portions of the gate spacers 86. The gate mask 96, comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, fills the recess, followed by a planarization process to remove additional portions of the dielectric material extending over the first ILD 88. The gate mask 96 is optional and may be omitted in some embodiments. In such embodiments, the gate stack may remain flush with the top surface of the first ILD 88.

[0138] As again Figure 18A and Figure 18BFurther illustration shows that a second ILD 108 is deposited above a first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flow-type CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 is subsequently formed ( Figure 19A and Figure 19B Pierce the second ILD 108 and the gate shield 96 (if present) to contact the top surface of the recessed gate electrode 94.

[0139] exist Figure 19A and Figure 19B In some embodiments, gate contact 110 and source / drain contact 112 are formed through a second ILD 108 and a first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening for the gate contact 110 is formed through the second ILD 108 and a gate mask 96 (if present). The openings can be formed using acceptable optical lithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, adhesive layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove additional material from the surface of the ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is solid and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is solid and electrically coupled to the gate electrode 106. The source / drain contact 112 and the gate contact 110 may be formed in different processes or in the same process. Although illustrated as being formed in the same cross-section, it should be understood that each of the source / drain contact 112 and the gate contact 110 may be formed in a different cross-section, which avoids short-circuiting of the contacts.

[0140] exist Figures 20A to 20EIn various embodiments, the implantation process described above can be performed with greater specificity regarding additional process parameters. Specifically, each implantation process may include one or more anisotropic implantation sub-steps designed to effectively implant dopant into the fin 52 to compensate for or traverse structures with multiple geometries in those specific regions. For example, the tilt angle θ and the twist angle Φ together specify the incident angle of the implantation beam 300 for each implantation sub-step. Furthermore, a wafer rotation protocol may be selected to rotate the wafer between implantation sub-steps and achieve additional structural features during the implantation process. Note that the illustrated implantation beam 300 may represent multiple implantation beams 300 having the same incident angle during each implantation sub-step. Furthermore, Figure 20C and Figure 20E The illustration shows a placement beam 300 with multiple incident angles indicating multiple placement sub-steps, with wafer rotation ranging from, for example, 90° or 180° between these sub-steps. Additionally, the tilt angle θ, twist angle Φ, and rotation agreement are illustrated and explained herein with respect to the following: a yz plane parallel to the illustrated dummy gate 72, an xz plane parallel to the illustrated fin 52A (e.g., the first fin 52A), and an xy plane parallel to the main surface of the wafer. However, any suitable combination of orientations may be used.

[0141] The tilt angle θ refers to the angle of the implantation beam relative to the z-axis. In some embodiments, a tilt angle θ greater than 0° can be used to implant dopant into the sidewall of the illustrated fin 52, provided that the torsion angle Φ (discussed in more detail below) is less than 90°. In some embodiments, the tilt angle θ can range from 0° (e.g., perpendicular or parallel to the z-axis) to 60°. A tilt angle θ less than or equal to 60° allows the implantation beam 300 to reach the fin 52 with minimal suppression of adjacent higher features (e.g., dummy gate 72). In embodiments where the implantation process is performed in regions with small pitch and / or large height of adjacent higher features, the tilt angle θ can be 30° or less. Implantation may include two implantation beams 300 such that the tilt angle θ of one implantation beam is a mirror image of the tilt angle θ of the other implantation beam.

[0142] The twist angle Φ refers to the angle of the implantation beam relative to the yz plane. In some embodiments, such as for the purpose of implanting dopant into several portions of the illustrated fin 52 below the dummy gate structure, a twist angle Φ greater than 0° can be used to implant dopant into the sidewalls of the illustrated dummy gate structure. The twist angle Φ can range from 0° (e.g., parallel to the yz plane) to 90° (e.g., parallel to the xz plane). In some embodiments, the implantation beam 300 may include multiple beams 300 with different incident angles, such as having two implantation beams 300. Thus, the twist angle Φ of each implantation beam 300 can be a mirror rotation toward the positive x-axis (not shown) or toward the negative x-axis (not shown). Similarly, like the tilt angle θ, the twist angle Φ can be selected based on the pattern geometry of the region to be implanted (e.g., adjacent higher features, such as the dummy gate structure).

[0143] Rotation protocols may include rotating the wafer over multiple placement sub-steps. For example, a placement process may include one placement sub-step. In some embodiments, a placement process may include two placement sub-steps with wafer rotations, for example, 180 degrees apart. In some embodiments, a placement process may include four placement sub-steps with wafer rotations, for example, 90 degrees apart.

[0144] Figure 20B The illustration shows an example of a fabrication process in one embodiment, where the first region 200A has adjacent higher features with extremely small pitch and / or extremely large height (e.g., an extremely high dummy gate structure compared to fin 52). For example, such as Figure 20B As illustrated, the tilt angle θ can be less than 30°, such as about 0°, to ensure that the implanted beam 300 reaches the fin 52 without suppressing the dummy gate structure. Therefore, a larger amount of dopant can be implanted into the upper surface of the fin 52 and a smaller amount (e.g., substantially zero) into the sidewall surfaces of the fin 52. Furthermore, the dopant can be implanted directly below the dummy gate structure in several portions of the fin 52 in a smaller amount (e.g., substantially zero). Therefore, the upper portion of the fin 52 with a higher concentration of dopant has a higher etch rate than the lower portion of the fin 52 with a lower concentration of dopant (and directly below the dummy gate structure). Note that in embodiments with a tilt angle of approximately 0°, any twist angle Φ has little or no effect on the incident angle of the implanted beam 300 on the fin 52. Similarly, the rotation agreement of more than one implantation sub-step will also have little or no effect on the implanted area on the fin 52 in subsequent implantation sub-steps.

[0145] Figure 20CThe illustration shows an example of a placement process in one embodiment, where the first region 200A has adjacent higher features with small pitch and / or large height. For example, the tilt angle θ can be 30°, and the twist angle Φ can be 0°. Furthermore, the rotation protocol can include rotating the wafer by up to 180° between two placement sub-steps. Therefore, compared to the several portions of fin 52 directly below the dummy gate structure, a larger amount of dopant can be placed on both the upper surface and sidewalls of fin 52. Thus, the etching rate of the material in the upper and lower portions of fin 52 can be increased by a similar amount compared to undoped fin 52. Alternatively, the rotation protocol can include rotating the wafer by up to 90° between four placement sub-steps. Therefore, dopant can also be placed in the several portions of fin 52 directly below the dummy gate structure, thereby increasing the etching rate of those portions.

[0146] Figure 20D The illustration shows an example of dopant placement to several portions of fin 52 directly beneath the dummy gate structure. Subsequent formation of the first source / drain recess 130A may include etching of the first fin 52A partially beneath the dummy gate structure, attributable to an increased concentration of dopant in those portions of the first fin 52A. Thus, the subsequently formed first epitaxial source / drain region 82A may extend partially beneath the dummy gate structure. For example, the tilt angle θ may be greater than 0°, such as ranging from 30° to 60°; and the twist angle Φ may be greater than or equal to 60°, such as 90°. For example, a rotation protocol may include rotating the wafer up to 180° between two placement sub-steps to allow dopant to reach fin 52 on opposite sides of the dummy gate structure. For example, a rotation protocol may include rotating the wafer up to 90° between four placement sub-steps to allow dopant to reach fin 52 on opposite sides of the gate structure and on opposite sidewalls of fin 52. Therefore, a larger amount of dopant can be implanted into the upper surface of fin 52 (and directly into several portions of the dummy gate structure) and a smaller amount into the sidewall surface of fin 52. Consequently, the material of the upper portion of fin 52 (e.g., with a higher concentration of dopant) can have a higher etching rate compared to the material of the lower portion of fin 52 (e.g., with a lower concentration of dopant).

[0147] Figure 20EThe illustrated example placement process provides relatively uniform placement of dopant to the upper and lower portions of fin 52, as well as placement of fin 52 directly beneath several portions of the dummy gate structure. For example, the tilt angle θ can range from 30° to 60°; and the twist angle Φ can range from 30° to 60°, such as about 45°. Rotation protocols may include rotating the wafer by up to 90° between four placement sub-steps to allow dopant to reach fin 52 on opposite sides of the dummy gate structure and on opposite sidewalls of fin 52 itself. As a result of dopant placement to the upper and side surfaces of fin 52, the etching rate of the material in the upper and lower portions of fin 52 can increase by a similar amount compared to undoped fin 52. Similarly, the etching rate of several portions of fin 52 directly beneath the dummy gate structure is increased compared to undoped fin 52.

[0148] Please note, Figures 20B to 20E Examples of the implantation process are provided in certain embodiments where the dopant will increase the etching rate of the material to which the dopant is implanted. However, these examples are not intended to be limiting. For instance, in embodiments where the dopant will reduce the etching rate of fin 52, different combinations of the above specifications may be selected.

[0149] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructure field-effect transistors (NSFETs) that are nanostructures (e.g., nanosheets, nanowires, all-around gates, or the like). In NSFET embodiments, fins are replaced by nanostructures, which are formed by alternating stacks of patterned channel layers and sacrificial layers. Dummy gate stacks (e.g., similar to dummy dielectric layer 60, dummy gate 72, and mask 74) and source / drain regions are formed in a manner similar to the embodiments described above. For example, a placement process can be used to adjust the etch rate of certain fins before forming source / drain recesses and growing epitaxial source / drain regions therein. After the dummy gate stack is removed, the sacrificial layer can be partially or completely removed from the channel region. Replacement gate stacks (e.g., similar to gate dielectric layer 92 and gate electrode) are formed in a manner similar to the embodiments described above, whereby the replacement gate stack can partially or completely fill the openings left by removing the sacrificial layer, and the replacement gate stack can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD, as well as the replacement gate stack and the contacts of the source / drain regions, can be formed in a manner similar to the embodiments described above. The nanostructure device can be formed as disclosed in U.S. Patent No. 9,647,071, which is incorporated herein by reference in its entirety.

[0150] Advantages can be achieved. The disclosed embodiments, for example, provide improved control, reliability, and consistency in the formation of the epitaxial source / drain regions 82 through improvements in the formation of the source / drain recess 130. Specifically, the difference in the geometry of the structure between the first region 200A and the second region 200B can cause a difference in the etching rate of those regions. However, the aforementioned modification of the material properties of, for example, the first region can be used to modify the etching rate of the first region to compensate for those differences. For example, in an embodiment where the first region may have a smaller pitch dummy gate structure than the second region, etching the first fin 52A to form the first source / drain recess 130A in the first region 200A may be slower than etching the second fin 52B to form the second source / drain recess 130B in the second region 200B. However, performing a placement process to place certain dopants into the first region 200A (before forming the source / drain recess 130) can increase the etching rate of the material, allowing the formation of the first source / drain recess 130A and the second source / drain recess 130B to be performed simultaneously and achieve the same specifications (e.g., the same depth). Furthermore, certain variations in the specifications or dimensions of the source / drain recess 130 can be achieved to the desired extent, and one or more placement processes can be performed to achieve those specific specifications. Due to the disclosed method, the resulting epitaxial source / drain regions 82 can be formed with increased efficiency and uniformity for the desired specifications. The resulting semiconductor device can be manufactured with increased yield and reliability.

[0151] In one embodiment, a method of forming a semiconductor device includes: forming a first dummy gate structure over a first region of a substrate and forming a second dummy gate structure over a second region of the substrate, the first region and the second region of the substrate having a first composite having a first etch rate; laterally implanting a plurality of dopants into the first region of the substrate adjacent to the first dummy gate structure, wherein after implanting the first region, the first region has a second composite having a second etch rate different from the first etch rate; etching a first recess in the first region of the substrate having the second composite and etching a second recess in the second region having the first composite; epitaxially growing a first source / drain region in the first recess and epitaxially growing a second source / drain region in the second recess. In another embodiment, the first dummy gate structure has a smaller pitch than the second dummy gate structure. In another embodiment, the second etch rate is greater than the first etch rate. In another embodiment, the method further includes masking the second region of the substrate before implanting the first region of the substrate; and not masking the second region of the substrate after implanting the first region of the substrate. In another embodiment, etching the first recess and the second recess includes etching the first recess and the second recess using the same etchant. In another embodiment, the method further includes lightly doping the first region and the second region with a plurality of first impurities after forming the first dummy gate structure and the second dummy gate structure. In another embodiment, the plurality of dopants are different from the plurality of first impurities. In another embodiment, the method further includes doping the first source / drain region and the second source / drain region with a plurality of second impurities, wherein the plurality of second impurities are different from the plurality of dopants.

[0152] In one embodiment, a method of forming a semiconductor device includes: forming a first gate structure over a first semiconductor region and forming a first isolation region adjacent to the first semiconductor region; forming a second gate structure over a second semiconductor region and forming a second isolation region adjacent to the second semiconductor region; forming a patterned mask layer having an opening, wherein the opening exposes a plurality of exposed portions of the first semiconductor region, the first gate structure, and the first isolation region, wherein the second semiconductor region, the second gate structure, and the second isolation region adjacent to the second gate structure remain covered by the patterned mask layer; and applying a doped... Dopant is implanted into the plurality of exposed portions of the first semiconductor region, the first gate structure, and the first isolation region, wherein the exposed portion of the first isolation region has a first concentration profile of the dopant extending from an upper surface of the first isolation region to the semiconductor substrate, wherein the first concentration region has a raised shape; the patterned mask layer is removed; the exposed portion of the first semiconductor region is etched to form a first recess in the first semiconductor region and a second recess in the second semiconductor region; and a first source / drain region is formed in the first recess and a second source / drain region is formed in the second recess. In another embodiment, the first concentration profile has a peak in a portion of the first isolation region. In another embodiment, the second isolation region is free of the dopant after the formation of the first source / drain region and the second source / drain region. In another embodiment, the first gate structure has a first spacing with a first adjacent gate structure, wherein the second gate structure has a second spacing with a second adjacent gate structure, and wherein the second spacing is greater than the first spacing. In another embodiment, the dopant comprises at least one of argon and germanium. In another embodiment, prior to the application of the dopant, the second isolation region comprises the dopant and has a second concentration profile of the dopant extending from an upper surface of the second isolation region to the semiconductor substrate, wherein the second concentration profile is flat. In another embodiment, the dopant comprises at least one of nitrogen and silicon.

[0153] In one embodiment, a semiconductor device includes: a first region comprising: a plurality of first gate electrodes having a first spacing; and a first epitaxial region disposed within a substrate and between the plurality of first gate electrodes, the first epitaxial region having a first depth below a top surface of the substrate; and a second region comprising: a plurality of second gate electrodes having a second spacing greater than the first spacing; and a second epitaxial region disposed within the substrate and between the plurality of second gate electrodes, the second epitaxial region having a second depth below the top surface of the substrate, the first depth being between 95% and 105% of the second depth. In another embodiment, the first region further includes a first isolation region comprising silicon oxide and a dopant, wherein the second region further includes a second isolation region comprising silicon oxide without the dopant. In another embodiment, the semiconductor device further includes a third region comprising: a plurality of third gate electrodes having the first spacing; and a third epitaxial region disposed within the substrate and located between the plurality of third gate electrodes, the third epitaxial region having a third depth below the top surface of the substrate, the third depth being less than the first depth. In another embodiment, the third region further includes a third isolation region free of the dopant. In another embodiment, a first concentration profile of the dopant in the first isolation region is curved, while a second concentration profile of the dopant in the second isolation region is flat.

[0154] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes the following steps: A first dummy gate structure is formed over a first region of a substrate and a second dummy gate structure is formed over a second region of the substrate. The first region and the second region of the substrate have a first composite material, and the first composite material has a first etching rate. Laterally adjacent to the first dummy gate structure, a first region of the substrate is implanted with a plurality of dopants. After implantation of the first region, the first region has a second complex with a second etch rate different from the first etch rate. The plurality of dopants include nitrogen, argon, silicon, germanium, or combinations thereof. The first region includes a first isolation region containing the plurality of dopants. The first isolation region has a plurality of first concentration profiles of the plurality of dopants extending from an upper surface of the first isolation region to the substrate. Each of the plurality of first concentration profiles has a convex shape and a peak value in a portion of the first isolation region. A first recess is etched in the first region of the substrate having the second composite, and a second recess is etched in the second region having the first composite; and A first source / drain region is epitaxially grown in the first recess and a second source / drain region is epitaxially grown in the second recess.

2. The method as described in claim 1, characterized in that, The first dummy gate structure has a smaller pitch than the second dummy gate structure.

3. The method as described in claim 1, characterized in that, The second etching rate is greater than the first etching rate.

4. The method as described in claim 1, characterized in that, Further steps include: Before implanting the substrate in the first region, the second region of the substrate is masked; and After the first region of the substrate is implanted, the second region of the substrate is not covered.

5. The method as described in claim 1, characterized in that, Etching the first recess and the second recess involves using the same etchant to etch the first recess and the second recess.

6. The method as described in claim 1, characterized in that, The method further includes a step of lightly doping the first region and the second region with a plurality of first impurities after forming the first dummy gate structure and the second dummy gate structure.

7. The method as described in claim 6, characterized in that, The plurality of dopants are different from the plurality of first impurities.

8. The method as described in claim 7, characterized in that, The method further includes the step of doping the first source / drain region and the second source / drain region with a plurality of second impurities, wherein the plurality of second impurities are different from the plurality of dopants.

9. A method for forming a semiconductor device, characterized in that, The method includes the following steps: A first gate structure is formed above a first semiconductor region and a first isolation region is formed adjacent to the first semiconductor region; A second gate structure is formed above a second semiconductor region and a second isolation region is formed adjacent to the second semiconductor region; A patterned mask layer is formed having an opening, wherein the opening exposes a plurality of exposed portions of the first semiconductor region, the first gate structure, and the first isolation region, wherein the second semiconductor region, the second gate structure, and the second isolation region adjacent to the second gate structure remain covered by the patterned mask layer; A dopant is implanted into the plurality of exposed portions of the first semiconductor region, the first gate structure, and the first isolation region, wherein the exposed portion of the first isolation region has a first concentration profile of the dopant extending from an upper surface of the first isolation region to a semiconductor substrate, wherein the first concentration profile has a convex shape and a peak in a portion of the first isolation region. Remove the patterned mask layer; The exposed portion of the first semiconductor region is etched to form a first recess in the first semiconductor region and a second recess in the second semiconductor region; and A first source / drain region is formed in the first recess and a second source / drain region is formed in the second recess.

10. The method as described in claim 9, characterized in that, Etching the first recess and the second recess involves using the same etchant to etch the first recess and the second recess.

11. The method as described in claim 9, characterized in that, After the first source / drain region and the second source / drain region are formed, the second isolation region is free of the dopant.

12. The method as described in claim 11, characterized in that, The first gate structure has a first spacing with a first adjacent gate structure, and the second gate structure has a second spacing with a second adjacent gate structure, wherein the second spacing is greater than the first spacing.

13. The method as described in claim 11, characterized in that, The dopant contains at least one of argon and germanium.

14. The method as described in claim 9, characterized in that, Before the dopant is applied, the second isolation region contains the dopant and has a second concentration profile of the dopant extending from an upper surface of the second isolation region to the semiconductor substrate, wherein the second concentration profile is flat.

15. The method as described in claim 14, characterized in that, The dopant contains at least one of nitrogen and silicon.

16. A semiconductor device, characterized in that, Include: Zone 1, comprising: A plurality of first gate electrodes having a first spacing; and A first epitaxial region, disposed within a substrate and between the plurality of first gate electrodes, the first epitaxial region having a first depth below a top surface of the substrate; and A first isolation region is disposed within the substrate, the first isolation region comprising a dopant, wherein the first isolation region has a first concentration profile of the dopant extending from an upper surface of the first isolation region to the substrate, wherein the first concentration profile has a raised shape and a peak value in a portion of the first isolation region; and Zone 1, Section 2, includes: A plurality of second gate electrodes, the plurality of second gate electrodes having a second spacing greater than the first spacing; and A second epitaxial region is disposed within the substrate and located between the plurality of second gate electrodes. The second epitaxial region has a second depth below the top surface of the substrate, and the first depth is between 95% and 105% of the second depth.

17. The semiconductor device as claimed in claim 16, characterized in that, The first isolation region comprises silicon oxide, and the second region further comprises a second isolation region comprising silicon oxide without the dopant.

18. The semiconductor device as claimed in claim 17, characterized in that, The semiconductor device further includes a third region, the third region comprising: A plurality of third gate electrodes having the first spacing; and A third epitaxial region is disposed within the substrate and located between the plurality of third gate electrodes. The third epitaxial region has a third depth below the top surface of the substrate, the third depth being less than the first depth.

19. The semiconductor device as claimed in claim 18, characterized in that, The third region further includes a third isolation region, which is free of the dopant.

20. The semiconductor device as claimed in claim 17, characterized in that, The second concentration profile of the dopant in the second isolation region is flat.

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