A method of forming a through-silicon via structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT TIANJIN
- Filing Date
- 2021-12-15
- Publication Date
- 2026-07-21
Smart Images
Figure CN116264183B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method for forming a through-silicon via (TSV) structure. Background Technology
[0002] In multilayer stacked wafers, the stacked wafers (also called functional wafers, hereinafter referred to as functional wafers) are connected by through silicon vias (TSVs) for electrical signals. The size of the TSV directly affects the electrical signal interconnection density between wafers, so the cross-sectional view of the TSV structure should be as close to a rectangle as possible rather than an inverted trapezoid to achieve precise control of the critical dimension of the TSV core.
[0003] Because TSV structures are relatively deep, in addition to using photoresist as a mask, a thick dielectric layer needs to be deposited as a hard mask layer when etching to form through-silicon vias (TSVs). Only with a thick hard mask layer can the TSV core size be precisely controlled. However, in current processes, the hard mask layer is formed on the bonded bottom wafer and functional wafer. Since the functional wafer and bottom wafer are already quite thick, this limits the thickness of the hard mask layer.
[0004] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the Invention
[0005] This application provides a method for forming a through-silicon via (TSV) structure, which can increase the thickness of the hard mask layer, thereby precisely controlling the core size of the TSV structure, and thus increasing the density of the TSV structure and the electrical signal interconnection density between functional wafers.
[0006] This application provides a method for forming a through-silicon via (TSV) structure, comprising: providing a carrier wafer, wherein a hard mask layer and a first bonding mark layer are sequentially formed on the surface of the carrier wafer; bonding a first side of the carrier wafer and a functional wafer through the bonding mark layer; providing a bottom wafer, wherein a first dielectric layer and a first metal layer located in the first dielectric layer are formed on the surface of the bottom wafer; bonding a second side of the bottom wafer and the functional wafer; removing the carrier wafer; etching the first bonding mark layer and the functional wafer using the hard mask layer as a mask to form a TSV that penetrates the first bonding mark layer and the functional wafer and exposes the first metal layer; and filling the TSV with metal to form a TSV structure.
[0007] In some embodiments of this application, an adhesion layer and a first etch stop layer are sequentially formed between the carrier wafer surface and the hard mask layer, and a second etch stop layer is formed between the hard mask layer and the first bonding mark layer.
[0008] In some embodiments of this application, the thickness of the adhesion layer is 50 to 200 angstroms, and the thickness of the first bonding marker layer is 3000 to 5000 angstroms.
[0009] In some embodiments of this application, the thickness of the hard mask layer is 10,000 to 40,000 angstroms, the thickness of the first etch stop layer is 500 to 2,000 angstroms, and the thickness of the second etch stop layer is 50 to 500 angstroms.
[0010] In some embodiments of this application, the thickness of the hard mask layer is 10,000 to 30,000 angstroms, the thickness of the first etch stop layer is 1,000 to 5,000 angstroms, and the thickness of the second etch stop layer is 1,000 to 2,000 angstroms.
[0011] In some embodiments of this application, the adhesion layer is also removed when the carrier wafer is removed.
[0012] In some embodiments of this application, a second bonding mark layer is further formed on the first side of the functional wafer, and the carrier wafer and the first side of the functional wafer are bonded together through the first bonding mark layer and the second bonding mark layer.
[0013] In some embodiments of this application, after bonding the first surfaces of the carrier wafer and the functional wafer through the bonding marker layer, the method further includes: thinning the functional wafer.
[0014] In some embodiments of this application, a third bonding mark layer is formed on the second side of the functional wafer.
[0015] In some embodiments of this application, a third etch stop layer and a fourth bonding mark layer are sequentially formed on the surface of the first dielectric layer of the bottom wafer, and the second surfaces of the bottom wafer and the functional wafer are bonded through the third bonding mark layer and the fourth bonding mark layer.
[0016] In some embodiments of this application, a method for etching the first bonding marker layer and the functional wafer using the hard mask layer as a mask to form a through-silicon via (TSV) that penetrates the first bonding marker layer and the functional wafer and exposes the first metal layer includes: forming a patterned photoresist layer on the surface of the first etch stop layer, the patterned photoresist layer defining the location of the TSV; first etching the first etch stop layer, the hard mask layer, the second etch stop layer, and the first bonding marker layer using the patterned photoresist layer as a mask to expose a first side of the functional wafer to form the TSV; second etching the functional wafer along the TSV to expose the third bonding marker layer; third etching the third bonding marker layer and the fourth bonding marker layer along the TSV to expose the third etch stop layer; and fourth etching the third etch stop layer along the TSV to expose the first metal layer.
[0017] In some embodiments of this application, after etching the third bonding mark layer and the fourth bonding mark layer along the through-silicon via to expose the third etch stop layer, the method further includes forming a barrier layer on the sidewall and bottom of the through-silicon via.
[0018] In some embodiments of this application, when the third etch stop layer is etched along the through-silicon via (TSV) to expose the first metal layer, the barrier layer at the bottom of the TSV is also etched.
[0019] This application provides a method for forming a through-silicon via (TSV) structure. A hard mask layer is fabricated on a carrier wafer, and then the hard mask layer is bonded to a functional wafer. This method can increase the thickness of the hard mask layer, thereby precisely controlling the core size of the TSV structure, and thus increasing the density of the TSV structure and the electrical signal interconnection density between functional wafers. Attached Figure Description
[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0021] in:
[0022] Figure 1 This is a cross-sectional view of a through-silicon via structure;
[0023] Figure 2 This is a planar distribution diagram of a through-silicon via structure;
[0024] Figure 3 This is a cross-sectional view of another through-silicon via structure;
[0025] Figure 4 This is a planar distribution diagram of another type of through-silicon via structure;
[0026] Figure 5 This is a flowchart of the method for forming a through-silicon via structure according to an embodiment of this application;
[0027] Figures 6 to 17 This is a schematic diagram of each step in the method for forming a through-silicon via structure according to an embodiment of this application. Detailed Implementation
[0028] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0029] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0030] Figure 1 This is a cross-sectional view of a through-silicon via structure. Figure 2 This is a planar distribution diagram of a through-silicon via (TSV) structure. It should be noted that... Figure 1 and Figure 2 This is a simplified diagram intended to concisely illustrate the shape and distribution of the through-silicon via (TSV) structure.
[0031] refer to Figure 1 As shown, a through-silicon via (TSV) structure 110 is formed in wafer 100. The cross-sectional shape of the TSV structure 110 is rectangular, and the three-dimensional shape of the TSV structure 110 is cylindrical. The dimensions of the upper surface of the TSV structure 110 are the same as the dimensions of the lower surface of the TSV structure 110.
[0032] refer to Figure 2 As shown, Figure 2 The distribution of the through-silicon via (TSV) structure 110 on the surface of the wafer 100 is shown. The TSV structure 110 is uniformly distributed on the surface of the wafer 100.
[0033] Figure 3 This is a cross-sectional view of another through-silicon via structure. Figure 4 This is a planar distribution diagram of another type of through-silicon via (TSV) structure. It should be noted that... Figure 3 and Figure 4 This is a simplified diagram intended to concisely illustrate the shape and distribution of the through-silicon via (TSV) structure.
[0034] refer to Figure 3 As shown, a through-silicon via (TSV) structure 210 is formed in wafer 200. The cross-sectional shape of the TSV structure 210 is an inverted trapezoid, and the three-dimensional shape of the TSV structure 210 is an inverted frustum. The upper surface dimension of the TSV structure 210 is larger than the lower surface dimension of the TSV structure 210.
[0035] refer to Figure 4 As shown, Figure 4 The distribution of the through-silicon via (TSV) structure 210 on the surface of the wafer 200 is shown. The TSV structure 210 is uniformly distributed on the surface of the wafer 200.
[0036] contrast Figure 1 and Figure 3 It can be concluded that, under the same core size (that is, under the same surface size of the through-silicon via structure), Figure 3 The upper surface dimension of the through-silicon via structure 210 shown is larger than that of the through-silicon via structure 210. Figure 1 The dimensions of the upper surface of the through-silicon via structure 110 are shown. Further comparison is needed. Figure 2 and Figure 4 It can be concluded that, given the same wafer surface area, Figure 4 The distribution density of the silicon through-hole structure 210 in the middle is less than that of the silicon through-hole structure 21 Figure 1 The distribution density of the through-silicon via (TSV) structure 110 in the structure. That is, Figure 1 and Figure 2 The high density of the through-silicon via (TSV) structure 110 shown can improve the electrical signal interconnection density between functional wafers.
[0037] When fabricating through-silicon via (TSV) structures using etching processes, a hard mask layer is required as a mask for etching. The thicker the hard mask layer, the closer the shape of the fabricated TSV structure will be to the desired shape. Figure 1 The shape of the through-silicon via (TSV) structure 110 is shown. In other words, the thicker the hard mask layer, the better it is for controlling the core size of the TSV structure, and the higher the distribution density of the TSV structure, thereby increasing the electrical signal interconnection density between functional wafers.
[0038] However, in current processes, hard mask layers are formed on the bonded bottom and functional wafers. The thicker the hard mask layer, the greater the stress it exerts on the functional and bottom wafers, leading to severe wafer warpage. Therefore, it is currently not possible to form thicker hard mask layers on the functional wafer, which limits improvements to the through-silicon via (TSV) structure.
[0039] To address the aforementioned issues, this application provides a method for forming a through-silicon via (TSV) structure. A hard mask layer is fabricated on a carrier wafer, and then the hard mask layer is bonded to a functional wafer. This method can increase the thickness of the hard mask layer, thereby precisely controlling the core dimensions of the TSV structure, and thus increasing the density of the TSV structure and the electrical signal interconnection density between functional wafers.
[0040] Figure 5 This is a flowchart of the method for forming a through-silicon via structure according to an embodiment of this application.
[0041] Embodiments of this application provide a method for forming a through-silicon via (TSV) structure, referencing... Figures 6 to 17 As shown, it includes:
[0042] Step S1: Provide a carrier wafer, on the surface of which a hard mask layer and a first bonding mark layer are sequentially formed;
[0043] Step S2: Bond the first surfaces of the carrier wafer and the functional wafer using the bonding marker layer;
[0044] Step S3: Provide a bottom wafer, wherein a first dielectric layer and a first metal layer located in the first dielectric layer are formed on the surface of the bottom wafer;
[0045] Step S4: Bond the second side of the bottom wafer and the functional wafer;
[0046] Step S5: Remove the carrier wafer;
[0047] Step S6: Using the hard mask layer as a mask, etch the first bonding mark layer and the functional wafer to form a through-silicon via that penetrates the first bonding mark layer and the functional wafer and exposes the first metal layer;
[0048] Step S7: Fill the through silicon via with metal to form a through silicon via structure.
[0049] Figure 5 This is a schematic diagram of each step in the method for forming a through-silicon via (TSV) structure according to an embodiment of this application. The method for forming a TSV structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0050] refer to Figure 6 and Figure 5 As shown, in step S1, a carrier wafer 300 is provided, on which a hard mask layer 330 and a first bonding mark layer 350 are sequentially formed. The hard mask layer 330 is used as a mask for the etching process during subsequent fabrication of the through-silicon via (TSV) structure. The first bonding mark layer 350 serves as a bonding interface when the carrier wafer 300 is subsequently bonded to the functional wafer. Bonding marks (not shown in the figure) for alignment are formed in the first bonding mark layer 350.
[0051] In conventional processes, a carrier wafer and a functional wafer are first bonded together, then the functional wafer and a bottom wafer are bonded together. The carrier wafer is then removed, and a hard mask layer is formed on both the functional and bottom wafers. This hard mask layer is then used as a mask to etch the functional wafer to create a through-silicon via (TSV) structure. Since the hard mask layer is formed on the functional and bottom wafers, and the fabrication process is performed at high temperatures (approximately 400 degrees Celsius), both the functional and bottom wafers are simultaneously heat-treated. This affects the device performance on these wafers and reduces device reliability. Furthermore, the functional and bottom wafers are already relatively thick, resulting in high overall wafer warpage. The compressive stress exerted by the hard mask layer on the functional and bottom wafers further exacerbates this warpage, affecting subsequent processes. This also limits the possibility of further increasing the thickness of the hard mask layer, restricting improvements to the TSV structure.
[0052] However, in the technical solution of this application, the hard mask layer 330 is not formed on the functional wafer and the bottom wafer, but on the carrier wafer 300, and then bonded to the functional wafer together with the carrier wafer 300. Therefore, it will not cause any impact on the functional wafer and the bottom wafer due to heat treatment. In addition, the hard mask layer 330 is bonded to the functional wafer after being rotated 180 degrees, and the stress direction of the hard mask layer 330 on the functional wafer is also rotated 180 degrees. Therefore, the hard mask layer 330 not only does not aggravate the warpage of the functional wafer and the bottom wafer, but can also neutralize the stress and reduce the warpage of the functional wafer and the bottom wafer. Moreover, since the hard mask layer 330 does not aggravate the warpage of the functional wafer and the bottom wafer, the thickness of the hard mask layer 330 can be thicker, thereby improving the through-silicon via (TSV) structure, that is, making the cross-sectional shape of the TSV structure closer to a rectangle, thereby increasing the distribution density of the TSV structure, and thus increasing the electrical signal interconnection density between functional wafers.
[0053] In some embodiments of this application, the carrier wafer 300 is, for example, a semiconductor wafer or a glass wafer. The carrier wafer 300 serves as a carrier for the functional wafer.
[0054] In some embodiments of this application, an adhesion layer 310 and a first etch stop layer 320 are sequentially formed between the surface of the carrier wafer 300 and the hard mask layer 330, and a second etch stop layer 340 is formed between the hard mask layer 330 and the first bonding mark layer 350.
[0055] The first etch stop layer 320 is used to protect the hard mask layer 330 from damage when the carrier wafer 300 and the adhesion layer 310 are removed in subsequent processes. The material of the first etch stop layer 320 is, for example, silicon nitride. The method for forming the first etch stop layer 320 is, for example, a chemical vapor deposition process or a physical vapor deposition process.
[0056] The adhesion layer 310 serves as a substrate for depositing the first etch stop layer 320. The first etch stop layer 320 is made of silicon nitride, which cannot be directly formed on the surface of a silicon wafer (i.e., the carrier wafer 300). Therefore, the adhesion layer 310 is needed as an intermediate medium to form the first etch stop layer 320. The material of the adhesion layer 310 is, for example, silicon oxide. The method for forming the adhesion layer 310 is, for example, a chemical vapor deposition process or a physical vapor deposition process.
[0057] The second etch stop layer 340 serves two purposes: firstly, to protect the hard mask layer 330 from damage during the formation of bonding marks in the first bonding mark layer 350; and secondly, to improve the uniformity of the bonding mark depth in the first bonding mark layer 350. The material of the second etch stop layer 340 is, for example, silicon nitride. The method for forming the second etch stop layer 340 is, for example, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.
[0058] In some embodiments of this application, the thickness of the adhesion layer 310 is 50 to 200 angstroms, and the thickness of the first bonding marker layer 350 is 3000 to 5000 angstroms.
[0059] In some embodiments of this application, the thickness of the hard mask layer 330 is 10,000 to 40,000 angstroms, the thickness of the first etch stop layer 320 is 500 to 2,000 angstroms, and the thickness of the second etch stop layer 340 is 50 to 500 angstroms. Since the hard mask layer 330 in this application is formed on the carrier wafer 300, its thickness can be greater.
[0060] In other embodiments of this application, the first etch stop layer 320 and the second etch stop layer 340 may also function as etch masks, similar to the hard mask layer 330. Specifically, the thickness of the hard mask layer 330 can be reduced, and then the thicknesses of the first etch stop layer 320 and the second etch stop layer 340 can be increased. Specifically, the thickness of the hard mask layer 330 is 10,000 to 30,000 angstroms, the thickness of the first etch stop layer 320 is 1,000 to 5,000 angstroms, and the thickness of the second etch stop layer 340 is 1,000 to 2,000 angstroms.
[0061] Continue to refer to Figure 7 andFigure 8 As shown, in step S2, the first surfaces of the carrier wafer 300 and the functional wafer 400 are bonded together through the bonding marker layer 350. The functional wafer 400 is, for example, a semiconductor wafer.
[0062] In some embodiments of this application, a second bonding mark layer 410 is further formed on the first side of the functional wafer 400, and the carrier wafer 300 and the first side of the functional wafer 400 are bonded together through the first bonding mark layer 350 and the second bonding mark layer 410. Bonding marks for alignment (not shown in the figures) are formed in the second bonding mark layer 410. The material of the second bonding mark layer 410 is, for example, silicon oxide. The method for forming the second bonding mark layer 410 is, for example, a chemical vapor deposition process or a physical vapor deposition process.
[0063] In some embodiments of this application, other films are also formed between the functional wafer 400 and the second bonding marker layer 410 (these are omitted for brevity). Examples include an etch stop layer below the second bonding marker layer 410, a metal interconnect layer on the surface of the functional wafer 400, and device structures on the functional wafer 400.
[0064] In some embodiments of this application, an edge trimming process is also required on the functional wafer 400 to remove a portion of the edge of the functional wafer 400 and the second bonding mark layer 410 located on the functional wafer 400. For the sake of brevity, this edge trimming process is omitted in this application.
[0065] refer to Figure 5 As shown, in some embodiments of this application, after bonding the first surfaces of the carrier wafer 300 and the functional wafer 400 through the bonding marker layer 350, the method further includes: thinning the functional wafer 400. The method for thinning the functional wafer 400 includes a chemical mechanical polishing process.
[0066] In some embodiments of this application, a third bonding mark layer 420 is formed on the second side of the functional wafer 400. After thinning the functional wafer 400, the third bonding mark layer 420 is formed on the second side of the functional wafer 400, and bonding marks for alignment (not shown) are formed in the third bonding mark layer 420. The third bonding mark layer 420 is used to bond the functional wafer 400 and the bottom wafer. The material of the third bonding mark layer 420 is, for example, silicon oxide. The method for forming the third bonding mark layer 420 is, for example, a chemical vapor deposition process or a physical vapor deposition process.
[0067] Continue to refer to Figure 9 and Figure 5As shown, in step S3, a bottom wafer 500 is provided, on which a first dielectric layer 510 and a first metal layer 520 are formed.
[0068] In some embodiments of this application, the bottom wafer 500 is, for example, a semiconductor wafer.
[0069] In some embodiments of this application, semiconductor devices and metal interconnect structures are also formed in the first dielectric layer 510. The first metal layer 520 is the top metal of the metal interconnect structure and is used to electrically connect the devices in the bottom wafer 500 and the devices in the functional wafer 400.
[0070] In some embodiments of this application, a third etch stop layer 530 and a fourth bonding mark layer 540 are sequentially formed on the surface of the first dielectric layer 510 of the bottom wafer 500.
[0071] The third etch stop layer 530 is used to protect the first metal layer 520 from damage during subsequent formation of the through-silicon via (TSV) structure. The material of the third etch stop layer 530 is, for example, silicon nitride. The method for forming the third etch stop layer 530 is, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD).
[0072] The fourth bonding marker layer 540 is used to bond the functional wafer 400 and the bottom wafer 500. Bonding marks (not shown) for alignment are formed in the fourth bonding marker layer 540. The material of the fourth bonding marker layer 540 is, for example, silicon oxide. The method for forming the fourth bonding marker layer 540 is, for example, a chemical vapor deposition process or a physical vapor deposition process.
[0073] Continue to refer to Figure 10 and Figure 5 As shown, in step S4, the second surfaces of the bottom wafer 500 and the functional wafer 400 are bonded together. Specifically, the second surfaces of the bottom wafer 500 and the functional wafer 400 are bonded together through the third bonding mark layer 420 and the fourth bonding mark layer 540.
[0074] Continue to refer to Figure 11 and Figure 5 As shown, in step S5, the carrier wafer 300 is removed.
[0075] In some embodiments of this application, the adhesion layer 310 is also removed when the carrier wafer 300 is removed.
[0076] In some embodiments of this application, the method for removing the carrier wafer 300 and the adhesion layer 310 includes: first, using a chemical mechanical polishing process to grind away most of the carrier wafer 300; and then using a wet etching process to etch away the remaining small portion of the carrier wafer 300 and the adhesion layer 310. Due to the protective effect of the first etch stop layer 320, the hard mask layer 330 will not be etched and will not be damaged.
[0077] In conventional processes, the hard mask layer 330 is formed on the functional wafer 400 and the bottom wafer 500 at this stage (i.e., after bonding the functional wafer 400 and the bottom wafer 500 together and removing the carrier wafer 300). Therefore, on the one hand, the high-temperature environment during the formation of the hard mask layer 330 will have a thermal impact on the functional wafer 400 and the bottom wafer 500, reducing the device reliability of the functional wafer 400 and the bottom wafer 500; on the other hand, the hard mask layer 330 will exert downward compressive stress on the functional wafer 400 and the bottom wafer 500, resulting in severe warpage of the functional wafer 400 and the bottom wafer 500, affecting subsequent processes.
[0078] However, in the technical solution of this application, the hard mask layer 330 is formed on the carrier wafer 300, and subsequently bonded together with the carrier wafer 300 to the functional wafer 400, and then to the bottom wafer 500. Therefore, on the one hand, there is no thermal impact on the functional wafer 400 and the bottom wafer 500; on the other hand, since the hard mask layer 330 is located on the carrier wafer 300 and then flipped 180 degrees before being bonded to the functional wafer 400 and the bottom wafer 500, the flipped hard mask layer 330 generates an upward tensile stress on the bottom wafer 300 (this is because film stress is a characteristic of the film itself, and after deposition, it is not affected by its orientation). This tensile stress can balance the stress of the functional wafer 400 and the bottom wafer 500, thereby reducing the warpage of the functional wafer 400 and the bottom wafer 500.
[0079] Continue to refer to Figures 12 to 17 and Figure 12 As shown, in step S6, the first bonding mark layer 350 and the functional wafer 400 are etched using the hard mask layer 330 as a mask to form a through-silicon via 600 that penetrates the first bonding mark layer 350 and the functional wafer 400 and exposes the first metal layer 520.
[0080] refer to Figure 13 As shown, a patterned photoresist layer 610 is formed on the surface of the first etch stop layer 320, and the patterned photoresist layer 610 defines the position of the through silicon via 600.
[0081] refer to Figure 14As shown, using the patterned photoresist layer 610 as a mask, the first etch stop layer 320, hard mask layer 330, second etch stop layer 340, first bonding mark layer 350, and second bonding mark layer 410 are etched to expose the first surface of the functional wafer 400 to form a through-silicon via 600.
[0082] The first etching process uses an etchant with high selectivity for etching silicon oxide, silicon nitride (the first etch stop layer 320, hard mask layer 330, second etch stop layer 340, first bonding mark layer 350, and second bonding mark layer 410 are all silicon oxide or silicon nitride), and silicon (the functional wafer 400 is made of silicon). This ensures that the first etching stops on the surface of the functional wafer 400.
[0083] In some embodiments of this application, the first etching is anisotropic etching. Due to the deep etching depth, the patterned photoresist layer 610 is completely consumed.
[0084] refer to Figure 15 As shown, the functional wafer 400 is etched a second time along the through-silicon via 600 to expose the third bonding marker layer 420.
[0085] The second etching process uses a second etchant that is highly selective for etching silicon materials (the functional wafer 400 is silicon material) and silicon oxide materials (the third bonding mark layer 420 is silicon oxide material). This ensures that the second etching stops on the surface of the third bonding mark layer 420.
[0086] In some embodiments of this application, the second etching is anisotropic etching. The first etch stop layer 320 is completely consumed, and the hard mask layer 330 is also partially consumed.
[0087] refer to Figure 16 As shown, the third bonding marker layer 420 and the fourth bonding marker layer 540 are etched along the silicon via 600 to expose the third etch stop layer 530. Due to the protection of the third etch stop layer 530, the first metal layer 520 is not etched and damaged.
[0088] The third etching process uses a highly selective etchant that is effective against both silicon oxide (the third bonding mark layer 420 and the fourth bonding mark layer 540 are made of silicon oxide) and silicon nitride (the third etch stop layer 530 is made of silicon nitride). This ensures that the third etching stops on the surface of the third etch stop layer 530.
[0089] In some embodiments of this application, the third etching is anisotropic etching. The hard mask layer 330, the second etch stop layer 340, and the first bonding marker layer 350 are completely consumed.
[0090] In some embodiments of this application, after etching the third bonding mark layer 420 and the fourth bonding mark layer 540 along the through-silicon via 600 to expose the third etch stop layer 530, a barrier layer (not shown in the figure) is formed on the sidewall and bottom of the through-silicon via 600.
[0091] The barrier layer is used to prevent metal particles in the via structure subsequently formed in the via 600 from diffusing into the functional wafer 400, thereby short-circuiting the functional wafer 400. The material of the barrier layer is, for example, silicon oxide. The method for forming the barrier layer is, for example, chemical vapor deposition or physical vapor deposition.
[0092] refer to Figure 5 As shown, the third etch stop layer 530 is etched along the silicon via 600 to expose the first metal layer 520.
[0093] In some embodiments of this application, when the third etch stop layer 530 is etched for the fourth time along the through-silicon via 600 to expose the first metal layer 520, the barrier layer at the bottom of the through-silicon via 600 is also etched.
[0094] In the technical solution of this application, because the first etch stop layer 320, the hard mask layer 330, and the second etch stop layer 340 (that is, the film layer that serves as the etch mask when etching to form the through-silicon via 600) are relatively thick, the shape of the through-silicon via 600 can be controlled more precisely, making the cross-sectional shape of the through-silicon via 600 closer to a rectangle rather than an inverted trapezoid. This increases the density of the subsequently formed through-silicon via structure and improves the electrical signal interconnection density between functional wafers.
[0095] Continue to refer to Figure 17 and As shown, in step S7, metal is filled into the through-silicon via 600 to form a through-silicon via structure 620. The through-silicon via structure 620 is electrically connected to the first metal layer 520.
[0096] In the technical solution of this application, the through-silicon via structure 620 has a high density, which can improve the electrical signal interconnection density between functional wafers.
[0097] The material of the through-silicon via structure 620 is, for example, copper or tungsten. The method of forming the through-silicon via structure 620 is, for example, an electroplating process.
[0098] This application provides a method for forming a through-silicon via (TSV) structure. A hard mask layer is fabricated on a carrier wafer, and then the hard mask layer is bonded to a functional wafer. This method can increase the thickness of the hard mask layer, thereby precisely controlling the core size of the TSV structure, and thus increasing the density of the TSV structure and the electrical signal interconnection density between functional wafers.
[0099] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0100] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0101] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0102] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0103] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a through-silicon via (TSV) structure, characterized in that, include: A carrier wafer is provided, wherein a hard mask layer and a first bonding mark layer are sequentially formed on the surface of the carrier wafer; The first surfaces of the carrier wafer and the functional wafer are bonded together through the bonding marker layer; A bottom wafer is provided, wherein a first dielectric layer and a first metal layer are formed on the surface of the bottom wafer; Bond the second side of the bottom wafer and the functional wafer; Remove the carrier wafer; Using the hard mask layer as a mask, the first bonding mark layer and the functional wafer are etched to form a through-silicon via that penetrates the first bonding mark layer and the functional wafer and exposes the first metal layer; Metal is filled into the through-silicon via to form a through-silicon via structure.
2. The method for forming a through-silicon via structure as described in claim 1, characterized in that, An adhesion layer and a first etch stop layer are sequentially formed between the surface of the carrier wafer and the hard mask layer, and a second etch stop layer is formed between the hard mask layer and the first bonding mark layer.
3. The method for forming a through-silicon via structure as described in claim 2, characterized in that, The thickness of the adhesion layer is 50 to 200 angstroms, and the thickness of the first bonding marker layer is 3000 to 5000 angstroms.
4. The method for forming a through-silicon via structure as described in claim 3, characterized in that, The thickness of the hard mask layer is 10,000 to 40,000 angstroms, the thickness of the first etch stop layer is 500 to 2,000 angstroms, and the thickness of the second etch stop layer is 50 to 500 angstroms.
5. The method for forming a through-silicon via structure as described in claim 3, characterized in that, The thickness of the hard mask layer is 10,000 to 30,000 angstroms, the thickness of the first etch stop layer is 1,000 to 5,000 angstroms, and the thickness of the second etch stop layer is 1,000 to 2,000 angstroms.
6. The method for forming a through-silicon via structure as described in claim 2, characterized in that, The adhesion layer is also removed when the carrier wafer is removed.
7. The method for forming a through-silicon via structure as described in claim 1, characterized in that, The first side of the functional wafer is further formed with a second bonding mark layer, and the first side of the carrier wafer and the functional wafer are bonded together through the first bonding mark layer and the second bonding mark layer.
8. The method for forming a through-silicon via structure as described in claim 1, characterized in that, After bonding the first side of the carrier wafer and the functional wafer through the bonding marker layer, the process further includes: thinning the functional wafer.
9. The method for forming a through-silicon via structure as described in claim 2, characterized in that, A third bonding marker layer is formed on the second side of the functional wafer.
10. The method for forming a through-silicon via structure as described in claim 9, characterized in that, A third etch stop layer and a fourth bonding mark layer are sequentially formed on the surface of the first dielectric layer of the bottom wafer, and the second surfaces of the bottom wafer and the functional wafer are bonded together through the third bonding mark layer and the fourth bonding mark layer.
11. The method for forming a through-silicon via structure as described in claim 10, characterized in that, A method for etching the first bonding mark layer and the functional wafer using the hard mask layer as a mask to form a through-silicon via (TSV) that penetrates the first bonding mark layer and the functional wafer and exposes the first metal layer includes: A patterned photoresist layer is formed on the surface of the first etch stop layer, and the patterned photoresist layer defines the location of the through silicon via; Using the patterned photoresist layer as a mask, a first etching stop layer, a hard mask layer, a second etching stop layer, and a first bonding marker layer are etched until the first surface of the functional wafer is exposed to form a through-silicon via; The functional wafer is etched along the through-silicon via a second etching process to expose the third bonding marker layer; The third bonding marker layer and the fourth bonding marker layer are etched along the through-silicon via until the third etch stop layer is exposed; The third etch stop layer is etched along the through-silicon via to expose the first metal layer.
12. The method for forming a through-silicon via structure as described in claim 11, characterized in that, After etching the third bonding mark layer and the fourth bonding mark layer along the through-silicon via to expose the third etch stop layer, the process further includes forming a barrier layer on the sidewall and bottom of the through-silicon via.
13. The method for forming a through-silicon via structure as described in claim 12, characterized in that, When the third etch stop layer is etched along the through-silicon via to expose the first metal layer, the barrier layer at the bottom of the through-silicon via is also etched.