Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The embodiments provide a semiconductor memory device capable of reducing the contact resistance of contacts connected to multiple conductive layers, and a method for manufacturing the semiconductor memory device. The semiconductor memory device of the embodiments includes: a laminate formed by alternately stacking multiple first conductive layers and multiple first insulating layers, including stepped portions where the multiple first conductive layers are processed into a stepped shape; pillars extending along the stacking direction within the laminate, which separates from the stepped portions in a first direction intersecting the stacking direction of the laminate, and forming memory cells at intersections with at least a portion of the multiple first conductive layers; and contact portions disposed on the stepped portions, connected to one of the multiple first conductive layers, the contact portions having a second conductive layer extending from the upper part of the stepped portions toward the first conductive layer and integrated with the first conductive layer.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-201619 (filed on December 13, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0003] In three-dimensional non-volatile memory, memory cells are arranged in a three-dimensional manner, for example, in a stack formed by stacking multiple conductive layers. Furthermore, by processing these multiple conductive layers into a stepped shape and connecting them to contact portions, multiple conductive layers can be electrically led out. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device capable of reducing the contact resistance of contacts connected to multiple conductive layers, and a method for manufacturing the semiconductor memory device.

[0005] The semiconductor memory device according to the embodiment includes: a stack formed by alternately stacking a plurality of first conductive layers and a plurality of first insulating layers, including stepped portions of the plurality of first conductive layers processed into a stepped shape; pillars extending along the stacking direction in the stack, which separates from the stepped portions in a first direction intersecting the stacking direction of the stack, and forming memory cells at the intersection portions with at least a portion of the plurality of first conductive layers; and a contact portion disposed in the stepped portion and connected to one of the plurality of first conductive layers, the contact portion having a second conductive layer extending from the upper part of the stepped portion toward the one first conductive layer and integrated with the one first conductive layer. Attached Figure Description

[0006] Figures 1A to 1E This is a cross-sectional view showing an example of the structure of a semiconductor memory device according to an embodiment.

[0007] Figures 2A to 2C This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0008] Figures 3A-3C This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0009] Figures 4A to 4C This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0010] Figures 5A to 5C This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0011] Figures 6A to 6D This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0012] Figures 7Aa to 7Bc This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0013] Figures 8A to 8D This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0014] Figures 9A to 9H This is a cross-sectional view showing a portion of the steps in a method for manufacturing a semiconductor memory device, illustrating a variation of the embodiments in sequence.

[0015] Label Explanation

[0016] 1 Semiconductor memory device; 22 Conductive layer; 23, 56 Liner layers; 51, 51a, NL, STPn insulating layers; BLK barrier layer; BM barrier metal layer; CC, CCm contacts; CN channel layer; CR core layer; HL contact hole; LM, LMG, LMs stack; ME memory layer; OL insulating layer; PL pillar; SGD, SGS select gate line; SL source line; STD, STS select gate; WL word line. Detailed Implementation

[0017] The present invention will now be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described below. Furthermore, the constituent elements in the following embodiments include constituent elements that are readily conceived by those skilled in the art or substantially the same constituent elements.

[0018] (Example of a semiconductor memory device structure)

[0019] Figures 1A to 1E This is a cross-sectional view showing an example of the structure of the semiconductor memory device 1 according to the embodiment. Figure 1A It is a cross-sectional view along the X direction including the storage region MR and the stepped region SR of the semiconductor memory device 1. Figure 1B It is a cross-sectional view along the Y direction of the storage region MR of the semiconductor storage device 1.

[0020] Figure 1C and Figure 1D This is an enlarged cross-sectional view of a portion of column PL of semiconductor memory device 1. Figure 1CThis is an enlarged view of the pillar PL at the height position of the selected gate line SGD and SGS. Figure 1D This is an enlarged view of the column PL at the height position of any character line WL.

[0021] Figure 1E This is an enlarged cross-sectional view of a portion of the stepped section SP of the semiconductor memory device 1 along the X direction.

[0022] Furthermore, in this specification, both the X and Y directions refer to directions along the plane of the word line WL (described later), and the X and Y directions are orthogonal to each other. Additionally, the electrical lead-out direction of the word line WL (described later) is sometimes referred to as the first direction, which is along the X direction. Furthermore, the direction intersecting the first direction is sometimes referred to as the second direction, which is along the Y direction. However, the semiconductor memory device 1 may contain manufacturing errors; therefore, the first and second directions are not necessarily orthogonal.

[0023] like Figure 1A and Figure 1B As shown, the semiconductor memory device 1 includes a source line SL, a stacked body LM, insulating layers 51-53, a plug CH, VO, a bit line BL, and upper layer wiring MX. Furthermore, in this specification, the direction towards the source line SL, corresponding to the source side, is defined as the downward direction of the semiconductor memory device 1, and the direction towards the bit line BL, corresponding to the drain side, is defined as the upward direction of the semiconductor memory device 1.

[0024] The source line SL can be, for example, a conductive polycrystalline silicon layer. Alternatively, the source line SL can also be part of a semiconductor substrate, such as a silicon substrate. In this case, the source line SL can be a conductive layer on the surface of the semiconductor substrate with dopants diffused therein.

[0025] A stacked body LM is disposed on the source line SL. Insulating layers 52 to 54, such as silicon oxide layers, are stacked on the stacked body LM in this order.

[0026] The stack-up LM has a structure consisting of multiple word lines WL, select gate lines SGD and SGS, and multiple insulating layers OL stacked alternately. One or more select gate lines SGD are arranged above the topmost word line WL, and one or more select gate lines SGS are arranged below the bottommost word line WL.

[0027] Word lines WL, which are multiple first conductive layers, and select gate lines SGD and SGS, which are multiple conductive layers, are, for example, tungsten layers or molybdenum layers. Insulating layers OL, which are multiple first insulating layers, are, for example, silicon oxide layers.

[0028] In addition, Figure 1A and Figure 1BIn this example, the stacked body LM includes eight word lines (WL). Additionally, the stacked body LM includes one select gate line (SGD) and one select gate line (SGS). However, the number of layers for the word lines WL and the select gate lines SGD and SGS is different from... Figure 1A and Figure 1B The examples are irrelevant but arbitrary.

[0029] The stacked matrix LM has a storage region MR with multiple pillars PL and a stepped region SR which includes multiple word lines WL and other stepped sections SP that are processed into a stepped shape.

[0030] Viewed from the stacking direction of the stacked body LM, multiple pillars PL, for example, have circular, elliptical, or small coin-shaped (oval) cross-sectional shapes, and are arranged in an alternating pattern in the storage region MR.

[0031] Each pillar PL connects the stacked structure LM to the source line SL. Additionally, each pillar PL has a storage layer ME and a channel layer CN sequentially arranged from its outer periphery. The channel layer CN is also disposed on the bottom surface of the pillar PL. A core layer CR is filled inside the channel layer CN. A cap layer CP is disposed in the insulating layer 52 on the channel layer CN.

[0032] like Figure 1C and Figure 1D As shown, the storage layer ME has a stacked structure in which a barrier insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are sequentially stacked from the outer periphery of the pillar PL. As described above, the pillar PL has a cross-sectional shape, such as a circle, and exhibits approximately the same shape when viewed in any cross-section, such as in the X or Y direction. Therefore, in Figure 1C and Figure 1D The cross-sectional direction is not shown.

[0033] The barrier insulating layer BK, tunnel insulating layer TN, and core layer CR are, for example, silicon oxide layers. The charge storage layer CT is, for example, a silicon nitride layer. The channel layer CN and capping layer CP are semiconductor layers such as polycrystalline silicon layers or amorphous silicon layers.

[0034] With this layered structure, the lower end of the channel layer CN is electrically connected to the source line SL, and the upper end of the channel layer CN is electrically connected to the cap layer CP. The cap layer CP is electrically connected to the bit line BL disposed in the insulating layer 54 via the plug CH disposed in the insulating layers 52 and 53.

[0035] like Figure 1D As shown, memory cells MC are formed at the intersections of pillar PL and multiple word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage or the like via the word lines WL. Thus, the semiconductor memory device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells MC are arranged in a three-dimensional manner.

[0036] like Figure 1C As shown, select gates STD and STS are formed at the intersection of pillar PL and select gate lines SGD and SGS, respectively. By applying a predetermined voltage through select gate lines SGD and SGS, select gates STD and STS are turned on (ON) or off (OFF), and the memory cells MC of pillar PL to which select gates STD and STS belong become selected or non-selected.

[0037] like Figure 1A As shown, the stepped region SR is disposed, for example, at one or both ends of the laminate LM in the X direction. The stepped region SR has each layer of the laminate LM, including the word line WL, select gate line SGD, SGS, and insulating layer OL, processed into stepped portions SP. In other words, for one or both ends of the laminate LM in the X direction, each layer of the laminate LM is processed into a stepped shape to form a termination.

[0038] The stepped portion SP is covered by an insulating layer 51, such as a silicon oxide layer. The insulating layer 51, which is a second insulating layer, extends at least to the height of the topmost layer of the laminate LM. The insulating layers 52 to 54 covering the laminate LM also cover the insulating layer 51 on the stepped portion SP.

[0039] The stepped section SP is provided with multiple contacts CC that pass through insulating layers 52 and 51 and are respectively connected to multiple word lines WL and select gate lines SGD and SGS. Each contact CC has a liner layer 56 and a conductive layer 22.

[0040] The liner layer 56, serving as the fourth insulating layer, is, for example, a silicon oxide layer and is disposed on the sidewall portion of the contact portion CC. A conductive layer 22, serving as the second conductive layer, is filled inside the liner layer 56. The conductive layer 22, like the word lines WL to which the contact portion CC is connected, is a tungsten layer or a molybdenum layer.

[0041] The lower end of conductive layer 22 is electrically connected to the word line WL or select gate line SGD, SGS of the connected object. The upper end of conductive layer 22 is electrically connected to the upper layer wiring MX disposed in insulating layer 54 via plug V0 disposed in insulating layer 53.

[0042] The upper layer wiring MX is electrically connected to peripheral circuitry (not shown). The peripheral circuitry includes transistors (not shown) and applies predetermined voltages to the memory cell MC and the select gates STD and STS via the upper layer wiring MX, plug V0, word line WL, and select gate lines SGD and SGS, thereby influencing the operation of the memory cell MC and the select gates STD and STS.

[0043] Here, the detailed structure of the word line WL and contact part CC in the stepped section SP is shown in... Figure 1E .

[0044] like Figure 1E As shown, in the insulating layer 51 covering the stepped portion SP, an insulating layer STPn is disposed along the shape of the stepped portion SP. The insulating layer STPn, serving as the first layer, is, for example, a silicon nitride layer, and is disposed above the stepped portion SP, separated from the insulating layer 51a, which is part of the insulating layer 51. The first layer may not be an insulator as long as it is not connected to other conductive structures. In this case, the first layer may be a polysilicon layer or the like, instead of a silicon nitride layer.

[0045] The conductive layer 22 of the contact portion CC penetrates the insulating layer 51 above the insulating layer STPn, the insulating layer STPn, and the insulating layer 51a below the insulating layer STPn, for example, reaching the word line WL of the connected object. The liner layer 56 of the contact portion CC extends from the upper end of the contact portion CC located on the upper surface side of the insulating layer 52 to at least the insulating layer 51a below the insulating layer STPn. However, the liner layer 56 may also penetrate the insulating layer 51a in the same way as the conductive layer 22.

[0046] Between the conductive layer 22 and the liner layer 56 of the contact portion CC, a barrier metal layer BM and a barrier layer BLK are sequentially sandwiched from the conductive layer 22 side.

[0047] The barrier metal layer BM, which serves as the fourth conductive layer, is, for example, a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer. It covers the sidewalls of the conductive layer 22 inside the liner layer 56 and the barrier layer BLK.

[0048] More specifically, the barrier metal layer BM extends from the upper end of the contact portion CC located on the upper surface side of the insulating layer 52 through the insulating layer 51 above the insulating layer STPn, the insulating layer STPn, and the insulating layer 51a below the insulating layer STPn.

[0049] Furthermore, the barrier metal layer BM extends continuously from the sidewall of the conductive layer 22 to the upper surface of the word line WL connected to the contact CC. More specifically, the barrier metal layer BM covers the entire word line WL except for the connection surface between the upper surface of the word line WL and the contact CC. That is, the barrier metal layer BM continuously covers the upper surface, the end face of the stepped terminal, and the lower surface of the word line WL from the sidewall of the conductive layer 22.

[0050] As a barrier layer BLK containing a metal insulating layer, such as an aluminum oxide layer, the sidewall of the conductive layer 22 is covered on the inside of the liner layer 56 through the barrier metal layer BM.

[0051] More specifically, the barrier layer BLK extends through the upper end of the contact portion CC located on the upper surface side of the insulating layer 52, passing through the insulating layer 51 above the insulating layer STPn, the insulating layer STPn, and the insulating layer 51a below the insulating layer STPn.

[0052] Furthermore, the barrier layer BLK extends continuously from the sidewall of the conductive layer 22 to the upper surface of the word line WL connected to the contact CC. More specifically, except for the connection surface between the upper surface of the word line WL and the contact CC, the barrier layer BLK completely covers the word line WL through the barrier metal layer BM. That is, the barrier layer BLK continuously covers the upper surface, the stepped end face, and the lower surface of the word line WL from the sidewall of the conductive layer 22 through the barrier metal layer BM.

[0053] Here, at the connection surface between the conductive layer 22 of the contact portion CC and the word line WL to which the connection is made, neither the barrier metal layer BM nor the blocking layer BLK is present. Furthermore, at the connection surface between the conductive layer 22 and the word line WL, there are no traces indicating that the conductive layer 22 and the word line WL are joined, nor is there an interface between the conductive layer 22 and the word line WL.

[0054] In this way, the conductive layer 22 of the contact portion CC is integrated with the word line WL of the connected object.

[0055] In addition, Figure 1E The diagram shows an enlarged view of any word line WL portion, but the connection structure with the contact CC in the select gate line SGD and SGS portions is the same as that in the word line WL portion.

[0056] That is, the contact portion CC connected to the select gate lines SGD and SGS has a conductive layer 22 that is integrated with the select gate lines SGD and SGS respectively. In other words, there are no traces or interfaces between the conductive layer 22 and the select gate lines SGD and SGS.

[0057] Furthermore, these contact portions CC have a barrier metal layer BM that continuously covers the sidewalls of the conductive layer 22 and the select gate lines SGD and SGS. Additionally, these contact portions CC have a barrier layer BLK that continuously covers the sidewalls of the conductive layer 22 and the select gate lines SGD and SGS outside the barrier metal layer BM.

[0058] In addition, these contact portions CC have a liner layer 56 that covers the sidewalls of the conductive layer 22 on the outside of the barrier layer BLK and reaches at least to a depth in the insulating layer 51a below the insulating layer STPn.

[0059] like Figure 1B As shown, the laminate LM is divided in the Y direction by multiple plate-shaped contact portions LI.

[0060] Multiple plate-shaped contacts LI extend within the laminate LM along the stacking direction of each layer of the laminate LM, and extend in the X-direction in the region within the laminate LM from the storage region MR to the step region SR. That is, the multiple plate-shaped contacts LI, at positions where they are separated in the Y-direction, penetrate the insulating layer 52 and the laminate LM to reach the source line SL.

[0061] An insulating layer 55, such as a silicon oxide layer, is disposed on the sidewall of the plate-shaped contact portion LI. A conductive layer 21, such as a tungsten layer, is filled inside the insulating layer 55. The conductive layer 21 of the plate-shaped contact portion LI is electrically connected to the upper layer wiring via a plug or the like (not shown). In addition, the lower end of the conductive layer 21 is electrically connected to the source line SL.

[0062] With the above structure, the plate-shaped contact portion LI functions as a source line contact, for example. However, instead of the plate-shaped contact portion LI, an insulating layer or the like that does not function as a source line contact can be used to divide the laminate LM in the Y direction.

[0063] Furthermore, the aforementioned insulating layer STPn is not positioned near the plate-shaped contact portion LI.

[0064] (Manufacturing method of semiconductor memory device)

[0065] Next, use Figures 2A to 8D An example of a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described. Figures 2A to 8D This is a cross-sectional view illustrating a portion of the steps in the manufacturing method of the semiconductor memory device 1 according to the embodiments.

[0066] First, it is shown in Figures 2A to 2C The condition of forming a stepped section SP. Figures 2A to 2C It is a cross-sectional view along the X direction that includes the stepped area SR during manufacturing.

[0067] like Figure 2A As shown, for example, a conductive polycrystalline silicon layer is formed into a film, or a dopant is diffused onto the surface of a semiconductor substrate to form a source line SL.

[0068] Additionally, a stacked structure LMs, serving as the first stacked structure, is formed on the source line SL. The stacked structure LMs has a structure in which multiple insulating layers NL and OL are alternately stacked layer by layer. The insulating layer NL is, for example, a sacrificial layer such as a silicon nitride layer. Subsequently, the insulating layer NL is replaced with a tungsten layer or a molybdenum layer, etc., to form the word line WL and the select gate lines SGD and SGS. An insulating layer 51 is formed on the stacked structure LMs.

[0069] like Figure 2BAs shown, the insulating layers NL and OL of the laminate LMs are processed into a stepped shape, forming a stepped portion SP at the end of the laminate LMs. For such a stepped portion SP, a mask layer such as a photoresist layer is formed on the upper surface of the laminate LMs. While the mask layer is thinned using oxygen plasma or the like, an insulating layer NL and an insulating layer OL are processed as a group, and these insulating layers NL and OL are processed repeatedly to form the stepped portion SP.

[0070] like Figure 2C As shown, an insulating layer 51 is formed that covers the stepped portion SP and reaches at least to the same height as the uppermost layer of the unprocessed laminate LMs. At this time, an insulating layer STPn (see reference) is sandwiched within the insulating layer 51. Figure 1E However, the insulating layer STPn is formed to avoid the area in the stepped portion SP where the plate-shaped contact portion LI is subsequently formed.

[0071] Additionally, an insulating layer 52 is formed that covers the unprocessed portion of the laminate LM and the insulating layer 51 on the stepped portion SP. Through the above, a structure including a stepped region SR of the stepped portion SP formed by multiple insulating layers NL and OL is formed in the laminate LMs.

[0072] Next, in Figures 3A to 5C The diagram shows the formation of column PL. Figures 3A to 5C It is a cross-sectional view along the Y direction containing the region that will later become the storage area MR.

[0073] like Figure 3A As shown, a storage via MH is formed in the region that subsequently becomes the storage region MR, through which the insulating layer 52 and the laminate LMs are penetrated to reach the source line SL.

[0074] like Figure 3B As shown, a storage layer ME is formed to cover the sidewalls of the storage aperture MH. The storage layer ME is formed by sequentially stacking a barrier insulating layer BK, a charge accumulation layer CT, and a tunnel insulating layer TN. Figure 1C and Figure 1D At this point, a storage layer ME is also formed on the upper surface of the insulating layer 52. The storage layer ME is removed from the bottom surface of the storage hole MH.

[0075] like Figure 3C As shown, a channel layer CN, including a semiconductor layer, is formed to cover the sidewalls and bottom surface of the memory hole MH. The channel layer CN is formed on the sidewalls of the memory hole MH, separated from the memory layer ME. At the same time, a channel layer CN is also formed on the upper surface of the insulating layer 52, separated from the memory layer ME.

[0076] Additionally, a core layer CR is filled inside the channel layer CN. At this time, a core layer CR is also formed on the upper surface of the insulating layer 52, separated by the storage layer ME and the channel layer CN.

[0077] like Figure 4A As shown, the core layer CR is etched back. At this time, the channel layer CN is used as an etch stop layer, and the core layer CR is etched back while maintaining selectivity with the channel layer CN. As a result, the core layer CR is removed from the upper surface of the insulating layer 52 and the upper end of the storage hole MH, forming a recess DN in the storage hole MH.

[0078] like Figure 4B As shown, the channel layer CN is etched back. At this time, the memory layer ME is used as an etch stop layer, and the channel layer CN is etched back while maintaining selectivity with the memory layer ME. As a result, the memory layer CN is removed from the upper surface of the insulating layer 52 and the upper end of the memory hole MH.

[0079] On the other hand, the core layer CR is a silicon oxide layer of the same type as the tunnel insulating layer TN included in the memory layer ME. Therefore, the core layer CR protrudes from the upper surface of the trench layer CN, which is excavated in the depth direction within the memory hole MH.

[0080] like Figure 4C As shown, the storage layer ME is etched back. This removes the storage layer ME from the upper surface of the insulating layer 52 and the upper end of the storage via MH.

[0081] At this point, by etching back the storage layer ME while maintaining at least selectivity with the channel layer CN, the removal of the channel layer CN within the storage via MH is suppressed. Furthermore, the core layer CR, protruding from the upper surface of the channel layer CN, is also a layer of the same type as the tunnel insulation layer TN included in the storage layer ME, and therefore is etched back. As a result, the depth positions within the storage via MH at the upper ends of the storage layer ME, the channel layer CN, and the core layer CR become approximately equal.

[0082] like Figure 5A As shown, the recess DN at the upper end of the storage hole MH is filled with a capping layer CP such as a semiconductor layer.

[0083] like Figure 5B As shown, the entire upper surface of the capping layer CP and the upper surface of the insulating layer 52 are etched back. As a result, the thickness of the insulating layer 52 and the capping layer CP is reduced.

[0084] like Figure 5C As shown, an insulating layer 52 is added by stacking. Thus, the capping layer CP is embedded within the insulating layer 52. This process forms the pillar PL.

[0085] Next, in Figures 6A to 6D The image shows the state of the contact hole HL, which becomes the contact portion CC after its formation. Figures 6A to 6D This is an enlarged sectional view of a portion of the stepped section SP along the X direction.

[0086] like Figures 6A to 6D As shown, on the stepped portion SP, while an insulating layer STPn, such as a silicon nitride layer, exists along the shape of the stepped portion SP, an insulating layer 51, such as a silicon oxide layer, is formed.

[0087] That is, a thin layer of insulating layer 51a is formed below the insulating layer STPn, covering the stepped portion SP along the stepped shape of the stepped portion SP. The insulating layer STPn covers the stepped portion SP in a manner that follows the stepped shape of the stepped portion SP, with the insulating layer 51a in between. An insulating layer 51 is formed on the insulating layer STPn, reaching the height of the uppermost layer of the laminate LMs, covering the stepped portion SP.

[0088] like Figure 6A As shown, contact holes HL are formed that penetrate the insulating layers 52 and 51 above the insulating layer STPn to reach the insulating layer STPn. At this time, the insulating layer STPn is used as an etch barrier layer, and while maintaining selectivity with the insulating layer STPn, dry etching or the like is performed on the insulating layer 51. As a result, each contact hole HL reaches the insulating layer STPn at a different depth position in the insulating layer 51.

[0089] like Figure 6B As shown, dry etching or other methods are performed on the insulating layer STPn to penetrate the insulating layer STPn at the lower end of the contact hole HL. As a result, each contact hole HL reaches at least a different depth position in the insulating layer 51a below the insulating layer STPn.

[0090] At this point, it is preferable that the lower end of the contact hole HL should thoroughly penetrate the insulating layer STPn, and remain within the insulating layer 51a without reaching the insulating layer NL. For this purpose, it is preferable to use the insulating layer 51a below the insulating layer STPn as an etch barrier layer, and perform dry etching targeting the insulating layer STPn while maintaining selectivity with the insulating layer 51a.

[0091] However, it is acceptable not to penetrate the insulating layer NL below the contact hole HL; for example, the lower end of the contact hole HL can reach the upper surface of the insulating layer NL. However, it is preferable that the lower end of the contact hole HL does not enter the insulating layer NL.

[0092] like Figure 6C As shown, a liner layer 56 is formed, which covers the sidewalls and bottom surface of the contact hole HL with a silicon oxide layer, etc. The liner layer 56 is also formed on the upper surface of the insulating layer 52.

[0093] like Figure 6D As shown, the liner layer 56 on the bottom surface of the contact hole HL and the insulating layer 51a below the liner layer 56 are removed. The liner layer 56 is also removed from the upper surface of the insulating layer 52. At this time, the insulating layer NL is used as an etch barrier layer, and dry etching or the like is performed while maintaining selectivity with the insulating layer NL.

[0094] In other words, the liner layer 56 uses a silicon oxide layer or the like that has the selectivity for dry etching compared to the insulating layer NL, which is the same as the insulating layer STPn, such as the silicon nitride layer.

[0095] This allows the lining layer 56 on the bottom surface of the contact hole HL and the insulating layer 51a below the insulating layer STPn to be connected, forming a contact hole HL with insulating layers NL reaching different depth positions.

[0096] Furthermore, the contact hole HL may be, for example, a tapered shape whose diameter decreases from the upper end to the lower end. Alternatively, the contact hole HL may be, for example, a convex shape whose diameter is maximized at a predetermined depth between the upper and lower ends.

[0097] Furthermore, near the lower end of the contact hole HL, the diameter of the contact hole HL can be further reduced by an amount corresponding to the thickness of the lining layer 56 in the planar direction of the insulating layer STPn, etc. In this case, the sidewalls of the contact hole HL can also be... Figure 6C The arrival position in the insulation layer 51a during the processing has a height difference.

[0098] However, in the above Figure 6B In the process, when the lower end of the contact hole HL reaches the upper surface of the insulating layer NL, Figure 6D In the process, the lining layer 56 on the bottom surface of the contact hole HL can be removed, thereby exposing the insulating layer NL on the bottom surface of the contact hole HL.

[0099] In addition, in the above Figure 6B In the process, if the lower end of the contact hole HL reaches the upper surface of the insulating layer NL, the lower end of the lining layer 56 of the sidewall of the contact hole HL will also reach the upper surface of the insulating layer NL. In this case, without... Figure 6D The process involves additional etching of the insulating layer 51a, so that the sidewalls of the contact hole HL may not have a height difference in the insulating layer 51a, and the diameter of the lower end of the contact hole HL will not become narrower.

[0100] Furthermore, in the above Figure 6B In the process, the lower end of the contact hole HL is kept at least on the upper surface of the insulating layer NL, preventing it from entering the insulating layer NL. This prevents the liner layer 56 covering the sidewall of the contact hole HL from protruding into the insulating layer NL. Consequently, it prevents the lower end of the liner layer 56 protruding into the insulating layer NL from hindering the formation of the word line WL (described later), thus preventing the word line WL from becoming locally thinner and its resistance from increasing.

[0101] Next, in Figures 7Aa to 7Bc The diagram shows a situation where multiple insulating layers NL are replaced with multiple word lines WL to form a laminate LM. Figures 7Aa to 7Ac With the above Figures 3A to 5C Similarly, this is a cross-sectional view along the Y direction containing the storage area MR. Figures 7Ba to 7Bc With the above Figures 2A to 2C Similarly, this is a cross-sectional view along the X direction containing the stepped area SR.

[0102] like Figure 7Aa As shown, multiple slots ST are formed that connect the insulating layer 52 and the laminate LMs to the source line SL. The slots ST have the following structure: within the laminate LMs, they extend from the storage region MR along the X direction to the stepped region SR, and then become plate-shaped contact LI.

[0103] like Figure 7Ba As shown, in the stepped region SR, as described above... Figures 6A to 6C As shown, multiple contact holes HL are formed that penetrate the insulating layers 52, 51, etc., and reach multiple insulating layers NL respectively.

[0104] like Figure 7Ab and Figure 7Bb As shown, the insulating layer NL in the laminate LMs is removed by injecting a solution such as hot phosphoric acid into the laminate LMs through the gap ST and the contact hole HL.

[0105] In the slot ST, the chemical solution enters from the sidewall portion of the slot ST towards the respective insulating layer NL in the laminate LMs, and multiple insulating layers NL are removed in parallel. On the other hand, in the contact hole HL, the chemical solution enters from the lower end of each contact hole HL towards the insulating layer NL connected to each contact hole HL, and multiple insulating layers NL are removed individually.

[0106] Thus, multiple insulating layers NL in the laminate LMs are removed, forming a laminate LMg as the second laminate with gap layers GP between the multiple insulating layers OL.

[0107] like Figure 7Ac and Figure 7Bc As shown, conductive material is injected into the laminate LMG via gap ST and contact hole HL, for example, by injecting a raw material gas or the like into the laminate LMG, and the conductive material is filled into multiple gap layers GP in the laminate LMG.

[0108] In the slotted section ST, the feed gas enters from the sidewall portion of the slotted section ST into the various interstitial layers NL in the laminate LMG, and multiple interstitial layers GP are filled in parallel with conductive material. At this time, part or all of the slotted section ST can also be filled with conductive material.

[0109] On the other hand, in the contact holes HL, the raw material gas enters from the lower end of each contact hole HL into the gap layers GP connected to each contact hole HL, and the multiple gap layers GP are filled with conductive material. At this time, the contact holes HL are also filled with conductive material.

[0110] Thus, a stack LM is formed, consisting of multiple word lines WL, select gate lines SGD and SGS, and multiple insulating layers OL, which are alternately stacked layer by layer as the third stack. Additionally, a contact portion CC is formed by filling the inner side of the liner layer 56 with a conductive layer 22.

[0111] In this way, multiple word lines WL, select gate lines SGD and SGS, and a conductive layer 22 of the stacked body LM are formed in parallel. Therefore, no interface is formed between the conductive layer 22 and the word lines WL and the select gate lines SGD and SGS, but the conductive layer 22 is integrated with the word lines WL and the select gate lines SGD and SGS respectively.

[0112] In addition, sometimes it will also be like Figures 7Aa to 7Bc The process of removing the insulating layer NL in the laminate LMs, forming the word line WL, and the select gate lines SGD and SGS as shown is called the substitution process.

[0113] Here, in Figures 8A to 8D The details of the replacement process are shown in the figure. Figures 8A to 8D Similar to Figure 6 above, this is an enlarged cross-sectional view of a portion of the stepped section SP along the X direction.

[0114] like Figure 8A As shown, multiple insulating layers NL are also removed in the stepped section SP via contact holes HL and gaps ST (see Figure 7A).

[0115] Furthermore, the insulating layer STPn is formed away from the region where the gap ST is formed. That is, the insulating layer STPn is not in contact with the gap ST. In addition, the contact hole HL and the insulating layer STPn are separated by the lining layer 56 on the sidewall of the contact hole HL.

[0116] Therefore, if the solution is not injected into the insulating layer STPn side from either the gap ST or the contact hole HL, the insulating layer STPn, which is of the same type as the insulating layer NL, such as a silicon nitride layer, is not removed.

[0117] like Figure 8B As shown, a raw material gas, such as a barrier layer BLK, is injected through the contact hole HL and the gap ST. As a result, a barrier layer BLK, such as an alumina layer, is formed on the sidewall of the contact hole HL, on the surfaces of the insulating layers OL facing each other on both sides of the stacking direction of the gap layer GP, and on the end face of the terminal portion of the gap layer GP.

[0118] That is, the barrier layer BLK covers the sidewall of the contact hole HL through the liner layer 56, except for the lower end of the contact hole HL. Furthermore, the barrier layer BLK directly covers the sidewall of the contact hole HL at the lower end of the contact hole HL. Additionally, the barrier layer BLK continues continuously from the sidewall of the contact hole to the surface of the insulating layer OL, which is sandwiched between the gap layer GP and faces each other on both sides of the laminate LMG in the lamination direction.

[0119] In addition, a barrier layer BLK is also formed on the end face of the gap ST sidewall of multiple insulating layers OL at this time.

[0120] like Figure 8C As shown, a raw material gas, such as a barrier metal layer BM, is injected through the contact hole HL and the gap ST. As a result, a barrier metal layer BM, such as a titanium nitride layer, is formed through the barrier layer BLK on the sidewall of the contact hole HL, on the surfaces of the insulating layers OL facing each other on both sides of the stacking direction of the gap layer GP, and on the end face of the terminal portion of the gap layer GP.

[0121] That is, the barrier metal layer BM, except for the lower end of the contact hole HL, covers the sidewall of the contact hole HL through the liner layer 56 and the barrier layer BLK. Furthermore, the barrier metal layer BM, in the lower end of the contact hole HL, covers the sidewall of the contact hole HL through the barrier layer BLK. Additionally, the barrier metal layer BM extends continuously from the sidewall of the contact hole to the surface of the insulating layer OL, which is sandwiched between the gap layer GP and faces each other on both sides of the laminate LMG in the lamination direction, inside the barrier layer BLK.

[0122] In addition, at this time, a barrier metal layer BM is also formed on the end face of the gap ST sidewall of multiple insulating layers OL, separated by a barrier layer BLK.

[0123] Barrier metal layer BM in Figure 8D In the subsequent processing shown, it functions as a seed layer when filling the contact hole HL and the gap layer GP of the laminate LMG with conductive material.

[0124] like Figure 8D As shown, a conductive material-containing gas is injected, for example, through the contact hole HL and the gap ST. This fills the inside of the barrier metal layer BM of the multiple interstitial layers GP in the laminate LMG with conductive material, forming multiple word lines WL and select gate lines SGD and SGS. Furthermore, conductive material is filled inside the barrier metal layer BM within the contact hole HL, forming a conductive layer 22 integrated with the multiple word lines WL and the select gate lines SGD and SGS.

[0125] Additionally, at this point, part or all of the gap ST is filled with conductive material. Through the above, the replacement process is complete.

[0126] Then, at least the conductive material and the barrier metal layer BM are removed from the gap ST. At this point, the barrier layer BLK can also be removed from the gap ST. However, the barrier layer BLK may remain partially or entirely on the end face of the gap ST sidewall of the multiple insulating layers OL.

[0127] Furthermore, an insulating layer 55 is formed on the sidewall of the gap ST, and a conductive layer 21 is formed on the inner side of the insulating layer 55. Thus, a plate-shaped contact portion LI is formed that functions as a source line contact portion.

[0128] At this time, the conductive layer 21 of the plate-shaped contact portion LI is insulated from the multiple word lines WL and the select gate lines SGD and SGS by the insulating layer 55. Furthermore, since the conductive material and the barrier metal layer BM are removed from the sidewall of the gap ST, the influence of the plate-shaped contact portion LI on the electrical characteristics of the multiple word lines WL and the select gate lines SGD and SGS can be suppressed. The barrier layer BLK is an insulating layer such as an aluminum oxide layer; therefore, even if it remains on the sidewall of the plate-shaped contact portion LI, it will not affect the electrical characteristics of the multiple word lines WL and the select gate lines SGD and SGS.

[0129] However, after removing at least the conductive material and the barrier metal layer BM from the gap ST, an insulating layer can be filled into the gap ST, without forming the conductive layer 21. In this case, the gap ST filled with the insulating layer does not function as a source line contact and becomes a structure that does not contribute to the function of the semiconductor memory device 1.

[0130] Additionally, an insulating layer 53 is formed on the insulating layer 52, and a plug V0 is formed that penetrates the insulating layer 53 and connects to the conductive layer 22 of the contact portion CC. Furthermore, a plug CH is formed that penetrates the insulating layers 53 and 52 and connects to the capping layer CP of the pillar PL. Additionally, an insulating layer 54 is formed on the insulating layer 53, and an upper layer wiring MX connected to the plug V0 and a bit line BL connected to the plug CH are formed in the insulating layer 54.

[0131] In addition, plugs V0, CH, upper-layer routing MX, and bit lines BL can also be formed together using methods such as dual damascene.

[0132] Through the above, the semiconductor memory device 1 of the embodiment has been manufactured.

[0133] (Summary)

[0134] In semiconductor memory devices such as three-dimensional non-volatile memories, for example, a laminate consisting of alternating layers of multiple sacrificial layers and multiple insulating layers is subjected to a gap replacement process to form a laminate with multiple conductive layers. Then, contact holes are formed that extend to multiple conductive layers in the stepped portions, and the contact holes are filled with conductive layers to form contact portions. As a result, each conductive layer can be electrically led out.

[0135] However, since the multiple conductive layers of the laminate and the conductive layers in the contact portion are formed through different processes, for example, when forming a contact hole, the exposed surfaces of the multiple conductive layers of the laminate may sometimes be oxidized in the bottom surface of the contact hole. As a result, the contact resistance of the contact portion may sometimes be higher than that of the multiple conductive layers of the laminate.

[0136] Furthermore, in recent years, there has been a trend towards increasing the number of layers in semiconductor memory devices in order to increase the storage capacity. In this case, the length of the stepped portion, that is, the length from the top conductive layer to the bottom conductive layer, becomes longer. Therefore, when performing replacement processing through gaps, it is difficult to completely fill the leading edge portion of the stepped portion with conductive material.

[0137] Therefore, voids may sometimes remain within the conductive layers of the laminate, increasing the wiring resistance of the conductive layers. Furthermore, if the conductive layers are voided, during the formation of contact holes, the lower end of the contact hole may sometimes penetrate the conductive layer to which the connection is intended, reaching the conductive layer below. Consequently, the contact may sometimes connect to a conductive layer that is not intended for connection, creating a short circuit between multiple conductive layers in the laminate.

[0138] According to the embodiment of the semiconductor memory device 1, the contact portion CC has a conductive layer 22 extending from the upper part of the stepped portion SP towards a word line WL and integrated with the word line WL. This reduces the contact resistance of the contact portion CC, which is connected to multiple word lines WL, etc.

[0139] According to the semiconductor memory device 1 of the embodiment, the liner layer 56 of the contact portion CC is a layer with selectivity based on dry etching relative to the insulating layer STPn and the insulating layer NL. As a result, it is possible to prevent the insulating layer NL from being penetrated when the liner layer 56 at the bottom surface of the contact hole HL and the underlying insulating layer 51a are penetrated, and it is possible to form a plurality of contact holes HL with different depths.

[0140] According to the semiconductor memory device 1 of the embodiment, the barrier metal layer BM of the contact portion CC extends continuously from the sidewall side of the conductive layer 22 to the upper surface of the word line WL to which the contact portion CC is connected, except for the connection surface with the contact portion CC, inside the barrier layer BLK. In this way, there is no barrier metal layer BM or the like at the connection surface between the contact portion CC and the word line WL, and therefore, the contact resistance of the contact portion CC can be further reduced.

[0141] According to the manufacturing method of the semiconductor memory device 1 according to the embodiment, multiple insulating layers NL are removed through multiple contact holes HL and gaps ST, and multiple gap layers GP are filled with conductive material through multiple contact holes HL and gaps ST.

[0142] This allows for more effective replacement of the laminate LM, ensuring sufficient filling of the conductive material into the front end of the stepped portion SP. Consequently, it suppresses voiding of word lines WL and prevents the contact hole HL from penetrating the word lines WL that are to be connected. Furthermore, it prevents short circuits from occurring between the contact portion CC and word lines WL that are not to be connected, or between multiple word lines WL.

[0143] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, dry etching is performed in which multiple insulating layers NL are used as etch barrier layers, so that the liner layer 56 on the bottom surface of multiple contact holes HL and the insulating layer 51a below the insulating layer STPn are connected, so that the multiple contact holes HL reach the multiple insulating layers NL respectively.

[0144] In this way, while obtaining a selectivity ratio with the insulating layer NL, the liner layer 56 and the insulating layer 51a are removed. In other words, by setting the liner layer 56, for example, to be a silicon oxide layer with a high selectivity ratio relative to the insulating layer NL, it is possible to form contact holes HL of different depths at the same time while suppressing the penetration of the insulating layer NL.

[0145] (Modified Example)

[0146] Next, use Figures 9A to 9H A modified example of the semiconductor memory device according to the embodiments will be described. The material of the liner layer 23 of the modified semiconductor memory device is different from that of the embodiment described above.

[0147] Figures 9A to 9H This is a cross-sectional view showing a portion of the steps in a method for manufacturing a semiconductor memory device, illustrating a variation of the embodiments in sequence. Figures 9A to 9H The image shows a magnified cross-section of a portion of the stepped section SP along the X direction, illustrating the relationship with the aforementioned... Figures 6A to 6D as well as Figures 8A to 8D The processing is quite complex. Furthermore, in... Figures 9A to 9HIn this document, the same reference numerals are sometimes assigned to structures that are the same as those in the semiconductor memory device 1 described in the above embodiments, and their descriptions are omitted.

[0148] Figure 9A and Figure 9B The processing shown is the same as that described in the above embodiments. Figure 6A and Figure 6B The process shown is the same. That is, as... Figure 9A As shown, the insulating layer STPn is used as an etch barrier layer to form a contact hole HL that penetrates the insulating layer 51 above the insulating layer STPn and reaches the insulating layer STPn. Additionally, as... Figure 9B As shown, dry etching is performed on the insulating layer STPn to bring the lower end of the contact hole HL to a predetermined depth position in the insulating layer 51a.

[0149] like Figure 9C As shown, a liner layer 23 is formed on the sidewalls and bottom surface of the contact hole HL. The liner layer 23 is also formed on the upper surface of the insulating layer 52.

[0150] The liner layer 23, which serves as the third conductive layer, is a conductive layer containing metal, such as a tungsten layer or a molybdenum layer. In this way, the metal-containing liner layer 23 has selectivity based on wet etching compared to the insulating layer 51a, such as a silicon oxide layer.

[0151] like Figure 9D As shown, the liner layer 23 on the bottom surface of the contact hole HL is removed. At this time, the insulating layer 51a below the insulating layer STPn is used as an etching barrier layer, and dry etching or the like is performed while maintaining selectivity with the insulating layer 51a. As a result, the liner layer 23 penetrates through the lower end of the contact hole HL. In addition, the liner layer 23 is also removed from the upper surface of the insulating layer 52.

[0152] Additionally, the insulating layer 51a beneath the liner layer 23 is removed. At this time, the insulating layer NL of the laminate LMs is used as an etch barrier layer, and wet etching is performed while maintaining selectivity with the insulating layer NL. In the wet etching, the insulating layer 51a is removed isotropically. However, since the sidewalls of the contact hole HL are covered by the liner layer 23, which is selective relative to the insulating layer 51a, the possibility of etching the insulating layer 51a onto the sidewalls of the contact hole HL is suppressed.

[0153] This allows the lining layer 23 on the bottom surface of the contact hole HL and the insulating layer 51a below the insulating layer STPn to be connected, forming a contact hole HL that reaches the insulating layer NL at different depth positions.

[0154] Furthermore, by removing the insulating layer 51a in an isotropic manner through wet etching, the lower end of the contact hole HL can also be formed with a slightly enlarged diameter.

[0155] After that, Figures 9E to 9H The processing shown is the same as the implementation method described above. Figures 8A to 8D The process shown is the same.

[0156] like Figure 9E As shown, multiple insulating layers NL are removed via contact holes HL and gaps ST (see Figure 7A).

[0157] Furthermore, as described above, the insulating layer STPn is formed away from the region where the gap ST is formed. Additionally, the contact hole HL and the insulating layer STPn are separated by the liner layer 23 on the sidewall of the contact hole HL. The liner layer 23 is resistant to solutions or the like used to remove the insulating layer NL. Therefore, the insulating layer STPn, which is a silicon nitride layer or the like, is not removed.

[0158] like Figure 9F As shown, a barrier layer BLK, such as an alumina layer, is formed on the sidewall of the contact hole HL, the surface of the insulating layer OL facing each other on both sides of the stacking direction of the gap layer GP, and the end face of the terminal part of the gap layer GP by injecting raw material gas, for example, through the contact hole HL and the gap ST.

[0159] like Figure 9G As shown, a barrier metal layer BM, such as a titanium nitride layer, is formed by injecting a raw material gas, such as a barrier metal layer BM, through a contact hole HL and a gap ST, on the sidewall of the contact hole HL, on the surface of the insulating layer OL facing each other on both sides of the stacking direction of the gap layer GP, and on the end face of the terminal part of the gap layer GP, with the barrier layer BLK in between.

[0160] like Figure 9H As shown, conductive layers 22 are formed by injecting a conductive material-based gas, for example, through contact holes HL and gaps ST, thereby integrating multiple word lines WL and select gate lines SGD and SGS. Additionally, contact portions CCm are formed including a stack LM comprising multiple word lines WL and select gate lines SGD and SGS, and a liner layer 23 containing the conductive layers.

[0161] In addition to the above, for the modified semiconductor memory device, Figures 9A to 9H Apart from the process shown, it is manufactured using the same process as that in the semiconductor memory device 1 of the above-described embodiment.

[0162] According to a modified example of the semiconductor memory device, the liner layer 23 of the contact portion CCm is a layer that has selectivity based on wet etching relative to the insulating layer 51a. Therefore, wet etching can be used to form the contact hole HL that penetrates the insulating layer 51a to reach the insulating layer NL.

[0163] Generally, wet etching can remove the insulating layer 51a, such as a silicon oxide layer, while maintaining higher selectivity than dry etching, compared to the insulating layer NL, such as a silicon nitride layer. Therefore, in the modified semiconductor memory device, it is possible to more effectively suppress the penetration of the insulating layer NL by each contact hole HL. This further suppresses the connection of the contact CCm to word lines WL that are not intended for connection, and prevents short circuits between multiple word lines WL.

[0164] In addition to the above, the semiconductor memory device according to the modified example can achieve the same effects as the semiconductor memory device 1 of the above embodiment.

[0165] (Other variations)

[0166] In the above-described embodiments and variations, the stepped portion SP is positioned at the end of the laminate LM in the X direction. However, stepped portions SP, where multiple letter lines WL are machined into a stepped shape, can also be positioned at the center of the laminate LM. In this case, for example, the center of the laminate LM can be machined into a bowl shape, allowing it to function as a stepped portion SP connecting multiple contact portions CC, CCm.

[0167] In the above-described embodiments and variations, insulating layers NL and OL are alternately stacked to form the laminate LMs. However, the laminate LMs can be formed in multiple tiers, in which case the pillar PL and the stepped portion SP can be formed in stages, with each tier of laminate LMs being formed. This allows for a further increase in the number of layers in the word line WL.

[0168] In the above-described embodiments and variations, a semiconductor memory device 1 or similar device is provided with peripheral circuitry that operates on the memory cell MC. The peripheral circuitry can be positioned above, below, or on the same layer as the stacked assembly.

[0169] For example, when the source line SL is part of a semiconductor substrate, the peripheral circuit can be disposed on the semiconductor substrate outside the stacked body LM. Furthermore, when the source line WL is a polysilicon layer or the like, by forming the peripheral circuit on the semiconductor substrate, covering it with an interlayer insulating layer, and forming the source line SL and the stacked body LM on the interlayer insulating layer, the peripheral circuit can be disposed below the stacked body LM.

[0170] Alternatively, by forming source lines SL and a stacked body LM on a support substrate, a semiconductor substrate with peripheral circuitry is attached above the stacked body LM, thereby enabling the peripheral circuitry to be positioned above the stacked body LM.

[0171] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A laminate formed by alternately stacking multiple first conductive layers and multiple first insulating layers, including the multiple first conductive layers being processed into stepped portions; A column extends along the stacking direction within the stack body that separates from the stepped portion in a first direction intersecting the stacking direction of the stack body, and forms a memory cell at the intersection with at least a portion of the plurality of first conductive layers. A contact portion, disposed on the stepped portion, is connected to one of the plurality of first conductive layers; and Multiple plate-shaped contact portions extend within the laminate in the lamination direction and the first direction, and divide the laminate in a second direction intersecting the lamination direction and the first direction. The contact portion has a second conductive layer that extends from the upper part of the stepped portion toward the first conductive layer and is integrated with the first conductive layer. An insulating layer is disposed on the sidewall of each of the plurality of plate-shaped contact portions, and a conductive layer is filled inside the insulating layer.

2. The semiconductor memory device according to claim 1, further comprising: A second insulating layer, which covers at least the stepped portion to the height of the uppermost layer of the laminate; and The first layer, which is arranged within the second insulating layer along the shape of the stepped portion, is of a different type from the second insulating layer. The contact portion has a lining layer that covers the sidewalls of the second conductive layer and extends at least below the first layer.

3. The semiconductor memory device according to claim 2, The lining layer is a layer that has selective dry etching relative to the first layer.

4. The semiconductor memory device according to claim 3, The lining layer is a fourth insulating layer of the same type as the second insulating layer.

5. The semiconductor memory device according to claim 2, The lining layer is a layer that is selectively wet-etched relative to the second insulating layer.

6. The semiconductor memory device according to claim 5, The lining layer is a third conductive layer containing metal.

7. The semiconductor memory device according to claim 2, The contact portion has a metal-containing insulating layer located between the second conductive layer and the lining layer and extending along the lamination direction within the second insulating layer. The metal-containing insulating layer penetrates the second insulating layer below the first layer.

8. The semiconductor memory device according to claim 7, The metal insulating layer extends continuously from the sidewall side of the second conductive layer to the upper surface of the first conductive layer, excluding the connection surface connected to the contact portion.

9. The semiconductor memory device according to claim 8, The contact portion has a fourth conductive layer located between the second conductive layer and the metal-containing insulating layer, and extending within the second insulating layer along the stacking direction. The fourth conductive layer penetrates the second insulating layer below the first layer.

10. The semiconductor memory device according to claim 9, The fourth conductive layer extends continuously from the sidewall of the second conductive layer to the upper surface of the first conductive layer, excluding the connection surface connected to the contact portion, on the inner side of the metal insulating layer.

11. A method for manufacturing a semiconductor memory device, comprising: A first laminate is formed by alternately stacking multiple sacrificial layers and multiple first insulating layers, including the multiple sacrificial layers being processed into stepped portions; A pillar is formed having a semiconductor layer and a memory layer, wherein the semiconductor layer extends along the stacking direction within the first laminate, which is separated from the step portion in a first direction intersecting the stacking direction of the first laminate, and the memory layer covers the sidewalls of the semiconductor layer; Multiple contact holes are formed, and the multiple contact holes are disposed in the stepped portion and respectively reach the multiple sacrificial layers; The plurality of sacrificial layers are removed through the plurality of contact holes to form a second laminate having a plurality of gap layers respectively disposed between the plurality of first insulating layers; A third laminate is formed by alternately stacking multiple first conductive layers and multiple first insulating layers using conductive material through the multiple contact holes. Furthermore, multiple contact portions are formed that are respectively connected to the multiple first conductive layers. A plurality of slits are formed within the first laminate, extending along the lamination direction and the first direction, and dividing the first laminate in a second direction intersecting the lamination direction and the first direction. During the formation of the second layer stack, the multiple sacrificial layers are removed via the multiple contact holes and the multiple gaps. During the formation of the third laminate and the plurality of contact portions, the plurality of gap layers are filled with the conductive material through the plurality of contact holes and the plurality of gaps. At least the conductive material is removed from the plurality of gaps. An insulating layer is formed on the sidewall of each of the plurality of slits, and a conductive layer is formed on the inner side of the insulating layer, thereby forming a plurality of plate-shaped contact portions.

12. The method for manufacturing a semiconductor memory device according to claim 11, When forming the third stack and the plurality of contact portions, a second conductive layer is formed that is filled into the plurality of contact holes and integrated with the plurality of first conductive layers.

13. The method for manufacturing a semiconductor memory device according to claim 11, Furthermore, by sandwiching a first layer of a different type than the second insulating layer within the second insulating layer along the shape of the stepped portion, a second insulating layer is formed that at least covers the stepped portion to the height of the uppermost layer of the first layer stack. When forming the plurality of contact holes Dry etching is performed, using the first layer as an etch barrier layer, to penetrate the second insulating layer above the first layer, so that the plurality of contact holes reach different depths within the first layer of the second insulating layer. After the plurality of contact holes reach the third insulating layer, dry etching is performed on the first layer, so that the contact holes reach different depths below the first layer.

14. The method for manufacturing a semiconductor memory device according to claim 13, When forming the plurality of contact holes A liner layer is formed that covers the sidewalls of each of the plurality of contact holes and the bottom surfaces of each of the plurality of contact holes at different depths below the first layer. Dry etching is performed, using the plurality of sacrificial layers as etch barriers, so that the liner layer penetrating the bottom surface of the plurality of contact holes and the second insulating layer below the first layer, so that the plurality of contact holes reach the plurality of sacrificial layers respectively.

15. The method for manufacturing a semiconductor memory device according to claim 14, The lining layer is a fourth insulating layer of the same type as the second insulating layer.

16. The method for manufacturing a semiconductor memory device according to claim 13, When forming the plurality of contact holes A liner layer is formed that covers the sidewalls of each of the plurality of contact holes and the bottom surfaces of each of the plurality of contact holes at different depths below the first layer. Dry etching is performed, using the second insulating layer below the first layer as an etching barrier layer, so that the liner layer penetrates the bottom surface of the plurality of contact holes, and the plurality of contact holes respectively reach the second insulating layer below the first layer. Wet etching is performed using the plurality of sacrificial layers as etch barrier layers, so that the second insulating layer below the first layer in the bottom surface of the plurality of contact holes is penetrated, and the plurality of contact holes reach the plurality of sacrificial layers respectively.

17. The method for manufacturing a semiconductor memory device according to claim 16, The lining layer is a third conductive layer containing metal.

18. The method for manufacturing a semiconductor memory device according to claim 11, When forming the third laminate and the plurality of contact portions, a metal-containing insulating layer is formed respectively, which covers at least the sidewalls of the lower ends of the plurality of contact holes and extends continuously from the sidewalls of the plurality of contact holes to the surfaces of the plurality of first insulating layers that are facing each other on both sides in the lamination direction, sandwiching the plurality of gap layers.

19. The method for manufacturing a semiconductor memory device according to claim 18, When forming the third laminate and the plurality of contact portions, a fourth conductive layer is formed respectively. The fourth conductive layer covers the sidewalls of the plurality of contact holes through the metal-containing insulating layer. Furthermore, the fourth conductive layer extends continuously from the sidewalls of the plurality of contact holes to the surfaces of the plurality of first insulating layers facing each other on both sides in the lamination direction, sandwiching the plurality of gap layers.

Images