Inclusion of electromagnetic interference radiation in capless semiconductor packages

Abstract

Embodiments of the present disclosure relate to inclusion of electromagnetic interference radiation in a capless semiconductor package. A semiconductor package can include a substrate, an application specific integrated circuit (ASIC) disposed on a first portion of a surface of the substrate, a memory device disposed on a second portion of the surface of the substrate, and a reinforcement plate disposed on a third portion of the surface of the substrate. The reinforcement plate can be spaced apart from the ASIC and the memory device and can enclose the ASIC and the memory device. The semiconductor package can include an electromagnetic interference (EMI) absorber disposed on a fourth portion of the surface of the substrate. The EMI absorber can be disposed between the reinforcement plate and the ASIC and the memory device. The EMI absorber can enclose the ASIC and the memory device and can block EMI radiation generated by the ASIC and the memory device.

Description

Technical Field

[0001] Embodiments of this disclosure relate to capless semiconductor packages. Background Technology

[0002] A capless semiconductor package offers improved thermal performance compared to heat sink-based (e.g., covered) semiconductor packages. Because no heat sink (e.g., a cover) is used in a capless semiconductor package, its manufacturing cost is also lower. In a capless semiconductor package, the exposure of the semiconductor device (e.g., an application-specific integrated circuit (ASIC)) allows for direct contact between the semiconductor device and the heat sink, which improves the thermal performance of the semiconductor device. Summary of the Invention

[0003] Some implementations described herein relate to a semiconductor package. The semiconductor package may include: a substrate; a semiconductor device disposed on a first portion of the surface of the substrate; and a reinforcing plate disposed on a second portion of the surface of the substrate. The second portion may be separable from the first portion, and the reinforcing plate may be configured to be spaced apart from and surround the semiconductor device. The semiconductor package may include an electromagnetic interference absorber disposed on a third portion of the surface of the substrate. The third portion may be separable from the first and second portions, and the electromagnetic interference absorber may be configured to be disposed between the semiconductor device and the reinforcing plate.

[0004] Some implementations described herein relate to an electromagnetic interference (EMI) absorber for a semiconductor package. The EMI absorber may include a body portion configured to be disposed on a first portion of a surface of a substrate, the substrate including a semiconductor device disposed on a second portion of the surface of the substrate and a reinforcing plate disposed on a third portion of the surface of the substrate. The first, second, and third portions may be separate. The reinforcing plate may be configured to be spaced apart from and surround the semiconductor device. The body portion may be configured to be disposed between the semiconductor device and the reinforcing plate. The EMI absorber may include a main opening disposed within the body portion and configured to receive the semiconductor device.

[0005] Some implementations described herein relate to a semiconductor package. The semiconductor package may include: a substrate; an ASIC disposed on a first portion of the surface of the substrate; a memory device disposed on a second portion of the surface of the substrate; and a reinforcing plate disposed on a third portion of the surface of the substrate. The reinforcing plate is configured to be spaced apart from and surround the ASIC and the memory device. The semiconductor package may include an electromagnetic interference absorber disposed on a fourth portion of the surface of the substrate. The first, second, third, and fourth portions may be separate. The electromagnetic interference absorber may be configured to be disposed between the reinforcing plate and the ASIC and the memory device. The electromagnetic interference absorber may be configured to surround the ASIC and the memory device and block electromagnetic interference radiation generated by the ASIC and the memory device. Attached Figure Description

[0006] Figures 1A to 1F This is an illustration of an example of a capless semiconductor package that includes electromagnetic interference (EMI) radiation.

[0007] Figure 2 This is a graph illustrating the performance of the example open-top semiconductor package in Figure 1 with and without an EMI absorber.

[0008] Figure 3 This is a diagram of an example component of an example open-cap semiconductor package, as shown in Figure 1. Detailed Implementation

[0009] The following detailed description of the example implementation is with reference to the accompanying drawings. The same reference numerals in different drawings can identify the same or similar elements.

[0010] While capless semiconductor packaging offers improved thermal performance, higher-speed capless semiconductor packaging requires additional components mounted on the substrate supporting the semiconductor device. These additional components can densely fill the substrate and are susceptible to electromagnetic interference (EMI) radiation generated by the semiconductor device. EMI is disturbance generated by external sources that affect the circuitry (e.g., additional components on the substrate) through electromagnetic induction, electrostatic coupling, or conduction. Disturbances can degrade circuit performance or even cause the circuit to stop working. In the case of network data paths, this effect can increase the data error rate or lead to complete data loss.

[0011] Current technologies for containing EMI radiation generated by semiconductor devices utilize EMI absorbers on a portion of the substrate supporting the semiconductor device. However, EMI absorbers cannot utilize the space occupied by additional components densely filling the substrate. Therefore, current technologies for containing EMI radiation generated by semiconductor devices consume computing resources (e.g., processing resources, memory resources, communication resources, etc.), networking resources, etc., which are associated with the degradation or inoperability of additional components on the substrate, increased error rates in network data due to degraded or inoperable additional components, and loss of network data due to degraded or inoperable additional components.

[0012] Some implementations described herein relate to capless semiconductor packages that contain EMI radiation. For example, a capless semiconductor package may include: a substrate; a semiconductor device disposed on a first portion of the surface of the substrate; and a reinforcing plate disposed on a second portion of the surface of the substrate. The second portion may be separable from the first portion, and the reinforcing plate may be configured to be spaced apart from and surround the semiconductor device. The semiconductor package may include an EMI absorber disposed on a third portion of the surface of the substrate. The third portion may be separable from the first and second portions, and the EMI absorber may be configured to be disposed between the semiconductor device and the reinforcing plate.

[0013] In this way, capless semiconductor packages can incorporate EMI radiation. For example, an EMI absorber can be placed around the semiconductor device within the capless semiconductor package. The EMI absorber can do not consume space in the substrate supporting the semiconductor device and can accommodate additional components supported by the substrate. The EMI absorber can absorb EMI radiation generated by the semiconductor device and can reduce the degradation or inoperability of substrate-supported additional components caused by this EMI radiation. Therefore, capless semiconductor packages save computing resources, networking resources, etc., which would otherwise be consumed by degrading or rendering additional components on the substrate inoperable, increasing the error rate of network data due to degraded or inoperable additional components, and losing network data due to degraded or inoperable additional components.

[0014] Figures 1A to 1F This is a diagram of example 100 associated with an open-top semiconductor package 105 that contains EMI radiation. (See diagram for example.) Figures 1A to 1F As shown, the capless semiconductor package 105 may include a substrate 110, a reinforcing plate 115, and one or more semiconductor devices (e.g., an ASIC 120 and / or a memory device 125). Further details of the substrate 110, the reinforcing plate 115, the ASIC 120, and the memory device 125 are provided elsewhere in this document.

[0015] like Figure 1AAs shown, a reinforcing plate 115 may be disposed on a first portion (e.g., an outer edge portion) of the surface (e.g., the top surface) of the substrate 110, and the ASIC 120 and memory device 125 may be disposed on a second portion (e.g., a central portion) of the surface of the substrate 110. The second portion of the substrate 110 may be separated from the first portion of the substrate 110. The reinforcing plate 115 may be spaced apart from the ASIC 120 and memory device 125 and may surround the ASIC 120 and memory device 125.

[0016] Substrate 110 can support components of capless semiconductor package 105 (e.g., reinforcement plate 115, ASIC 120, and memory device 125). Substrate 110 may include conductive or semiconductive materials (e.g., silicon, aluminum, copper, etc.) and may include printed circuit board materials, etc. The size and shape of substrate 110 can be configured to support one or more capless semiconductor packages 105. For example, substrate 110 can support multiple sets of reinforcement plates 115, ASIC 120, and memory devices 125 to provide multiple capless semiconductor packages 105.

[0017] The reinforcing plate 115 may include a frame-like structure that does not cover the central portion of the substrate 110, and may reinforce the substrate 110 by adding a reinforcing boundary around the ASIC 120 and the memory device 125. In this way, the reinforcing plate 115 allows the substrate 110 to adequately support the ASIC 120 and the memory device 125 without bending or buckling. The reinforcing plate 115 may be formed of various materials, such as silicon, aluminum, copper, polymeric materials (e.g., silicone rubber mixed with aluminum particles and zinc oxide)). The size and shape of the reinforcing plate 115 may be determined based on the size and shape of the ASIC 120 and the memory device 125. For example, the size and shape of the reinforcing plate 115 may be determined such that the reinforcing plate 115 does not cover the central portion of the substrate 110 and that the reinforcing plate 115 is spaced apart from and surrounds the ASIC 120 and the memory device 125.

[0018] ASIC 120 may include an integrated circuit chip that is customized for a specific purpose rather than intended for general use. In some implementations, ASIC 120 may be replaced by one or more other semiconductor devices, such as Application Standard Product (ASSP) chips, industry-standard integrated circuit chips, etc. ASIC 120 may be formed from various materials, such as, for example, metal-oxide-semiconductor (MOS) materials. The size and shape of ASIC 120 may be determined based on the functionality of ASIC 120 and based on the size and shape of the reinforcing plate 115. For example, the size and shape of ASIC 120 may be determined such that the reinforcing plate 115 is spaced apart from and surrounds ASIC 120.

[0019] Each memory device 125 may include means for storing information for use in a computer or related computer hardware and digital electronic devices. In some implementations, each memory device 125 may include a high-bandwidth memory (HBM) device that provides a high-speed computer memory interface for three-dimensional stacked synchronous dynamic random access memory (SDRAM). The size and shape of each memory device 125 may be determined based on the functionality of each memory device 125 and based on the size and shape of the reinforcing plate 115. For example, the size and shape of the memory device 125 may be determined such that the reinforcing plate 115 is spaced apart from and surrounds the memory device 125. Although Figure 1A Two memory devices 125 are shown, but in some implementations, the capless semiconductor package 105 may include one memory device 125 or more than two memory devices 125.

[0020] like Figure 1BAs shown, since the reinforcing plate 115 is spaced apart from and surrounds the ASIC 120 and memory device 125, an unused substrate region 130 (e.g., shown in crosshairs) on the surface of the substrate 110 can be formed in the capless semiconductor package 105. The unused substrate region 130 may include space on the substrate 110 that is not occupied by additional components that densely fill the substrate 110. As further shown, the unused substrate region 130 may include a first size and a second size, which depend on the size and shape of the reinforcing plate 115, the ASIC 120, and / or the memory device 125. In some implementations, the first size may include a range from approximately two millimeters (2 mm) to approximately fifteen millimeters (15 mm). In some implementations, the second size may include a range from approximately two millimeters (2 mm) to approximately eighteen millimeters (18 mm). Depending on the size and shape of the reinforcing plate 115, the ASIC 120, and the memory device 125, the first and / or second sizes may include different ranges.

[0021] like Figure 1C As shown, an EMI absorber 135 can be supported on the surface of substrate 110 using an unused substrate region 130. The EMI absorber 135 can be disposed between a semiconductor device (e.g., ASIC 120 and memory device 125) and a reinforcing plate 115. In some implementations, the EMI absorber 135 can absorb EMI radiation generated by ASIC 120 and / or memory device 125. In some implementations, the EMI absorber 135 can reduce the EMI radiation generated by ASIC 120 and / or memory device 125 from reaching one or more components (not shown) disposed on the surface of substrate 110. The size and shape of the EMI absorber 135 can be configured to fit within an unused substrate region 130 of substrate 110. The EMI absorber 135 can be formed from various materials, such as metallic materials, carbon materials, ceramic materials, cement materials, polymer materials, hybrid materials, etc.

[0022] In some implementations, the EMI absorber 135 can block EMI radiation in the frequency range of approximately two GHz to approximately forty GHz. In some implementations, the EMI absorber 135 can block at least 10 dB more EMI radiation than an open-cap semiconductor package without the EMI absorber 135. In some implementations, the thickness of the EMI absorber 135 can depend on the amount of EMI radiation to be generated by the ASIC 120 and / or the memory device 125.

[0023] like Figure 1DAs shown, an EMI absorber 135 may be disposed on an unused substrate region 130 between the reinforcing plate 115 and the ASIC 120 and memory device 125. The EMI absorber 135 may include a frame-like structure that does not cover the ASIC 120 and memory device 125, but does substantially cover the unused substrate region 130. In some implementations, the EMI absorber 135 may include one or more openings to expose one or more additional components disposed on the substrate 110 (e.g., if disposed on the unused substrate region 130). In some implementations, if the unused substrate region 130 does not include additional components, one or more openings may be omitted from the EMI absorber 135.

[0024] like Figure 1E As shown, the EMI absorber 135 may include a body portion 140, a main opening 145 disposed in the body portion 140, and one or more openings 150 disposed in the body portion 140. The body portion 140 may surround the ASIC 120 and the memory device 125. The body portion 140 may absorb EMI radiation generated by the ASIC 120 and / or the memory device 125. The body portion 140 may reduce the EMI radiation generated by the ASIC 120 and / or the memory device 125 from reaching one or more components disposed on the surface of the substrate 110. The body portion 140 may be formed of various materials, such as metallic materials, carbon materials, ceramic materials, cement materials, polymer materials, hybrid materials, etc. In some implementations, the body portion 140 may block EMI radiation in the frequency range of approximately two GHz to approximately forty GHz. In some implementations, the body portion 140 may block at least 10 dB more EMI radiation than an open semiconductor package without the EMI absorber 135.

[0025] The main opening 145 can accommodate and expose the top portion of the ASIC 120 and memory device 125. One or more openings 150 can accommodate one or more corresponding components disposed on an unused substrate region 130. (e.g.) Figure 1E As shown, the EMI absorber 135 may include a thickness depending on the amount of EMI radiation to be generated by the ASIC 120 and / or memory device 125. In some implementations, the thickness of the EMI absorber 135 may include a range from about 0.5 mm to about 10 mm.

[0026] like Figure 1FAs shown, the ASIC 120 and memory device 125 can be disposed within the main opening 145 of the body portion 140 of the EMI absorber 135. In some implementations, one or more components 155 can be disposed in an unused substrate region 130. One or more components 155 can be disposed within one or more openings 150 of the body portion 140 of the EMI absorber 135. In this way, the EMI absorber 135 can shield EMI radiation generated by the ASIC 120 and / or memory device 125 from one or more components 155.

[0027] In this way, the capless semiconductor package 105 can contain EMI radiation. For example, the capless semiconductor package 105 can have an EMI absorber 135 disposed around the semiconductor device (e.g., ASIC 120 and / or memory device 125) of the capless semiconductor package 105. The EMI absorber 135 can not consume space in the substrate 110 supporting the semiconductor device and can accommodate additional components supported by the substrate 110. The EMI absorber 135 can absorb EMI radiation generated by the semiconductor device and can reduce the degradation or inoperability of the additional components supported by the substrate 110 due to such EMI radiation. Therefore, the capless semiconductor package 105 saves computing resources, networking resources, etc., which would otherwise be consumed by degrading or inoperable additional components on the substrate 110, increasing the error rate of network data due to degraded or inoperable additional components, losing network data due to degraded or inoperable additional components, etc.

[0028] As indicated above, Figures 1A to 1F Provided as an example. Other examples may be provided for use with reference to [specific examples]. Figures 1A to 1F The content described is different. Figures 1A to 1F The number and arrangement of the devices shown are provided as examples. In fact, with... Figures 1A to 1F Compared to the device shown, there may be additional devices, fewer devices, different devices, or devices arranged in a different manner. Furthermore, in Figures 1A to 1F The two or more devices shown can be implemented within a single device, or Figures 1A to 1F The single device shown can be implemented as multiple distributed devices. Additionally or alternatively, Figures 1A to 1F The set of devices shown (e.g., one or more devices) can perform what is described as being performed by Figures 1A to 1F The other set of devices shown performs one or more functions.

[0029] Figure 2 Graph 200 depicts the performance of the example capless semiconductor package 105 shown in Figure 1. Figure 2As shown, the first line (e.g., at the top) can be associated with the power radiated by the uncovered semiconductor package 105 without the EMI absorber 135. This first line can be based on frequency fluctuations and can include 25.834023 dBmW of power at a frequency level of 20 GHz. As further shown, the second line (e.g., at the bottom) can be associated with the power radiated by the uncovered semiconductor package 105 with the EMI absorber 135. This second line can be independent of frequency fluctuations (e.g., indicating a consistent total radiated power) and can include 15.816733 dBmW of power at a frequency level of 20 GHz. The difference between the maximum powers is 10.07 dB at the 20 GHz frequency level. Therefore, the EMI absorber 135 can block at least 10 dB more EMI radiation than the uncovered semiconductor package 105 without the EMI absorber 135. Figure 2 The power and frequency described are provided as examples and may differ in other implementations.

[0030] Figure 3 This is an illustration of example components that may be included in device 300, which may correspond to capless semiconductor package 105. In some implementations, capless semiconductor package 105 may include one or more devices 300 and / or one or more components of device 300. Figure 3 As shown, device 300 may include bus 310, processor 320, memory 330, input component 340, output component 350 and communication interface 360.

[0031] Bus 310 includes one or more components that enable wired and / or wireless communication between components of device 300. Bus 310 can connect components such as via operative coupling, communicative coupling, electronic coupling, and / or electrical coupling. Figure 3 Two or more components are coupled together. Processor 320 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 320 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 320 includes one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0032] Memory 330 includes volatile and / or non-volatile memory. For example, memory 330 may include random access memory (RAM), read-only memory (ROM), hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 330 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus). Memory 330 may be a non-transient computer-readable medium. Memory 330 stores information, instructions, and / or software (e.g., one or more software applications) related to the operation of device 300. In some implementations, memory 330 includes one or more memories, such as those coupled to one or more processors (e.g., processor 320) via bus 310.

[0033] Input component 340 enables device 300 to receive input, such as user input and / or sensed input. For example, input component 340 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, accelerometer, gyroscope, and / or actuator. Output component 350 enables device 300 to provide output, such as via a display, speaker, and / or light-emitting diode. Communication interface 360 ​​enables device 300 to communicate with other devices via wired and / or wireless connections. For example, communication interface 360 ​​may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0034] Apparatus 300 may perform one or more operations or procedures described herein. For example, a non-transient computer-readable medium (e.g., memory 330) may store a set of instructions (e.g., one or more instructions or code) for execution by processor 320. Processor 320 may execute the set of instructions to perform one or more operations or procedures described herein. In some implementations, execution of the set of instructions by one or more processors 320 causes one or more processors 320 and / or apparatus 300 to perform one or more operations or procedures described herein. In some implementations, a hard-wired circuit system may be used instead of instructions or in combination with instructions to perform one or more operations or procedures described herein. Additionally or alternatively, processor 320 may be configured to perform one or more operations or procedures described herein. Therefore, the implementations described herein are not limited to any particular combination of hardware circuit systems and software.

[0035] Figure 3 The number and arrangement of the components shown are provided as an example. Figure 3Compared to the components shown, device 300 may include additional components, fewer components, different components, or components arranged in a different manner. Additionally or alternatively, the set of components of device 300 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of device 300.

[0036] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications may be made in light of the foregoing disclosure, or may be derived from the practice of implementation.

[0037] As used herein, the term "component" is intended to be interpreted broadly as hardware, firmware, or a combination of hardware and software. It is evident that the systems and / or methods described herein can be implemented in various forms as hardware, firmware, and / or combinations of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the implementation. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software code—it should be understood that the systems and / or methods can be implemented using software and hardware based on the descriptions herein.

[0038] Although specific combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features can be combined in ways not specifically recited in the claims and / or disclosed in the specification. While each dependent claim listed below may depend directly on only one claim, the disclosure of various implementations includes each dependent claim in combination with every other claim in the set of claims.

[0039] Therefore, unless explicitly stated otherwise, no element, action, or instruction used herein should be construed as critical or necessary. Furthermore, as used herein, the articles “a” and “one” are intended to include one or more items and may be used interchangeably with “one or more.” Further, as used herein, the article “the” is intended to include one or more items referenced in combination with the article “the” and may be used interchangeably with “one or more.” Additionally, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.) and may be used interchangeably with “one or more.” The phrase “only one” or similar language is used where only one item is anticipated. Furthermore, as used herein, the terms “has / have / having” are intended as open-ended terms. Further, unless explicitly stated otherwise, the phrase “based on” is intended to mean “at least partially based on.” Furthermore, as used herein, unless otherwise expressly stated (e.g., in the case of use in conjunction with “either of” or “only one of”), the term “or” is intended to be inclusive when used serially and may be used interchangeably with “and / or”.

[0040] Various exemplary embodiments have been described in the foregoing description with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made to the various exemplary embodiments, and additional embodiments can be implemented without departing from the broader scope of the invention as set forth in the following claims. Therefore, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: Substrate; A semiconductor device is disposed on a first portion of the surface of the substrate; A reinforcing plate is disposed on a second portion of the surface of the substrate. The second part is separate from the first part. The reinforcing plate is configured to be spaced apart from and surround the semiconductor device; as well as An electromagnetic interference absorber is disposed on a third portion of the surface of the substrate. The third part is separate from the first part and the second part. The electromagnetic interference absorber is configured to be disposed between the semiconductor device and the reinforcing plate. The electromagnetic interference absorber includes one or more openings for receiving one or more corresponding components disposed on the surface of the substrate, between the reinforcing plate and the electromagnetic interference absorber.

2. The semiconductor package of claim 1, wherein the semiconductor device comprises one or more of the following: Application-specific integrated circuits, or Memory device.

3. The semiconductor package of claim 1, wherein the electromagnetic interference absorber is configured to absorb electromagnetic interference radiation generated by the semiconductor device.

4. The semiconductor package of claim 1, wherein the electromagnetic interference absorber comprises: Main body part; as well as The main opening is provided in the body portion and configured to accommodate the semiconductor device.

5. The semiconductor package of claim 4, wherein the body portion of the electromagnetic interference absorber is configured to reduce electromagnetic interference radiation generated by the semiconductor device from reaching the one or more components disposed on the surface of the substrate.

6. The semiconductor package of claim 1, wherein the electromagnetic interference absorber comprises one or more of the following: Metallic materials Carbon materials Ceramic materials cement materials polymer materials, or Mixed materials.

7. The semiconductor package of claim 1, wherein the electromagnetic interference absorber is configured to block electromagnetic interference radiation at frequencies in the range of two gigahertz to forty gigahertz.

8. The semiconductor package according to claim 1, wherein the semiconductor package is a capless application-specific integrated circuit package.

9. The semiconductor package of claim 1, wherein the electromagnetic interference absorber is configured to block at least 10 Bass more electromagnetic interference radiation than a package without the electromagnetic interference absorber.

10. The semiconductor package of claim 1, wherein the thickness of the electromagnetic interference absorber depends on the amount of electromagnetic interference radiation to be generated by the semiconductor device.

11. An electromagnetic interference absorber for semiconductor packaging, the electromagnetic interference absorber comprising: The body portion is configured to be disposed on a first portion of the surface of a substrate, the substrate including a semiconductor device disposed on a second portion of the surface of the substrate and a reinforcing plate disposed on a third portion of the surface of the substrate. The first part, the second part, and the third part are separate. The reinforcing plate is configured to be spaced apart from and surround the semiconductor device. The body portion is configured to be disposed between the semiconductor device and the reinforcing plate; A main opening is provided in the body portion and configured to accommodate the semiconductor device; as well as One or more openings for accommodating one or more corresponding components disposed on the surface of the substrate, between the reinforcing plate and the electromagnetic interference absorber.

12. The electromagnetic interference absorber of claim 11, wherein the semiconductor device comprises one or more of the following: Application-specific integrated circuits, or Memory device.

13. The electromagnetic interference absorber of claim 11, wherein the body portion is configured to absorb electromagnetic interference radiation generated by the semiconductor device.

14. The electromagnetic interference absorber according to claim 11, wherein the semiconductor package is a capless application-specific integrated circuit package.

15. The electromagnetic interference absorber of claim 14, wherein the body portion of the electromagnetic interference absorber is configured to reduce electromagnetic interference radiation generated by the semiconductor device from reaching the one or more components disposed on the surface of the substrate.

16. The electromagnetic interference absorber according to claim 11, wherein the body portion comprises one or more of the following: Metallic materials Carbon materials Ceramic materials cement materials polymer materials, or Mixed materials.

17. The electromagnetic interference absorber of claim 11, wherein the body portion is configured to block electromagnetic interference radiation at frequencies in the range of two gigahertz to forty gigahertz.

18. The electromagnetic interference absorber of claim 11, wherein the body portion is configured to block at least ten Bass more electromagnetic interference radiation than a semiconductor package without the electromagnetic interference absorber.

19. The electromagnetic interference absorber of claim 11, wherein the thickness of the body portion depends on the amount of electromagnetic interference radiation to be generated by the semiconductor device.

20. A semiconductor package, comprising: Substrate; An application-specific integrated circuit is disposed on a first portion of the surface of the substrate; A memory device is disposed on a second portion of the surface of the substrate; A reinforcing plate is disposed on a third portion of the surface of the substrate. The reinforcing plate is configured to be spaced apart from and surround the application-specific integrated circuit and the memory device; as well as An electromagnetic interference absorber is disposed on a fourth portion of the surface of the substrate. The first part, the second part, the third part, and the fourth part are separate. The electromagnetic interference absorber is configured to be disposed between the reinforcing plate and the application-specific integrated circuit and the memory device. The electromagnetic interference absorber is configured to surround the application-specific integrated circuit (ASIC) and the memory device and block electromagnetic interference radiation generated by the ASIC and the memory device. The electromagnetic interference absorber includes one or more openings for receiving one or more corresponding components disposed on the surface of the substrate, between the reinforcing plate and the electromagnetic interference absorber.

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