Traveling wave transimpedance amplifier

Abstract

An illustrative high-bandwidth transimpedance amplifier includes a distributed amplifier having a plurality of transistors that receive a propagating input signal at respective nodes of an input signal line and drive corresponding nodes of an amplified signal line that propagates an amplified signal to an output voltage buffer. A feedback impedance couples the output voltage to a feedback node in the distributed amplifier, making the output voltage proportional to a current of the input signal. An illustrative method includes propagating an input signal current along an input signal line of a distributed amplifier, the distributed amplifier responsively propagating an amplified signal along an amplified signal line; buffering the amplified signal from a final node of the amplified signal line to produce an output voltage signal; and using the output voltage signal to draw the input signal current from the final node of the input signal line via the feedback impedance.

Description

Background Technology

[0001] The ever-increasing demand for data communication volume and speed continues, and sophisticated technologies for transmitting and receiving higher-frequency and higher-bandwidth signals through various forms of wireless and physical media are gradually meeting this demand. For example, the bandwidth limitation of fiber optic channels is typically determined by the capabilities of the electronic components at each end, rather than by the characteristics of the fiber optic cable that actually forms the channel. With the performance of these electronic components enhanced, the channel can support higher bandwidth communication.

[0002] Transimpedance amplifiers (TIAs) are key components in high-bandwidth fiber optic receivers. A TIA is a current-to-voltage converter, desirable for sensors such as photodiodes and other photodetectors with a more linear current response than their voltage response. Notably, for a given reverse bias voltage, the relationship between light intensity and photocurrent in a photodiode is quite linear. TIAs exhibit low input impedance while isolating the photodiode from output voltage variations, thereby stabilizing the reverse bias voltage and optimizing the photodetector response.

[0003] Complementary metal-oxide-semiconductor (CMOS) processing is commonly used in high-bandwidth electronic components because it typically provides fast, efficient switching that can support the processing of high-bandwidth signals. However, transistors created using this processing often have significant gate capacitance. In transimpedance amplifiers (TIAs) with input transistors of sufficient size to mitigate input reference noise, the gate capacitance of the input transistors, combined with the feedback resistor, forms a (bandwidth-limiting) low-pass filter, as described in the Wikipedia entry for transimpedance amplifiers. This problem can undesirably limit the communication bandwidth of fiber optic channels and other systems employing existing TIA designs. Summary of the Invention

[0004] Therefore, this paper discloses a traveling-wave transimpedance amplifier and method for reducing the effect of the gate capacitance of input transistors and thereby increasing their signal bandwidth. An illustrative high-bandwidth transimpedance amplifier includes: a voltage buffer, a distributed amplifier, and a feedback impedance. The voltage buffer is coupled to an output node to provide an output voltage signal. The distributed amplifier has an input signal line for propagating the input signal and a plurality of transistors that receive the input signal at corresponding nodes on the input signal line and responsively drive corresponding nodes on an amplified signal line, which propagates the amplified signal to the voltage buffer. The feedback impedance couples the output node to a feedback node in the distributed amplifier, such that the output voltage signal is proportional to the current of the input signal.

[0005] Another illustrative transimpedance amplifier includes: a set of input signal line inductors, which, if the set of input signal line inductors has more than one inductor, are connected in series, each amplification signal line inductor being coupled between two nodes in the input signal line; a set of amplification signal line inductors, which, if the set of amplification signal line inductors has more than one inductor, are connected in series, each amplification signal line inductor being coupled between two nodes in the amplification signal line; a common drain amplifier that buffers the voltage from the final node in the amplification signal line to drive the output node; a set of two or more transistors, each transistor having a gate connected to a corresponding node in the input signal line to receive a current signal propagating along the input signal line, each transistor also having a drain connected to a corresponding node in the amplification signal line to propagate a voltage signal responsively along the amplification signal line to the gate of the output transistor; and a feedback impedance that couples the output node to the final node in the input signal line, the output node generating a voltage signal that draws the current signal to the output node through the feedback impedance.

[0006] An illustrative method includes: propagating an input signal current along an input signal line of a distributed amplifier, the distributed amplifier responsively propagating an amplified signal along an amplified signal line; buffering the amplified signal from the final node of the amplified signal line to generate an output voltage signal; and using the output voltage signal to draw the input signal current from the final node of the input signal line via a feedback impedance.

[0007] Each of the above can be implemented individually or in combination, and can be implemented in any suitable combination with any one or more of the following features: 1. The input signal line includes a first set of inductors series-coupled to the corresponding nodes of the input signal line. 2. The amplified signal line includes a second set of inductors series-coupled to the corresponding nodes of the amplified signal line. 3. One of the plurality of transistors is a final transistor that receives the input signal from the final node of the input signal line and drives the final node of the amplified signal line. 4. A voltage buffer buffers the voltage at the final node of the amplified signal line. 5. The feedback node is the final node of the input signal line. 6. One of the plurality of transistors is a starting transistor that receives the input signal from the starting node of the input signal line and drives the starting node of the amplified signal line. 7. Each inductor in the first set of inductors has an inductance L. G Furthermore, each inductor in the second group of inductors has an inductance L. D 8. The input signal passes through L G The input inductance of / 2 is coupled to the starting node of the input signal line. 9. The feedback impedance includes the feedback resistor and L. G10. The multiple transistors of the distributed voltage amplifier are each configured as a common-source amplifier. 11. The initial pull-up impedance is coupled to the start node of the amplified signal line, and the final pull-up impedance is coupled to the final node of the amplified signal line. 12. The initial pull-up impedance and the final pull-up impedance each include a pull-up resistor and an L. D 13. The bias circuit biases multiple transistors of the distributed voltage amplifier via initial and final pull-up impedances. 14. The bias circuit biases the drains of two or more transistors via amplified signal lines. 15. The voltage buffer is a common-drain amplifier. 16. The propagated input signal uses an inductor whose gate capacitances of two transistors each coupled to the distributed amplifier are connected in series. 17. The propagated amplified signal uses an inductor whose drain capacitances of two transistors each coupled to the distributed amplifier are connected in series. Attached Figure Description

[0008] Figure 1 This is a three-dimensional view illustrating a fiber optic cable connector.

[0009] Figure 2 This is a block diagram illustrating a fiber optic cable connector.

[0010] Figure 3 This is a schematic diagram of an illustrative transimpedance amplifier (TIA).

[0011] Figure 4 This is a schematic diagram illustrating the traveling wave (TIA).

[0012] Figure 5 This is a schematic diagram illustrating the bias circuit.

[0013] Figure 6 This is another illustrative diagram of a traveling wave (TIA). Detailed Implementation

[0014] Although specific embodiments are given in the accompanying drawings and the following description, please remember that they do not limit this disclosure. Rather, they provide a basis for those skilled in the art to identify alternatives, equivalents, and modifications that fall within the scope of the appended claims.

[0015] Use this as an illustrative context. Figure 1A fiber optic cable connector is shown, which can be used to connect computers and network equipment in a data processing center. Connector frame 102 houses a printed circuit board (PCB) assembly 104 configured with edge connector contacts 106. The edge connector contacts 106 mate with contacts in a socket at a host device network interface port to send and receive electrical signals. PCB assembly 104 includes one or more packaged integrated circuit (IC) chips or discrete electrical components mounted on contact pads on the PCB. For example, PCB assembly 104 may include a digital data recovery and remodulation (DRR) device 108 that equalizes received signals, recovers data, and retransmits the recovered data via optional error correction, signal format conversion, and channel realignment.

[0016] PCB assembly 104 includes an optical coupling module 110 that couples an integrated photodetector and photoemitter to one or more optical paths. When mated with the optical coupling module 110, a ferrule 112 aligns one or more optical fibers of the fiber optic cable 114 with one or more optical paths. The optical coupling module 110 typically uses lenses and prisms to define the optical path for coupling optical signals between the optical fibers and the photodetector and photoemitter; however, other optical elements (e.g., mirrors, gratings) may also be suitable.

[0017] Although not shown here, the fiber optic cable connector may further include a cover and a finger grip 116 to protect other components from damage during normal use.

[0018] Figure 2 This is a block diagram that more clearly illustrates the signal flow of the illustrative fiber optic cable connector 202. The DRR device 204 is coupled to the network interface port to receive, for example, 28 or 56 gigabits (GBd) electrical transmit signals from the host on each of the four channels, and to provide 28 or 56 GBd electrical receive signals to the host on each of the four channels. The electrical transmit and receive signals are differential signals that can employ either non-return-to-zero (NRZ) signaling or 4-level pulse amplitude modulation (PAM4) signaling. Taking overhead into account, the four signal channels in this example collectively transmit data at a nominal 100 or 200 gigabits per second (Gbps) for NRZ and at a nominal 200 or 400 Gbps for PAM4.

[0019] Connector 202 may further include a microcontroller unit (MCU) 205 coupled to the network interface port via a management data bus, such as an internal integrated circuit (I2C) bus or a management data input / output (MDIO) bus. The host can use the management data bus to identify the cable's function, determine connection status, diagnose faults, and / or configure the cable connector's operation. MCU 205 processes commands received via the management data bus to appropriately read or set the control registers of DRR device 204. In at least some cases, MCU 205 is integrated into DRR device 204.

[0020] Optical coupling module 110 ( Figure 1 The array includes a photoelectric emitter array 206, an optical path coupler 210, and a photodetector array 208. The DRR device 204 converts the electrical emission signal into a remodulated electrical emission signal that drives the photoelectric emitter array 206. As an example, the photoelectric emitter in the array is a vertical-cavity surface-emitting laser (VCSEL). The electrical drive signal induces a current in the photoelectric emitter, which in turn emits a light signal with an intensity corresponding to the amplitude of that current.

[0021] Optical path coupler 210 optically couples the optical signal from the photoemitter to the optical fiber in cable 114, and then couples the optical signal from the optical fiber cable 114 to an array of photodetectors 208. Various suitable implementations of photodetectors are available in the literature. As an example, the photodetectors in the array are reverse-biased light-emitting diodes, each generating a photocurrent signal corresponding to the intensity of the received optical signal. A transimpedance amplifier (TIA) converts the photocurrent signal into a voltage signal, amplifying the signal while isolating the photodiodes from output voltage variations. In this way, the modulated optical signal intensity is converted into a modulated voltage signal for equalization and demodulation into a digital data stream by a DRR device.

[0022] Figure 3 An illustrative TIA is shown, comprising an output node driven by an output transistor M1 in a source follower (aka common-drain amplifier) ​​configuration to buffer voltage signals on intermediate node 302. A second transistor M2 is coupled to this output node with a bias voltage V. B Bias is applied to act as a current sink and minimize the output impedance of the TIA.

[0023] The third transistor M3 operates in a common-source amplifier configuration to drive intermediate node 302 using an amplified version of the voltage signal at the input node. Drain resistor R D The gain of the common-source amplifier is determined, but the output impedance of the common-source amplifier configuration may be limited (therefore including transistors M1 and M2).

[0024] Feedback resistor R F Couple the output node to the input node. The feedback resistor tightly connects the output voltage to the input signal current, making the output voltage V... o With input signal current I IN Basically proportional, thus through the feedback resistor R F It draws input signal current. The output voltage can be expressed as V. o =-R F *I IN The feedback arrangement makes the voltage at the input node insensitive to the input current and isolated from the voltage at the output node, at least at low frequencies.

[0025] Feedback resistor R F Combined with the gate capacitance of transistor M3, a low-pass filter is formed, thereby attenuating the high-frequency components of the input signal current. Other considerations (i.e., input reference noise) prevent the feedback resistor and input transistor size from being reduced to sufficiently increase the filter cutoff frequency. Therefore, the inventors propose using a distributed amplifier (also known as a "traveling-wave amplifier") to reduce the apparent input gate capacitance, and thereby reduce the attenuation of high-frequency signal components.

[0026] Figure 4 An illustrative traveling wave (TIA) is shown. Figure 3 The input transistor M3 is in Figure 4 The transistor is replaced by a group of multiple transistors connected in a distributed amplifier arrangement. Four transistors M3-M6 are shown here, but the number of transistors can be any integer greater than 1. The total number of transistors can have a [missing information - likely a specific configuration or feature]. Figure 3 The input transistor M3 has approximately the same channel area. Therefore, for example, Figure 4 The four transistors M3-M6 in the structure can each have approximately Figure 3 The input transistor M3 has a channel width that is one-quarter of the channel width (and gate capacitance), and otherwise can share similar dimensions, such as dielectric thickness, doping distribution and channel length.

[0027] When the input signal flows along a set of inductors L connected in series with the gates of the transistors... G As the input signal propagates along the formed input line, the distributed amplifier arrangement causes multiple transistors M3-M6 to operate sequentially. This arrangement of inductors and gate capacitors simulates the behavior of a transmission line, causing the signal to propagate with a characteristic delay (approximately...). And it is passed from node to node (and from gate to gate) with virtually no attenuation.

[0028] With gate capacitance C G Adjust the inductor L appropriately GThe size of the transmission line is chosen to provide a matched impedance to the input signal source, for example, 50 ohms. (Impedance matching does not need to be precise; a 6dB matching performance has been observed to be sufficient.) The characteristic transmission line impedance, which can be used as a rule of thumb, is calculated as follows:

[0029]

[0030] However, parasitic effects and other design considerations may prompt the use of regulated L G value.

[0031] Inductor L in the input signal line G Gate capacitor C is provided G Isolation from the input signal source and from the feedback signal relaxes the bandwidth limitations that might otherwise be imposed by combining the gate capacitance with resistors in the input and feedback paths. Additional inductors L can optionally be provided at the input of the input signal line and in the feedback path. G / 2, to further isolate the gate capacitance effect of the starting transistor M6 and the final transistor M3 of the distributed amplifier.

[0032] When multiple transistors M3-M6 receive input signals at their respective gates, they generate amplified voltage signals at their drains. The drain is formed by a series of inductors L. D Connections, these inductors L D An amplified signal line is formed, propagating its respective amplified voltage signal to intermediate node 302 at the same propagation rate as the input signal line. This propagation rate matching allows the amplified voltage signals from multiple transistors to be superimposed and combined at intermediate node 302. Figure 3 Similarly, the output transistor M1 is configured as a source follower to drive the output node, thereby buffering the voltage signal from the intermediate node 302.

[0033] The intrinsic drain capacitance C of the transistor D The inductor L of the amplified signal line was adjusted accordingly. D The dimensions are to provide a characteristic propagation delay (approximate) with the input signal line. Feature propagation delay (approximate) for matching Through impedance matching, the amplifier can perform well even if the propagation delay is not perfectly matched.

[0034] Although the above description of the signal lines assumes reliance solely on inductor elements and intrinsic capacitance, it should be recognized that this design allows for the inclusion of additional capacitive elements to individually adjust the gate and / or drain capacitance.

[0035] In order to properly bias multiple transistors M3-M6, the bias voltage V H Coupled to the amplified signal line via one or more pull-up impedances. Figure 4 In the process, the start and end nodes of the amplified signal line are each connected via resistor 2R. D and inductor L D / 2 pull-up impedance is coupled to the bias voltage V H .

[0036] The amplifier exhibits optimal (most linear) performance when each transistor M1-M6 is saturated. Transistor M2 is biased by voltage V. B Direct control, bias voltage V B It can be generated using a standard Widlar or Wilson current mirror or any known variant thereof. Figure 5 This illustrates the generation of bias voltage V for a distributed amplifier. H An illustrative circuit.

[0037] Figure 5 The bias circuit includes a set of "replica" transistors M 1,r -M 3,r These replicated transistors are matched with transistors M1-M3, but since their sole purpose is to provide a voltage reference, the replicated transistors can be scaled down to a smaller size to reduce power consumption. Using a bias voltage V... B Bias transistor M 2,r , to be used as a current sink relative to the replicated output node 501. Transistor M 1,r It operates in a source follower configuration to control the voltage of the replicated output node 501. The replicated output node voltage is connected to transistor M in a common-source configuration. 3,r The gate of the transistor M 3,r With drain resistor R D,r To coordinate with and control M 1,r The gate voltage.

[0038] Current source I REF Drive current through drain resistor R D,r Increase M 1,r The gate voltage, thereby increasing M 3,r The gate voltage until the current required for the common-source amplifier to conduct (i.e., I) REF At this time, M 3,r The drain voltage and the cross-drain resistor R D,r The voltage drop is combined to limit the reference voltage V. REF Then, voltage regulator 502 adjusts the bias voltage node V. H To match the reference voltage V REF . Figure 5 Voltage regulator 502 is shown as a low dropout (LDO) regulator, but any suitable regulator configuration can be used.

[0039] Figure 6 Another illustrative traveling wave TIA is shown. In this implementation, the transmission line segment replaces... Figure 4 The lumped inductor element. The transmission segment of the input signal line is designed to have a characteristic impedance Z0 equal to the desired input impedance TIA, for example, 50 ohms. The transmission segment of the amplified signal line is designed to have a pull-up resistor (e.g., 2R). D The characteristic impedance of the match.

[0040] Note that in Figure 6 In this context, the designation L refers to the length of the transmission line segment, not the inductance. Since the same processing is used to construct the transmission lines for both the input signal line and the amplified signal line, their propagation rates will be approximately the same, resulting in their propagation delay being primarily determined by the length of the transmission line segment.

[0041] Input signal line components and amplification signal line components, whether implemented as lumped inductors or transmission lines, will actually exhibit behavior somewhere in between. Standard circuit simulation techniques can be used to model the performance of traveling-wave TIAs and improve performance by adjusting the parameter values ​​of the signal line components.

[0042] By reducing the effective input capacitance, the traveling wave TIA can, under any circumstances, be relatively... Figure 3 The TIA design significantly increases bandwidth and has little or no cost in terms of input reference noise and power consumption.

[0043] Once fully understanding the above disclosure, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, this disclosure illustrates the use of such transistors due to the availability and speed of n-type metal-oxide-semiconductor field-effect transistors (“nMOS” or “n-MOSFET”) in existing CMOS processes; however, it should be recognized that the disclosed principles apply to any other available transistor type. As a more specific example, the disclosed circuitry can be implemented using junction field-effect transistors (JFETs) and bipolar junction transistors (BJTs) in silicon, as well as other semiconductors having n-type, p-type, and hybrid forms. The claims are intended to be construed as covering all such alternatives, equivalents, and modifications included within the scope of the appended claims.

Claims

1. A high-bandwidth transimpedance amplifier, characterized in that, The high-bandwidth transimpedance amplifier includes: A voltage buffer, coupled to the output node, provides the output voltage signal; A distributed amplifier has an input signal line for propagating an input signal, and a plurality of transistors that receive the input signal at corresponding nodes of the input signal line and operate to drive corresponding nodes of the amplified signal line, the amplified signal line propagating the amplified signal to a voltage buffer. The input signal line includes a first set of inductors that series-couple the corresponding nodes of the input signal line, and the amplified signal line includes a second set of inductors that series-couple the corresponding nodes. One of the plurality of transistors is a final transistor that receives the input signal from the final node of the input signal line and drives the final node of the amplified signal line. The voltage buffer operates to buffer the voltage at the final node of the amplified signal line. The feedback impedance couples the output node to the final node of the input signal line, making the output voltage signal proportional to the current of the input signal.

2. The high-bandwidth transimpedance amplifier as described in claim 1, characterized in that, One of the plurality of transistors is a start transistor that receives the input signal from the start node of the input signal line and drives the start node of the amplified signal line, wherein each of the inductors in the first set of inductors has an inductance Lg, and wherein the input signal is coupled to the start node of the input signal line via an input inductance of Lg / 2.

3. The high-bandwidth transimpedance amplifier as described in claim 2, characterized in that, The feedback impedance includes a feedback resistor and a feedback inductance of Lg / 2.

4. The high-bandwidth transimpedance amplifier as described in claim 2, characterized in that, The plurality of transistors in the distributed amplifier are each configured as a common source amplifier.

5. The high-bandwidth transimpedance amplifier as described in claim 4, characterized in that, Each of the inductors in the second group has an inductance Ld, wherein an initial pull-up impedance is coupled to the starting node of the amplified signal line and a final pull-up impedance is coupled to the final node of the amplified signal line, and wherein the initial pull-up impedance and the final pull-up impedance each include a pull-up resistor and a pull-up inductance of Ld / 2.

6. The high-bandwidth transimpedance amplifier as described in claim 5, characterized in that, The high-bandwidth transimpedance amplifier further includes a bias circuit that biases the plurality of transistors of the distributed amplifier via the initial pull-up impedance and the final pull-up impedance.

7. The high-bandwidth transimpedance amplifier as described in claim 1, characterized in that, The voltage buffer is a common-drain amplifier.

8. A transimpedance amplifier, characterized in that, The transimpedance amplifier includes: A set of input signal line inductors, the set of input signal line inductors being connected in series, each input signal line inductor being coupled between two nodes in the input signal line; A set of amplified signal line inductors, the set of amplified signal line inductors being connected in series, each amplified signal line inductor being coupled between two nodes in the amplified signal line; The output transistor in a common-drain amplifier configuration drives the output node; A group of two or more transistors, each transistor having a gate connected to a corresponding node in the input signal line to receive a current signal propagating along the input signal line, and each transistor also having a drain connected to a corresponding node in the amplified signal line to responsively propagate a voltage signal along the amplified signal line to the gate of the output transistor; and The feedback impedance couples the output node to the final node in the input signal line. The output node generates a voltage signal, and the voltage signal draws the current signal to the output node through the feedback impedance.

9. The transimpedance amplifier as described in claim 8, characterized in that, The transimpedance amplifier further includes a bias circuit that biases the drains of the two or more transistors via the amplified signal line.

10. The transimpedance amplifier as claimed in claim 9, characterized in that, The bias circuit is coupled to the starting node of the amplified signal line with an initial pull-up impedance and to the final node of the amplified signal line with a final pull-up impedance.

11. The transimpedance amplifier as claimed in claim 10, characterized in that, The amplified signal line inductances each have a value of Ld, wherein the initial pull-up impedance and the final pull-up impedance each include a pull-up resistor and a pull-up inductance of Ld / 2.

12. The transimpedance amplifier as described in claim 8, characterized in that, The input signal line inductances each have a value of Lg, and the input signal is coupled to the starting node of the input signal line via an input inductance of Lg / 2.

13. The transimpedance amplifier as described in claim 12, characterized in that, The feedback impedance includes a feedback resistor and a feedback inductance of Lg / 2.

14. A method for operating a transimpedance amplifier, characterized in that, The method includes: The input signal current propagates along the input signal line of the distributed amplifier of the transimpedance amplifier, and the amplified signal is propagated in response along the amplified signal line of the distributed amplifier. Buffer the amplified signal from the final node of the amplified signal line to generate an output voltage signal; and The output voltage signal is used to draw the input signal current from the final node of the input signal line via the feedback impedance of the transimpedance amplifier.

15. The method as described in claim 14, characterized in that, The propagation input signal is transmitted through an inductor whose two transistor gate capacitors are each coupled in series to the distributed amplifier.

16. The method as described in claim 15, characterized in that, The propagated amplified signal is transmitted through an inductor whose drain capacitors are each coupled in series with the drain capacitors of the two transistors of the distributed amplifier.

17. The method as described in claim 14, characterized in that, The buffer uses a common-drain amplifier.

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