Method for operating an automatic tuning device

Abstract

A method for operating an automatic tuning device, comprising: providing an automatic tuning device for tuning filter bandwidth; performing N tuning steps, each tuning step comprising: a second capacitor array unit performing a discharge step, a comparator performing a comparison step after the second capacitor array unit performing the discharge step, and a counter performing a counting step after the comparator performing the comparison step; after performing the N tuning steps, assigning values of first to Nth second control words output by a second control word output terminal to first to Nth first control words output by a first control word output terminal. The technical scheme of the present application automatically, accurately and quickly locks the bandwidth of the filter through the automatic tuning circuit based on the successive approximation binary search algorithm.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for operating an automatic tuning device. Background Technology

[0002] In integrated circuits, the bandwidth of filters can vary by 30% to 30% due to changes in manufacturing process, voltage, and temperature. Therefore, precise calibration of the filter bandwidth is necessary.

[0003] In existing technologies, the bandwidth of a filter can be automatically tuned using a traditional binary search algorithm.

[0004] However, in the above methods, the calibration speed of the automatic tuning device based on the traditional binary search algorithm is slow, which increases the testing cost. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an automatic tuning device and its working method, which automatically, accurately and quickly locks the bandwidth of a filter through an automatic tuning circuit based on a binary search algorithm of successive approximation (SAR).

[0006] To solve the above-mentioned technical problems, the present invention provides a method for operating an automatic tuning device, comprising: providing an automatic tuning device for tuning the bandwidth of a filter, wherein the filter includes a first capacitor array unit and a first resistor; the automatic tuning device includes: a control logic unit, the control logic unit including a waveform generator, the waveform generator including: a first logic output terminal, a second logic output terminal, a third logic output terminal, N first control word output terminals, N second control word output terminals connected to the first capacitor array unit, and a fourth logic input terminal, wherein N is a natural number greater than or equal to 1; an integrator unit, the integrator unit including: a second capacitor array unit identical to the first capacitor array unit, a second resistor identical to the first resistor, a first reference voltage output terminal, a first logic input terminal connected to the first logic output terminal, and a second logic input terminal connected to the second logic output terminal, the second capacitor array unit including: and The control logic unit includes N first control word input terminals connected one-to-one with each of the first control word output terminals, a first power input terminal connected to a power line, and a first voltage output terminal; a comparator, the comparator including: a first positive input terminal connected to the first voltage output terminal, a first negative input terminal connected to the first reference voltage output terminal, a third logic input terminal connected to the third logic output terminal, and a fourth logic output terminal connected to the fourth logic input terminal; the control logic unit further includes: a counter; performing N tuning steps, each tuning step including: a discharging step of the second capacitor array unit, a comparison step of the comparator after the discharging step of the second capacitor array unit, and a counting step of the counter after the comparison step of the comparator; after performing N tuning steps, the values ​​of the 1st to Nth second control words output by the second control word output terminal are assigned to the 1st to Nth first control words output by the first control word output terminal.

[0007] Optionally, the value of the counter is n, and the initial value of the counter is N, where n is a natural number greater than or equal to 1 and less than or equal to N.

[0008] Optionally, the method of the discharge step includes: the first logic output terminal of the waveform generator outputs a first signal; after the first logic output terminal of the waveform generator outputs the first signal, the first logic input terminal of the second capacitor array unit acquires the first signal; after the first logic input terminal of the second capacitor array unit acquires the first signal, the second capacitor array unit discharges.

[0009] Optionally, the method for the (N-n+1)th comparison step includes: outputting N first control words from the N first control word output terminals of the waveform generator, outputting a second signal from the second logic output terminal of the waveform generator, and outputting a third signal from the third logic output terminal of the waveform generator; after the N first control words are output from the N first control word output terminals of the waveform generator, the first control word input terminal of the second capacitor array unit acquires the N first control words; after the second logic output terminal of the waveform generator outputs the second signal, the second logic input terminal of the integrator acquires the second signal; after the N first control words are acquired from the first control word input terminal of the second capacitor array unit and the second logic input terminal of the integrator acquires the second signal, the first voltage output terminal of the second capacitor array unit outputs a first voltage, and the first reference voltage output terminal of the integrator outputs a first reference voltage; after the first voltage output terminal of the second capacitor array unit acquires the second signal, the first voltage output terminal of the second capacitor array unit outputs a first voltage, and the first reference voltage output terminal of the integrator outputs a first reference voltage; After the first voltage is output from the output terminal and the first reference voltage is output from the first reference voltage output terminal of the integrator, the first positive input terminal of the comparator acquires the first voltage and the first negative input terminal of the comparator acquires the first reference voltage. After the third signal is output from the third logic output terminal of the waveform generator, the third logic input terminal of the comparator acquires the third signal. After the first voltage is acquired from the first positive input terminal of the comparator, the first reference voltage is acquired from the first negative input terminal of the comparator, and the third signal is acquired from the third logic input terminal of the comparator, the first voltage and the first reference voltage are compared using the comparator, and the fourth logic output terminal of the comparator outputs a fourth signal. After the fourth signal is output from the fourth logic output terminal of the comparator, the fourth logic input terminal of the control logic unit acquires the fourth signal. According to the fourth signal, the value of the nth first control word is assigned the value of the fourth signal.

[0010] Optionally, when the value of the counter is N, the first signal, the second signal, and the third signal simultaneously output the initial signal, and the periods of the first signal, the second signal, and the third signal are all the time of each tuning step.

[0011] Optionally, in one cycle, the initial signal of the first signal is high level, and the discharge step is triggered by the first signal flipping from high level to low level; at the end of the discharge step, the first signal flips from low level to high level.

[0012] Optionally, in one cycle, the second signal is initially at a low level, and after the first signal flips from a low level to a high level, the second signal flips from a low level to a high level; after a first time, the second signal flips from a high level to a low level, where the first time is the time constant corresponding to the bandwidth required by the filter.

[0013] Optionally, in one cycle, the third signal is initially at a low level, and after the second signal flips from a high level to a low level, the third signal flips from a low level to a high level; at the end of the comparison step, the third signal flips from a high level to a low level.

[0014] Optionally, the method for the (N-n+1)th counting step includes: assigning n a value of n-1.

[0015] Optionally, each of the first control words has an initial value.

[0016] Optionally, the second capacitor array unit further includes: 1 fixed capacitor, N unit capacitors, and N switches corresponding to each unit capacitor. The capacitance value of the fixed capacitor is Cfix, the capacitance value of the i-th unit capacitor is 2i-1×Cu, each unit capacitor and the fixed capacitor are connected in parallel, each unit capacitor and each switch are connected in series, and the i-th switch is connected to the i-th first control word input terminal, where i is a natural number greater than or equal to 1 and less than or equal to N.

[0017] Optionally, the integrator unit further includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a fifth resistor, a first operational amplifier, and a first inverter. The first operational amplifier includes a second positive input terminal and a second negative input terminal. The first terminal of the third resistor is connected to a power supply line. The second terminal of the third resistor is connected to the first reference voltage output terminal and the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the second positive input terminal and the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to a ground line. The second negative input terminal is connected to the first terminal of the second resistor and the source of the first transistor. The second resistor is connected to the ground wire, the output terminal of the first operational amplifier is connected to the gate of the first transistor, the drain of the first transistor is connected to the source of the second transistor and the third transistor respectively, the drain of the second transistor is connected to the power supply line, the gate of the second transistor is connected to the output terminal of the first inverter, the gate of the third transistor is connected to the input terminal of the first inverter and the second logic input terminal respectively, the drain of the third transistor is connected to the first voltage output terminal and the drain of the fourth transistor respectively, the source of the fourth transistor is connected to the power supply line, and the gate of the fourth transistor is connected to the first logic input terminal.

[0018] Optionally, the first transistor, the second transistor, and the third transistor are all of type N, and the fourth transistor is of type P.

[0019] Optionally, the third resistor, the fourth resistor, and the fifth resistor may be of the type of fixed resistor.

[0020] Optionally, the second resistor is a variable resistor.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The automatic tuning device provided by this invention is used to tune the filter bandwidth. The automatic tuning device includes N first control word output terminals and N second control word output terminals. The automatic tuning device operates by performing N tuning steps. After these N tuning steps, the values ​​of the first to Nth second control words output by the second control word output terminals are assigned to the first to Nth first control words output by the first control word output terminals. The tuning method is a successive approximation (SAR) binary search algorithm. For the automatic tuning device with N first control word output terminals and N second control word output terminals, this invention only needs to perform N comparisons to successively determine the N first control words from the Nth to the first first control word. This allows finding the N first control words corresponding to the required filter bandwidth. By assigning the values ​​of the first to Nth second control words to the first to Nth first control words, the filter bandwidth can be quickly locked. In summary, the automatic tuning device and its working method provided by the present invention automatically, accurately and quickly lock the bandwidth of the filter through an automatic tuning circuit based on a binary search algorithm of successive approximation (SAR). Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the working method of the automatic tuning device in an embodiment of the present invention; Figures 2 to 4 This is a schematic diagram of the automatic tuning device in an embodiment of the present invention; Figure 5 This is a flowchart illustrating each tuning step. Figure 6 This is a timing diagram of the first signal, the second signal, the third signal, the first voltage, and the first reference voltage. Detailed Implementation

[0023] As described in the background section, the bandwidth of a filter can be automatically tuned using a traditional binary search algorithm. However, automatic tuning devices based on traditional binary search algorithms have slow calibration speeds, increasing testing costs.

[0024] To address the aforementioned technical problem, embodiments of the present invention provide an automatic tuning device operation method that uses an automatic tuning circuit based on a binary search algorithm of successive approximation (SAR) to automatically, accurately, and quickly lock the bandwidth of a filter.

[0025] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram illustrating the operation method of the automatic tuning device in an embodiment of the present invention. Please refer to it. Figure 1 ,include: Step S100: Provide an automatic tuning device for tuning the filter bandwidth; Step S110: Perform N tuning steps, each tuning step including: a discharge step of the second capacitor array unit, a comparison step of the comparator after the discharge step of the second capacitor array unit, and a counting step of the counter after the comparison step of the comparator. Step S120: After performing N tuning steps, the values ​​of the first to Nth second control words output by the second control word output terminal are assigned to the first to Nth first control words output by the first control word output terminal.

[0027] The following will be described in detail with reference to the accompanying drawings.

[0028] Figures 2 to 4 This is a schematic diagram of the automatic tuning device in an embodiment of the present invention.

[0029] Please refer to Figure 2An automatic tuning device is provided for tuning the bandwidth of a filter, the filter including a first capacitor array unit and a first resistor; the automatic tuning device includes: a control logic unit 100, the control logic unit 100 including a waveform generator 101, the waveform generator 101 including: a first logic output terminal A, a second logic output terminal B, a third logic output terminal C, N first control word output terminals D, N second control word output terminals F connected to the first capacitor array unit, and a fourth logic input terminal g, wherein N is a natural number greater than or equal to 1; an integrator unit 110, the integrator unit 110 including: a second capacitor array unit 111 identical to the first capacitor array unit, and a second resistor identical to the first resistor. Rn, a first reference voltage output terminal H, a first logic input terminal a connected to the first logic output terminal A, and a second logic input terminal b connected to the second logic output terminal B; the second capacitor array unit 111 includes: N first control word input terminals d connected to each of the first control word output terminals D, a first power input terminal i connected to the power line Vdd, and a first voltage output terminal E; comparator 120 includes: a first positive input terminal e connected to the first voltage output terminal E, a first negative input terminal h connected to the first reference voltage output terminal H, a third logic input terminal c connected to the third logic output terminal C, and a fourth logic output terminal G connected to the fourth logic input terminal g.

[0030] The waveform generator 101 functions to: discharge the second capacitor array unit 111 using a signal output from the first logic output terminal A; charge the second capacitor array unit 111 using a signal output from the second logic output terminal B; provide the power supply voltage for the comparator 120 using a signal output from the third logic output terminal C; adjust the capacitance value of the second capacitor array unit 111 using signals output from the N first control word output terminals D; and adjust the capacitance value of the first capacitor array unit of the filter using signals output from the N second control word output terminals F.

[0031] The number N of the first control word output terminal D and the second control word output terminal F represents the precision with which the automatic tuning device adjusts the bandwidth of the filter; the larger N is, the higher the precision with which the automatic tuning device adjusts the bandwidth of the filter. N is a natural number greater than or equal to 1; in this embodiment, N = 5.

[0032] Since the second capacitor array unit 111 is the same as the first capacitor array unit of the filter, and the signals output by the N first control word output terminals D adjust the capacitance value of the second capacitor array unit 111, and the signals output by the N second control word output terminals F adjust the capacitance value of the first capacitor array unit of the filter, therefore, as long as the signals output by the N first control word output terminals D are assigned to the signals output by the N second control word output terminals F, it is equivalent to adjusting the capacitance value of the first capacitor array unit of the filter to be the same as the capacitance value of the second capacitor array unit 111. Thus, by adjusting the signals output by the N first control word output terminals D, the capacitance value of the first capacitor array unit of the filter can be adjusted.

[0033] Please continue to refer to this. Figure 2 The control logic unit 100 further includes a counter 102, the value of which is n, and the initial value of which is N, wherein n is a natural number greater than or equal to 1 and less than or equal to N.

[0034] The counter 102 is used to control the waveform generator 101 to output signals N times from the first logic output terminal A, the second logic output terminal B, and the third logic output terminal C. In this embodiment, N=5.

[0035] In this embodiment, N=5, and the initial value of the counter 102 is 5.

[0036] Figure 3 This is a schematic diagram of the structure of the second capacitor array unit in an embodiment of the present invention.

[0037] Please refer to Figure 3 The second capacitor array unit 111 further includes: one fixed capacitor C0 and N unit capacitors C i , and each of the unit capacitors C i The corresponding N switches b i The capacitance value of the fixed capacitor C0 is Cfix, and the capacitance value of the i-th unit capacitor C i The capacitance value is 2 i-1 ×Cu, the unit capacitors C of each unit i The fixed capacitor C0 is connected in parallel with each of the unit capacitors C. i With each of the aforementioned switches b i In series, the i-th switch b i It is connected to the i-th input terminal d of the first control word, where i is a natural number greater than or equal to 1 and less than or equal to N.

[0038] When the signal output by the i-th first control word output terminal D is high, the switch b iClosed; when the signal output by the i-th first control word output terminal D is low, the switch b i Open.

[0039] The capacitance value of the second capacitor array unit 111 is Cbank = Cfix + m × Cu, where m is greater than or equal to 0 and less than or equal to 2. i -1 is a natural number.

[0040] In this embodiment, N=5, and the capacitance value of the second capacitor array unit 111 is Cbank=Cfix+m×Cu, where m is a natural number greater than or equal to 0 and less than or equal to 31.

[0041] Since the second capacitor array unit 111 is the same as the first capacitor array unit of the filter, and the signals output by the N first control word output terminals D are controlled by switch b i The capacitance value Cbank of the second capacitor array unit 111 is adjusted by the signals output by the N second control word output terminals F, and the capacitance value of the first capacitor array unit of the filter is adjusted by the signals output by the N first control word output terminals D. Therefore, as long as the signals output by the N first control word output terminals D are assigned to the signals output by the N second control word output terminals F, it is equivalent to adjusting the capacitance value of the first capacitor array unit of the filter to be the same as the capacitance value of the second capacitor array unit 111.

[0042] Figure 4 This is a circuit diagram of the automatic tuning device in an embodiment of the present invention.

[0043] Please refer to Figure 4The integrator unit 110 further includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a third resistor Rm, a fourth resistor Rk, a fifth resistor Rp, a first operational amplifier 112, and a first inverter 113. The first operational amplifier 112 includes: a second positive input terminal j and a second negative input terminal k. The first terminal of the third resistor Rm is connected to a power supply line. The second terminal of the third resistor Rm is connected to the first reference voltage output terminal H and the first terminal of the fourth resistor Rk. The second terminal of the fourth resistor Rk is connected to the second positive input terminal j and the first terminal of the fifth resistor Rp. The second terminal of the fifth resistor Rp is connected to a ground line. The second negative input terminal k is connected to the first terminal of the second resistor Rn and the first transistor M1. The source of transistor M1 is connected to the ground wire, the second end of the second resistor Rn is connected to the ground wire, the output terminal of the first operational amplifier 112 is connected to the gate of the first transistor M1, the drain of the first transistor M1 is connected to the source of the second transistor M2 and the third transistor M3 respectively, the drain of the second transistor M2 is connected to the power supply line, the gate of the second transistor M2 is connected to the output terminal of the first inverter 113, the gate of the third transistor M3 is connected to the input terminal of the first inverter 113 and the second logic input terminal b respectively, the drain of the third transistor M3 is connected to the first voltage output terminal E and the drain of the fourth transistor M4 respectively, the source of the fourth transistor M4 is connected to the power supply line, and the gate of the fourth transistor M4 is connected to the first logic input terminal a.

[0044] The first operational amplifier 112 serves as a voltage buffer.

[0045] The function of the first inverter 113 is that when the signal output from the second logic output terminal of the waveform generator 101 is low, the drain of the first transistor M1 has a power supply voltage Vdd.

[0046] In this embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 are all of type N, and the fourth transistor M4 is of type P.

[0047] In this embodiment, the third resistor Rm, the fourth resistor Rk, and the fifth resistor Rp are of the following types: fixed resistors, and the second resistor Rn is of the following type: variable resistor.

[0048] Execute step S110 and perform N tuning steps.

[0049] In this embodiment, N=5, and 5 tuning steps are performed.

[0050] The method for tuning step S110 is a successive approximation (SAR) binary search algorithm. For the automatic tuning device with N first control word output terminals and N second control word output terminals, compared to an automatic tuning device based on a traditional binary algorithm, it requires 2... N-1 Next to 2 N The bandwidth of the filter can only be locked by N comparisons. The technical solution of the present invention only needs to perform N comparisons to determine the signal output from the Nth first control word output terminal to the first first control word output terminal. This will find the N first control word output terminals corresponding to the required filter bandwidth. By assigning the signals output from the first to the Nth second control word output terminals to the signals output from the first to the Nth first control word output terminals, the filter bandwidth can be locked quickly.

[0051] In this embodiment, N=5. The automatic tuning device only needs to go through 5 tuning steps to successively determine the signals output from the 5th first control word output terminal to the 1st first control word output terminal. This allows it to find the signals output from the 5 first control word output terminals corresponding to the bandwidth of the required filter. Then, the signals from the 1st to 5th second control word output terminals are assigned the values ​​of the signals output from the 1st to 5th first control word output terminals. This enables the rapid locking of the filter bandwidth. Compared to the automatic tuning device based on the traditional binary algorithm, which requires 16 to 32 comparisons to lock the filter bandwidth, the present invention only requires 5 comparisons to lock the filter bandwidth, thus improving the speed of locking the filter bandwidth.

[0052] In this embodiment, please refer to Figure 5 , Figure 5 A flowchart illustrating each tuning step, including: Step S111, the second capacitor array unit discharge step; Step S112, the comparator comparison step after the discharge step of the second capacitor array unit; Step S113: After the comparator comparison step, the counter performs a counting step.

[0053] The following is a detailed description in conjunction with the accompanying drawings.

[0054] Please continue to refer to this. Figure 2 and Figure 4The method of the discharge step S111 includes: the first logic output terminal A of the waveform generator 101 outputs a first signal Clk_rst; after the first logic output terminal A of the waveform generator 101 outputs the first signal Clk_rst, the first logic input terminal a of the second capacitor array unit 111 acquires the first signal Clk_rst; after the first logic input terminal a of the second capacitor array unit 111 acquires the first signal Clk_rst, the second capacitor array unit 111 discharges.

[0055] When the first signal Clk_rst is low, the fourth transistor M4, being a P-type transistor, is effectively turned on, thus discharging the second capacitor array unit 111. The function of the discharge step S111 is to initialize the second capacitor array unit 111 through discharge before the comparison step S112.

[0056] Please continue to refer to this. Figure 2 and Figure 4The method for the N-n+1th comparison step S112 includes: the N first control word output terminals D of the waveform generator 101 output N first control words, the second logic output terminal B of the waveform generator 101 outputs a second signal Clk_int, and the third logic output terminal C of the waveform generator 101 outputs a third signal Clk_cmp; after the N first control words are output from the N first control word output terminals D of the waveform generator 101, the first control word input terminal d of the second capacitor array unit 111 acquires the N first control words; and the second logic output terminal B of the waveform generator 101 outputs... After the second signal Clk_int, the second logic input terminal b of the integrator 110 acquires the second signal Clk_int; after the N first control words are acquired at the first control word input terminal d of the second capacitor array unit 111, and the second logic input terminal b of the integrator 110 acquires the second signal Clk_int, the first voltage output terminal E of the second capacitor array unit 111 outputs the first voltage Vc(t), and the first reference voltage output terminal H of the integrator 110 outputs the first reference voltage Vref1; the first voltage output terminal E of the second capacitor array unit 111 outputs the first voltage Vc(t). After a voltage Vc(t) is obtained and the first reference voltage Vref1 is output from the first reference voltage output terminal H of the integrator 110, the first positive input terminal e of the comparator 120 obtains the first voltage Vc(t), and the first negative input terminal h of the comparator 120 obtains the first reference voltage Vref1; after the third logic output terminal C of the waveform generator 101 outputs the third signal Clk_cmp, the third logic input terminal c of the comparator 120 obtains the third signal Clk_cmp; the first voltage Vc(t) is obtained from the first positive input terminal e of the comparator 120, and the first reference voltage Vref1 is output from the first reference voltage output terminal H of the integrator 110, the first reference voltage Vref1 is obtained from the first reference voltage output terminal H of the integrator 120, and the first reference voltage Vref1 is output from the first reference voltage output terminal H of the integrator 110, the first reference voltage Vref1 is obtained from the first reference voltage output terminal H of the integrator 120, and the first reference voltage Vref1 is obtained from the first reference voltage output terminal H of the integrator 12 ... After the first negative input terminal h of 0 obtains the first reference voltage Vref1 and the third logic input terminal c of comparator 120 obtains the third signal Clk_cmp, the comparator is used to compare the first voltage Vc(t) and the first reference voltage Vref1. The fourth logic output terminal G of comparator 120 outputs the fourth signal. After the fourth logic output terminal G of comparator 120 outputs the fourth signal, the fourth logic input terminal g of control logic unit 100 obtains the fourth signal. According to the fourth signal, the value of the nth first control word is assigned the value of the fourth signal.

[0057] Before step S110, each of the first control words has an initial value.

[0058] Please continue to refer to this. Figure 4The voltage of the input power line is Vdd, the voltage of the second positive input terminal j is Vref2=(Rp / (Rm+Rk+Rp))×Vdd, and the voltage of the first reference voltage output terminal H is Vref1= ((Rk+Rp) / (Rm+Rk+Rp))×Vdd. That is, the voltage of the first positive input terminal e of the comparator 120 is Vref1= ((Rk+Rp) / (Rm+Rk+Rp))×Vdd.

[0059] Due to the function of the first operational amplifier 112, the voltage at the first terminal of the second resistor Rn is Vref2, therefore the current Id flowing through the second resistor Rn is Id = Vref2 / Rn. When the output voltage of the second logic output terminal B of the waveform generator 101 is high, the third transistor M3 and the first transistor M1 are turned on, and the current Id flowing through the second resistor Rn charges the second capacitor array unit 111.

[0060] Since the relationship between the voltage Vc(t) output from the first voltage output terminal of the second capacitor array unit 111 and the charging time t is Vc(t) = Vdd - Id / Cbank × t, therefore Vc(t) = Vdd - Vref2 / (Rn × Cbank) × t. According to the relationship between Vref1, Vref2 and Vdd, when Vc(t) = Vref1, Rn × Cbank = t.

[0061] The bandwidth of the filter has a corresponding time constant, which is the capacitance value of the first capacitor array unit multiplied by the resistance value of the first resistor. Since the second capacitor array unit 111 is the same as the first array capacitor unit, and the second resistor Rn is the same as the first resistor, the time constant is also equal to Rn × Cbank, that is, the time constant is also equal to the charging time t. Therefore, as long as the charging time t is set as the time constant corresponding to the bandwidth of the desired filter, when Vc(t) = Vref1, the capacitance value Cbank of the second capacitor array unit 111 is the capacitance value of the first capacitor array unit of the filter corresponding to the bandwidth of the desired filter.

[0062] Please continue to refer to this. Figure 4 The comparator 120 is used to find the first voltage Vc(t) that is closest to the first reference voltage Vref1 by comparing the first voltage Vc(t) with the first reference voltage Vref1 N times, thereby obtaining the signals output by the N first control word output terminals D corresponding to the first voltage Vc(t).

[0063] The function of the comparison step S112 is to find the first voltage Vc(t) that is closest to the first reference voltage Vref1 through N comparisons, thereby determining the required capacitance value Cbank of the second capacitor array unit 111, that is, finding the capacitance value of the first capacitor array unit of the filter corresponding to the bandwidth of the required filter.

[0064] Figure 6 This is a timing diagram of the first signal, the second signal, the third signal, the first voltage, and the first reference voltage.

[0065] Please refer to Figure 6 When the value of the counter is N, the first signal Clk_rst, the second signal Clk_int, and the third signal Clk_cmp simultaneously output the initial signal, and the periods of the first signal Clk_rst, the second signal Clk_int, and the third signal Clk_cmp are all the time Tclk of each tuning step S110.

[0066] Please continue to refer to this. Figure 6 In one cycle Tclk, the initial signal of the first signal Clk_rst is high level, and the discharge step S111 is triggered by the first signal Clk_rst flipping from high level to low level; at the end of the discharge step S111, the first signal Clk_rst flips from low level to high level.

[0067] When the first signal Clk_rst is low, the function of the second signal Clk_rst is to discharge the second capacitor array unit 111.

[0068] Please continue to refer to this. Figure 6 In one cycle Tclk, the second signal Clk_int is initially at a low level. After the first signal Clk_rst flips from a low level to a high level, the second signal Clk_int flips from a low level to a high level. After a first time T, the second signal Clk_int flips from a high level to a low level. The first time T is the time constant corresponding to the bandwidth required by the filter.

[0069] When the second signal Clk_int is high, its function is to charge the second capacitor array unit 111. The first time T is the charging time t.

[0070] Please continue to refer to this. Figure 6In one cycle Tclk, the third signal Clk_cmp is initially at a low level. After the second signal Clk_int flips from a high level to a low level, the third signal Clk_cmp flips from a low level to a high level. At the end of comparison step S112, the third signal Clk_cmp flips from a high level to a low level.

[0071] When the third signal Clk_cmp is high, its function is to provide power supply voltage to the comparator 120. When the first voltage Vc(t) is greater than the first reference voltage Vref1, the fourth signal output by the fourth logic output terminal G of the comparator 120 is high; when the first voltage Vc(t) is less than the first reference voltage Vref1, the fourth signal output by the fourth logic output terminal G of the comparator 120 is low.

[0072] The counting step S113 is performed, and the method for the (N-n+1)th counting step includes: assigning the value of n to n-1.

[0073] The function of the counting step S113 is to control the number of cycles of the tuning step S110 to be N, and to ensure that the first control word determined in the nth tuning step S110 is the nth first control word. Since the value n of the counter decreases by 1 in each tuning step S110, the first control word is determined one by one from the nth to the first.

[0074] Execute step S120 to perform the assignment step, so that the values ​​of the first to Nth second control words output by the second control word output terminal F are assigned to the first to Nth first control words output by the first control word output terminal D.

[0075] The assignment step is to make the values ​​of the N second control words equal to the N first control words of the Nth tuning step, so that the first capacitor array unit of the filter can be adjusted to the same capacitance value as the second capacitor array unit.

[0076] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for operating an automatic tuning device, characterized in that, include: An automatic tuning device is provided for tuning the bandwidth of a filter, the filter including a first capacitor array unit and a first resistor; The automatic tuning device includes: a control logic unit, which includes a waveform generator comprising: a first logic output terminal, a second logic output terminal, a third logic output terminal, N1 first control word output terminals, N1 second control word output terminals connected to the first capacitor array unit, and a fourth logic input terminal, wherein N1 is a natural number greater than or equal to 1; and an integrator unit, which includes: a second capacitor array unit identical to the first capacitor array unit, a second resistor identical to the first resistor, a first reference voltage output terminal, and a first reference voltage output terminal connected to the first logic output terminal. The second capacitor array unit includes: N1 first control word input terminals connected to each of the first control word output terminals, a first power input terminal connected to a power line, and a first voltage output terminal; a comparator, the comparator including: a first positive input terminal connected to the first voltage output terminal, a first negative input terminal connected to the first reference voltage output terminal, a third logic input terminal connected to the third logic output terminal, and a fourth logic output terminal connected to the fourth logic input terminal; the control logic unit further includes: a counter; The tuning process is performed N2 times, each tuning step including: a discharge step of the second capacitor array unit, a comparison step of the comparator after the discharge step of the second capacitor array unit, and a counting step of the counter after the comparison step of the comparator. After performing N2 tuning steps, the values ​​of the first to N1st second control words output by the second control word output terminal are assigned to the first to N1st first control words output by the first control word output terminal; The method for the N2-n+1th comparison step includes: The waveform generator outputs N1 first control words from its N1 first control word output terminals, outputs a second signal from its second logic output terminal, and outputs a third signal from its third logic output terminal. After the waveform generator outputs N1 first control words from its N1 first control word output terminals, the second control word input terminal of the second capacitor array unit acquires the N1 first control words. After the waveform generator outputs the second signal from its second logic output terminal, the integrator's second logic input terminal acquires the second signal. After the second capacitor array unit acquires the N1 first control words from its first control word input terminal and the integrator acquires the second signal from its second logic input terminal, the second capacitor array unit outputs a first voltage from its first voltage output terminal and the integrator's first reference voltage output terminal outputs a first reference voltage. Wherein, the value of the counter is n, the initial value of the counter is N1, where n is a natural number greater than or equal to 1 and less than or equal to N1, N1 is the number of the first control word output terminal and the second control word output terminal, and N2 is the number of cycles of the tuning step.

2. The operating method of the automatic tuning device as described in claim 1, characterized in that, The method of the discharge step includes: the first logic output terminal of the waveform generator outputs a first signal; after the first logic output terminal of the waveform generator outputs the first signal, the first logic input terminal of the second capacitor array unit acquires the first signal; after the first logic input terminal of the second capacitor array unit acquires the first signal, the second capacitor array unit discharges.

3. The operating method of the automatic tuning device as described in claim 2, characterized in that, The method for the N2-n+1th comparison step further includes: after outputting a first voltage at the first voltage output terminal of the second capacitor array unit and outputting a first reference voltage at the first reference voltage output terminal of the integrator, the first positive input terminal of the comparator acquires the first voltage and the first negative input terminal of the comparator acquires the first reference voltage; after outputting a third signal at the third logic output terminal of the waveform generator, the third logic input terminal of the comparator acquires the third signal; after acquiring the first voltage at the first positive input terminal of the comparator, the first reference voltage at the first negative input terminal of the comparator, and the third signal at the third logic input terminal of the comparator, the comparator is used to compare the first voltage and the first reference voltage, and the fourth logic output terminal of the comparator outputs a fourth signal; after outputting the fourth signal at the fourth logic output terminal of the comparator, the fourth logic input terminal of the control logic unit acquires the fourth signal; according to the fourth signal, the value of the nth first control word is assigned the value of the fourth signal.

4. The operating method of the automatic tuning device as described in claim 3, characterized in that, When the value of the counter is N, the first signal, the second signal, and the third signal simultaneously output the initial signal, and the periods of the first signal, the second signal, and the third signal are all the time of each tuning step.

5. The operating method of the automatic tuning device as described in claim 4, characterized in that, In one cycle, the first signal is initially at a high level, and the discharge step is triggered by the first signal flipping from a high level to a low level; at the end of the discharge step, the first signal flips from a low level to a high level.

6. The operating method of the automatic tuning device as described in claim 4, characterized in that, In one cycle, the second signal is initially at a low level. After the first signal transitions from a low level to a high level, the second signal transitions from a low level to a high level. After a first time interval, the second signal transitions from a high level to a low level. The first time interval is the time constant corresponding to the bandwidth required by the filter.

7. The operating method of the automatic tuning device as described in claim 4, characterized in that, In one cycle, the third signal is initially at a low level, and after the second signal flips from a high level to a low level, the third signal flips from a low level to a high level; at the end of the comparison step, the third signal flips from a high level to a low level.

8. The method of operating the automatic tuning device as described in claim 1, characterized in that, The method for the N2-n+1th counting step includes: assigning n the value of n-1.

9. The method of operating the automatic tuning device as described in claim 1, characterized in that, Each of the first control words has an initial value.

10. The method of operating the automatic tuning device as described in claim 1, characterized in that, The second capacitor array unit further includes: one fixed capacitor, N1 unit capacitors, and N1 switches corresponding to each unit capacitor. The capacitance value of the fixed capacitor is Cfix, and the capacitance value of the i-th unit capacitor is 2. i-1 ×Cu, each of the unit capacitors and the fixed capacitor are connected in parallel, each of the unit capacitors is connected in series with each of the switches, and the i-th switch is connected to the i-th first control word input terminal, where i is a natural number greater than or equal to 1 and less than or equal to N1.

11. The method of operating the automatic tuning device as described in claim 1, characterized in that, The integrator unit further includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a fifth resistor, a first operational amplifier, and a first inverter. The first operational amplifier includes a second positive input terminal and a second negative input terminal. The first terminal of the third resistor is connected to a power supply line. The second terminal of the third resistor is connected to the first reference voltage output terminal and the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the second positive input terminal and the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to a ground wire. The second negative input terminal is connected to the first terminal of the second resistor and the source of the first transistor. The second end of the second resistor is connected to the ground line. The output terminal of the first operational amplifier is connected to the gate of the first transistor. The drain of the first transistor is connected to the source of the second transistor and the third transistor, respectively. The drain of the second transistor is connected to the power supply line. The gate of the second transistor is connected to the output terminal of the first inverter. The gate of the third transistor is connected to the input terminal of the first inverter and the second logic input terminal, respectively. The drain of the third transistor is connected to the first voltage output terminal and the drain of the fourth transistor, respectively. The source of the fourth transistor is connected to the power supply line. The gate of the fourth transistor is connected to the first logic input terminal.

12. The method of operating the automatic tuning device as described in claim 11, characterized in that, The first transistor, the second transistor, and the third transistor are all of type N, and the fourth transistor is of type P.

13. The method of operating the automatic tuning device as described in claim 11, characterized in that, The types of the third resistor, the fourth resistor, and the fifth resistor include: fixed resistors.

14. The method of operating the automatic tuning device as described in claim 1, characterized in that, The second resistor is a variable resistor.

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