System for designing integrated circuit device, integrated circuit device and operating method thereof

Abstract

An integrated circuit (IC) device includes a main latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the main latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input through a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input through a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit device, a system for designing an integrated circuit device, and a method for operating an integrated circuit device. Background Technology

[0002] An integrated circuit (IC) device comprises one or more semiconductor devices, representing an IC layout (also known as a "layout" or "layout diagram"). The layout is hierarchical and contains multiple modules that implement higher-level functions according to the design specifications of the semiconductor device. These modules are typically composed of combinations of cells, each representing one or more semiconductor architectures used to perform specific functions. Cells with pre-designed layouts, sometimes called standard cells, are stored in a standard cell database (hereinafter referred to as a "database" or "cell database") and can be accessed by various tools, such as electronic design automation (EDA) tools, to generate, optimize, and verify IC designs. For example, the IC design layout is generated based on the placement and routing operations of the IC design, where different circuits or cells are placed in the layout, and then routing is used to define the electrical connections within the circuits or cells. Summary of the Invention

[0003] Some embodiments of this disclosure include an integrated circuit device comprising a main latch circuit including a first clock input and a data output, a secondary latch circuit including a second clock input and a data input, the data input being electrically coupled to the data output of the main latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input via a first electrical connection having a first time delay, the first time delay being between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input via a second electrical connection having a second time delay, the second time delay being between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

[0004] Some embodiments of this disclosure include a system for designing an integrated circuit device comprising at least one processor and at least one memory storing computer program code for one or more programs. When the at least one processor executes the computer program code stored in the at least one memory, the computer program code and the at least one processor cause the system to execute and generate a layout of an integrated circuit device, the layout being stored in a non-transitory computer-readable medium. Generating the layout includes: placing a main latch circuit, a secondary latch circuit, and a clock circuit in the layout, and performing wiring to electrically couple the clock circuit to the main latch circuit and the secondary latch circuit. In the wiring, a first electrical connection wiring extends from the clock circuit to the main latch circuit, the first electrical connection being longer than a second electrical connection, and the second electrical connection wiring extends from the clock circuit to the secondary latch circuit.

[0005] Some embodiments of this disclosure include a method of operating an integrated circuit device comprising: supplying a clock pulse from a clock circuit to a main latch circuit and a secondary latch circuit. The method further comprises, in the main latch circuit, latching input data in response to a first edge of the clock pulse, and outputting the latched input data as intermediate data to the secondary latch circuit in response to a second edge of the clock pulse. The method further comprises, in the secondary latch circuit, outputting previously latched intermediate data as output data in response to the first edge of the clock pulse, and receiving intermediate data from the primary latch circuit in response to the second edge of the clock pulse. After the clock pulse arrives at the secondary latch circuit, the clock pulse arrives at the main latch circuit. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings and the following detailed description. It should be understood that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity.

[0007] Figure 1 This is a block diagram of an IC device according to some embodiments;

[0008] Figure 2A This is a schematic logic diagram of a flip-flop circuit according to some embodiments;

[0009] Figure 2B This is a circuit diagram of a flip-flop circuit according to some embodiments;

[0010] Figure 2C This is a schematic timing diagram of the operation of a flip-flop circuit according to some embodiments;

[0011] Figures 2D to 2F This is a circuit diagram illustrating the operation of a flip-flop circuit according to some embodiments;

[0012] Figures 3A to 3H It is a simplified schematic diagram of the layout of various circuit regions of one or more IC devices according to some embodiments;

[0013] Figure 4 This is a schematic logic diagram of a multi-bit flip-flop circuit according to some embodiments;

[0014] Figures 5A to 5B It is a simplified schematic diagram of the layout of various circuit regions of one or more IC devices according to some embodiments;

[0015] Figure 6 This is a schematic logic diagram of a flip-flop circuit according to some embodiments;

[0016] Figures 7A to 7C It is a simplified schematic diagram of the layout of various circuit regions of one or more IC devices according to some embodiments;

[0017] Figure 8A It is a circuit diagram based on some embodiments;

[0018] Figure 8B This is a schematic diagram of the layout of the units according to some embodiments;

[0019] Figure 8C This is a schematic cross-sectional view of the circuit region of an IC device according to some embodiments;

[0020] Figures 9A to 9E This is a schematic perspective view of various conductive structures configured with electrical connections for wiring clock signals according to some embodiments;

[0021] Figures 10A to 10D These are flowcharts of various methods according to some embodiments;

[0022] Figure 11 This is a block diagram of an electronic design automation (EDA) system according to some embodiments;

[0023] Figure 12 This is a block diagram of an IC device manufacturing system according to some embodiments, and the associated IC manufacturing process.

[0024] [Symbol Explanation]

[0025] 100, 800C, 1260: IC devices

[0026] 102: Mega Series

[0027] 104: Area

[0028] 200, 600: Flip-Flip Circuit

[0029] 210, 310, 610, 710, 781: Main latch circuit

[0030] 211, 221: Data Input

[0031] 212, 222: Intermediate nodes

[0032] 213, 223: Data Output

[0033] 214, 224: Data holding circuits

[0034] 216, 226: First clock input

[0035] 217, 227: Second clock input

[0036] 218, 219, 228, 229, 311-314, 321-325, 331-335, 341-345, 351-354, 361, 363, 373, 511, 513, 551-554, 711, 712, 721, 722, 731, 732, 791, 792: Electrical connections

[0037] 220, 320, 620, 720, 782: Secondary latch circuit

[0038] 230, 330, 330A, 330B, 530, 730, 783: Clock circuits

[0039] 231, 232: Clock output

[0040] 233: Clock Input

[0041] 240, 640, 740: Input circuit

[0042] 241, 242, 800A: Circuit

[0043] 243, 244: Nodes

[0044] 250: Output circuit

[0045] 260: Selection Circuit

[0046] 270: Clock Pulse

[0047] 271, 276, 276', 277: Rising Edge

[0048] 272: Descent Edge

[0049] 273: Line

[0050] 275, 275': Pulse

[0051] 300A~300H, 500A~500B, 700A~700C: Circuit Area

[0052] 301~304、820: Boundary

[0053] 305-307, 785, 786: Other circuits

[0054] 400: Multi-bit flip-flop circuit

[0055] 460: Selection Circuit

[0056] 501-504: Clock bus

[0057] 800B: Unit

[0058] 801, 802: Active Area

[0059] 803, 804: Source regions

[0060] 805, 806: Drain region

[0061] 810: Gate region

[0062] 818, 819: Dummy gate regions

[0063] 821-824: Edge

[0064] 835~837: Contact Structure

[0065] 838, 839, 901~903, 912, 913, 921~923, 926, 928, 929, 931, 943, 945, 947, 949, 951, 961~963, 966, 968: Through holes

[0066] 841–844, 905, 915, 925, 927, 930, 932, 935, 944, 946, 948, 950, 952, 965, 969, 975: Conductive patterns

[0067] 860: Substrate

[0068] 861: First side

[0069] 862: Second side

[0070] 868: Interconnection Structure

[0071] 869: Backside interconnect structure

[0072] 900A~900E: Conductive Structure

[0073] 942: Shortest Path

[0074] 1000A~1000D: Method

[0075] 1002, 1004, 1012, 1014, 1022, 1024, 1032, 1034, 1036: Operations

[0076] 1100: System

[0077] 1102: Processor

[0078] 1104: Media

[0079] 1106: Code

[0080] 1107: Unit Library

[0081] 1108: Bus

[0082] 1110: I / O Interface

[0083] 1112: Network Interface

[0084] 1114: Network

[0085] 1142: User Interface

[0086] 1200: System

[0087] 1220: Design Studio

[0088] 1222: Design Layout Diagram

[0089] 1230: Shelter Room

[0090] 1232: Data Preparation

[0091] 1244: Mask Manufacturing

[0092] 1245: Mask, Mask Group

[0093] 1250: IC fab

[0094] 1252: Manufacturing Tools

[0095] 1253: Semiconductor wafer Detailed Implementation

[0096] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements, materials, values, steps, or arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other elements, materials, values, steps, or arrangements may also be considered. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0097] Furthermore, spatially related terms used herein, such as “below,” “under,” “below,” “above,” “on,” etc., are for descriptive purposes to describe the relationship between one element or feature and another (or other) element or feature as shown in the figures. In addition to the orientations shown in the figures, these spatially related terms are intended to encompass different orientations of the apparatus during use or operation. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially related descriptors used herein should be interpreted accordingly.

[0098] A flip-flop circuit (or flip-flop) is a component of digital electronic systems such as computers or communication systems. A flip-flop circuit includes a main latch circuit (or main latch), a secondary latch circuit (or secondary latch), and a clock circuit. The main latch circuit stores (or latches) its data input and transmits the stored (or latched) data from its data output to the secondary latch circuit's data input. The secondary latch circuit stores (or latches) the data received from the main latch circuit and transmits the stored (or latched) data to its output. The clock circuit controls the timing of the main latch circuit and the secondary latch circuit.

[0099] In some embodiments, the time delay from the clock circuit to the main latch circuit is increased to be greater than the time delay from the clock circuit to the sub-latch circuit. In at least one embodiment, with a larger time delay from the clock circuit to the main latch circuit, the setup time of the flip-flop circuit is reduced, resulting in an increase in flip-flop speed, for example, the flip-flop circuit will operate faster. In some embodiments, the flip-flop speed is increased by 1 to 10%. In one or more embodiments, the flip-flop speed is increased by 5 to 15%. In some embodiments, by placing the main latch circuit, sub-latch circuit, and clock circuit in a specific physical arrangement in the IC layout and / or by performing routing in the main latch circuit, sub-latch circuit, and clock circuit with a specific wiring length relationship, the time delay from the clock circuit to the main latch circuit may be increased to be greater than the time delay from the clock circuit to the sub-latch circuit, thus improving the performance of the IC device manufactured based on the layout.

[0100] Figure 1 This is a block diagram of an IC device 100 according to some embodiments.

[0101] exist Figure 1 In this embodiment, IC device 100 includes a macro 102 and other objects. In some embodiments, macro 102 includes one or more of the following: memory, electrical grid, one or more cells, inverters, latches, buffers, and / or any other type of circuit arrangement that can be digitally represented in a cell library. In some embodiments, macro 102 is understood in a context similar to the architectural hierarchy of modular programming, where subprograms / programs are called by a main program (or by other subprograms) to perform a given computational function. In this case, IC device 100 uses macro 102 to perform one or more given functions. Accordingly, in this case and in terms of the architectural hierarchy, IC device 100 is similar to a main program and macro 102 is similar to a subprogram / program. In some embodiments, macro 102 is a soft macro. In some embodiments, macro 102 is a hard macro. In some embodiments, macro 102 is a soft macro described digitally in register-transfer level (RTL) code. In some embodiments, composition, placement, and routing have not yet been performed on macro 102, allowing the soft macro to be composed, placed, and routed to multiple process nodes. In some embodiments, macro 102 is a hard macro digitally described in a binary file format (e.g., Graphic Database System II (GDSII) streaming format), wherein the binary file format represents the planar geometry, text labels, other information, etc., of one or more layout diagrams of macro 102 in a hierarchical manner. In some embodiments, composition, placement, and routing have been performed on macro 102, making the hard macro specific to a particular process node.

[0102] Macro 102 includes region 104, which contains at least one flip-flop circuit. In some embodiments, region 104 further includes one or more other circuits or units. Examples of circuits or units in region 104 include, but are not limited to, logic gate units or memory units. In some embodiments, examples of logic gate units include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, AND-OR-NOT (AOI), OR-NAND-NOT (OAI), MUX, flip-flop, buffer, latch, delay, or clock unit, etc. In some embodiments, examples of memory units include, but are not limited to, static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), or read-only memory (ROM), etc. In some embodiments, the unit includes one or more active or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, and planar MOS transistors with raised source / drain. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors. In some embodiments, region 104 includes a semiconductor substrate on which circuitry is formed in front-end-of-line (FEOL) fabrication. Furthermore, above and / or below the semiconductor substrate, region 104 includes various metal layers stacked above and / or below an insulating layer in back-end-of-line (BEOL) fabrication. The BEOL provides wiring for circuitry of IC device 100, which includes macrogroup 102 and region 104. The metal layers include conductive patterns extending along the X-axis or a Y-axis transverse to the X-axis. The X-axis is sometimes referred to herein as a first direction or a second direction, and the Y-axis is sometimes referred to herein as a second direction or a first direction. In some embodiments, the first direction is perpendicular to the second direction.

[0103] Figure 2A This is a schematic logic diagram of a flip-flop circuit 200 according to some embodiments. According to some embodiments, although the details given herein... Figure 2A and one The description of the other figures is for a flip-flop circuit, including a main latch circuit, a secondary latch circuit, and a clock circuit, and any circuit that can be configured to have a time delay from the clock circuit to the main latch circuit greater than the time delay from the clock circuit to the secondary latch circuit to improve performance is within the scope of the various embodiments. Furthermore, regarding Figure 2AThe specific flip-flop circuit configuration described is for illustrative purposes only. Other flip-flop circuit configurations are within the scope of various embodiments. For example, regarding... Figure 6 The described alternative flip-flop circuit configuration.

[0104] exist Figure 2A In this circuit, the flip-flop circuit 200 includes a main latch circuit 210, a secondary latch circuit 220, a clock circuit 230, an input circuit 240, and an output circuit 250. In some embodiments, the input circuit 240 and / or the output circuit 250 are omitted.

[0105] The main latch circuit 210 (referred to as "main latch" in the figure) includes transmission gates TG1m and TG2m, inverters INV1m and INV2m, a data input 211, an intermediate node 212, and a data output 213. Transmission gate TG1m is coupled between the data input 211 and the intermediate node 212. Transmission gate TG2m is coupled between the intermediate node 212 and the inverter INV2m. Inverter INV1m has an input coupled to the intermediate node 212 and an output coupled to the data output 213 of the main latch circuit 210. Inverter INV2m has an input coupled to the data output 213 of the main latch circuit 210. Transmission gate TG2m and inverters INV1m and INV2m are configured together at the intermediate node 212 as a data holding circuit 214 coupled to transmission gate TG1m. The main latch circuit 210 further includes a first clock input 216, which is electrically coupled via a connection 218 to receive a first clock signal clkb from the clock output 231 of the clock circuit 230, and is also coupled to the corresponding gates of the transmission gates TG1m and TG2m. The main latch circuit 210 further includes a second clock input 217, which is electrically coupled via a connection 219 to receive a second clock signal clkbb from the clock output 232 of the clock circuit 230, and is also coupled to the corresponding other gates of the transmission gates TG1m and TG2m.

[0106] The secondary latch circuit 220 (referred to as "secondary latch" in the figure) includes transmission gates TG1s and TG2s, inverters INV1s and INV2s, a data input 221, an intermediate node 222, and a data output 223. The data input 221 of the secondary latch circuit 220 is coupled to the data output 213 of the primary latch circuit 210. Transmission gate TG1s is coupled between the data input 221 and the intermediate node 222. Transmission gate TG2s is coupled between the intermediate node 222 and the inverters INV2s. Inverters INV1s have an input coupled to the intermediate node 222 and an output coupled to the data output 223 of the secondary latch circuit 220. Inverters INV2s have an input coupled to the data output 223 of the secondary latch circuit 220. The transmission gates TG2s and inverters INV1s and INV2s are configured together at intermediate node 222 as a data holding circuit 224 coupled to the transmission gate TG1s. The secondary latch circuit 220 further includes a first clock input 226, which is electrically coupled via connection 228 to receive a first clock signal clkb from the clock output 231 of the clock circuit 230, and is coupled to the corresponding gates of the transmission gates TG1s and TG2s. The secondary latch circuit 220 further includes a second clock input 227, which is electrically coupled via connection 229 to receive a second clock signal clkbb from the clock output 232 of the clock circuit 230, and is coupled to the corresponding other gates of the transmission gates TG1s and TG2s. In at least one embodiment, the primary latch circuit 210 and the secondary latch circuit 220 have the same and identical configuration. In at least one embodiment, electrical connection 218 has a larger physical length and / or a larger time delay than electrical connection 228, and / or electrical connection 219 has a larger physical length and / or a larger time delay than electrical connection 229.

[0107] Clock circuit 230 (denoted as "CK" in the figure) includes inverters INVA and INVB, clock output 231, clock output 232, and clock input 233. The input of inverter INVA is coupled to clock input 233 to receive the input clock signal Clock supplied to clock input 233. The output of inverter INVA is coupled to clock output 231. Inverter INVA is used to invert the input clock signal Clock to output a first clock signal clkb at clock output 231. Clock output 231 is coupled to the first clock inputs 216 and 226 of the main latch circuit 210 and the secondary latch circuit 220 to supply the first clock signal clkb to the main latch circuit 210 and the secondary latch circuit 220. The input of inverter INVB is coupled to clock output 231 to receive the first clock signal clkb. The output of inverter INVB is coupled to clock output 232. The inverter INVB inverts the first clock signal clkb to output a second clock signal clkbb at clock output 232. In other words, the second clock signal clkbb is inverted compared to the first clock signal clkb. Clock output 232 is coupled to the second clock inputs 217 and 227 of the main latch circuit 210 and the secondary latch circuit 220 to supply the second clock signal clkbb to the main latch circuit 210 and the secondary latch circuit 220.

[0108] Input circuitry 240 includes a multiplexer MUX. The multiplexer MUX includes a data input D, a scan input Si, a scan enable input So, and an output (not shown) coupled to a data input 211 of the main latch circuitry 210. In some embodiments, data is output from the scan input Si to the main latch circuitry 210 in response to a first logic value at the scan enable input So. Data is output from the data input D to the main latch circuitry 210 in response to a different second logic value at the scan enable input So. The configuration of input circuitry 240 described is illustrative. Other configurations for input circuitry 240 are within the scope of various embodiments. In one example, input circuitry 240 includes an inverter instead of a multiplexer MUX. In another example, input circuitry 240 includes a NAND gate instead of a multiplexer MUX. In at least one embodiment, input circuitry 240 is omitted, for example, by directly supplying input data for the flip-flop circuitry 200 to the data input 211 of the main latch circuitry 210.

[0109] Output circuit 250 includes an inverter INVo, which has an input coupled to a data output 223 of the sub-latch circuit 220 and an output coupled to an output Q of the flip-flop circuit 200. The configuration of output circuit 250 described is illustrative. Other configurations for output circuit 250 are within the scope of various embodiments. In at least one embodiment, output circuit 250 is omitted, for example, the data output 223 of the sub-latch circuit 220 is directly coupled to the output Q of the flip-flop circuit 200.

[0110] The main latch circuit 210 and the secondary latch circuit 220 operate according to clock signals clkb and clkbb. In some embodiments, when the first clock signal clkb is at a logic high level and the second clock signal clkbb is at a logic low level, transmission gates TG1m and TG2s are turned on and transmission gates TG2m and TG1s are turned off. The turned-on transmission gate TG1m transmits input data to intermediate node 212 at data input 211, and because transmission gate TG2m is turned off, it stores (or latches) the input data as intermediate data through data holding circuit 214. The turned-on transmission gate TG2s transmits the intermediate data previously stored (or latched) by data holding circuit 224 to output Q during the preceding clock cycle.

[0111] When the first clock signal clkb is at a logic high level and the second clock signal clkbb is at a logic low level, transmission gates TG1m and TG2s are turned off, and transmission gates TG2m and TG1s are turned on. The turned-on transmission gates TG2m and TG1s transmit the intermediate data stored (or latched) by the data holding circuit 214 to the intermediate node 222 of the sub-latch circuit 220 through data output 213 and data input 221. Transmission gate TG2s is turned off, and the intermediate data stored (or latched) by the data holding circuit 224 is used to output to output Q in subsequent clock cycles.

[0112] exist Figure 2A In the example configuration, flip-flop circuit 200 is a D flip-flop. Other flip-flop configurations, including but not limited to SR flip-flops, JK flip-flops, delayed flip-flops, or inverting flip-flops, are within the scope of various embodiments. In some embodiments, flip-flop circuit 200 and / or any other flip-flop circuit described herein are included in an IC device to manufacture one or more circuits including, but not limited to, memories, shift registers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), counters, clocks, registers, or cache memory for temporarily storing information in a microprocessor or central processing unit.

[0113] Figure 2B This is a circuit diagram of a flip-flop circuit 200 according to some embodiments. Figure 2B The circuit diagram in is Figure 2A Examples of circuit implementations of the logic diagram are provided. Other circuit configurations are within the scope of various embodiments. Figure 2A , Figure 2B Corresponding components are labeled with the same reference numerals. For simplicity, unless otherwise specified, signals and nodes that generate / supply signals to / from are represented by the same reference numerals. For example, the signal in node ml_b is referred to as signal ml_b.

[0114] exist Figure 2BIn the circuit, the flip-flop circuit 200 includes inputs D, SI, and SE, a clock input CP, and an output Q. Inputs D, SI, and SE correspond to the data input D, scan input Si, and scan enable input So of the multiplexer MUX. The clock input CP corresponds to clock input 233.

[0115] The main latch circuit corresponding to the main latch circuit 210 (not shown in) Figure 2B The circuit (C) includes transmission gates TG1m and TG2m and inverters INV1m and INV2m. Transmission gate TG1m includes a pair of transistors T1 and T2 with corresponding gates coupled to receive a second clock signal clkbb and a first clock signal clkb. Transistors T1 and T2 are of opposite types. For example, transistor T1 is a p-type transistor, and transistor T2 is an n-type transistor. In some embodiments, transistor T1 is a p-channel metal-oxide-semiconductor (PMOS) transistor, and transistor T2 is an n-channel metal-oxide-semiconductor (NMOS) transistor. Other transistor configurations are within the scope of various embodiments. The source / drain of transistor T1 is coupled to the source / drain of transistor T2 at node ml_ax corresponding to intermediate node 212. The source / drain of another transistor T1 and the source / drain of another transistor T2 are correspondingly coupled to circuits 241 and 242 at nodes 243 and 244, respectively. As described herein, circuits 241 and 242 constitute a multiplexer corresponding to a multiplexer MUX.

[0116] The transmission gate TG2m includes a pair of transistors T3 and T4 with gates correspondingly coupled to receive a first clock signal clkb and a second clock signal clkbb. In some embodiments, transistor T3 is a PMOS transistor and transistor T4 is an NMOS transistor. The source / drain of transistor T3 is coupled to the source / drain of transistor T4 at node ml_ax. The source / drain of the other transistor T3 and the source / drain of the other transistor T4 are coupled to the output of inverter INV2m.

[0117] The inverter INV1m contains a PMOS transistor (not labeled) and an NMOS transistor (not labeled) connected in series between the power supply voltage VDD and the ground voltage VSS. The gates of the PMOS and NMOS transistors are coupled to node ml_ax. The source / drain of the PMOS transistor is coupled to the source / drain of the NMOS transistor at node ml_b, which corresponds to the data output of the main latch-up circuit.

[0118] The inverter INV2m contains a PMOS transistor (not shown) and an NMOS transistor (not shown) connected in series between the power supply voltage VDD and the ground voltage VSS. The gates of the PMOS and NMOS transistors are coupled to node ml_b. The source / drain of the PMOS transistor and the source / drain of the NMOS transistor configure the output of the inverter INV2m and are coupled to the transmission gate TG2m.

[0119] The secondary latching circuit corresponding to the secondary latching circuit 220 (not shown in) Figure 2B The (intermediate) configuration includes transmission gates TG1s and TG2s and inverters INV1s and INV2s. Transmission gate TG1s includes a pair of transistors S1 and S2 with corresponding gates coupled to receive a first clock signal clkb and a second clock signal clkbb. In some embodiments, transistor S1 is a PMOS transistor, and transistor S2 is an NMOS transistor. The source / drain of transistor S1 is coupled to the source / drain of transistor S2 at node ml_b. The source / drain of the other transistor S1 and the source / drain of the other transistor S2 are coupled to node sl_a of the corresponding intermediate node 222.

[0120] The transmission gate TG2s includes a pair of transistors S3 and S4 with corresponding gates coupled to receive the second clock signal clkbb and the first clock signal clkb. In some embodiments, transistor S3 is a PMOS transistor and transistor S4 is an NMOS transistor. The source / drain of transistor S3 is coupled to the source / drain of transistor S4 at node sl_a. The source / drain of the other transistor S3 and the source / drain of the other transistor S4 are coupled to the output of inverter INV2s.

[0121] The inverter INV1s contains a PMOS transistor (not shown) and an NMOS transistor (not shown) connected in series between the power supply voltage VDD and the ground voltage VSS. The gates of the PMOS and NMOS transistors are coupled to node sl_a. The source / drain of the PMOS transistor is coupled to the source / drain of the NMOS transistor at the node corresponding to the data output 223 of the sub-latch circuit.

[0122] The inverter INV2s comprises a PMOS transistor (not shown) and an NMOS transistor (not shown) connected in series between the power supply voltage VDD and the ground voltage VSS. The gates of the PMOS and NMOS transistors are coupled to node sl_bx. The source / drain of the PMOS transistor and the source / drain of the NMOS transistor configure the output of the inverter INV2s and are coupled to the transmission gate TG2s.

[0123] Clock circuit 230 includes a first inverter corresponding to inverter INVA and a second inverter corresponding to inverter INVB. The first inverter includes a PMOS transistor CK1 and an NMOS transistor CK2 connected in series between the power supply voltage VDD and the ground voltage VSS. The gates of transistors CK1 and CK2 are coupled to the clock input CP to receive the input clock signal corresponding to the input clock signal Clock. The source / drain of transistor CK1 and the source / drain of transistor CK2 are commonly coupled to define the output of the first inverter, generating a first clock signal clkb at the output of the first inverter to be supplied to the main latch-up circuit and the secondary latch-up circuit. The second inverter includes a PMOS transistor CK3 and an NMOS transistor CK4 connected in series between the power supply voltage VDD and the ground voltage VSS. The gates of transistors CK3 and CK4 are coupled to the output of the first inverter to receive the first clock signal clkb. The source / drain of transistor CK3 and the source / drain of transistor CK4 are coupled together to define the output of the second inverter. The output of the second inverter generates a second clock signal clkbb to supply the main latch-up circuit and the secondary latch-up circuit.

[0124] Output circuit 250 includes an inverter configured with PMOS and NMOS transistors, the inverter being similar to one or more inverters described in detail herein. The input of output circuit 250 is coupled to node sl_bx. Output circuit 250 is used to invert the signal sl_bx at node sl_bx to output the output signal Q.

[0125] Selection circuit 260 (denoted as "SEL" in the figures) includes an inverter configured with PMOS and NMOS transistors, the inverter being similar to one or more inverters described in detail herein. The input of selection circuit 260 is coupled to input SE. Selection circuit 260 is used to invert the selection signal SE at input SE to output signal seb. In at least one embodiment, selection circuit 260 is omitted.

[0126] The multiplexer corresponding to the multiplexer MUX includes circuits 241 and 242. Circuit 241 includes four PMOS transistors (not shown) with gates corresponding to receive signals SI, seb, SE, and D. The PMOS transistors with gates corresponding to receive signals SI and seb are connected in series between the power supply voltage VDD and node 243. The PMOS transistors with gates corresponding to receive signals SE and D are connected in series between the power supply voltage VDD and node 243. Circuit 242 includes four NMOS transistors (not shown) with gates corresponding to receive signals SE, SI, D, and seb. The NMOS transistors with gates corresponding to receive signals SE and SI are connected in series between the ground voltage VSS and node 244. The NMOS transistors with gates corresponding to receive signals D and seb are connected in series between the ground voltage VSS and node 244. Figure 2B In the example configuration, when the signal SE is at the logic high level, the signal SI is transmitted to the transmission gate TG1m via the multiplexer, and when the signal SE is at the logic low level, the signal D is transmitted to the transmission gate TG1m via the multiplexer.

[0127] The flip-flop speed Sp of flip-flop circuit 200 is calculated by the following formula (1).

[0128] Sp = 1 / (T) setup + T cp2q (1).

[0129] In formula (1), T setup Alternatively, the time can be set to the data arrival time before the clock shift, and is calculated using the following formula (2), and T cp2q Alternatively, the output delay time can be calculated using the following formula (2).

[0130] T setup = T D2ml_b - T ck2mTXG (2)

[0131] T cp2q = T ck2slTXG + T ml_b2Q (3).

[0132] In formula (2), T D2ml_b The time delay from D to ml_b is the time delay related to the transmission gate TG1m, and indicates the time required to transmit the input data at data input D to node ml_b when the transmission gate TG1m is turned on. D2ml_b This is related to the configuration and / or manufacturing process of the transmission gate TG1m and is assumed to be constant. Regarding Figure 2C Further description of TD2ml_b .

[0133] Similarly, in formula (2), T ck2mTXG The time delay from the clock to the main transmission gate is the time delay related to the clock transmission path from the clock circuit 230 to the main latching circuit, and indicates the time required for the clock transition in the clock signal at the output of the clock circuit 230 to reach the transmission gate TG1m to turn on the transmission gate TG1m. In some embodiments, as described herein, T ck2mTXG Configuration can be achieved through placement and wiring operations. About Figure 2C Further description of T ck2mTXG .

[0134] In formula (3), T ck2slTXG The time delay from clock to sub-transmission gate is the time delay related to the clock transmission path from clock circuit 230 to sub-latch circuit, and indicates the time required for the clock transition in the clock signal at the output of clock circuit 230 to reach transmission gate TG1s to turn on transmission gate TG1s.

[0135] Similarly, in formula (3), T ml_b2Q The time delay from node ml_b to output Q is the time delay related to transmission gate TG1s, and indicates the time required for transmission gate TG1s to transmit data at node ml_b to output Q when transmission gate TG1s is turned on. ml_b2Q It is related to the configuration and / or manufacturing process of the transmission gate TG1s and is assumed to be constant.

[0136] From formulas (1) to (3), the flip-flop speed Sp of the flip-flop circuit 200 is calculated by the following formula (4).

[0137] Sp = 1 / (T) D2ml_b + T ml_b2Q + T ck2slTXG - T ck2mTXG (4).

[0138] Considering T D2ml_b and T ml_b2Q Assumed to be constant, to improve performance or to increase the flip-flop speed Sp,T of flip-flop circuit 200. ck2slTXG To be reduced and / or T ck2mTXG This needs to be increased. In some embodiments, considering various design considerations, it is best to minimize the resistance and capacitance of the clock network used to transmit the clock signal. That is, to attempt to route the clock circuit to the latching circuit with the shortest possible metal wiring (clock network) with minimal ambient influence (e.g., with the smallest possible time delay). Therefore, it is difficult to further reduce T. ck2slTXG To improve efficiency.

[0139] However, in one or more embodiments, it is possible to increase T ck2mTXG To improve performance, for example, by increasing the flip-flop speed Sp of the flip-flop circuit 200. This is done during a larger time delay T. ck2mTXG Set time T setup The flip-flop speed Sp of the flip-flop circuit 200 is increased, and the flip-flop speed Sp of the flip-flop circuit 200 is reduced. In some embodiments, T is increased through placement and wiring operations. ck2mTXG (For example, the time delay from the clock circuit to the main latch circuit) increases to greater than T. ck2slTXG (For example, the time delay from the clock circuit to the secondary latch circuit). Therefore, the secondary latch circuit responds to clock switching (or clock transitions) faster than the primary latch circuit, resulting in improved performance in one or more embodiments. In some embodiments, T ck2slTXG The goal is to minimize the time delay from the clock circuit to the secondary latch circuit, which is permitted by various design rules for IC devices. In at least one embodiment, a FEOL layout is generated (e.g., during a placement operation) to physically place the clock circuit such that the secondary latch circuit is closer to the clock circuit than the primary latch circuit, for example, as per [reference to...]. Figures 3A to 3D , Figure 5A , Figures 7A to 7B As described above. In at least one embodiment, a BEOL wiring path is generated (e.g., during wiring operations) to couple the clock circuit to the main latch circuit via an electrical path (or electrical connection) that is physically longer than the path from the clock circuit to the secondary latch circuit, for example, as per [reference to...]. Figures 3A to 3H , Figures 5A to 5B , Figures 7A to 7C As stated above.

[0140] Figure 2C This is a schematic timing diagram of the operation of a flip-flop circuit 200 according to some embodiments.

[0141] exist Figure 2C The upper part of the timing diagram illustrates the clock pulse 270 (also corresponding to the second clock signal clkbb) of the input clock signal CP. Clock pulse 270 has a rising edge 271 corresponding to a clock transition from a logic low level (e.g., 0) to a logic high level (e.g., 1). Clock pulse 270 further has a falling edge 272 corresponding to a clock transition from 1 to 0. Line 273 indicates the timing at which the signal level at the rising edge 271 is sufficient to turn on the transmission gate TG1m of the main latch circuit. (See also: Regarding...) Figure 2BIn response to the rising edge 271 of the clock pulse 270, the main latch circuit latches the input data D, and in response to the falling edge 272 of the clock pulse 270, the main latch circuit outputs the latched input data as intermediate data to the sub-latch circuit. Furthermore, in response to the rising edge 271 of the clock pulse 270, the sub-latch circuit outputs the previously latched intermediate data as output data at output Q, and in response to the falling edge 272 of the clock pulse 270, the sub-latch circuit latches the intermediate data received from the main latch circuit.

[0142] exist Figure 2C The middle part of the timing diagram illustrates pulse 275 of signal ml_b. Pulse 275 of signal ml_b has a rising edge 276 corresponding to the rising edge 271 of clock pulse 270, and a rising edge (illustrated as rising edge 277) of data D at the data input of the main latch circuit. Specifically, when the signal level at the rising edge 271 of clock pulse 270 is sufficient to turn on the transmission gate TG1m of the main latch circuit, data D at the data input (e.g., data input 211) is transmitted to node ml_b through transmission gate TG1m. When data D transmitted through transmission gate TG1m arrives at node ml_b, rising edge 277 of data D becomes rising edge 276. The time delay between rising edges 277 and 276 is T. D2ml_b The time delay between the rising edges 271 and 276 is T. ck2mTXG The time delay between the rising edges 277 and 271 is the set time T. setup .

[0143] exist Figure 2C The lower part of the timing diagram in the figure, according to some embodiments, is in T ck2mTXG Increase (e.g., increase to T') ck2mTXG In the case of ), the pulse 275' of signal ml_b is illustrated. With the increase of T' ck2mTXG and the same (or unchanged) T D2ml_b Set the time shorter (e.g., T) setup_boost The rising edge 276' of pulse 275' is later than the discussed point regarding... Figure 2C The middle portion of the timing diagram reaches node ml_b; however, in at least one embodiment, the setup time is shortened and the performance of the flip-flop circuit is increased. In some embodiments, in Figure 2C The middle and lower portions of the timing diagram also reflect the timing relationship between the arrival of clock pulse 270 in the secondary latch circuit (middle portion) and the later arrival of clock pulse 270 in the primary latch circuit (lower portion).

[0144] Figures 2D to 2FThis is a circuit diagram illustrating the operation of a flip-flop circuit 200 according to some embodiments.

[0145] exist Figure 2D During the read operation, the input clock signal CP and the second clock signal clkbb are at 0, the first clock signal clkb is at 1, transmission gates TG1m and TG2s are turned on, and transmission gates TG2m and TG1s are turned off. Arrow 281 illustrates the transmission of data D to signal ml_b through the turned-on transmission gate TG1m. The latched data is stored in data holding circuit 214. The previously latched data stored in data holding circuit 224 of the sub-latch circuit is transmitted to output Q.

[0146] exist Figure 2E During the intermediate stage, a clock transition occurs in the clock circuit 230, and the input clock signal CP and the second clock signal clkbb become 1, while the first clock signal clkb becomes 0. This clock transition corresponds to... Figure 2C The falling edge 272 of the clock pulse 270. The time delay (e.g., T) of the electrical connection from the clock circuit 230 to the sub-latch circuit. ck2slTXG Shorter than the time delay of the electrical connection from clock circuit 230 to main latch circuit (e.g., T). ck2mTXG The clock transition occurring in clock circuit 230 (e.g., falling edge 272) arrives at the sub-latch circuit before reaching the main latch circuit. Therefore, the transmission gate TG1s of the sub-latch circuit is turned on, while the transmission gate TG1m remains on. The transmission gate TG2s of the sub-latch circuit is turned off. Arrow 281 illustrates that the turned-on transmission gate TG1s transmits previously latched data stored in the data holding circuit 214 of the main latch circuit to the sub-latch circuit. Because the transmission gate TG1m remains on during the intermediate phase, in one or more embodiments, there is still sufficient time to successfully transmit data D to node ml_b, despite the shortened setup time. The intermediate phase corresponds to the period between the arrival of the falling edge 272 of the clock pulse 270 in the sub-latch circuit and the arrival after the falling edge 272 of the clock pulse 270 in the main latch circuit.

[0147] After the intermediate stage and in Figure 2F In the output operation, the clock transition occurring in clock circuit 230 (e.g., falling edge 272) reaches the main latch circuit, turning off transmission gate TG1m and turning on transmission gate TG2m. Data D is latched by data holding circuit 214 of the main latch circuit. The operation is repeated in the next clock cycle (e.g., the next clock pulse).

[0148] Figures 3A to 3HThis is a simplified schematic diagram of the layout of various circuit regions 300A-300H of one or more IC devices according to some embodiments. In some embodiments, one or more circuit regions 300A-300H are included in region 104 of IC device 100. Figures 2A to 2F and Figures 3A to 3H The corresponding parts are labeled with the same reference numerals.

[0149] exist Figure 3A In the circuit region 300A, a boundary 304 is included, within which a main latch circuit 310, a secondary latch circuit 320, a clock circuit 330, and other circuits 305 and 306 are placed. In some embodiments, the main latch circuit 310, the secondary latch circuit 320, and the clock circuit 330 correspond to the main latch circuit 210, the secondary latch circuit 220, and the clock circuit 230, respectively. In some embodiments, each of the other circuits 305 and 306 corresponds to one or more of the input circuit 240, the output circuit 250, and the selection circuit 260. In at least one embodiment, at least one of the other circuits 305 and 306 includes information regarding... Figures 2A to 2F The circuit is other than one or more of the circuits described. In at least one embodiment, at least one of the other circuits 305, 306 is omitted.

[0150] In some embodiments, at least one of the main latch circuit 310, the secondary latch circuit 320, the clock circuit 330, and other circuits 305 and 306 is a cell stored in or retrieved from one or more cell libraries. For example, the main latch circuit 310 is a cell having a boundary 301 within which transistors T1 to T4 are arranged and electrically coupled to form transmission gates TG1m and TG2m. The main latch circuit 310 further includes transistors forming inverters INV1m and INV2m. Figure 3A For simplicity, the text has been omitted. In some embodiments, the example layout of a pair of transistors T1, T2 or a pair of transistors T3, T4 is similar to that described above. Figure 8B The example layout is described. The sub-latch circuit 320 is a unit with a boundary 302, within which transistors S1 to S4 are arranged and electrically coupled to form transmission gates TG1s and TG2s. The sub-latch circuit 320 further includes transistors forming inverters INV1s and INV2s. Figure 3A For simplicity, the details are omitted. In some embodiments, the example layout of a pair of transistors S1, S2 or a pair of transistors S3, S4 is similar to that described above. Figure 8B The example layout is described above. Clock circuit 330 is a unit with a boundary 303, within which transistors CK1 to CK4 are arranged and electrically coupled to form inverters INVA and INVB. In some embodiments, the example layout of a pair of transistors CK1, CK2 or a pair of transistors CK3, CK4 is similar to that described above. Figure 8BThe example layout described herein is exemplified by the arrangement of transistors in the main latch circuit 310, the secondary latch circuit 320, and the clock circuit 330. Other configurations are within the scope of various embodiments.

[0151] The main latch circuit 310, the secondary latch circuit 320, the clock circuit 330, and other circuits 305 and 306 are arranged along the U-axis. The V-axis is transverse to the U-axis. In some embodiments, the V-axis is perpendicular to the U-axis. In at least one embodiment, the U-axis corresponds to one of the X-axis and the Y-axis, and the V-axis corresponds to the other of the X-axis and the Y-axis. In at least one embodiment, at least one of the U-axis or the V-axis cannot correspond to either the X-axis or the Y-axis. Although the boundaries of boundaries 301, 302, 303 and the boundaries of other circuits 305 and 306 (not shown) are... Figure 3A The diagram illustrates that the circuits are spaced apart from each other along the U-axis, and in at least one embodiment, the boundaries of adjacent circuits are placed adjacent to each other.

[0152] Circuit region 300A further includes electrical connections 311 and 312, which are electrically coupled to clock circuit 330 corresponding to the main latch circuit 310 and the secondary latch circuit 320, and are used to supply a first clock signal clkb to the main latch circuit 310 and the secondary latch circuit 320. Circuit region 300A further includes electrical connections 313 and 314, which are electrically coupled to clock circuit 330 corresponding to the main latch circuit 310 and the secondary latch circuit 320, and are used to supply a second clock signal clkbb to the main latch circuit 310 and the secondary latch circuit 320. In some embodiments, electrical connections 311, 312, 313, and 314 correspond to electrical connections 218, 219, 228, and 229. For simplicity, electrical connections 311 to 314 are... Figure 3A The arrows in the middle illustrate the point. Regarding... Figures 9A to 9B Describe example electrical connections for one or more of the corresponding electrical connections 311-314. In at least one embodiment, as per [reference to...] Figures 8B to 8C The electrical connections 311 to 314 include one or more metal layers on the front side of the substrate of the IC device, and / or one or more back metal layers on the back side of the substrate.

[0153] In circuit region 300A, the clock circuit 330 is placed (e.g., during placement) such that the secondary latch circuit 320 is physically closer to the clock circuit 330 than the primary latch circuit 310. Specifically, the secondary latch circuit 320 is placed along the U-axis between the primary latch circuit 310 and the clock circuit 330. Therefore, when wiring electrical connections 311-314 during wiring operations, the physical length of electrical connections 311, 313 for supplying the first clock signal clkb and the second clock signal clkbb from the clock circuit 330 to the primary latch circuit 310 is greater than the physical length of electrical connections 312, 314 for supplying the first clock signal clkb and the second clock signal clkbb from the clock circuit 330 to the secondary latch circuit 320. Corresponding to the first clock signal clkb and the second clock signal clkbb, compared with the lengths of electrical connections 312 and 314, the lengths of electrical connections 311 and 313 are larger, resulting in a time delay (T) in electrical connections 311 and 313. ck2mTXG The time delay (T) of electrical connections 312 and 314 is greater than that of electrical connections 312 and 314. ck2slTXG Therefore, in at least one embodiment, performance can be improved, for example, by increasing the flip-flop speed, with respect to both the first clock signal clkb and the second clock signal clkbb.

[0154] In at least one embodiment, the secondary latch circuit 320 is placed as close as possible to the clock circuit 330. For example, the boundary 302 of the secondary latch circuit 320 is placed adjacent to the boundary 303 of the clock circuit 330. In at least one embodiment, the wiring connections 311-314 are arranged to form the shortest path between the clock circuit 330 and the main latch circuit 310 and the secondary latch circuit 320 (with the smallest possible time delay), which is permitted by various design rules of IC devices. The time delays of the electrical connections 311 and 313, although between the shortest paths between the clock circuit 330 and the main latch circuit 310, are still greater than the time delays of the electrical connections 312 and 314, because the placement of the main latch circuit 310 makes the clock circuit 330 farther away from the main latch circuit 310 than the secondary latch circuit 320.

[0155] exist Figure 3B In this embodiment, circuit region 300B, unlike circuit region 300A, is configured as two clock circuits 330A and 330B that are physically separate via other circuits 307 and electrically coupled via electrical connection 325. Clock circuit 330A includes transistors CK1 and CK2 and corresponds to inverter INVA. Clock circuit 330B includes transistors CK3 and CK4 and corresponds to inverter INVB. In some embodiments, other circuits 307 include circuitry corresponding to at least one of input circuit 240, output circuit 250, selection circuit 260, or other circuits. In at least one embodiment, other circuits 307 are omitted.

[0156] During placement, other circuits 305, main latch circuit 310, other circuits 306, secondary latch circuit 320, clock circuit 330A, other circuits 307, and clock circuit 330B are placed along the U-axis in the order described. Specifically, secondary latch circuit 320 is placed between main latch circuit 310 and each of clock circuits 330A and 330B.

[0157] In the wiring operation, wiring corresponds to electrical connections 321-324 of electrical connections 311-314. Specifically, wiring electrical connections 321 and 322 are electrically coupled to clock circuit 330A, corresponding to the main latch circuit 310 and the secondary latch circuit 320, to supply a first clock signal clkb to the main latch circuit 310 and the secondary latch circuit 320. Wiring electrical connections 323 and 324 are electrically coupled to clock circuit 330B, corresponding to the main latch circuit 310 and the secondary latch circuit 320, to supply a second clock signal clkbb to the main latch circuit 310 and the secondary latch circuit 320. Also, wiring electrical connection 325 is electrically coupled to clock circuit 330A to clock circuit 330B to supply the first clock signal clkb to clock circuit 330B so that clock circuit 330B can output the second clock signal clkbb. In at least one embodiment, the wiring electrical connection 325 is configured to be the shortest path between clock circuit 330A and clock circuit 330B.

[0158] The physical lengths of electrical connections 321 and 323 supplying the first clock signal clkb and the second clock signal clkbb from the clock circuit 330 to the main latch circuit 310 are greater than the physical lengths of electrical connections 322 and 324 supplying the first clock signal clkb and the second clock signal clkbb from the clock circuit 330 to the secondary latch circuit 320. Regarding both the first clock signal clkb and the second clock signal clkbb, the electrical connections 321 and 323, which are longer than electrical connections 322 and 324, are configured to have a greater time delay than electrical connections 322 and 324. Therefore, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved with respect to both the first clock signal clkb and the second clock signal clkbb.

[0159] In at least one embodiment, the boundary of adjacent circuits placed in circuit region 300B is adjacent. In at least one embodiment, wiring connections 321-324 are arranged to form the shortest path (with the smallest possible time delay) between the corresponding clock circuits 330A, 330B and the main latch circuit 310, sub-latch circuit 320, as permitted by various design rules of IC devices.

[0160] exist Figure 3CIn this embodiment, circuit regions 300C and 300B differ from those in the placement operation. The placement clock circuit 330A is located between the main latch circuit 310 and the secondary latch circuit 320, and other circuits 306 are omitted. In the wiring operation, wiring corresponds to electrical connections 331-335 of electrical connections 321-325. In some embodiments, wiring electrical connections 331-334 are designed to be the shortest path (with the smallest possible time delay) between the corresponding clock circuits 330A, 330B and the main latch circuit 310, secondary latch circuit 320, which is permitted by various design rules of IC devices. In at least one embodiment, wiring electrical connection 335 is designed to be the shortest path between clock circuits 330A and 330B. In at least one embodiment, electrical connections 331 and 332 have the same physical length and the same time delay.

[0161] The physical length of the electrical connection 333 supplying the second clock signal clkbb from clock circuit 330B to main latch circuit 310 is greater than the physical length of the corresponding electrical connection 334 supplying the second clock signal clkbb from clock circuit 330B to secondary latch circuit 320, because the main latch circuit 310 is positioned such that clock circuit 330B is further away from the main latch circuit 310 than secondary latch circuit 320. Therefore, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved at least with respect to the second clock signal clkbb. In at least one embodiment, clock circuits 330A and 330B are physically swapped, thus improving performance, such as increased flip-flop speed, can be achieved at least with respect to the first clock signal clkb. In at least one embodiment, the boundary of an adjacent circuit placed in circuit region 300C is adjacent to the boundary of the adjacent circuit.

[0162] exist Figure 3D In this embodiment, circuit region 300D and circuit region 300C differ from clock circuit 330A and other circuits 305 in that their positions are interchanged. During placement, the main latch circuit 310 is placed between clock circuit 330A and secondary latch circuit 320, and clock circuit 330A is physically closer to the main latch circuit 310 than secondary latch circuit 320. During routing, wiring corresponds to electrical connections 341-345 of electrical connections 331-335. In some embodiments, wiring electrical connections 342-344 are located between the corresponding clock circuits 330A, 330B and the main latch circuit 310, secondary latch circuit 320 to form the shortest path (with the smallest possible time delay), which is permitted by various design rules of IC devices. In at least one embodiment, wiring electrical connection 345 is used to form the shortest path between clock circuit 330A and clock circuit 330B.

[0163] Electrical connection 341 includes redundant wiring. In at least one embodiment, the redundant wiring includes additional conductive patterns to make the physical length of electrical connection 341 longer (e.g., with a larger time delay) than the shortest possible path between clock circuit 330A and main latch circuit 310. Therefore, electrical connection 341 has approximately the same or larger physical length and time delay compared to the shortest path between clock circuit 330A and main latch circuit 310. Regarding Figure 9D Example electrical connections with redundant wiring are described. In some embodiments, the electrical connection between the main latch circuit 310 and the clock circuit 330A corresponds to the shortest path between the main latch circuit 310 and the clock circuit 330A. The physical length of the electrical connection 343 supplying the second clock signal clkbb from the clock circuit 330B to the main latch circuit 310 is greater than the physical length of the corresponding electrical connection 344 supplying the second clock signal clkbb from the clock circuit 330B to the secondary latch circuit 320. Therefore, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved at least with respect to the second clock signal clkbb. In at least one embodiment, the clock circuits 330A and 330B are physically swapped, thus improving performance, such as increased flip-flop speed, can be achieved at least with respect to the first clock signal clkb. In at least one embodiment, the boundaries of adjacent circuits are placed adjacent to each other in the circuit region 300D.

[0164] Figures 3A to 3D As an example, this example illustrates that by placing the main latch circuit 310 such that the clock circuits 330, 330A, 330B are physically further away from the main latch circuit 310 than the secondary latch circuit 320, in one or more embodiments, it is possible to increase the time delay of the electrical connection between the main latch circuit 310 and the clock circuits 330, 330A, 330B by wiring along the shortest possible path between the corresponding main or secondary latch circuit and the corresponding clock circuit, making it greater than the time delay of the electrical connection between the secondary latch circuit 320 and the clock circuits 330, 330A, 330B. Figures 3E to 3H This is an example illustrating that even when the physical length of the primary latch circuit 310 to the clock circuits 330, 330A, 330B is approximately the same as the physical length of the secondary latch circuit 320 to the clock circuits 330, 330A, 330B, in one or more embodiments, through appropriate wiring operations, it is still possible to increase the time delay of the electrical connection between the primary latch circuit 310 and the clock circuits 330, 330A, 330B to be greater than the time delay of the electrical connection between the secondary latch circuit 320 and the clock circuits 330, 330A, 330B.

[0165] exist Figure 3EIn this configuration, circuit region 300E and circuit region 300A are physically interchanged, unlike clock circuit 330 and secondary latch circuit 320. During placement, clock circuit 330 is positioned between primary latch circuit 310 and secondary latch circuit 320.

[0166] In at least one embodiment, the shortest path from clock circuit 330 to main latch circuit 310 and the shortest path from clock circuit 330 to sub-latch circuit 320 have approximately the same physical length and time delay. Regarding the first clock signal clkb, to increase the time delay between clock circuit 330 and main latch circuit 310, the electrical connection between main latch circuit 310 and clock circuit 330 includes series-coupled electrical connection 352 and electrical connection 351. Wiring is provided between electrical connection 352 between clock circuit 330 and sub-latch circuit 320. Electrical connection 351 is electrically coupled to electrical connection 352, and wiring is provided between sub-latch circuit 320 and main latch circuit 310. Therefore, the electrical connection between clock circuit 330 and main latch circuit 310 is physically longer than the shortest path between clock circuit 330 and main latch circuit 310, and physically longer than the electrical connection 352 between clock circuit 330 and sub-latch circuit 320. In at least one embodiment, the wiring electrical connections 351, 352 are designed to be the shortest path from the sub-latch circuit 320 to the main latch circuit 310 and clock circuit 330 (with the smallest possible time delay), which is permitted by various design rules of IC devices. Regarding Figure 9C Describe example electrical connections for corresponding electrical connections 351 and 352.

[0167] Similarly, regarding the second clock signal clkbb, the wiring corresponding to electrical connections 353 and 354 of electrical connections 351 and 352 is routed from the secondary latch circuit 320 to the primary latch circuit 310 and the clock circuit 330. In at least one embodiment, the wiring connections 353 and 354 are designed to be the shortest paths from the secondary latch circuit 320 to the primary latch circuit 310 and the clock circuit 330 (with the smallest possible time delay), which is permitted by various design rules of IC devices. In at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved with respect to both the first clock signal clkb and the second clock signal clkbb. In at least one embodiment, the boundaries of adjacent circuits are placed adjacent to each other in the circuit region 300E.

[0168] exist Figure 3F In the circuit regions 300F and 300E, the circuit regions 300F and 300E, which are different from the electrical connections 351 and 353, are replaced by electrical connections 361 and 362, which contain redundant wiring. Regarding... Figure 3D , Figure 9DAn example of redundant wiring is described. Redundant wiring increases the physical length and time delay of electrical connections 361, 362 between clock circuit 330 and main latch circuit 310, making them greater than the physical length and time delay of electrical connections 352, 354 between clock circuit 330 and secondary latch circuit 320. In at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved with respect to both the first clock signal clkb and the second clock signal clkbb. In at least one embodiment, the boundaries of adjacent circuits are placed adjacent to each other in circuit region 300F.

[0169] exist Figure 3G In circuit regions 300G and 300E, the electrical connection 353 is replaced by an electrical connection 373 that is routed between the clock circuit 330 and the main latch circuit 310. In some embodiments, the electrical connection 373 is routed to become the shortest path from the autonomous latch circuit 310 to the clock circuit 330 (with the smallest possible time delay). In at least one embodiment, the electrical connection 373 has the same physical length and time delay as the electrical connection 354. In at least one embodiment, improved performance, such as increased flip-flop speed, can still be achieved with respect to at least the first clock signal clkb. In some embodiments, in Figure 3G In this embodiment, regarding at least the second clock signal clkbb, the electrical connections for the first clock signal clkbb and the electrical connections for the second clock signal clkbb are swapped to improve performance, such as increasing the flip-flop speed. In at least one embodiment, the boundaries of adjacent circuits are placed adjacent to each other in the circuit region 300G.

[0170] exist Figure 3H In the circuit regions 300H and 300F, the electrical connection 363, which differs from the redundant wiring, is replaced by electrical connection 373. In at least one embodiment, with respect to at least the first clock signal clkb, improved performance, such as increased flip-flop speed, can be achieved. In some embodiments, in Figure 3H In this embodiment, regarding at least the second clock signal clkbb, the electrical connections for the first clock signal clkbb and the electrical connections for the second clock signal clkbb are swapped to improve performance, such as increasing the flip-flop speed. In at least one embodiment, the boundaries of adjacent circuits are placed adjacent to each other in the circuit region 300H.

[0171] Figure 4 This is a schematic logic diagram of a multi-bit flip-flop circuit 400 according to some embodiments.

[0172] The multi-bit flip-flop circuit 400 includes multiple flip-flop circuits MB1 to MB8. Each of the flip-flop circuits MB1 to MB8 includes an input circuit, a main latch circuit, a secondary latch circuit, and an output circuit corresponding to the input circuit 240, the main latch circuit 210, the secondary latch circuit 220, and the output circuit 250. The flip-flop circuits MB1 to MB8 are used to receive the corresponding input data D (bits D1 to D8) and to output the corresponding output data Q (bits Q1 to Q8). The flip-flop circuits MB1 to MB8 are connected in series and coupled to each other, such that the output of one flip-flop circuit is electrically coupled to the input SI (or Si) of the subsequent flip-flop circuit. For example, the output Q1 of flip-flop circuit MB1 is electrically coupled to the input SI (or Si) of the subsequent flip-flop circuit MB2.

[0173] The multi-bit flip-flop circuit 400 includes a common clock circuit 230 and a common selection circuit 460 for all flip-flop circuits MB1 to MB8. Compared to selection circuit 260, selection circuit 460 includes an additional inverter, and the inverter of selection circuit 460 is used to output signals seb1 and seb2, both of which are inverted from the selection signal SE. One of signals seb1 and seb2 is supplied to half of the input SE (or So) of flip-flop circuits MB1 to MB8, and the other is supplied to the other half of the input SE (or So) of flip-flop circuits MB1 to MB8. Other configurations are within the scope of various embodiments.

[0174] Figures 5A to 5B This is a simplified schematic diagram of the layout of various circuit regions 500A-500B of one or more IC devices according to some embodiments. Circuit regions 500A and 500B include multi-bit flip-flop circuits 400. In some embodiments, one or more circuit regions 500A-500B are included in region 104 of IC device 100. Figures 2A to 2F , Figures 3A to 3H , Figure 4 , Figures 5A to 5B The corresponding parts are labeled with the same reference numerals.

[0175] exist Figure 5AIn circuit region 500A, flip-flop circuits MB1 to MB8 are physically arranged along the V-axis, such that the main latch circuits of flip-flop circuits MB1 to MB8 are arranged in one row (not shown) along the V-axis, and the secondary latch circuits of flip-flop circuits MB1 to MB8 are arranged in another row (not shown) along the V-axis. The row of secondary latch circuits is arranged along the U-axis and between the clock circuit 530 of the corresponding clock circuit 230 and the row of the main latch circuits of flip-flop circuits MB1 to MB8. Clock buses 501 and 503 are arranged along the row above the main latch circuits and are coupled to the main latch circuits to supply the first clock signal clkb and the second clock signal clkbb to the main latch circuits respectively. Clock buses 502 and 504 are arranged along the row above the secondary latch circuits and are coupled to the secondary latch circuits to supply the first clock signal clkb and the second clock signal clkbb to the secondary latch circuits respectively.

[0176] The wiring corresponding to electrical connections 311 and 313, and electrical connections 511 and 513, are from the clock circuit 530 to the clock buses 501 and 503 to supply the first clock signal clkb and the second clock signal clkbb to the main latch circuit. The wiring corresponding to other electrical connections 312 and 314 (not shown) are from the clock circuit 530 to the clock buses 502 and 504 to supply the first clock signal clkb and the second clock signal clkbb to the secondary latch circuit. (See also: Regarding...) Figure 3A As described, compared to the electrical connections of the clock buses 502, 504 to the secondary latch circuit, the electrical connections 511, 513 to the clock buses 501, 503 to the primary latch circuit have a larger physical length and a larger time delay. Therefore, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved with respect to both the first clock signal clkb and the second clock signal clkbb. In at least one embodiment, the electrical connections 511, 513 and the corresponding electrical connections 312, 314 (not shown) are arranged to form the shortest path (with the smallest possible time delay) from the clock circuit 530 to the clock buses 501, 503 of the primary latch circuit and the clock buses 502, 504 of the secondary latch circuit, which is permitted by various design rules of IC devices.

[0177] exist Figure 5B In this circuit, circuit regions 500B and 500A differ from clock circuit 530 and are arranged along the U-axis between the rows of the secondary latch circuits of flip-flop circuits MB1 to MB8 and the rows of the primary latch circuits. Wiring corresponding to electrical connections 352 and 354 is provided from clock circuit 530 to clock bus 502 and 504 to supply the first clock signal clkb and the second clock signal clkbb to the secondary latch circuit.

[0178] The clock buses 502 and 504 are connected in series to the corresponding electrical connections 551 and 553, which are then connected to electrical connections 552 and 554. Corresponding wiring connections 551 and 553 connect from clock buses 502 and 504 to clock buses 501 and 503 respectively, supplying the first clock signal clkb and the second clock signal clkbb to the main latching circuit. (See also: Regarding...) Figure 3E As described, the electrical connection from clock circuit 530 to the main latch circuit includes series-coupled electrical connections 551 and 552 for the first clock signal clkb, and series-coupled electrical connections 553 and 554 for the second clock signal clkbb, which have a larger physical length and a larger time delay compared to the electrical connections 552 and 554 for wiring from clock circuit 530 to the secondary latch circuit. Therefore, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved with respect to both the first clock signal clkb and the second clock signal clkbb. In at least one embodiment, the wiring connections 551 and 552 are arranged to form the shortest path (with the smallest possible time delay) from the clock bus 502 to the clock bus 501 and clock circuit 530, as permitted by various design rules of IC devices. In at least one embodiment, wiring connections 553 and 554 are configured to be the shortest paths from clock bus 504 to clock bus 502 and clock circuit 530 (with the smallest possible time delay), as permitted by various design rules of IC devices.

[0179] In some embodiments, regarding Figures 3B to 3D and Figures 3F to 3H The described one or more configurations are suitable for multi-bit flip-flop circuits to increase the time delay of the clock signal supplied to the main latch circuit to be greater than the time delay of the clock signal supplied to the secondary latch circuit, and to improve the performance of the multi-bit flip-flop circuit.

[0180] Figure 6 This is a schematic logic diagram of a flip-flop circuit 600 according to some embodiments. The flip-flop circuit 600 includes a main latch circuit 610, a secondary latch circuit 620, a clock circuit 230, and an input circuit 640.

[0181] Input circuit 640 includes an inverter INVi having an input coupled to data input D and an output. Other circuit configurations for input circuit 640 are within the scope of various embodiments. In at least one embodiment, input circuit 640 is omitted.

[0182] The main latch circuit 610 includes NAND gates NAND1m to NAND4m. A first input of gate NAND1m is coupled to data input D, and a first input of gate NAND2m is coupled to the output of inverter INVi. Second inputs of gates NAND1m and NAND2m are configured as clock inputs and coupled via clock circuit 230 to receive a first clock signal clkb output. Outputs of gates NAND1m and NAND2m are correspondingly coupled to the first inputs of gates NAND3m and NAND4m. Second inputs of gates NAND3m and NAND4m are correspondingly coupled to the outputs of gates NAND4m and NAND3m, and the outputs of gates NAND4m and NAND3m are configured to output the main latch circuit 610.

[0183] The secondary latch circuit 620 includes NAND gates NAND1s to NAND4s. The first inputs of gates NAND1s and NAND2s are correspondingly coupled to the output gates of NAND3m and NAND4m. The second inputs of gates NAND1s and NAND2s are configured as clock inputs and coupled via clock circuit 230 to receive the second clock signal clkbb output. The outputs of gates NAND1s and NAND2s are correspondingly coupled to the first inputs of gates NAND3s and NAND4s. The second inputs of gates NAND3s and NAND4s are correspondingly coupled to the outputs of gates NAND4s and NAND3s, and the outputs of gates NAND4s and NAND3s are configured as the differential outputs Q and Qbar of the flip-flop circuit 600. Figure 6 In the example configuration, the flip-flop circuit 600 is an SR flip-flop.

[0184] In some embodiments, the time delay of the first clock signal clkb from the clock circuit 230 to the main latch circuit 610 is greater than the time delay of the second clock signal clkbb from the clock circuit 230 to the secondary latch circuit 620. Therefore, as described herein, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved.

[0185] Figures 7A to 7C This is a simplified schematic diagram of the layout of various circuit regions 700A-700C of one or more IC devices according to some embodiments. Circuit regions 700A-700C include flip-flop circuitry as described herein. In some embodiments, one or more circuit regions 700A-700C are included in region 104 of IC device 100. Figures 2A to 2F , Figures 3A to 3H , Figure 6 Figures 7A to 7C The corresponding parts are labeled with the same reference numerals.

[0186] exist Figure 7AIn the circuit region 700A, there are input circuits 640, 610, 620, 730 corresponding to the flip-flop circuit 600, and input circuits 740, 710, 720, and 730 corresponding to the clock circuit 230. The input circuits 740, 710, 720, and 730 are arranged along the U-axis in the aforementioned order. The clock circuit 730 is positioned such that the secondary latch circuit 720 is closer to the clock circuit 730 than the primary latch circuit 710. Electrical wiring connection 711 extends from the clock circuit 730 to the primary latch circuit 710 to supply a first clock signal clkb from the clock circuit 730 to the primary latch circuit 710. Electrical wiring connection 712 extends from the clock circuit 730 to the secondary latch circuit 720 to supply a second clock signal clkbb from the clock circuit 730 to the secondary latch circuit 720. The physical length and time delay of electrical connection 711 are greater than those of electrical connection 712. Therefore, as described herein, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved. In at least one embodiment, the wiring of electrical connections 711 and 712 is configured to be the shortest path from the clock circuit 730 to the main latch circuit 710 and the secondary latch circuit 720 (with the smallest possible time delay), as permitted by various design rules of IC devices.

[0187] exist Figure 7B In circuit region 700B, a secondary latch circuit 720 is placed adjacent to the clock circuit 730 along the U-axis and adjacent to the primary latch circuit 710 along the V-axis. Therefore, the clock circuit 730 is positioned such that the secondary latch circuit 720 is closer to the clock circuit 730 than the primary latch circuit 710. A wiring connection 721 extends from the clock circuit 730 to the primary latch circuit 710 to supply a first clock signal clkb from the clock circuit 730 to the primary latch circuit 710. The wiring connection 721 includes a first portion (not shown) extending along the U-axis and a second portion (not shown) extending along the V-axis. Regarding... Figure 9E Example electrical connections with portions extending in various directions are described. Wiring connection 722 extends from clock circuit 730 to sub-latch circuit 720 to supply a second clock signal clkbb from clock circuit 730 to sub-latch circuit 720. The physical length and time delay of electrical connection 721 are greater than those of electrical connection 722. Therefore, as described herein, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved. In at least one embodiment, wiring connections 721, 722 are designed to be the shortest paths from clock circuit 730 to the main latch circuit 710 and sub-latch circuit 720 (with the smallest possible time delay), which is permitted by various design rules of IC devices.

[0188] exist Figure 7CIn this embodiment, circuit region 700C includes a main latch circuit 781, a secondary latch circuit 782, a clock circuit 783, and other circuits 785 and 786. In some embodiments, the main latch circuit 781 corresponds to one or more of the main latch circuits described herein, and / or the secondary latch circuit 782 corresponds to one or more of the secondary latch circuits described herein, and / or the clock circuit 783 corresponds to one or more clock circuits described herein. In at least one embodiment, at least one of the other circuits 785 and 786 corresponds to one or more of the other circuits 305 and 306. The clock circuit 783 has an increased height (e.g., twice the height) along the V-axis and is adjacent to both the main latch circuit 781 and the secondary latch circuit 782 along the U-axis.

[0189] To increase the time delay between clock circuit 783 and main latch circuit 781, wiring is provided between main latch circuit 781 and clock circuit 783 via secondary latch circuit 782, and the electrical connection includes series-coupled electrical connections 792 and 791. Electrical connection 792 is routed along the U-axis between clock circuit 783 and secondary latch circuit 782. Electrical connection 791 is electrically coupled to electrical connection 792, and electrical connection 791 is routed along the V-axis between secondary latch circuit 782 and main latch circuit 781. Therefore, the electrical connection between clock circuit 783 and main latch circuit 781 is physically longer than the shortest path between clock circuit 783 and main latch circuit 781, and physically longer than electrical connection 792 between clock circuit 783 and secondary latch circuit 782. In at least one embodiment, the wiring connections 791, 792 are configured to form the shortest paths (with the smallest possible time delay) from the secondary latch circuit 782 to the primary latch circuit 781 and the clock circuit 783, as permitted by various design rules of IC devices. Regarding Figure 9E Example electrical connections corresponding to electrical connections 791 and 792 are described. As described herein, in at least one embodiment, improved performance, such as increased flip-flop speed, can be achieved.

[0190] Figure 8A This is a circuit diagram of circuit 800A according to some embodiments. Circuit 800A includes a PMOS transistor PM and an NMOS transistor NM. Figure 8A The example configuration in the image shows transistors PM and NM coupled, corresponding to configuration circuit 800A. Figures 2A to 2F An inverter of one or more of the described inverters. In at least one embodiment, transistors PM and NM are coupled to configuration circuit 800A corresponding to... Figures 2A to 2F The transmission gate described is one or more of the transmission gates.

[0191] exist Figure 8AIn this inverter configuration, transistors PM and NM are connected in series between the power supply voltage VDD and the ground voltage VSS. Specifically, transistor PM includes a gate region GP, ​​a source region SP, and a drain region DP. Transistor NM includes a gate region GN, a source region SN, and a drain region DN. Gate regions GP and GN are coupled to the input node IN. Drain regions DP and DN are coupled to the output node OUT. Source region SP is coupled to the power supply voltage VDD, and source region SN is coupled to the ground voltage VSS.

[0192] Figure 8B This is a schematic diagram of the layout of cell 800B of the corresponding circuit 800A according to some embodiments. In at least one embodiment, cell 800B is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium.

[0193] Cell 800B includes active regions 801, 802, a gate region 810, and a boundary 820. Active regions 801 and 802 are arranged within the boundary 820 and extend along the X-axis. Active regions are sometimes referred to as oxide-definition (OD) regions and are schematically illustrated as “OD” in the figures. According to at least one embodiment, as described herein, in the IC device corresponding to cell 800B, active regions 801 and 802 are on a first side (or front side) of the substrate. Active regions 801 and 802 contain P-type dopants and / or N-type dopants to form one or more circuit elements or devices. Gate region 810 is arranged within the boundary 820 and extends along the Y-axis across active regions 801 and 802. Gate region 810 contains a conductive material (e.g., polysilicon) and is schematically illustrated as “PO” in the figures. Other conductive materials (e.g., metals) for the gate region are within the scope of various embodiments.

[0194] The active region 801 includes a source region 803 and a drain region 805 on the opposite side of the first portion of the gate region 810, and the gate region 810 extends over the active region 801. The source region 803, the drain region 805, and the first portion of the gate region 810 correspond to each other with respect to... Figure 8A The source region SP, drain region DP, and gate region GP are described. Active region 802 includes source region 804 and drain region 806 on the opposite side of the second portion of gate region 810, the second portion of gate region 810 extending over active region 802. Source region 804, drain region 806, and the second portion of gate region 810 correspond to... Figure 8A The source region SN, drain region DN, and gate region GN are described.

[0195] Boundary 820 includes edges 821, 822, 823, and 824 that are connected to form a closed boundary. In the placement and routing operation described herein (also known as "automated placement and routing" (APR)), cells are placed adjacent to each other at their respective boundaries in the IC layout. Boundary 820 is sometimes referred to as the "placement and routing boundary" and is schematically illustrated in the figures as "prBoundary". Figure 8B In the example configuration, boundary 820 has a rectangular shape with edges 821, 823 parallel to the Y-axis and edges 822, 824 parallel to the X-axis. Other configurations are within the scope of various embodiments.

[0196] Unit 800B further includes dummy gate regions 818, 819 along corresponding edges 821, 823 of boundary 820. In at least one embodiment, the centerline of the dummy gate regions 818, 819 coincides with the corresponding edges 821, 823 of boundary 820. Gate region 810 is an example of a "functional gate region" that, together with the underlying active region, configures a transistor and / or electrically couples it to one or more other circuit elements. Dummy gate regions (or non-functional gate regions) distinct from functional gate regions are not used to form transistors together with the underlying active region, and / or the one or more transistors formed by the dummy gate regions and the underlying active regions are not electrically coupled to other circuit elements. In at least one embodiment, the dummy gate regions contain dielectric material in the manufactured IC device. In some embodiments, the dummy gate regions and functional gate regions are arranged along the X-axis at the same spacing CPP (e.g., center-to-center distance). In the placement and wiring operations of placement unit 800B in a layout adjacent to other units, the dummy gate regions 818, 819 along the edges 821, 823 of boundary 820 are merged with the corresponding dummy gate regions of other units. Other configurations are within the scope of various embodiments. For example, in one or more embodiments, one or more of the edges 821, 823 of boundary 820 are not arranged along the dummy gate regions 818, 819.

[0197] Unit 800B further includes contact structures in active regions 801 and 802, said contact structures being above and electrically contacting the corresponding source / drain regions. These contact structures are sometimes referred to as metal-to-device structures and are schematically illustrated in the figures as "MD". The MD contact structure includes conductive material formed in the corresponding active region and above the corresponding source / drain region to define electrical connections from one or more devices formed in the active region to other circuits. Figure 8BIn the example configuration, MD contact structures 835 and 836 are on and electrically contacted with the corresponding source regions 803 and 804, and MD contact structure 837 extends continuously along the Y-axis to be on and electrically contacted with the corresponding drain regions 805 and 806. MD contact structure 837 is electrically coupled to the drain regions 805 and 806. In some embodiments, MD contact structures and gate regions (including both functional and dummy gate regions) are alternately arranged along the X-axis. The spacing between directly adjacent MD contact structures (e.g., the center-to-center distance along the X-axis) is equal to the spacing CPP between directly adjacent gate regions. Example conductive materials for the MD contact structures include metals. Other configurations are within the scope of various embodiments.

[0198] Cell 800B further includes a via electrically contacting the corresponding gate region or MD contact structure. A via electrically contacting the MD contact structure is sometimes referred to as a via-to-device (VD). A via electrically contacting the gate region is sometimes referred to as a via-to-gate (VG). VD and VG vias are schematically illustrated in the figures as "VD / VG". Figure 8B In the example configuration, VG via 838 is above and electrically contacts gate region 810, and VD via 839 is above and electrically contacts MD contact structure 837. The example materials for the VD and VG vias include metal. Other configurations are within the scope of various embodiments.

[0199] Unit 800B further includes one or more metal layers and via layers, which are arranged successively and alternately over the VD and VG vias. The lowest metal layer immediately above and electrically in contact with the VD and VG vias is the metal zero (M0) layer. In other words, the M0 layer is the lowest metal layer above or closest to the active regions 801 and 802 on the front side of the substrate. The next metal layer immediately above the M0 layer is the metal one (M1) layer, etc. The via layers Vn are arranged between the Mn layer and the Mn+1 layer and electrically coupled to the Mn layer and the Mn+1 layer, where n is an integer greater than or equal to zero. For example, the via zero (V0) layer is the lowest via layer, arranged between the M0 layer and the M1 layer and electrically coupled to the M0 layer and the M1 layer. Other via layers are V1 or V2, etc. The metal layer (e.g., M0 or M1) and via layer (e.g., V0 or V1) on the front side of the substrate are referred to herein as the front metal layer and the front via layer.

[0200] exist Figure 8BIn the example configuration, cell 800B contains M0 conductive patterns 841, 842, 843, and 844 along the corresponding tracks M0_1, M0_2, M0_3, and M0_4 in the M0 layer. Tracks M0_1, M0_2, M0_3, or M0_4 are also referred to herein as M0 tracks. Tracks M0_1, M0_2, M0_3, and M0_4 and the corresponding M0 conductive patterns 841, 842, 843, and 844 extend along the X-axis and are spaced apart from each other along the Y-axis. Figure 8B In the example configuration, tracks M0_1, M0_2, M0_3, and M0_4 are spaced apart from each other along the Y-axis by a spacing p, and coincide with the centerlines of the corresponding M0 conductive patterns 841, 842, 843, and 844. Tracks M0_1, M0_2, M0_3, and M0_4 define the positions in the M0 layer where the M0 conductive patterns are formed to ensure that predetermined design rules are met. The number of four tracks for the M0 conductive patterns above cell 800B is an example. Other numbers of tracks for the M0 conductive patterns above cells are within the scope of various embodiments.

[0201] M0 conductive patterns 841, 842, 843, and 844 are used to electrically couple various devices in cell 800B to the internal circuitry of cell 800B, and / or to the internal circuitry having external circuitry (e.g., to other cells of an IC device). For example, M0 conductive pattern 841 overlaps and is electrically coupled to VD via 839, and M0 conductive pattern 842 overlaps and is electrically coupled to VG via 838. Therefore, M0 conductive pattern 841 is electrically coupled to drain regions 805 and 806 through MD contact structure 837 and VD via 839, and M0 conductive pattern 842 is electrically coupled to gate region 810 through VG via 838. M0 conductive pattern 841 corresponds to... Figure 8A The output node OUT in the M0 conductive pattern 842 corresponds to the output node OUT in the M0 conductive pattern 842. Figure 8A The input node IN in the model. M0 conductive patterns 843 and 844 are unconnected M0 conductive patterns. Other configurations are within the scope of various embodiments.

[0202] In the example, when cell 800B is used as inverter INVB in clock circuit 230, M0 conductive pattern 841 corresponds to clock output 232, and M0 conductive pattern 842 corresponds to clock output 231. In another example, when a transmission gate cell similar to cell 800B is used as transmission gate TG1m, the internal connections of the transmission gate cell are configured as different inputs or outputs from each of the M0 conductive patterns 841-844, such as a clock input for the first clock signal clkb, a clock input for the second clock signal clkbb, a data input for data D, and a data output coupled to node ml_ax or 212. Other configurations are within the scope of various embodiments.

[0203] In some embodiments, unit 800B includes one or more metal layers and via layers on the back side of a substrate for connection to a power supply voltage, internal connection within the device of unit 800B, and / or external connection to other units. Regarding Figure 8C Describe the details of the back metal layer and the back via layer.

[0204] Figure 8C This is a schematic cross-sectional view of the circuit region of an IC device 800C according to some embodiments. The IC device 800C includes one or more units, such as unit 800B.

[0205] like Figure 8C As shown, the IC device 800C includes a substrate 860 on which circuit elements and structures corresponding to one or more units are formed. The substrate 860 has a first side 861 and a second side 862 that are opposite to each other along the thickness direction of the substrate 860 (e.g., along the Z-axis). In at least one embodiment, the first side 861 is referred to as the "upper side," "front side," or "device side," while the second side 862 is referred to as the "lower side" or "back side." In at least one embodiment, the substrate 860 comprises silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor or dielectric materials.

[0206] IC device 800C further includes N-type and P-type dopants added to substrate 860 to correspondingly form NMOS active regions and PMOS active regions. Figure 8C The designation "OD" is used to represent this. In some embodiments, an insulating structure is formed between adjacent active regions. For simplicity, the insulating structure is... Figure 8C Omitted. In at least one embodiment, in Figure 8C The active region in the middle corresponds to about Figure 8B The active regions 801 and 802 described are one or more of them.

[0207] IC device 800C further includes various gate structures above the active region and above at least one of the front side 861 or the back side 862. Figure 8C In the example configuration, the gate structure is indicated by "PO" and is above the active region and above both the front side 861 and the back side 862. In at least one embodiment, the gate structure is above the active region above the front side 861, but not above the active region above the back side 862. One or more gate dielectric layers (not shown) are interposed between the active region and each gate structure. Example materials for single or multiple gate dielectric layers include HfO2 or ZrO2, etc. Example materials for the gate structure include polysilicon or metal, etc. In some embodiments, the gate structure corresponds to as described above. Figure 8B One or more of the gate regions 810, 818, and 819. In at least one embodiment, the gate structure corresponding to the dummy gate region comprises a dielectric material.

[0208] IC device 800C further includes MD contact structures for electrically coupling the source / drain of various transistors in the active region to other circuit elements. In some embodiments, such as regarding Figure 8B The MD contact structure corresponds to one or more of the MD contact structures 835-837. The IC device 800C further includes a VD via and a VG via, which are respectively located on the MD contact structure and the gate structure and are in electrical contact with the MD contact structure and the gate structure.

[0209] The IC device 800C further includes an interconnect structure (also referred to as a "rewiring structure") 868 above the front side 861. The interconnect structure 868 includes, above the VD and VG vias, a plurality of metal layers M0, M1, ... and a plurality of via layers V0, V1, ... arranged alternately in the thickness direction of the substrate 860 (e.g., along the Z-axis). The interconnect structure 868 further includes various interlayer dielectric (ILD) layers (not shown or unlabeled) embedded therein with the metal layers and via layers. The metal layers and via layers of the interconnect structure 868 are used to electrically couple various components or circuits of the IC device 800C to each other and to external circuits. For simplicity, the metal layer and via layer above the M1 layer... Figure 8C The middle part is omitted.

[0210] The IC device 800C further includes a back-side interconnect structure 869 above the back side 862. The back-side interconnect structure 869 includes at least one back-side metal layer, such as a back-side metal zero (BM0 or MO_B) layer, below the back side 862 of the substrate 860. Above the back side 862 of the substrate 860, the MO_B layer is the highest metal layer below the active region or source / drain of the transistor in the IC device 800C, or the metal layer closest to the active region or source / drain of the transistor in the IC device 800C. The conductive pattern in the MO_B layer is coupled to the active region through one or more VD_B vias and / or coupled to the gate structure PO through one or more VG_B vias. In at least one embodiment, the IC device 800C includes one or more other via layers, dielectric layers, and metal layers (not shown) below the MO_B layer to form interconnects in the circuit elements of the IC device 800C and / or to form electrical connections to external circuitry. The via layer and the metal layer below the MO_B layer are sometimes referred to as the back-side via layer and the back-side metal layer. Example materials for the back-side via and the back-side metal layer include metal. Other configurations are within the scope of various embodiments. For simplicity, the dielectric layer, the back-side via layer, and the back-side metal layer below the MO_B layer are... Figure 8C Omitted.

[0211] In some embodiments, regarding Figures 3A to 3H , Figures 5A to 5B , Figures 7A to 7C One or more of the described layouts comprise various units, each of which comprises having information about Figure 8A The layout of PMOS and NMOS transistors is described. In each cell, the PMOS and NMOS transistors are coupled to configure the cell as an inverter, main latch-up circuit, secondary latch-up circuit, or multiplexer, etc. For example, in... Figure 3A In this configuration, the main latch circuit 310 is one unit, the secondary latch circuit 320 is another unit, and the clock circuit 330 is yet another unit. The units are arranged in the aforementioned manner within the layout of the circuit region 300A. A clock network (e.g., electrical connections from the clock circuit to the main latch circuit or the secondary latch circuit) is routed in one or more metal layers and / or via layers of at least one of the interconnect structure 868 or the back-side interconnect structure 869. Regarding... Figures 9A to 9E An example electrical connection is described in the interconnect structure 868 above the front side 861 of the substrate 860. In some embodiments, electrical connections are similarly configured in the back side interconnect structure 869.

[0212] Figures 9A to 9E This is a schematic perspective view of various conductive structures 900A to 900E configured for wiring clock signals according to some embodiments.

[0213] exist Figure 9AIn this embodiment, the conductive structure 900A includes a conductive pattern 905 in the metal layer Mk+1, where k is an integer. The conductive pattern 905 is coupled to the main latch circuit, the sub-latch circuit, and the clock circuit via vias 901, 902, and 903 in the via layer Vk. The physical length of the conductive pattern 905 between vias 901 and 903 is used for the electrical connection supplying a clock signal (e.g., clkb or clkbb) from the clock circuit to the main latch circuit. The physical length of the conductive pattern 905 between vias 902 and 903 is used for the electrical connection supplying a clock signal from the clock circuit to the sub-latch circuit. Compared to the electrical connection supplying a clock signal from the clock circuit to the sub-latch circuit, the electrical connection supplying a clock signal from the clock circuit to the main latch circuit has a larger physical length and a larger time delay. Therefore, in at least one embodiment, improved performance, such as increased speed, can be achieved. In some embodiments, as per […] Figures 3A to 3D , Figure 5A The conductive structure 900A corresponds to electrical connections 311, 312 or electrical connections 313, 314, etc.

[0214] exist Figure 9B In the conductive structure 900B, conductive patterns 905 and 915 are included in the metal layer Mk+1. Conductive pattern 905 is coupled to the main latch circuit and the clock circuit via vias 901 and 903 in the via layer Vk. Conductive pattern 915 is coupled to the secondary latch circuit and the clock circuit via vias 912 and 913 in the via layer Vk. Conductive pattern 905 is used for electrical connections for supplying clock signals from the clock circuit to the main latch circuit, and conductive pattern 915 is used for electrical connections for supplying clock signals from the clock circuit to the secondary latch circuit. The physical length and time delay of conductive pattern 905 for supplying clock signals from the clock circuit to the main latch circuit are greater than the physical length and time delay of conductive pattern 915 for supplying clock signals from the clock circuit to the secondary latch circuit. Therefore, in at least one embodiment, as per [the relevant context]... Figures 3A to 3D , Figure 5A As described above, performance can be improved, for example, by increasing speed. In some embodiments, the conductive structure 900B corresponds to electrical connections 311, 312 or electrical connections 313, 314, etc.

[0215] exist Figure 9C In this structure, conductive structure 900C includes conductive pattern 925 in metal layer Mk+1. Conductive pattern 925 is coupled to sub-latch circuit and clock circuit via vias 922 and 923 in via layer Vk. Conductive pattern 925 provides electrical connections for supplying clock signals from clock circuit to sub-latch circuit.

[0216] The conductive structure 900C further includes a conductive pattern 935 in the metal layer Mk+3. One end of the conductive pattern 935 is coupled to a lower end of the conductive pattern 925 through a via 928 in the via layer Vk+2, the conductive pattern 927 in the metal layer Mk+2, and a via 926 in the via layer Vk+1. The other end of the conductive pattern 935 is coupled to the main latching circuit through a via 929 in the via layer Vk+2, the conductive pattern 930 in the metal layer Mk+2, a via 931 in the via layer Vk+1, the conductive pattern 932 in the metal layer Mk+1, and a via 921 in the via layer Vk. The conductive pattern extends along one of the X-axis and Y-axis in the metal layer Mk+2, while the conductive pattern extends along the other of the X-axis and Y-axis in the metal layers Mk+1 and Mk+3.

[0217] Conductive patterns 925 and 935 together form an electrical connection for supplying a clock signal from the clock circuit to the main latch circuit, the physical length and time delay of which are greater than the physical length and time delay of the electrical connection for supplying a clock signal from the clock circuit to the secondary latch circuit. Therefore, in at least one embodiment, improved performance, such as increased speed, can be achieved. In some embodiments, as per [reference to...] Figure 3E , Figure 3G , Figure 5B The conductive structure 900C corresponds to electrical connections 351, 352, 353, 354, 551, 552, or 553, 554.

[0218] exist Figure 9D In this circuit, conductive structure 900D provides an electrical connection for supplying a clock signal from the clock circuit to the main latch circuit, the connection having redundant wiring. Instead of wiring a conductive pattern along the shortest path 942 in metal layer Mk+1 to electrically couple the clock circuit and the main latch circuit, conductive structure 900D includes redundant wiring.

[0219] In the conductive structure 900D, the clock circuit is coupled to a via 943 in via layer Vk, then to a conductive pattern 944 in metal layer Mk+1, then to a via 945 in via layer Vk+1, and then to one end of a conductive pattern 946 in metal layer Mk+2. The other end of conductive pattern 946 is coupled to a via 947 in via layer Vk+2, then to one end of a conductive pattern 948 in metal layer Mk+3. The other end of conductive pattern 948 is coupled to a via 949 in via layer Vk+2, then to one end of a conductive pattern 950 in metal layer Mk+2. The other end of conductive pattern 950 is coupled to a via 951 in via layer Vk+1, then to a conductive pattern 952 in metal layer Mk+1, and then to the main latch circuit through a via 941 in via layer Vk. In some embodiments, conductive pattern 948 is in metal layer Mk+1, and vias 947 and 949 are in via layer Vk+1.

[0220] The physical length of conductive pattern 948 is approximately the same as the physical length of the shortest path 942, and the physical lengths of conductive patterns 946 and 950 provide redundant wiring to increase the physical length and time delay of the electrical connection from the clock circuit to the main latch circuit. Therefore, in at least one embodiment, improved performance, such as increased speed, can be achieved. In some embodiments, as per [reference to...] Figure 3D , Figure 3F , Figure 3H The conductive structure 900D corresponds to one or more of the electrical connections 341, 361, and 363.

[0221] exist Figure 9E In this structure, conductive structure 900E includes conductive pattern 965 in metal layer Mk+1. Conductive pattern 965 is coupled to sub-latch circuit and clock circuit via vias 962 and 963 in via layer Vk. Conductive pattern 965 provides electrical connections for supplying clock signals from clock circuit to sub-latch circuit.

[0222] The conductive structure 900E further includes a conductive pattern 975 in the metal layer Mk+2. One end of the conductive pattern 975 is coupled to a lower end of the conductive pattern 965 through a via 966 in the via layer Vk+1. The other end of the conductive pattern 975 is coupled to the main latching circuit through a via 968 in the via layer Vk+1, a conductive pattern 969 in the metal layer Mk+1, and a via 961 in the via layer Vk.

[0223] Conductive patterns 965 and 975 together form an electrical connection for supplying a clock signal from the clock circuit to the main latch circuit, the physical length and time delay of which are greater than the physical length and time delay of the electrical connection for supplying a clock signal from the clock circuit to the secondary latch circuit. Therefore, in at least one embodiment, improved performance, such as increased speed, can be achieved. In some embodiments, as per [reference to...] Figure 7B , Figure 7C The conductive structure 900E corresponds to electrical connection 721 or electrical connections 791 and 792.

[0224] Figure 10A This is a flowchart of a method 1000A for generating a layout and manufacturing an IC device using the layout, according to some embodiments.

[0225] According to some embodiments, method 1000A is implementable, for example using EDA system 1100 ( Figure 11 (discussed below) and integrated circuit manufacturing system 1200 ( Figure 12 (Discussed below). Examples of layouts for method 1000A include the layouts disclosed herein. Examples of IC devices manufactured according to method 1000A include the IC devices disclosed herein. Figure 10AIn the example, method 1000A includes operations 1002 and 1004.

[0226] In operation 1002, a layout is generated, the layout containing representations as shown regarding... Figures 3A to 3H , Figures 5A to 5B , Figures 7A to 7C or Figure 8B Patterns and other objects of one or more circuit regions as described above. The following section discusses... Figure 10B Let's discuss Operation 1002 in more detail. The process proceeds from Operation 1002 to Operation 1004.

[0227] In operation 1004, based on the layout diagram, at least one of the following steps is performed: (A) performing one or more photolithography exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating one or more components in a layer of an IC device. The following section discusses... Figure 10C Let's discuss operation 1004 in more detail.

[0228] Figure 10B This is a flowchart of a layout generation method 1000B according to some embodiments. More specifically, according to one or more embodiments, Figure 10B The flowchart illustrates additional operations, which can be implemented in... Figure 10A An example of the program in operation 1002. Figure 10B In the example, operation 1002 includes operations 1012 and 1014.

[0229] In operation 1012, the main latch circuit, the secondary latch circuit, and the clock circuit are placed in the layout, for example, in a placement operation using an APR tool or system. For example, each of the main latch circuit, the secondary latch circuit, and the clock circuit is a cell extracted from one or more cell libraries. Alternatively, a combination of more than one of the main latch circuit, the secondary latch circuit, and the clock circuit is contained within cells extracted from one or more cell libraries. Regarding... Figures 3A to 3H , Figures 5A to 5B , Figures 7A to 7C Describe the placement of the main latch circuit, the secondary latch circuit, and the clock circuit in a layout in one or more ways.

[0230] In operation 1014, wiring is performed to electrically couple the clock circuit to the main latch circuit and the sub-latch circuit, for example, during the wiring operation using an APR tool or system. As a result of the wiring, the first electrical connection from the clock circuit to the main latch circuit is physically longer and therefore has a greater time delay compared to the second electrical connection from the clock circuit to the sub-latch circuit. Therefore, in at least one embodiment, improved performance, such as increased speed, can be achieved. In at least one embodiment, the resulting IC device layout is stored in a non-transitory computer-readable medium.

[0231] In some embodiments, such as regarding Figures 3A to 3D , Figure 5A , Figure 7A , Figure 7B In the placement operation, the clock circuit is physically placed such that the secondary latch circuit is closer to the clock circuit than the primary latch circuit. Therefore, when wiring is performed, according to some embodiments, it is readily apparent that the electrical connection from the clock circuit to the primary latch circuit is physically longer and has a greater time delay compared to the electrical connection from the clock circuit to the secondary latch circuit.

[0232] In some embodiments, even when the placement operation is performed with the clock circuit unnecessarily positioned so that the secondary latch circuit is closer to the clock circuit than the primary latch circuit, the wiring operation may result in a physically longer electrical connection from the clock circuit to the primary latch circuit with a larger time delay compared to the electrical connection from the clock circuit to the secondary latch circuit. In at least one embodiment, as per [reference to...] Figures 3A to 3E , Figure 3G , Figures 5A to 5B , Figures 7A to 7C The electrical connection from the clock circuit to the main latch circuit passes through the area of ​​the secondary latch circuit before reaching the main latch circuit to increase the distance or electrical path from the clock circuit to the main latch circuit. In at least one embodiment, as per [the relevant context]... Figure 3F , Figure 3H The method involves adding redundant wiring between the clock circuit and the main latch to increase the distance or electrical path from the clock circuit to the main latch circuit.

[0233] Figure 10C This is a flowchart of a method 1000C for manufacturing one or more components of a layout-based IC device according to some embodiments. More specifically, according to one or more embodiments, Figure 10C The flowchart illustrates additional operations that can be implemented in... Figure 10A An example of the program in operation 1004.

[0234] In operation 1022, in the FEOL process, for example, regarding... Figures 3A to 3H , Figures 5A to 5B , Figures 7A to 7C , Figure 8C The aforementioned method involves forming multiple transistors of a flip-flop circuit on a substrate.

[0235] For example, the manufacturing process begins with a substrate (e.g., substrate 860). In at least one embodiment, substrate 860 comprises a silicon substrate. In at least one embodiment, substrate 860 comprises silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor materials. In some embodiments, a plurality of active regions are formed in substrate 860. An insulating structure (not shown) is formed in substrate 860, for example by etching corresponding regions of substrate 860 and filling the etched regions with an insulating material.

[0236] Various transistors are formed on substrate 860 in the front-end process. For example, a gate dielectric is deposited on substrate 860 having an active region. Example materials for the gate dielectric include, but are not limited to, silicon oxide (e.g., thermally generated silicon oxide) or high-k dielectrics (e.g., metal oxides, etc.). Example high-k dielectrics include, but are not limited to, HfO2, Ta2O5, Al2O3, TiO2, TiN, ZrO2, SnO, or SnO2, etc. In some embodiments, the gate dielectric is deposited on substrate 860 by atomic layer deposition (ALD) or other suitable techniques. A gate material is deposited or formed on the gate dielectric. Example materials for the gate material include, but are not limited to, polysilicon, metals, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and / or other suitable conductive materials. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., are used. Deposition (PVD or sputtering), electroplating, ALD, and / or other suitable processes are used to deposit the gate material. The gate dielectric and gate material are patterned in multiple ways, each gate structure comprising a gate electrode and an underlying gate dielectric layer. In some embodiments, the patterning of the gate dielectric and gate material includes photolithography operations.

[0237] By using a masked gate structure to perform ion implantation in various regions adjacent to the active region of the gate structure, N+ implantation regions are obtained, contained within a P-type well or P-type substrate to form an N-type transistor, and / or source / drain regions of a P+ implantation region in an N-type well or N-type substrate to form a P-type transistor. Other types of implantation and / or wells are within the scope of various embodiments. In some embodiments, spacers (not shown) are deposited around each gate structure. Correspondingly, various MD contact structures and / or VD / VG vias are formed, for example, by deposition of conductive material in the space above the source / drain regions and between the spacers and / or gate structures.

[0238] In operation 1024, in the BEOL process, as regarding... Figures 3A to 3H , Figures 5A to 5B , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9E The process involves repeatedly performing an damascene process to fabricate a redistribution structure on and / or under a substrate. The redistribution structure electrically couples multiple transistors to a flip-flop circuit, wherein a first electrical connection from the clock circuit to the main latch circuit is longer than a second electrical connection from the clock circuit to the secondary latch circuit.

[0239] For example, after the front-end process, a back-end process is performed to form a redistribution structure 868 on the substrate 860 and / or a back-side redistribution structure 869 below the substrate 860. In at least one embodiment, fabricating the redistribution structure 868 includes successively depositing a metal layer and a via layer. The metal layer and via layer respectively include a metal layer M0 or M1 and a via layer V0 or V1. In at least one embodiment, the redistribution structure 868 is fabricated layer by layer upwards from the substrate 860, for example by repeatedly performing a damascene process. In such a damascene process, a dielectric layer is deposited on the substrate 860 having various transistors and contact features formed thereon. The dielectric layer is patterned to form a damascene structure having a bottom via with conductive vias corresponding to the via layer Vj to be formed later, and a top recess feature corresponding to the conductive pattern of the metal layer Mj+1 to be formed later, where j is an integer. An example patterning process for forming the damascene structure includes two or more photolithography patterning and anisotropic etching steps to first form the bottom via and then form the top recess feature. Conductive material is deposited on substrate 860 to fill the damascene structure to obtain conductive vias in via layer Vj and overlay conductive patterns in metal layer Mj+1. The damascene process is performed one or more times to successively form vias and conductive patterns in the higher via layers and metal layers of the redistribution structure 868 until the top metal layer is completed. The backside redistribution structure 869 is fabricated in a similar manner.

[0240] In the manufactured rewiring structure 868 and / or back-side rewiring structure 869, the first electrical connection entity of the main latch circuit from the clock circuit to the flip-flop circuit is longer than the second electrical connection of the secondary latch circuit from the clock circuit to the flip-flop circuit. Regarding Figures 9A to 9E An example electrical connection with increased physical length is described in a rewiring structure. In at least one embodiment, improved performance, such as increased speed, can be achieved.

[0241] Figure 10D This is a flowchart of a method 1000D for operating a flip-flop circuit according to some embodiments. In some embodiments, the flip-flop circuit corresponds to... Figures 2A to 2F The flip-flop circuit 200 is described.

[0242] In operation 1032, clock pulses are supplied from the clock circuit to the main latch circuit and the secondary latch circuit. For example, regarding... Figures 2A to 2F The clock circuit 230 supplies clock pulses 270 to the main latch circuit 210 and the secondary latch circuit 220.

[0243] In operation 1034, in the main latch circuit, in response to the first edge of the clock pulse, the input data is latched, and in response to the second edge of the clock pulse, the input data of the output latch is sent as intermediate data to the secondary latch circuit. For example, regarding... Figures 2A to 2FIn response to the rising edge 271 of the clock pulse 270, transmission gate TG1m is turned on (and transmission gate TG2m is turned off) to transmit input data D to data holding circuit 214 to latch input data D through main latch circuit 210. Then, in response to the falling edge 272 of the clock pulse 270, transmission gate TG2m is turned on (and transmission gate TG1m is turned off) to output latched input data as intermediate data to sub-latch circuit 220.

[0244] In operation 1036, in the secondary latch circuit, in response to the first edge of the clock pulse, the intermediate data of the previous latch is output as output data, and in response to the second edge of the clock pulse, the latch receives the intermediate data of the autonomous latch circuit.

[0245] For example, regarding Figures 2A to 2F In response to the rising edge 271 of clock pulse 270, transmission gate TG2s is turned on (and transmission gate TG1s is turned off) to output the previously latched intermediate data as output data in output Q. Then, in response to the falling edge 272 of clock pulse 270, transmission gate TG1s is turned on (and transmission gate TG2s is turned off) to transmit the intermediate data received from the autonomous latching circuit 210 to the data holding circuit 224 to latch the received intermediate data therein.

[0246] After the clock pulse arrives at the secondary latch circuit, the clock pulse arrives at the primary latch circuit. For example, regarding... Figures 2A to 2F The arrival of the clock pulse 270 in the secondary latching circuit 220 (similar to...) Figure 2C After the middle part), the clock pulse 270 arrives at the main latch circuit 210. Figure 2C (The lower part of the document). The late arrival of the clock pulse at the main latch circuit is caused by a large time delay in the electrical connection from the clock circuit supplying the clock signal to the main latch circuit. In at least one embodiment, as described herein, this arrangement reduces the setup time of the flip-flop circuit and improves performance.

[0247] The method includes example operations, but these example operations do not necessarily need to be performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or deleted according to the spirit and scope of the embodiments disclosed herein. Embodiments combining different features and / or different embodiments are within the scope of this disclosure and will be apparent to those skilled in the art upon reading this disclosure.

[0248] In some embodiments, at least one of the methods discussed herein is performed wholly or partially by at least one EDA system. In some embodiments, the EDA system may be used as part of the design room of the IC manufacturing system discussed below.

[0249] Figure 11This is a block diagram of an electronic design automation (EDA) system 1100 according to some embodiments.

[0250] In some embodiments, EDA system 1100 includes an APR system. The methods described herein, based on design layout diagrams of one or more embodiments, indicate that wire routing arrangements are feasible, for example, using EDA system 1100 according to some embodiments.

[0251] In some embodiments, the EDA system 1100 is a general-purpose computing device comprising a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. Among other things, the storage medium 1104 is encoded (e.g., stored) using computer program code 1106 (e.g., a set of executable instructions). Execution of the code 1106 represents (at least partially) an EDA tool implemented by the hardware processor 1102, the EDA tool carrying out some or all of a method, such as those discussed herein with respect to one or more embodiments (hereinafter, referred to as the processes and / or methods).

[0252] Processor 1102 is electrically coupled to computer-readable storage medium 1104 via bus 1108. Processor 1102 is also electrically coupled to I / O interface 1110 via bus 1108. Network interface 1112 is also electrically connected to processor 1102 via bus 1108. Network interface 1112 is connected to network 1114, enabling processor 1102 and computer-readable storage medium 1104 to be connected to external components via network 1114. Processor 1102 is used to execute computer program code 1106 encoded in computer-readable storage medium 1104, such that system 1100 can be used to perform some or all of the process and / or method. In one or more embodiments, processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0253] In one or more embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1104 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 1104 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0254] In one or more embodiments, storage medium 1104 stores computer program code 1106, which causes system 1100 (where such execution represents (at least partially) an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, storage medium 1104 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 1104 stores a cell library 1107 containing cells as disclosed herein.

[0255] EDA system 1100 includes I / O interface 1110. I / O interface 1110 is coupled to external circuitry. In one or more embodiments, I / O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for exchanging information and commands with processor 1102.

[0256] EDA system 1100 also includes a network interface 1112 coupled to processor 1102. Network interface 1112 allows system 1100 to communicate with network 1114, to which one or more other computer systems are connected. Network interface 1112 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the described process and / or method are implemented in two or more systems 1100.

[0257] System 1100 receives information via I / O interface 1110. The information received via I / O interface 1110 includes instructions, data, design rules, standard cell libraries, and / or one or more other parameters for processing by processor 1102. The information is transferred to processor 1102 via bus 1108. EDA system 1100 receives information about the UI via I / O interface 1110. The information is stored in computer-readable media 1104, which serves as user interface (UI) 1142.

[0258] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application, which is part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application, which is part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by EDA system 1100. In some embodiments, a layout diagram including standard cells uses, for example... The tool or another suitable layout generation tool can be used to generate the layout. It can be purchased from CADENCEDESIGN SYSTEMS.

[0259] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), etc.

[0260] Figure 12 This is a block diagram of an IC manufacturing system 1200 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1200 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0261] exist Figure 12In this IC manufacturing system 1200, entities such as design room 1220, mask room 1230, and IC fabricator (fab) 1250 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 1260. The entities in system 1200 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1220, mask room 1230, and IC fab 1250 are owned by a single larger company. In some embodiments, two or more of design room 1220, mask room 1230, and IC fab 1250 coexist in a shared facility and use shared resources.

[0262] Design studio (or design team) 1220 generates IC design layout 1222. IC design layout 1222 contains various geometric patterns designed for IC device 1260. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that form various components of the IC device 1260 to be manufactured. Various layers are combined to form various IC features. For example, portions of IC design layout 1222 include various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which are formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design studio 1220 implements suitable design procedures to form IC design layout 1222. These design procedures include logic design, physical design, or placement and routing, or one or more of these. IC design layout 1222 exists in one or more data files containing information about the geometric patterns. For example, IC design layout 1222 may be represented in GDSII or DFII file format.

[0263] Mask chamber 1230 includes data preparation 1232 and mask fabrication 1244. Mask chamber 1230 fabricates one or more masks 1245 using an IC design layout 1222. The masks 1245 are intended for use in fabricating various layers of an IC device 1260 according to the IC design layout 1222. Mask chamber 1230 performs mask data preparation 1232, in which the IC design layout 1222 is converted into a representative data file (RDF). Mask data preparation 1232 provides the RDF to mask fabrication 1244. Mask fabrication 1244 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 1245 or a semiconductor wafer 1253. The design layout 1222 is manipulated by mask data preparation 1232 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1250. Figure 12 In this paper, mask data preparation 1232 and mask manufacturing 1244 are described as separate elements. In some embodiments, mask data preparation 1232 and mask manufacturing 1244 may be collectively referred to as mask data preparation.

[0264] In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which uses lithography techniques to compensate for aberrations, such as those caused by diffraction, interference, and other process effects. The OPC adjusts the IC design layout diagram 1222. In some embodiments, mask data preparation 1232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-change masks, and other suitable techniques or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats the OPC as an inverse image problem.

[0265] In some embodiments, mask data preparation 1232 includes a mask rule checker (MRC) that checks the IC design layout 1222, which has undergone processing in the OPC, using a set of mask generation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for constraints during mask manufacturing 1244, which may eliminate portions of the modifications performed by the OPC to satisfy the mask generation rules.

[0266] In some embodiments, mask data preparation 1232 includes lithography process checking (LPC), which simulates the processes performed by IC fab 1250 to manufacture IC device 1260. The LPC simulates this process based on IC design layout 1222 to create a simulated manufactured element, such as IC device 1260. The processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial imaging contrast, depth of focus (DOF), mask error enhancement factor (MEEF), and other suitable factors, or combinations thereof. In some embodiments, after a simulated manufactured device has been created by the LPC, if the simulated device is not close enough to the shape to meet design rules, the OPC and / or MRC are repeated to further improve the IC design layout 1222.

[0267] It should be understood that, for clarity, the above description of masking data preparation 1232 has been simplified. In some embodiments, data preparation 1232 includes additional features such as logic operations (LOPs) to modify the IC design layout 1222 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1222 during data preparation 1232 can be performed in various different sequences.

[0268] After mask data preparation 1232 and during mask manufacturing 1244, a mask 1245 or mask group 1245 is manufactured based on a modified IC design layout 1222. In some embodiments, mask manufacturing 1244 includes performing one or more lithography exposures based on the IC design layout 1222. In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams is used to pattern the mask (photomask or master mask) 1245 based on the modified IC design layout 1222. The mask 1245 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1245. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1245 comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1245 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1245, various features in a pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1244 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1253, in etching processes to form various etched regions in semiconductor wafer 1253, and / or in other suitable processes.

[0269] IC fab 1250 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC fab 1250 is a semiconductor manufacturing plant. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end-of-line, BEOL) for interconnecting and packaging the IC products, and a third manufacturing facility for providing other services to the manufacturing company.

[0270] IC fab 1250 includes a wafer fabrication tool 1252 for performing various fabrication operations on a semiconductor wafer 1253 such that an IC device 1260 is fabricated according to a mask (e.g., mask 1245). In various embodiments, the fabrication tool 1252 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0271] IC fab 1250 is used to fabricate IC device 1260 using mask 1245 manufactured by mask chamber 1230. Thus, IC fab 1250 is used at least indirectly to fabricate IC device 1260 using IC design layout 1222. In some embodiments, semiconductor wafer 1253 is fabricated using IC fab 1250 to form IC device 1260 via mask 1245. In some embodiments, IC fabrication includes performing one or more lithography exposures at least indirectly based on IC design layout 1222. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1253 further includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0272] In some embodiments, an integrated circuit device includes a main latch circuit including a first clock input and a data output, a secondary latch circuit including a second clock input and a data input, the data input being electrically coupled to the data output of the main latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input via a first electrical connection having a first time delay, the first time delay being between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input via a second electrical connection having a second time delay, the second time delay being between the clock circuit and the second clock input. The first time delay is longer than the second time delay. In some embodiments, the first electrical connection is physically longer than the second electrical connection. In some embodiments, the secondary latch circuit is physically closer to the clock circuit than the main latch circuit. In some embodiments, the secondary latch circuit is physically located between the clock circuit and the main latch circuit. In some embodiments, the clock circuit includes a first clock output for outputting a first clock signal and a second clock output for outputting a second clock signal, the second clock signal being inverted compared to the first clock signal. The first clock output is electrically coupled to a first clock input and a second clock input respectively via a first electrical connection and a second electrical connection. The main latch circuit further includes a third clock input, the third clock input being electrically coupled to the second clock output via a third electrical connection. The secondary latch circuit further includes a fourth clock input, the fourth clock input being electrically coupled to the second clock output via a fourth electrical connection. In some embodiments, the third electrical connection is configured to have a third time delay, the third time delay being between the clock circuit and the third clock input. The fourth electrical connection is configured to have a fourth time delay, the fourth time delay being between the clock circuit and the fourth clock input. The third time delay is longer than the fourth time delay. In some embodiments, the clock circuit includes a first circuit having a first clock output for outputting a first clock signal at the first clock output, and a second circuit having a second clock output for outputting a second clock signal at the second clock output. In some embodiments, the sub-latch circuit is physically located between the main latch circuit and the first circuit, and the first circuit is physically located between the sub-latch circuit and the second circuit. In some embodiments, the first circuit is physically located between the main latch circuit and the sub-latch circuit, and the sub-latch circuit is physically located between the first circuit and the second circuit. In some embodiments, the main latch circuit is physically located between the first circuit and the sub-latch circuit, and the sub-latch circuit is physically located between the main latch circuit and the second circuit. In some embodiments, the first electrical connection includes: a second electrical connection extending from the clock circuit to the sub-latch circuit, and a third electrical connection series-coupled to the second electrical connection, and the third electrical connection extending from the sub-latch circuit to the main latch circuit. In some embodiments, the clock circuit is physically located between the main latch circuit and the sub-latch circuit.In some embodiments, the integrated circuit device further includes a plurality of main latch circuits; a plurality of secondary latch circuits; a first clock bus electrically coupled to the main latch circuits; and a second clock bus electrically coupled to the secondary latch circuits. The main latch circuits and secondary latch circuits are configured together as a plurality of flip-flop circuits, the flip-flop circuits being connected in series and electrically coupled to each other. Each secondary latch circuit in the secondary latch circuits has a data input electrically coupled to a data output corresponding to a main latch circuit in the main latch circuits, forming a corresponding flip-flop circuit in the flip-flop circuits. In some embodiments, the main latch circuits are physically arranged in a first row along a first direction, the secondary latch circuits are physically arranged in a second row along the first direction, and in a second direction transverse to the first direction, the second row of secondary latch circuits is located between the clock circuits and the first row of main latch circuits. In some embodiments, the primary latch circuit is physically arranged in a first row along a first direction, and the secondary latch circuit is physically arranged in a second row along the first direction. In a second direction transverse to the first direction, the clock circuit is physically located between the first row of the primary latch circuit and the second row of the secondary latch circuit. A first clock bus and a second clock bus extend along the first direction. A first electrical connection includes: a second electrical connection extending along the second direction from the clock circuit to the second clock bus; and a third electrical connection, series-coupled to the second electrical connection, extending along the second direction from the second clock bus to the first clock bus. In some embodiments, the primary latch circuit is physically adjacent to the secondary latch circuit in a first direction, and the clock circuit is physically adjacent to the secondary latch circuit in a second direction transverse to the first direction.

[0273] In some embodiments, a system for designing an integrated circuit device includes at least one processor and at least one memory storing computer program code for one or more programs. When the at least one processor executes the computer program code stored in the at least one memory, the computer program code and the at least one processor cause the system to execute and generate a layout of an integrated circuit device, the layout being stored in a non-transitory computer-readable medium. Generating the layout includes: placing a main latch circuit, a secondary latch circuit, and a clock circuit in the layout, and performing wiring to electrically couple the clock circuit to the main latch circuit and the secondary latch circuit. In the wiring, a first electrical connection wiring extends from the clock circuit to the main latch circuit, the first electrical connection being longer than a second electrical connection, and a second electrical connection wiring extends from the clock circuit to the secondary latch circuit. In some embodiments, placement includes placing the clock circuit, with the secondary latch circuit physically closer to the clock circuit than the main latch circuit.

[0274] In some embodiments, a method of operating an integrated circuit device includes supplying a clock pulse from a clock circuit to a main latch circuit and a secondary latch circuit. The method further includes, in the main latch circuit, latching input data in response to a first edge of the clock pulse, and outputting the latched input data as intermediate data to the secondary latch circuit in response to a second edge of the clock pulse. The method further includes, in the secondary latch circuit, outputting previously latched intermediate data as output data in response to the first edge of the clock pulse, and receiving intermediate data from the primary latch circuit in response to the second edge of the clock pulse. After the clock pulse arrives at the secondary latch circuit, the clock pulse arrives at the main latch circuit. In some embodiments, each of the main latch circuit and the sub-latch circuit includes a transmission gate and a data holding circuit coupled to the transmission gate. The transmission gate of the main latch circuit responds to the on and off states corresponding to the first and second edges of a clock pulse, and the transmission gate of the sub-latch circuit responds to the on and off states corresponding to the first and second edges of a clock pulse. The transmission gates of both the main latch circuit and the sub-latch circuit are turned on at an intermediate stage, which is between the arrival of the second edge of the clock pulse of the sub-latch circuit and the arrival of the clock pulse of the main latch circuit after the second edge of the clock pulse.

[0275] The foregoing has outlined features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, characterized in that, Include: A main latch circuit includes a first clock input and a data output; A latching circuit includes a second clock input and a data input, the data input being electrically coupled to the data output of the main latching circuit; as well as One clock circuit, in The clock circuit is electrically coupled to the first clock input via a first electrical connection, the first electrical connection having a first time delay, the first time delay being between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input via a second electrical connection, the second electrical connection being configured to have a second time delay, the second time delay being between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

2. The integrated circuit device as claimed in claim 1, characterized in that, The first electrical connection entity is longer than the second electrical connection.

3. The integrated circuit device as claimed in claim 1, characterized in that, The secondary latch circuit is physically closer to the clock circuit than the primary latch circuit.

4. The integrated circuit device as claimed in claim 1, characterized in that, The secondary latch circuit is physically located between the clock circuit and the primary latch circuit.

5. The integrated circuit device as claimed in claim 1, characterized in that, The clock circuit includes: A first clock output, used to output a first clock signal, and A second clock output is provided to output a second clock signal that is inverted compared to the first clock signal. The first clock output is electrically coupled to the first clock input and the second clock input via the first electrical connection and the second electrical connection, respectively. The main latch circuit further includes a third clock input, which is electrically coupled to the second clock output via a third electrical connection. The secondary latching circuit further includes a fourth clock input, which is electrically coupled to the second clock output via a fourth electrical connection.

6. The integrated circuit device as claimed in claim 5, characterized in that, The third electrical connection is configured to have a third time delay, which is located between the clock circuit and the third clock input. The fourth electrical connection is configured to have a fourth time delay, the fourth time delay being between the clock circuit and the fourth clock input, and The third time delay is longer than the fourth time delay.

7. The integrated circuit device as claimed in claim 5, characterized in that, The clock circuit includes: A first circuit having the first clock output and for outputting the first clock signal at the first clock output, and A second circuit having the second clock output and used to output the second clock signal at the second clock output.

8. The integrated circuit device as claimed in claim 7, characterized in that, The secondary latching circuit is physically located between the primary latching circuit and the first circuit, and The first circuit entity is located between the secondary latching circuit and the second circuit.

9. The integrated circuit device as claimed in claim 7, characterized in that, The first circuit entity is located between the main latch circuit and the secondary latch circuit, and The secondary latching circuit is physically located between the first circuit and the second circuit.

10. The integrated circuit device as claimed in claim 7, characterized in that, The main latch circuit is physically located between the first circuit and the secondary latch circuit, and The secondary latch circuit is physically located between the primary latch circuit and the second circuit.

11. The integrated circuit device as claimed in claim 1, characterized in that, The first electrical connection includes: The second electrical connection extends from the clock circuit to the secondary latch circuit, and A third electrical connection is connected in series with the second electrical connection, and the third electrical connection extends from the secondary latch circuit to the primary latch circuit.

12. The integrated circuit device as claimed in claim 11, characterized in that, The clock circuit is physically located between the main latch circuit and the secondary latch circuit.

13. The integrated circuit device as claimed in claim 1, characterized in that, Further includes: Multiple master latch circuits, including the master latch circuit; Multiple secondary latching circuits, including the secondary latching circuit; A first clock bus, electrically coupled to the first electrical connection of the plurality of master latch circuits; as well as A second clock bus, electrically coupled to the second electrical connection of the plurality of sub-latch circuits; in The plurality of main latching circuits and the plurality of secondary latching circuits are configured together as a plurality of flip-flop circuits, which are electrically coupled in series with each other. Each of the plurality of secondary latching circuits has a data input electrically coupled to a data output of a corresponding primary latching circuit in the plurality of primary latching circuits, thereby forming a corresponding flip-flop circuit in the plurality of flip-flop circuits.

14. The integrated circuit device as claimed in claim 13, characterized in that, The plurality of master latch circuits are physically arranged in a first row along a first direction. The plurality of sub-latch circuits are physically arranged in a second row along the first direction, and In a second direction transverse to the first direction, the second row of the plurality of secondary latching circuits is located between the clock circuit and the first row of the plurality of primary latching circuits.

15. The integrated circuit device as claimed in claim 13, characterized in that, The plurality of master latch circuits are physically arranged in a first row along a first direction. The plurality of sub-latch circuits are physically arranged in a second row along the first direction. In a second direction transverse to the first direction, the clock circuit entity is located between the first row of the plurality of main latch circuits and the second row of the plurality of sub-latch circuits. The first clock bus and the second clock bus extend along the first direction, and The first electrical connection includes: The second electrical connection extends along the second direction from the clock circuit to the second clock bus, and A third electrical connection is connected in series with the second electrical connection and extends along the second direction from the second clock bus to the first clock bus.

16. The integrated circuit device as claimed in claim 1, characterized in that, The main latch circuit is physically adjacent to the secondary latch circuit in a first direction, and The clock circuit is physically adjacent to the latching circuit in a second direction, which is transverse to the first direction.

17. A system for designing integrated circuit devices, characterized in that, Include: At least one processor; and At least one memory unit stores computer program code for one or more programs. Wherein, when the at least one processor executes the computer program code stored in the at least one memory, the computer program code and the at least one processor cause the system to generate a layout of an integrated circuit device, the layout being stored in a non-transitory computer-readable medium, the generation of the layout comprising: In this layout, a main latch circuit, a secondary latch circuit, and a clock circuit are placed; and The wiring is executed to electrically couple the clock circuit to the main latch circuit and the secondary latch circuit. In this wiring configuration, a first electrical connection wiring extends from the clock circuit to the main latching circuit, and the first electrical connection entity is longer than a second electrical connection wiring, which extends from the clock circuit to the secondary latching circuit.

18. The system as claimed in claim 17, characterized in that, The placement includes placing the clock circuit, with the secondary latch circuit physically closer to the clock circuit than the primary latch circuit.

19. A method of operating an integrated circuit device, characterized in that, Include: A clock pulse is supplied from a clock circuit to a main latch circuit and a secondary latch circuit; In this main latch circuit, In response to a first edge of the clock pulse, the input data is latched, and In response to a second edge of the clock pulse, the input data of the output latch is sent as intermediate data to the secondary latch circuit; as well as In this latching circuit, In response to the first edge of the clock pulse, the previously latched intermediate data is output as output data, and In response to the second edge of the clock pulse, the latch receives intermediate data from the main latch circuit. After the clock pulse arrives at the secondary latch circuit, the clock pulse arrives at the primary latch circuit.

20. The method as described in claim 19, characterized in that, Each of the main latch circuit and the secondary latch circuit includes a transmission gate and a data holding circuit coupled to the transmission gate. The transmission gate of the main latch circuit responds to the on and off states corresponding to the first and second edges of the clock pulse. The transmission gate of the secondary latching circuit responds to the on and off states corresponding to the first and second edges of the clock pulse, and The transmission gates of both the main latch circuit and the secondary latch circuit are turned on at an intermediate stage, which is between the arrival of the second edge of the clock pulse of the secondary latch circuit and the arrival after the second edge of the clock pulse of the main latch circuit.

Images