Flash memory device and method of manufacturing the same

Abstract

The application provides a flash memory device and a preparation method thereof, and the preparation method comprises the following steps: providing a substrate, wherein a floating gate structure layer and a word line are formed on the substrate; a sidewall of the word line and between the word line and the substrate are formed with a tunneling oxide layer; forming an isolation layer, wherein the isolation layer covers the surface of the floating gate structure layer, the top of the word line and the tunneling oxide layer located on the sidewall of the word line; forming a control gate layer, wherein the control gate layer covers the surface of the isolation layer; etching the control gate layer, the isolation layer and the floating gate structure layer by using a self-aligned etching process to form a control gate, an isolation structure and a floating gate, wherein the isolation structure is L-shaped and comprises an isolation horizontal part and an isolation vertical part which are connected, the isolation horizontal part is located between the floating gate and the control gate, and the isolation vertical part is located between the tunneling oxide layer on the sidewall of the word line and the control gate. The application forms the control gate by using the self-aligned etching process, and the problem of the sharp corner at the top end of the control gate is avoided. The isolation horizontal part and the isolation vertical part are made by using an integrated process, and the process is simplified.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically relating to a flash memory device and its preparation method. Background Technology

[0002] Flash memory has become a widely used volatile memory element in personal computers and electronic devices because it can perform multiple data storage, retrieval, and erasure operations, and the stored data will not be lost after power is turned off.

[0003] In flash memory manufacturing, the morphology of the control gate plays a crucial role in the product's performance. Currently, in flash memory manufacturing processes, the top of the control gate is prone to forming sharp corners, which affects the overall performance of the flash memory; moreover, the manufacturing process is relatively complex. Summary of the Invention

[0004] The purpose of this invention is to provide a flash memory device and its fabrication method. This invention takes a novel approach by forming the control gate using a self-aligned etching process, thus avoiding the problem of sharp corners at the control gate tip. The horizontal and vertical isolation portions are fabricated as a single unit, simplifying the process.

[0005] This invention provides a method for fabricating a flash memory device, comprising:

[0006] A substrate is provided on which a floating gate structure layer and word lines are formed, the word lines being distributed along a direction perpendicular to the substrate, and a portion of the word lines being embedded in the floating gate structure layer; a tunneling oxide layer is formed on the sidewalls of the word lines and between the word lines and the substrate.

[0007] An isolation layer is formed, which covers the surface of the floating grid structure layer, the top of the word line, and the tunneling oxide layer located on the sidewall of the word line;

[0008] A control gate layer is formed, which covers the surface of the isolation layer;

[0009] The control gate layer, the isolation layer, and the floating gate structure layer are etched using a self-aligned etching process to form a control gate, an isolation structure, and a floating gate. The isolation structure is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion. The control gate fills the L-shaped space of the isolation structure. The horizontal isolation portion is located between the floating gate and the control gate, and the vertical isolation portion is located between the tunneling oxide layer on the word line sidewall and the control gate.

[0010] Furthermore, the floating gate structure layer includes a floating gate oxide layer and a floating gate layer sequentially located on the substrate.

[0011] Furthermore, the substrate is provided, specifically comprising:

[0012] The floating gate structure layer and the sacrificial layer are sequentially formed on the substrate;

[0013] An opening is formed that penetrates the sacrificial layer and the floating gate structure layer to expose the substrate;

[0014] A tunneling oxide layer is formed, which covers the sidewalls and bottom of the opening;

[0015] A word line is formed, which fills the opening after the tunneling oxide layer is formed;

[0016] Remove the sacrificial layer.

[0017] Furthermore, after forming the word line, a word line oxide layer covering the word line is also formed on the top of the opening after forming the tunnel oxide layer.

[0018] Furthermore, forming the opening specifically includes:

[0019] A dry etching process is used to form an opening that penetrates the sacrificial layer and the floating gate layer, exposing the surface of the floating gate oxide layer;

[0020] The floating gate oxide layer exposed by the opening is removed by a wet etching process, thereby exposing the substrate; during the wet etching process, the sacrificial layer on both sides of the opening is also removed by a certain width to expose the corner of the floating gate layer, and the opening after wet etching constitutes the opening.

[0021] Furthermore, the control gate layer includes a first horizontal portion, a vertical portion, and a second horizontal portion; the vertical portion covers the portion of the isolation layer located on the sidewall of the word line, the first horizontal portion covers the portion of the isolation layer located on the surface of the floating gate layer, and the second horizontal portion covers the portion of the isolation layer located above the word line.

[0022] Furthermore, the control gate, the isolation structure, and the floating gate are formed using a self-aligned etching process, specifically including: etching away the second horizontal portion of the control gate layer and the isolation layer below it, and etching away the first horizontal portion of the control gate layer and the isolation layer and the floating gate layer below it to expose the floating gate oxide layer, thereby forming the floating gate, the isolation structure, and the control gate.

[0023] The present invention also provides a flash memory device, the flash memory device comprising a plurality of flash memory cells, the flash memory cells comprising:

[0024] A substrate on which word lines are formed, and on the substrate on both sides of the word lines, floating gates and control gates are sequentially disposed;

[0025] A tunneling oxide layer is located on the sidewalls on both sides of the word line and between the word line and the substrate;

[0026] An isolation structure, which is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion, wherein the control gate fills the L-shaped space of the isolation structure; the horizontal isolation portion is located between the floating gate and the control gate, and the vertical isolation portion is located between the tunneling oxide layer on the sidewall of the word line and the control gate.

[0027] Furthermore, the flash memory cell also includes a word line oxide layer, which is located at the top of the word line, and the tunneling oxide layer is also disposed on the sidewalls on both sides of the word line oxide layer.

[0028] Furthermore, the isolation structure exposes the corner of the floating gate near the word line, and the word line wraps around the upper surface and sidewall of the corner of the floating gate through the tunneling oxide layer.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] This invention provides a flash memory device and its fabrication method. The fabrication method includes: providing a substrate, on which a floating gate structure layer and word lines are formed; a tunneling oxide layer is formed on the sidewalls of the word lines and between the word lines and the substrate; forming an isolation layer covering the surface of the floating gate structure layer, the top of the word lines, and the tunneling oxide layer located on the sidewalls of the word lines; forming a control gate layer covering the surface of the isolation layer; and etching the control gate layer, the isolation layer, and the floating gate structure layer using a self-aligned etching process to form a control gate, an isolation structure, and a floating gate. The isolation structure is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion. The horizontal isolation portion is located between the floating gate and the control gate, and the vertical isolation portion is located between the tunneling oxide layer on the sidewalls of the word lines and the control gate. This invention takes a novel approach by forming the control gate using a self-aligned etching process, avoiding the problem of sharp corners at the top of the control gate. The horizontal isolation portion and the vertical isolation portion are fabricated as a single unit, simplifying the process. Attached Figure Description

[0031] Figures 1 to 3 This is a schematic diagram of the steps involved in the fabrication of a flash memory device.

[0032] Figure 4 This is a schematic diagram of the fabrication process of a flash memory device according to an embodiment of the present invention.

[0033] Figures 5 to 13 This is a schematic diagram of the steps in the fabrication method of the flash memory device according to an embodiment of the present invention.

[0034] The reference numerals in the attached figures are as follows:

[0035] 001-Substrate; 002-Floating gate layer; 003-Spacer layer; 004-Control gate layer; 005-Hard mask layer; 006-First sidewall; 007-Second sidewall; a-Sharp corner;

[0036] 100 - Substrate; 101 - Floating gate oxide layer; 102 - Floating gate layer; 103 - Sacrificial layer; V - Opening; 104 - Opening; 105 - Tunneling oxide layer; 106 - Word line; 107 - Word line oxide layer; 108 - Isolation layer; 109 - Control gate layer; 109a - Vertical portion of control gate layer; 109b - First horizontal portion of control gate layer; 109c - Second horizontal portion of control gate layer; 112 - Floating gate; 118 - Isolation structure; 118a - Vertical portion of isolation; 118b - Horizontal portion of isolation; 119 - Control gate. Detailed Implementation

[0037] As described in the background section, in current flash memory manufacturing processes, the top of the control gate is prone to forming sharp corners, which affects the overall performance of the flash memory, and the manufacturing process is relatively complex.

[0038] Specifically, such as Figure 1 As shown, a floating gate layer 002, a spacer layer 003, a control gate layer 004, and a hard mask layer 005 are sequentially formed on a substrate 001. An opening is formed in the hard mask layer 005, and the two sidewalls of the opening form first sidewalls 006. Using the first sidewalls 006 as a mask, the control gate layer 004 is dry-etched to expose the spacer layer 003. The sidewalls of the exposed control gate layer 004 are damaged during the plasma etching process. Figure 2 As shown, the wet etching spacer layer 003 exposes the floating gate layer 002. During the wet etching process of the spacer layer 003, the sidewall of the damaged control gate layer 004 is also damaged to a certain extent by the wet etching, which causes the sidewall of the control gate layer 004 to be side-cut (drilled), thus forming a sharp corner a at the top of the control gate layer 004. Finally, the top of the control gate formed by etching the control gate layer 004 also has this sharp corner a.

[0039] like Figure 3 As shown, a second sidewall 007 is formed, covering the sidewalls of the spacer layer 003, the control gate layer 004, and part of the sidewall of the first sidewall 006. Word lines are formed between the second sidewalls 007 and the first sidewalls 006 on both sides of the subsequent opening. The second sidewall 007 is used to electrically isolate the word lines and the control gate layer 004. The spacer layer 003 is used to electrically isolate the floating gate layer 002 and the control gate layer 004. In this manufacturing process, the second sidewall 007 and the spacer layer 003 are formed separately in two processes, making the process relatively complex. Furthermore, the top of the control gate is prone to forming sharp corners. These sharp corners (a) easily accumulate charge, and excessive charge accumulation makes the sharp corners of the control gate easily break down, reducing the withstand voltage between the control gate and the word lines, thus affecting the overall performance of the flash memory.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0041] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0042] This invention provides a method for fabricating a flash memory device, such as... Figure 4 As shown, it includes:

[0043] Step S1: Provide a substrate on which a floating gate structure layer and word lines are formed. The word lines are distributed in a direction perpendicular to the substrate, and a portion of the word lines are embedded in the floating gate structure layer. A tunneling oxide layer is formed on the sidewalls of the word lines and between the word lines and the substrate.

[0044] Step S2: Form an isolation layer that covers the surface of the floating grid structure layer, the top of the word line, and the tunneling oxide layer located on the sidewall of the word line;

[0045] Step S3: Form a control gate layer, the control gate layer covering the surface of the isolation layer;

[0046] Step S4: The control gate layer, the isolation layer, and the floating gate structure layer are etched using a self-aligned etching process to form a control gate, an isolation structure, and a floating gate. The isolation structure is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion. The control gate fills the L-shaped space of the isolation structure. The horizontal isolation portion is located between the floating gate and the control gate, and the vertical isolation portion is located between the tunneling oxide layer on the word line sidewall and the control gate.

[0047] The following is combined with Figures 5 to 13 The following details each step of the method for fabricating the flash memory device according to an embodiment of the present invention.

[0048] Please refer to Figure 5 A substrate 100 is provided; in this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator, or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0049] A floating gate structure layer is formed on the substrate 100. The floating gate structure layer includes a floating gate oxide layer 101 and a floating gate layer 102 located on the floating gate oxide layer 101. The material of the floating gate oxide layer 101 includes silicon oxide; the material of the floating gate layer 102 includes polysilicon. The process for forming the floating gate layer 102 is a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition.

[0050] After forming a floating gate structure layer on the substrate 100, a sacrificial layer 103 is formed on the floating gate structure layer. The material of the sacrificial layer 103 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the material of the sacrificial layer 103 includes silicon nitride.

[0051] Please refer to Figure 5 and Figure 6 An opening 104 is formed, penetrating the sacrificial layer 103 and the floating gate structure layer to expose the substrate 100. Forming the opening 104 specifically includes: forming an aperture V using a dry etching process, the aperture V penetrating the sacrificial layer 103 and the floating gate layer 102 to expose the surface of the floating gate oxide layer 101. A wet etching process is then used to remove the floating gate oxide layer 101 exposed by the aperture V, thereby exposing the substrate 100; during the wet etching process, a certain width of the sacrificial layer 103 on both sides of the aperture V is also removed to expose the corner of the floating gate layer 102. The aperture after wet etching constitutes the opening 104. The opening 104 is for the subsequent formation of the tunneling oxide layer 105 and the word line 106. Figure 8 Provide space.

[0052] Please refer to Figure 7 A tunneling oxide layer 105 is formed; the tunneling oxide layer 105 covers the sidewalls and bottom of the opening 104 and the upper surface of the sacrificial layer 103, with the tunneling oxide layer 105 covering the bottom of the opening 104 located on the surface of the substrate 100. The tunneling oxide layer 105 is used for electrical isolation between the subsequently formed word line 106 and the floating gate 112. Figure 13 The material of the tunneling oxide layer 105 includes a dielectric material, which includes silicon oxide or silicon oxynitride.

[0053] Please refer to Figure 8 and Figure 9 The word line 106 is formed by extending upwards from the bottom of the opening after the tunneling oxide layer 105 is formed, with a certain space reserved at the top of the opening for subsequent formation of a word line oxide layer 107 covering the word line 106. The material of the word line 106 is polycrystalline silicon. The process for forming the word line 106 is a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition. Next, a chemical mechanical polishing process is performed to remove the tunneling oxide layer 105 located on the upper surface of the sacrificial layer 103. Next, the word line oxide layer 107 is formed; the material of the word line oxide layer 107 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbonitride.

[0054] Word lines 106 tunnel through oxide layer 105 to wrap the upper surface and sidewalls of the corner of floating gate layer 102, increasing the impact of word lines 106 on the subsequent floating gate 112 formed by floating gate layer 102. Figure 13 The encapsulation of the word line 106 increases the area of ​​the floating grid 112 encapsulated by the word line 106, thereby increasing the pressure difference between the word line 106 and the floating grid 112 and improving the erasing effect.

[0055] Please refer to Figure 10 Remove the sacrificial layer 103; the process for removing the sacrificial layer 103 on the floating gate structure layer includes dry etching or wet etching.

[0056] Please refer to Figure 11 An isolation layer 108 is formed; the isolation layer 108 covers the upper surface of the word line oxide layer 107, the sidewall surface and the upper surface of the tunneling oxide layer 105, and extends to cover the upper surface of the floating gate layer 102. Exemplarily, the isolation layer 108 includes a stacked first oxide layer (not shown), a nitride layer and a second oxide layer; the stacked first oxide layer, nitride layer and second oxide layer are referred to as the ONO layer.

[0057] Please refer to Figure 12 A control gate layer 109 is formed, which covers the surface of the isolation layer 108. The control gate layer 109 is made of polysilicon. The process for forming the control gate layer 109 is a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition.

[0058] Please refer to Figure 12 and Figure 13The flash memory device structure is formed using a self-aligned dry etching process. The control gate layer 109 includes a first horizontal portion 109b, a vertical portion 109a, and a second horizontal portion 109c. The vertical portion 109a covers the portion of the isolation layer 108 located on the word line sidewall, the first horizontal portion 109b covers the portion of the isolation layer 108 located on the surface of the floating gate layer 102, and the second horizontal portion 109c covers the portion of the isolation layer 108 located above the word line 106. The thickness of the vertical portion 109a is h2, and the thickness of the first horizontal portion 109b is h1. The self-aligned etching process is achieved by utilizing the difference between the thickness h2 of the vertical portion 109a and the thickness h1 of the first horizontal portion 109b. This self-aligned dry etching is an anisotropic dry etching process, thus the vertical portion 109a of the control gate layer located on the sidewall of word line 106 is retained, while the first horizontal portion 109b and the second horizontal portion 109c of the control gate layer parallel to the substrate 100 direction are etched. By implementing a self-aligned process, the area of ​​the flash memory device can be further reduced, while not being limited by photolithography. The control gate 119 is formed through the self-aligned dry etching process, avoiding the limitations of existing processes (…). Figure 2 During the wet etching process of the spacer layer 003 to expose the floating gate layer 002, damage is caused to the sidewall of the control gate layer 004, forming the sharp corner a at the top of the control gate.

[0059] Etching removes the second horizontal portion 109c of the control gate layer and the isolation layer 108 below it, etches removes the first horizontal portion 109b of the control gate layer and the isolation layer 108 below it, and the floating gate layer 102 exposes the floating gate oxide layer 101, forming a floating gate 112, an isolation structure 118, and a control gate 119. The isolation structure 118 is an L-shaped structure, including a connected isolation horizontal portion 118b and an isolation vertical portion 118a. The material of the isolation structure 118 includes a stacked first oxide layer (not shown), a nitride layer, and a second oxide layer; the stacked first oxide layer, nitride layer, and second oxide layer are referred to as the ONO layer. The isolation horizontal portion 118b is located between the floating gate 112 and the control gate 119, and the control gate 119 is formed within the L-shaped space enclosed by the isolation horizontal portion 118b and the isolation vertical portion 118a; the isolation vertical portion 118a is located on the sidewall of the tunneling oxide layer 105 above the floating gate 112. During the erasure operation, a voltage is applied to the word line 106, and electrons are transferred from the floating gate 112 through the tunneling oxide layer 105 to the word line 106 to complete the erasure. The horizontal isolation portion 118b is used to separate the floating gate 112 and the control gate 119, and the vertical isolation portion 118a is used to isolate the control gate 119 and the tunneling oxide layer 105.

[0060] This invention forms the control gate 119 using a self-aligned etching process, avoiding the sharp corners formed at the top of the control gate in existing processes. The isolation horizontal portion 118b (e.g., an ONO layer) and the isolation vertical portion 118a (flash memory cell sidewalls) in this invention are fabricated using a single process. Compared with existing processes... Figure 3 Compared to the separate manufacturing processes for the second sidewall 007 and the spacer layer 003, the process is simplified. Structurally, it avoids the problem of controlling the grid tip angle, and in terms of manufacturing, it saves on furnace tubes and other corresponding processes.

[0061] This invention also provides a flash memory device, such as... Figure 13 As shown, the flash memory device includes several flash memory cells. Figure 13 The image shows two flash memory cells, each comprising:

[0062] A substrate 100 has a word line 106 formed on it, and a floating gate 112 and a control gate 119 are sequentially disposed on the substrate 100 on both sides of the word line 106.

[0063] The tunneling oxide layer 105 is located on the sidewalls on both sides of the word line 106 and between the word line 106 and the substrate 100.

[0064] The isolation structure 118 is L-shaped and includes a connected horizontal isolation portion 118b and a vertical isolation portion 118a. The control gate 119 fills the L-shaped space of the isolation structure. The horizontal isolation portion 118b is located between the floating gate 112 and the control gate 119, and the vertical isolation portion 118a is located between the tunneling oxide layer 105 on the sidewall of the word line 106 and the control gate 119.

[0065] A word line oxide layer 107 is located on top of the word line 106, and tunneling oxide layers 105 are also provided on the sidewalls of both sides of the word line oxide layer 107. The isolation structure 118 exposes the corner of the floating gate 112 near the word line 106, and the word line 106 wraps the upper surface and sidewalls of the corner of the floating gate 112 through the tunneling oxide layer 105. This increases the impact of the word line 106 on the subsequent floating gate 112 formed by the floating gate layer 102. Figure 13 The encapsulation of the word line 106 increases the area of ​​the floating grid 112 encapsulated by the word line 106, thereby increasing the pressure difference between the word line 106 and the floating grid 112 and improving the erasing effect.

[0066] In summary, this invention provides a flash memory device and its fabrication method. The fabrication method includes: providing a substrate, on which a floating gate structure layer and word lines are formed; a tunneling oxide layer is formed on the sidewalls of the word lines and between the word lines and the substrate; forming an isolation layer covering the surface of the floating gate structure layer, the top of the word lines, and the tunneling oxide layer located on the sidewalls of the word lines; forming a control gate layer covering the surface of the isolation layer; and etching the control gate layer, the isolation layer, and the floating gate structure layer using a self-aligned etching process to form a control gate, an isolation structure, and a floating gate. The isolation structure is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion. The horizontal isolation portion is located between the floating gate and the control gate, and the vertical isolation portion is located between the tunneling oxide layer on the sidewalls of the word lines and the control gate. This invention takes a novel approach by forming the control gate using a self-aligned etching process, avoiding the problem of sharp corners at the top of the control gate. The horizontal isolation portion and the vertical isolation portion are fabricated as a single unit, simplifying the process.

[0067] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0068] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided on which a floating gate structure layer and word lines are formed, the word lines being distributed along a direction perpendicular to the substrate, and a portion of the word lines being embedded in the floating gate structure layer; A tunneling oxide layer is formed on the sidewalls of the word line and between the word line and the substrate; An isolation layer is formed, which covers the surface of the floating grid structure layer, the top of the word line, and the tunneling oxide layer located on the sidewall of the word line; A control gate layer is formed, which covers the surface of the isolation layer; The control gate layer, the isolation layer, and the floating gate structure layer are etched using a self-aligned etching process to form a control gate, an isolation structure, and a floating gate. The isolation structure is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion. The control gate fills the L-shaped space of the isolation structure. The horizontal isolation portion is located between the floating grid and the control grid, and the vertical isolation portion is located between the tunneling oxide layer on the word line sidewall and the control grid.

2. The method for fabricating a flash memory device as described in claim 1, characterized in that, The floating gate structure layer includes a floating gate oxide layer and a floating gate layer sequentially located on the substrate.

3. The method for fabricating a flash memory device as described in claim 2, characterized in that, The substrate provided specifically includes: The floating gate structure layer and the sacrificial layer are sequentially formed on the substrate; An opening is formed that penetrates the sacrificial layer and the floating gate structure layer to expose the substrate; A tunneling oxide layer is formed, which covers the sidewalls and bottom of the opening; A word line is formed, which fills the opening after the tunneling oxide layer is formed; Remove the sacrificial layer.

4. The method for fabricating a flash memory device as described in claim 3, characterized in that, After forming the word line, a word line oxide layer covering the word line is also formed on the top of the opening after the tunnel oxide layer is formed.

5. The method for fabricating a flash memory device as described in claim 3, characterized in that, Forming the opening specifically includes: A dry etching process is used to form an opening that penetrates the sacrificial layer and the floating gate layer, exposing the surface of the floating gate oxide layer; The floating gate oxide layer exposed by the opening is removed by a wet etching process, thereby exposing the substrate; during the wet etching process, the sacrificial layer on both sides of the opening is also removed by a certain width to expose the corner of the floating gate layer, and the opening after wet etching constitutes the opening.

6. The method for fabricating a flash memory device as described in claim 2, characterized in that, The control gate layer includes a first horizontal portion, a vertical portion, and a second horizontal portion; the vertical portion covers the portion of the isolation layer located on the sidewall of the word line, the first horizontal portion covers the portion of the isolation layer located on the surface of the floating gate layer, and the second horizontal portion covers the portion of the isolation layer located above the word line.

7. The method for fabricating a flash memory device as described in claim 6, characterized in that, The control gate, the isolation structure, and the floating gate are formed using a self-aligned etching process, specifically including: etching away the second horizontal portion of the control gate layer and the isolation layer below it, and etching away the first horizontal portion of the control gate layer and the isolation layer and the floating gate layer below it to expose the floating gate oxide layer, thereby forming the floating gate, the isolation structure, and the control gate.

8. A flash memory device, characterized in that, The flash memory device is formed using the manufacturing method of any one of claims 1 to 7, and the flash memory device comprises a plurality of flash memory cells, wherein the flash memory cells comprise: A substrate on which word lines are formed, and on the substrate on both sides of the word lines, floating gates and control gates are sequentially disposed; A tunneling oxide layer is located on the sidewalls on both sides of the word line and between the word line and the substrate; An isolation structure, which is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion, wherein the control gate fills the L-shaped space of the isolation structure; the horizontal isolation portion is located between the floating gate and the control gate, and the vertical isolation portion is located between the tunneling oxide layer on the sidewall of the word line and the control gate.

9. The flash memory device as claimed in claim 8, characterized in that, The flash memory cell also includes: The character line oxide layer is located at the top of the character line, and the tunneling oxide layer is also provided on the sidewalls on both sides of the character line oxide layer.

10. The flash memory device as claimed in claim 8, characterized in that, The isolation structure exposes the corner of the floating gate near the word line, the word line being wrapped by the tunneling oxide layer around the upper surface and sidewalls of the corner of the floating gate.

Images