Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor device capable of forming a suitable laminated film and a manufacturing method thereof. The semiconductor device of the embodiments of the present application includes a substrate and a laminated film including a plurality of first layers and a plurality of second layers alternately arranged on the substrate. The device further includes a charge accumulation layer arranged on a side of the laminated film via a first insulating film and a semiconductor layer arranged on a side of the charge accumulation layer via a second insulating film. Furthermore, one of the plurality of first layers includes a first region including carbon at a first concentration and a second region including carbon at a second concentration higher than the first concentration, including a lower side region arranged on a lower side of the first region or an upper side region arranged on an upper side of the first region.

Description

[0001] [Reference to relevant applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-200961 (filed on December 10, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] Semiconductor devices may include multilayer films comprising multiple layers, such as multilayer films that alternately comprise multiple insulating layers and multiple electrode layers, or multilayer films that alternately comprise multiple insulating layers and multiple sacrificial layers. In this case, the shape of the layers within the multilayer film may be deformed, or the etch resistance of the layers within the multilayer film may deteriorate. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device capable of forming a suitable multilayer film and a method thereof.

[0006] According to one embodiment, a semiconductor device includes: a substrate; and a multilayer film comprising a plurality of first layers and a plurality of second layers alternately disposed on the substrate. The device further includes: a charge storage layer disposed on a side of the multilayer film, separated by a first insulating film; and a semiconductor layer disposed on a side of the charge storage layer, separated by a second insulating film. Furthermore, one of the plurality of first layers includes: a first region containing a first concentration of carbon; and a second region containing a second concentration of carbon higher than the first concentration, comprising a lower region disposed below the first region or an upper region disposed above the first region. Attached Figure Description

[0007] Figure 1 This is a perspective view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figures 3-7 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0010] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device of the first comparative example of the first embodiment.

[0011] Figure 9This is a cross-sectional view showing the structure of the semiconductor device of the second comparative example of the first embodiment.

[0012] Figure 10 (a) and (b) are figures and tables used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0013] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0014] Figure 12 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

[0015] Figures 13-15 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the fourth embodiment.

[0016] Figure 16 (a) to (d) are top views showing details of the manufacturing method of the semiconductor device according to the fourth embodiment.

[0017] Figure 17 This is a cross-sectional view showing details of the manufacturing method of the semiconductor device according to the fourth embodiment. Detailed Implementation

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 17 In this context, identical components are marked with the same symbol, and repeated descriptions are omitted.

[0019] (First Embodiment)

[0020] Figure 1 This is a perspective view showing the structure of the semiconductor device according to the first embodiment. Figure 1 Semiconductor devices, for example, have three-dimensional semiconductor memories.

[0021] Figure 1 The semiconductor device includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a barrier insulating film 5, and an electrode layer 6. The barrier insulating film 5 includes an insulating film 5a and an insulating film 5b. The electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The insulating film 5a, the tunnel insulating film 3, and the channel semiconductor layer 2 are examples of the first insulating film, the second insulating film, and the semiconductor layer, respectively.

[0022] exist Figure 1 In this process, multiple insulating layers and multiple electrode layers are alternately deposited on the substrate, and memory holes H1 are disposed within these insulating layers and electrode layers. Figure 1 One of these electrode layers, layer 6, is shown. These electrode layers function, for example, as word lines in a three-dimensional semiconductor memory. Figure 1The X and Y directions, which are parallel to and perpendicular to the surface of the substrate, and the Z direction, which is perpendicular to the surface of the substrate, are shown. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. The -Z direction may or may not be aligned with the direction of gravity.

[0023] A core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge accumulation layer 4, and an insulating film 5a are formed within a memory aperture H1, constituting a storage cell of a three-dimensional semiconductor memory. The insulating film 5a is formed on the surface of multiple insulating layers and multiple electrode layers within the memory aperture H1, and the charge accumulation layer 4 is formed on the surface of the insulating film 5a. The charge accumulation layer 4 can accumulate the signal charge of the three-dimensional semiconductor memory. The tunnel insulating film 3 is formed on the surface of the charge accumulation layer 4, and the channel semiconductor layer 2 is formed on the surface of the tunnel insulating film 3. The channel semiconductor layer 2 functions as a channel for the storage cell. The core insulating film 1 is formed within the channel semiconductor layer 2.

[0024] The insulating film 5a is, for example, a SiO2 film (silicon oxide film). The charge storage layer 4 is, for example, an insulating film such as a SiN film (silicon nitride film). The charge storage layer 4 can also be a semiconductor layer such as a polycrystalline silicon layer. The tunnel insulating film 3 is, for example, a SiON film (silicon oxynitride film). The tunnel insulating film 3 can also be a SiO2 film. The channel semiconductor layer 2 is, for example, a polycrystalline silicon layer. The core insulating film 1 is, for example, a SiO2 film.

[0025] An insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are formed between two adjacent insulating layers in the Z direction, sequentially formed on the lower surface of the upper insulating layer, the upper surface of the lower insulating layer, and the side surface of the insulating film 5a. The insulating film 5b is, for example, a metallic insulating film such as an Al2O3 film (alumina film). The barrier metal layer 6a is, for example, a TiN film (titanium nitride film). The electrode material layer 6b is, for example, a W (tungsten) layer.

[0026] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0027] Figure 2 It shows Figure 1 The longitudinal section of memory hole H1 is shown. (See reference...) Figure 1 As explained, the semiconductor device of this embodiment includes a plurality of insulating layers 8 and a plurality of electrode layers 6 alternately deposited on a substrate 7. Figure 2These insulating layers 8 and electrode layers 6 constitute a multilayer film 9. Within the multilayer film 9, these electrode layers 6 are separated from each other in the Z direction. Each electrode layer 6 includes the barrier metal layer 6a and the electrode material layer 6b. Each electrode layer 6 is an example of a second layer. The substrate 7 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Each insulating layer 8 is, for example, a SiO2 film. Each insulating layer 8 is an example of a first layer or a first insulating layer. Further details regarding each insulating layer 8 are described below.

[0028] An insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 are sequentially formed on the side of the stacked film 9 within the memory hole H1, i.e., on the side of the multiple insulating layers 8 and multiple electrode layers 6 within the memory hole H1. A barrier metal layer 6a and an electrode material layer 6b within each electrode layer 6 are sequentially formed on the lower surface of the upper insulating layer 8, the upper surface of the lower insulating layer 8, and the side of the insulating layer 5a, separated by the insulating film 5b.

[0029] Next, continue to refer to Figure 2 The insulating layers 8 of this embodiment will be described.

[0030] Each insulating layer 8 in this embodiment contains silicon (Si), oxygen (O), and carbon (C), such as a SiO2 film containing carbon as an impurity. The concentration of C atoms (hereinafter referred to as "C concentration") within each insulating layer 8 varies depending on the region within each insulating layer 8.

[0031] Specifically, such as Figure 2 As shown, each insulating layer 8 in this embodiment includes a main region 8a, a lower region 8b, and an upper region 8c. The main region 8a, lower region 8b, and upper region 8c are all SiO2 films containing carbon as an impurity. The main region 8a is an example of a first region. The lower region 8b and upper region 8c are examples of a second region.

[0032] The main body region 8a is located approximately at the center of each insulating layer 8. The Z-direction thickness of the main body region 8a is, for example, 15–20 nm. The C concentration within the main body region 8a is, for example, 1.4–2.6 atomic%. This C concentration is an example of a first concentration. The C concentration within the main body region 8a in this embodiment is given by dividing the number of C atoms in the main body region 8a by the number of Si atoms, O atoms, and C atoms in the main body region 8a. The same applies to other C concentrations described below.

[0033] The lower region 8b is located below the main region 8a within each insulating layer 8. The Z-direction thickness of the lower region 8b is thinner than the Z-direction thickness of the main region 8a, for example, less than 1 nm. The C concentration in the lower region 8b is higher than the C concentration in the main region 8a, for example, more than 2.8 atomic%. This C concentration is an example of a second concentration. The lower region 8b is, for example, in contact with the upper surface of the lower insulating film 5b.

[0034] The upper region 8c is located above the main region 8a within each insulating layer 8. The Z-direction thickness of the upper region 8c is thinner than the Z-direction thickness of the main region 8a, for example, less than 1 nm. The C concentration in the upper region 8c is higher than the C concentration in the main region 8a, for example, more than 2.8 atomic%. This C concentration is also an example of a second concentration. The upper region 8c is, for example, in contact with the lower surface of the upper insulating film 5b.

[0035] In this embodiment, all insulating layers 8 within the laminated film 9 include a main region 8a, a lower region 8b, and an upper region 8c. However, only some insulating layers 8 within the laminated film 9 may include the main region 8a, the lower region 8b, and the upper region 8c. Further details regarding the insulating layers 8 are described below.

[0036] Figures 3-7 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0037] First, a substrate 7 is prepared, and multiple insulating layers 8 and multiple sacrificial layers 11 are alternately formed on the substrate 7. Figure 3 As a result, a multilayer film 12 comprising these insulating layers 8 and sacrificial layers 11 is formed on the substrate 7. Each sacrificial layer 11 is, for example, a SiN film. Each sacrificial layer 11 is an example of a second layer or a second insulating layer.

[0038] In this embodiment, each insulating layer 8 is formed to include a main region 8a, a lower region 8b, and an upper region 8c. The thickness of the main region 8a is, for example, 15 to 20 nm. The C concentration in the main region 8a is, for example, 1.4 to 2.6 atomic%. The thickness of the lower region 8b and the upper region 8c is, for example, 1 nm or less. The C concentration in the lower region 8b and the upper region 8c is, for example, 2.8 atomic% or more. Each insulating layer 8 is formed such that the lower region 8b is formed, the main region 8a is formed on the lower region 8b, and the upper region 8c is formed on the main region 8a.

[0039] In this embodiment, each insulating layer 8 is a SiO2 film containing carbon as an impurity, formed using a source gas containing silicon (Si source gas) and a source gas containing carbon (C source gas). The Si source gas is, for example, a silane gas such as SiH4 gas, TEOS (tetraethyl orthosilicate) gas, or a mixture containing one or more of these (H represents hydrogen). The C source gas is, for example, CO gas, CO2 gas, or C... X H Y Gases, including SiH3(CH3) gas (monomethylsilane gas), SiH2(CH3)2 gas (dimethylsilane gas), SiH(CH3)3 gas (trimethylsilane gas), Si(CH3)4 gas (tetramethylsilane gas), or mixtures containing one or more of these gases (X represents an integer from 1 to 4, and Y represents an integer from 1 to 4). The Si-sourced gas is an example of the second gas, and the C-sourced gas is an example of the first gas.

[0040] In this embodiment, each insulating layer 8 is formed by setting different conditions for forming the main region 8a and for forming the lower region 8b and upper region 8c. For example, when supplying Si source gas to the cavity containing the substrate 7, the flow rate of the Si source gas during the formation of the lower region 8b and upper region 8c can be set to be lower than the flow rate of the Si source gas during the formation of the main region 8a. Similarly, when supplying C source gas to the cavity containing the substrate 7, the flow rate of the C source gas during the formation of the lower region 8b and upper region 8c can be set to be lower than the flow rate of the C source gas during the formation of the main region 8a. According to this embodiment, by employing one or two of these flow rate conditions, the C concentration in the lower region 8b and upper region 8c can be set to be higher than the C concentration in the main region 8a. Further details regarding these conditions are described below.

[0041] Next, multiple memory holes H1 are formed in the stacked film 12 using photolithography and dry etching. Figure 4 ). Figure 4 One of these memory holes H1 is illustrated. Each memory hole H1 is formed to extend along the Z direction and penetrate the laminated film 12. In this embodiment, each memory hole H1 is cylindrical in shape.

[0042] Next, an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 are sequentially formed within each memory hole H1. Figure 5 As a result, the insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, the channel semiconductor layer 2 and the core insulating film 1 are sequentially formed on the side of the stacked film 12, that is, on the side of the plurality of insulating layers 8 and the plurality of sacrificial layers 11.

[0043] Next, slits (not shown) are formed within the stacked film 12, and each sacrificial layer 11 is removed by wet etching through the slits. Figure 6 As a result, multiple cavities H2 are formed within the stacked film 12. These cavities H2 are examples of recesses. The wet etching is performed, for example, using hydrofluoric acid or phosphoric acid.

[0044] Next, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are sequentially formed in each cavity H2. Figure 7 As a result, a barrier insulating film 5 comprising insulating films 5a and 5b, and an electrode layer 6 comprising a barrier metal layer 6a and an electrode material layer 6b are formed. Furthermore, a multilayer film 9, alternately comprising multiple insulating layers 8 and multiple electrode layers 6, is formed on the substrate 7. In other words, the sacrificial layer 11 is replaced with the electrode layer 6, and the multilayer film 12 is replaced with the multilayer film 9.

[0045] Then, the substrate 7 and various layers on the substrate 7 are annealed, and various plug layers, wiring layers, interlayer insulating films, etc. are formed on the substrate 7. In this way, the semiconductor device of this embodiment is manufactured.

[0046] Furthermore, while the main region 8a and lower region 8b within each insulating layer 8 are made of the same insulating film (e.g., a SiO2 film) in this embodiment, they can also be made of different insulating films. For example, the main region 8a can be a SiO2 film containing carbon as an impurity, and the lower region 8b can be a SiON film containing carbon as an impurity. In this case, it is ideal to set the C concentration in the lower region 8b to be higher than the C concentration in the main region 8a. The same applies to the main region 8a and upper region 8c within each insulating layer 8.

[0047] Next, refer to Figure 8 and Figure 9 The semiconductor device of this embodiment is compared with the semiconductor device of the comparative example.

[0048] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device of the first comparative example of the first embodiment.

[0049] The semiconductor device of this comparative example has the same semiconductor device as that of the first embodiment ( Figure 2 The same constituent elements. In this comparative example, each insulating layer 8 includes only the main region 8a containing a low concentration of C atoms, and does not include the lower region 8b and the upper region 8c containing a high concentration of C atoms.

[0050] In this case, when using Figures 3-7 When manufacturing the semiconductor device of this comparative example using the method shown, in Figure 6During the stages shown, the shape of insulating layer 8 may be deformed, or in Figure 6 As shown in the diagram, the etch resistance of the insulating layer 8 may deteriorate. Figure 6 The steps for removing the sacrificial layer 11 by wet etching as described above are shown.

[0051] exist Figure 6 Because the insulating layer 8 is exposed in the cavity H2, its shape may be curved. This curvature may become more pronounced as the laminated film 12 is miniaturized or highly laminated. This is because the thickness of the insulating layer 8 decreases or the stress applied to it increases with miniaturization or high lamination. Furthermore, the shape of the insulating layer 8 becomes thinner at the tip during wet etching, which also contributes to its curvature.

[0052] The verification results clearly show that the higher the C concentration within the main body region 8a, the less likely these problems are to occur. For example, the higher the C concentration within the main body region 8a, the lower the stress applied to the insulating layer 8. Furthermore, the higher the C concentration within the main body region 8a, the higher the resistance of the insulating layer 8 to wet etching.

[0053] Figure 9 This is a cross-sectional view showing the structure of the semiconductor device of the second comparative example of the first embodiment.

[0054] The semiconductor device in this comparative example also has the same semiconductor device as in the first embodiment ( Figure 2 The same constituent elements. In this comparative example, each insulating layer 8 does not only include a main region 8a containing a low concentration of C atoms, but only a main region 8d containing a high concentration of C atoms. The C concentration in the main region 8d is, for example, 2.8 atomic% or more.

[0055] In this case, when using Figures 3-7 When the semiconductor device of this comparative example is manufactured using the method shown, it is possible to suppress [the following]: Figure 6 The shape of the insulating layer 8 is deformed in the stage shown, or Figure 6 The etch resistance of the insulating layer 8 deteriorates during the stage shown. However, because the insulating layer 8 contains a high concentration of C atoms, a large leakage current may be generated due to the insulating layer 8 during semiconductor device operation. That is, when the C concentration in the main region 8d increases, the leakage current in the semiconductor device may increase.

[0056] Therefore, each insulating layer 8 in this embodiment includes a main region 8a containing a low concentration of C atoms, and a lower region 8b and an upper region 8c containing a high concentration of C atoms. Figure 2Therefore, by reinforcing and protecting the surface of each insulating layer 8 with the lower region 8b and the upper region 8c, shape deformation of the insulating layer 8 and deterioration of its etch resistance can be suppressed. Furthermore, by including the main region 8a in each insulating layer 8, the average C concentration within the insulating layer 8 can be reduced, thereby reducing leakage current in the semiconductor device. In this way, according to this embodiment, a multilayer film 12(9) with suitable properties can be formed.

[0057] Furthermore, the C concentration in the main region 8a, lower region 8b, and upper region 8c is ideally set to a value that can appropriately suppress shape deformation of the insulating layer 8, deterioration of the etching resistance of the insulating layer 8, and increase in leakage current. According to this embodiment, by setting the C concentration in the lower region 8b and upper region 8c to 2.8 atomic% or more, shape deformation of the insulating layer 8 and deterioration of the etching resistance of the insulating layer 8 can be sufficiently suppressed. Moreover, according to this embodiment, by setting the C concentration in the main region 8a to 1.4 to 2.6 atomic%, leakage current can be sufficiently suppressed.

[0058] Furthermore, the verification results show that the deformation and etching resistance problems can be suppressed by using a lower region 8b and an upper region 8c with a thickness of less than 1 nm. Therefore, the thickness of the lower region 8b and the upper region 8c in this embodiment is ideally set to less than 1 nm. This effectively suppresses the increase in leakage current and suppresses the deformation and etching resistance problems.

[0059] Figure 10 These are figures and tables used to explain the manufacturing method of the semiconductor device according to the first embodiment.

[0060] Figure 10 (a) is used to... Figure 3 The diagram illustrates the steps involved in forming the laminated film 12. Figure 10 (a) The horizontal axis represents the time in the step of forming the laminated film 12. Figure 10 (a) The vertical axis represents the C concentration of each portion of the laminated film 12. For example, when forming the main region 8a within each insulating layer 8, the C concentration in the main region 8a is set to be low, while when forming the lower region 8b and upper region 8c within each insulating layer 8, the C concentration in the lower region 8b and upper region 8c is set to be high. The C concentration within each insulating layer 8 can be set to be high, for example, by reducing the flow rate of the Si source gas or reducing the flow rate of the C source gas.

[0061] Figure 10(b) shows various parameters that can increase the C concentration within the insulating layer 8. For example, the C concentration within the insulating layer 8 can be increased by reducing the flow rate of silane gas, which is the Si source gas. Furthermore, the C concentration within the insulating layer 8 can be increased by reducing the flow rate of CO2 gas, which is the C source gas.

[0062] During the formation of the insulating layer 8, a Si-source gas, a C-source gas, and an inert gas can be supplied to the cavity housing the substrate 7. The inert gas is, for example, a rare gas such as Ar (argon) or N2 (nitrogen). According to... Figure 10 (b) By increasing the flow rate of Ar gas or decreasing the flow rate of N2 gas, the C concentration within the insulating layer 8 can be increased. For example, the C concentration in the lower region 8b and the upper region 8c can be higher than the C concentration in the main region 8a by setting the flow rate of Ar gas when forming the lower region 8b and the upper region 8c to be greater than the flow rate of Ar gas when forming the main region 8a.

[0063] according to Figure 10 (b) By reducing the pressure within the cavity housing the substrate 7, the C concentration within the insulating layer 8 can be increased. For example, the C concentration in the lower region 8b and the upper region 8c can be higher than the C concentration in the main region 8a by setting the pressure within the cavity when forming the lower region 8b and the upper region 8c to be lower than the pressure within the cavity when forming the main region 8a.

[0064] Figure 10 (b) shows HF (High Frequency) and LF (Low Frequency) as representing the high-frequency and low-frequency RF (Radio Frequency) power when the insulating layer 8 is formed. According to Figure 10 (b) The C concentration in the insulating layer 8 can be increased by reducing the high-frequency RF power or increasing the low-frequency RF power. For example, the C concentration in the lower region 8b and the upper region 8c can be higher than the C concentration in the main region 8a by setting the low-frequency RF power when forming the lower region 8b and the upper region 8c to be higher than the low-frequency RF power when forming the main region 8a.

[0065] According to this embodiment, by adjusting these parameters, the C concentration in each insulating layer 8 can be easily varied according to the region within each insulating layer 8.

[0066] As described above, each insulating layer 8 in this embodiment includes a main layer 8a, and a lower region 8b and an upper region 8c having a C concentration higher than that in the main layer 8a. Therefore, according to this embodiment, a suitable multilayer film 9 (12) can be formed that can suppress shape deformation of the insulating layer 8, deterioration of the etching resistance of the insulating layer 8, and increase in leakage current.

[0067] (Second and Third Embodiments)

[0068] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0069] The semiconductor device of this embodiment has the same features as the semiconductor device of the first embodiment. Figure 2 The same constituent elements. In this embodiment, each insulating layer 8 includes a main region 8a containing a low concentration of C atoms and a lower region 8b containing a high concentration of C atoms, but does not include an upper region 8c containing a high concentration of C atoms.

[0070] Figure 12 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

[0071] The semiconductor device of this embodiment also has the same characteristics as the semiconductor device of the first embodiment. Figure 2 The same constituent elements. In this embodiment, each insulating layer 8 includes a main region 8a containing a low concentration of C atoms and an upper region 8c containing a high concentration of C atoms, but does not include a lower region 8b containing a high concentration of C atoms.

[0072] According to these embodiments, compared with the first comparative example, it is possible to suppress the shape deformation of the insulating layer 8 and the deterioration of the etching resistance of the insulating layer 8. Furthermore, according to these embodiments, compared with the second comparative example, it is possible to reduce leakage current.

[0073] (Fourth implementation)

[0074] Figures 13-15 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the fourth embodiment.

[0075] Figures 13-15 The steps shown are Figures 5-7 Example of a variation of the steps shown. Figure 13 and Figure 5 Similarly, the steps of sequentially forming an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 within each memory hole H1 are also shown. Figure 14 and Figure 6 Similarly, the steps of removing each sacrificial layer 11 to form a plurality of cavities H2 within the laminated film 12 are also shown. Figure 15 and Figure 7 Similarly, the steps of sequentially forming an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b within each cavity H2 are also shown. As a result, the sacrificial layer 11 is replaced with the electrode layer 6, and the laminated film 12 is replaced with the laminated film 9.

[0076] in, Figure 14The steps shown are performed by removing only a portion of each sacrificial layer 11, without removing all of them. As a result, Figure 15 The illustrated structure includes not only the electrode layer 6 (stacked film 9) generated by replacing the sacrificial layer 11 (stacked film 12), but also the sacrificial layer 11 (stacked film 12) that remains after not being replaced as the electrode layer 6 (stacked film 9). Therefore, the finished semiconductor device of this embodiment includes the electrode layer 6, the insulating layer 8, and the sacrificial layer 11, and each memory hole H1 is provided within the stacked film including the electrode layer 6, the insulating layer 8, and the sacrificial layer 11. The insulating layer 8 is an example of a first layer, and the electrode layer 6 and the sacrificial layer 11 are examples of second layers. Furthermore, the insulating layer 8 is an example of a first insulating layer, and the sacrificial layer 11 is an example of a second insulating layer.

[0077] The sacrificial layer 11 can remain in any part of the finished semiconductor device as long as it does not impede the operation of the finished semiconductor device. For example, in the case where the finished semiconductor device has a via plug through which a multilayer film containing the electrode layer 6, the insulating layer 8 and the sacrificial layer 11 is passed, the sacrificial layer 11 can remain near the via plug.

[0078] Figure 16 This is a top view showing details of the manufacturing method of the semiconductor device according to the fourth embodiment.

[0079] like Figure 16 As shown in (a), the substrate (wafer) 7 of this embodiment includes a plurality of regions R1. Each region R1 corresponds to a single exposure area during the manufacture of the semiconductor device of this embodiment.

[0080] like Figure 16 As shown in (b), each region R1 contains multiple regions R2. Each region R2 corresponds to one semiconductor device (chip) in this embodiment.

[0081] like Figure 16 As shown in (c), each region R2 contains multiple regions R3. Each region R3 corresponds to one memory plane within each chip in this embodiment.

[0082] like Figure 16 As shown in (d), each region R3 includes a central portion P1 and an end portion P2. The central portion P1 is located within the region enclosed by two slits. The end portion P2 is located within the region not enclosed by two slits. Further details regarding the central portion P1 and the end portion P2 are described below.

[0083] Figure 17 This is a cross-sectional view showing details of the manufacturing method of the semiconductor device according to the fourth embodiment.

[0084] Figure 17 express Figure 14 Specific examples of the steps shown. Therefore, Figure 17The steps of removing each sacrificial layer 11 to form a plurality of cavities H2 within the laminated film 12 are illustrated. Figure 17 In this process, not all of the sacrificial layers 11 were removed, but only a portion of them were removed.

[0085] Figure 17 express Figure 16 The central portion P1 and the end portion P2 shown are examples of multiple slits ST disposed within the laminated film 12. Each slit ST extends in the Y direction and the Z direction, penetrating the laminated film 12. Figure 17 The stacked film 12 shown includes, in addition to multiple insulating layers 8 and multiple sacrificial layers 11, an insulating layer 21 disposed between two adjacent sacrificial layers 11, and an insulating layer 22 disposed on the uppermost sacrificial layer 11. The insulating layers 21 and 22 are, for example, SiO2 films. Figure 17 In the middle, the central part P1 is located in the region sandwiched by two slits ST, and the end part P2 is located in the region not sandwiched by two slits ST.

[0086] Figure 17 The diagram also shows a plurality of columnar portions CL disposed within the laminated film 12. Each columnar portion CL sequentially comprises the insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 described above. Figure 17 Each columnar portion CL shown includes: a lower columnar portion CL1, which is disposed within and below the insulating layer 21; and an upper columnar portion CL2, which is disposed within and above the insulating layer 21.

[0087] exist Figure 17 In the steps shown, slits ST are formed within the stacked film 12, and each sacrificial layer 11 is removed by wet etching through the slits ST. At this time, each sacrificial layer 11 in the central portion P1 is sandwiched between two slits ST, so it is generally completely removed by this wet etching. On the other hand, each sacrificial layer 11 in the end portion P2 is not sandwiched between two slits ST, so it is generally only partially removed by this wet etching. Therefore, Figure 17 The sacrificial layer 11 remaining within end P2 is shown.

[0088] Then, as described above, proceed as follows: Figure 15 The steps shown. As a result, the finished semiconductor device manufactured under these conditions will also have an electrode layer 6, an insulating layer 8 and a sacrificial layer 11, and will have memory holes H1 in the multilayer film containing the electrode layer 6, the insulating layer 8 and the sacrificial layer 11.

[0089] The foregoing has described several embodiments, but these embodiments are merely illustrative and not intended to limit the scope of the invention. The novel apparatus and method described herein can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass all such embodiments or variations as included in the scope or spirit of the invention.

[0090] [Explanation of Symbols]

[0091] 1: Core insulating film

[0092] 2: Channel semiconductor layer

[0093] 3: Tunnel insulation film

[0094] 4: Charge accumulation layer

[0095] 5: Barrier insulating film

[0096] 5a: Insulating film

[0097] 5b: Insulating film

[0098] 6: Electrode layer

[0099] 6a: Barrier metal layer

[0100] 6b: Electrode material layer

[0101] 7: Substrate

[0102] 8: Insulation layer

[0103] 8a: Main area

[0104] 8b: Lower region

[0105] 8c: Upper region

[0106] 8d: Main area

[0107] 9: Stacked membranes

[0108] 11: Sacrifice Layer

[0109] 12: Stacked membrane.

Claims

1. A semiconductor device comprising: Substrate; A laminated film comprising a plurality of first layers and a plurality of second layers alternately disposed on the substrate; A charge storage layer is disposed on the side of the laminated film, separated from the first insulating film; and A semiconductor layer is disposed on the side of the charge storage layer, which is separated from the second insulating film. One of the plurality of first layers includes: Region 1 contains carbon of concentration 1; and The second region contains a second concentration of carbon higher than the first concentration. The second region includes a lower region or an upper region. The lower region is located below the first region, has an upper surface that contacts the lower surface of the first region, is in contact with the first insulating film, and is located in a first direction of the first region. The upper region is located above the first region, has a lower surface that contacts the upper surface of the first region, is in contact with the first insulating film, and is located in a second direction of the first region. The first direction and the second direction are perpendicular to the surface of the substrate.

2. The semiconductor device according to claim 1, wherein The first concentration is 1.4–2.6 atomic%. The second concentration is 2.8 atomic% or higher.

3. The semiconductor device according to claim 1, wherein The second region includes both the lower region and the upper region.

4. The semiconductor device according to claim 1, wherein The second region includes only the lower region and the lower region of the upper region.

5. The semiconductor device according to claim 1, wherein The second region includes only the lower region and the upper region of the upper region.

6. The semiconductor device according to claim 1, wherein The thickness of the lower region or the upper region is thinner than the thickness of the first region.

7. The semiconductor device according to claim 1, wherein The thickness of the lower region or the upper region is less than 1 nm.

8. The semiconductor device according to claim 1, wherein Each of the plurality of first layers includes a first insulating layer. Each of the plurality of second layers contains an electrode layer.

9. The semiconductor device according to claim 1, wherein Each of the plurality of first layers includes a first insulating layer. Each of the plurality of second layers comprises a second insulating layer that is different from the first insulating layer.

10. The semiconductor device of claim 1, wherein Each of the plurality of first layers contains silicon, oxygen, and carbon.

11. The semiconductor device of claim 10, wherein Each of the plurality of first layers is a silicon oxide film containing carbon as an impurity.

12. The semiconductor device according to claim 1, wherein The first region is in contact with the first insulating film.

13. The semiconductor device according to claim 1, wherein The second region includes only one of the lower region and the upper region.

14. The semiconductor device of claim 1, wherein Each of the plurality of first layers includes a first insulating layer. Each of the plurality of second layers includes an electrode layer and a second insulating layer that is different from the first insulating layer.

15. The semiconductor device according to claim 1, wherein The laminated film includes a third region and a fourth region, the third region including a plurality of first insulating layers and a plurality of electrode layers alternately disposed on the substrate, and the fourth region including the plurality of first insulating layers and a plurality of second insulating layers alternately disposed on the substrate.

16. A method for manufacturing a semiconductor device, comprising: Forming a laminated film comprising a plurality of first layers and a plurality of second layers alternately disposed on a substrate; A charge storage layer is formed by separating the first insulating film on the side of the laminated film; A semiconductor layer is formed by separating a second insulating film on the side of the charge accumulation layer; One of the plurality of first layers is configured to include: Region 1 contains carbon of concentration 1; and The second region contains a second concentration of carbon higher than the first concentration. The second region includes a lower region or an upper region. The lower region is located below the first region, has an upper surface that contacts the lower surface of the first region, is in contact with the first insulating film, and is located in a first direction of the first region. The upper region is located above the first region, has a lower surface that contacts the upper surface of the first region, is in contact with the first insulating film, and is located in a second direction of the first region. The first direction and the second direction are perpendicular to the surface of the substrate.

17. The method of manufacturing a semiconductor device according to claim 16, wherein... Each of the plurality of first layers includes a first insulating layer. Each of the plurality of second layers comprises a second insulating layer that is different from the first insulating layer; The method for manufacturing the semiconductor device further includes: Multiple recesses are formed by removing the multiple second layers; Multiple electrode layers are formed within the multiple recesses.

18. The method of manufacturing a semiconductor device according to claim 16, wherein The first and second regions are formed in such a way that the lower region is formed, the first region is formed on the lower region, and the upper region is formed on the first region.

19. The method of manufacturing a semiconductor device according to claim 16, wherein The first and second regions are formed using a first gas containing carbon.

20. The method of manufacturing a semiconductor device according to claim 19, wherein The flow rate of the first gas when the second region is formed is set to be less than the flow rate of the first gas when the first region is formed.

21. The method of manufacturing a semiconductor device according to claim 19, wherein The first gas contains CO, CO2, and C. X H Y One or more of SiH3(CH3), SiH2(CH3)2, SiH(CH3)3 and Si(CH3)4, wherein, C represents carbon, O represents oxygen, H represents hydrogen, Si represents silicon, X represents an integer from 1 to 4, and Y represents an integer from 1 to 4.

22. The method of manufacturing a semiconductor device according to claim 19, wherein... The first and second regions are formed using the first gas containing carbon and the second gas containing silicon.

23. The method of manufacturing a semiconductor device according to claim 22, wherein... The flow rate of the second gas when forming the second region is set to be less than the flow rate of the second gas when forming the first region.

24. The method of manufacturing a semiconductor device according to claim 16, wherein The chamber pressure, RF power, or inert gas flow rate when forming the second region are set to values ​​different from those when forming the first region.

25. The method for manufacturing a semiconductor device according to claim 16, further comprising: A plurality of slits extending in the first and third directions are formed within the laminated film; By wet etching from the plurality of slits, a first portion of the plurality of second insulating layers contained in the plurality of second layers is removed, thereby forming a plurality of cavities within the laminated film; as well as Multiple electrode layers are formed within the multiple cavities; and The laminated film includes a region not sandwiched by the plurality of slits; The wet etching is performed in such a way that the second portion of the plurality of second insulating layers is retained in the area not sandwiched by the plurality of slits.

26. The method of manufacturing a semiconductor device according to claim 25, wherein The plurality of first layers comprises a plurality of first insulating layers.

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