Magnetic memory device

Abstract

Embodiments provide a magnetic memory device that improves memory cell retention characteristics. According to one embodiment, a magnetic memory device includes first, second, and third conductor layers; and a memory cell coupled to the first, second, and third conductor layers. The memory cell includes a fourth conductor layer and a magnetoresistive effect element. The fourth conductor layer includes first, second, and third portions coupled to the first, second, and third conductor layers, respectively. The third portion is located between the first and second portions. The magnetoresistive effect element is coupled between the third conductor layer and the fourth conductor layer. The fourth conductor layer includes a magnetic layer and a non-magnetic layer located between the magnetic layer and the magnetoresistive effect element. The magnetic layer has a first saturation magnetization during a standby state or a read state of the memory cell, and has a second saturation magnetization greater than the first saturation magnetization during a write state of the memory cell.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Japanese Patent Application 2021-201548, filed December 13, 2021, and U.S. Patent Application 17 / 901773, filed September 1, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to magnetic storage devices. Background Technology

[0004] Magnetic memory devices that use magnetoresistive elements as storage elements are known. Various methods have been proposed for writing data into magnetoresistive elements. Summary of the Invention

[0005] The embodiments provide a magnetic memory device that improves the retention characteristics of memory cells.

[0006] Generally, according to one embodiment, a magnetic memory device includes: a first conductor layer; a second conductor layer; a third conductor layer; and a three-terminal memory cell coupled to the first conductor layer, the second conductor layer, and the third conductor layer. The memory cell includes: a fourth conductor layer comprising a first portion coupled to the first conductor layer, a second portion coupled to the second conductor layer, and a third portion coupled to the third conductor layer and located between the first and second portions; and a magnetoresistive element coupled between the third conductor layer and the fourth conductor layer. The fourth conductor layer includes a magnetic layer and a first non-magnetic layer disposed between the magnetic layer and the magnetoresistive element. The magnetic layer has a first saturation magnetization during a standby state or a read state of the memory cell, and a second saturation magnetization greater than the first saturation magnetization during a write state of the memory cell. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a configuration example of a magnetic storage device according to a first embodiment.

[0008] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of a memory primitive array according to the first embodiment.

[0009] Figure 3 This is a plan view showing an example of a planar layout of a memory primitive array according to the first embodiment.

[0010] Figure 4 It is along Figure 3 The cross-sectional view taken by line IV-IV shows an example of the cross-sectional structure of the memory primitive array according to the first embodiment.

[0011] Figure 5 yes Figure 4 A cross-sectional view of region V shows an example of the cross-sectional structure of the magnetoresistive element and peripheral wiring according to the first embodiment.

[0012] Figure 6 yes Figure 4 A cross-sectional view of region V shows an example of the cross-sectional structure of the magnetoresistive element and peripheral wiring according to the first embodiment.

[0013] Figure 7 This is a view illustrating an example of the relationship between the temperature of the magnetic layer and the saturation magnetization according to the first embodiment.

[0014] Figure 8 This is a view illustrating an example of the relationship between various operations and the characteristics of the magnetic layer in a magnetic storage device according to a first embodiment.

[0015] Figure 9 This is a circuit diagram illustrating an example of a write operation in a magnetic storage device according to a first embodiment.

[0016] Figure 10 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a first embodiment.

[0017] Figure 11 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a first embodiment.

[0018] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element and the peripheral wiring according to the second embodiment.

[0019] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element and the peripheral wiring according to the second embodiment.

[0020] Figure 14 This is a view illustrating an example of the relationship between the magnetic layer composition and the saturation magnetization according to the second embodiment.

[0021] Figure 15 This is a view illustrating an example of the relationship between the composition of the magnetic layer and the coercivity according to the second embodiment.

[0022] Figure 16 This is a view illustrating an example of the relationship between various operations and the characteristics of the magnetic layer in a magnetic storage device according to a second embodiment.

[0023] Figure 17 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a second embodiment.

[0024] Figure 18 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a second embodiment.

[0025] Figure 19 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to a first variant.

[0026] Figure 20 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to the second variation.

[0027] Figure 21 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to the third variation. Detailed Implementation

[0028] In the following description, some embodiments will be described with reference to the accompanying drawings. In this description, components having the same function and configuration are identified by common reference numerals. Furthermore, when distinguishing multiple components with common reference numerals, a suffix is ​​added to the common reference numerals to differentiate these components. When it is not necessary to distinguish multiple components, only the common reference numerals are added to the multiple components, without adding subscripts. Suffixes are not limited to subscripts and superscripts; for example, they include lowercase letters, symbols, and indices indicating the order in which they are added to the end of the reference numerals.

[0029] In this specification, a magnetic memory device is, for example, a magnetoresistive random access memory (MRAM). A magnetic memory device includes magnetoresistive elements as storage elements. A magnetoresistive element is a variable resistive element that exhibits a magnetoresistive effect through a magnetic tunnel junction (MTJ). A magnetoresistive element is also referred to as an MTJ element.

[0030] 1. First Embodiment

[0031] The first embodiment will be described.

[0032] 1.1 Configuration

[0033] First, the configuration of the magnetic storage device according to the first embodiment will be described.

[0034] 1.1.1 Magnetic storage devices

[0035] Figure 1 This is a block diagram illustrating a configuration example of a magnetic storage device according to a first embodiment. The magnetic storage device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0036] The memory cell array 10 is a data storage unit in the magnetic storage device 1. The memory cell array 10 includes a plurality of memory cells MC. Each of the plurality of memory cells MC is associated with a group of rows and columns. Memory cells MC in the same row are coupled to the same word line WL, and memory cells MC in the same column are coupled to the same group of read bit lines RBL and write bit lines WBL.

[0037] Row selection circuit 11 is a circuit that selects rows of memory cell array 10. Row selection circuit 11 is coupled to memory cell array 10 via word lines WL. Decoding result (row address) of address ADD is provided to row selection circuit 11 from decoding circuit 13. Row selection circuit 11 selects the word line WL corresponding to the row based on the decoding result of address ADD. In the following text, the selected word line WL is referred to as the selected word line WL. In addition, word lines WL other than the selected word line WL are referred to as non-selected word lines WL.

[0038] Column selection circuit 12 is a circuit that selects columns of memory cell array 10. Column selection circuit 12 is coupled to memory cell array 10 via read bit line RBL and write bit line WBL. Decoding result (column address) of address ADD is provided to column selection circuit 12 from decoding circuit 13. Column selection circuit 12 selects the read bit line RBL and write bit line WBL corresponding to the column based on the decoding result of address ADD. In the following text, the selected read bit line RBL and the selected write bit line WBL will be referred to as selected bit line RBL and selected bit line WBL, respectively. Furthermore, read bit line RBL other than selected bit line RBL and write bit line WBL other than selected bit line WBL will be referred to as non-selected bit line RBB and non-selected bit line WBL, respectively.

[0039] Decoding circuit 13 is a decoder that decodes the address ADD from input / output circuit 17. Decoding circuit 13 provides the decoding result of address ADD to row selection circuit 11 and column selection circuit 12. Address ADD includes column address and row address.

[0040] The write circuit 14 includes, for example, a write driver (not shown). The write circuit 14 writes data to the memory primitive MC.

[0041] The read circuit 15 includes, for example, a sense amplifier (not shown). The read circuit 15 reads data from the memory cell MC.

[0042] The voltage generation circuit 16 uses a power supply voltage provided from an external source (not shown) to the magnetic storage device 1 to generate voltages for various operations of the memory cell array 10. For example, the voltage generation circuit 16 generates various voltages required for write operations and outputs these voltages to the write circuit 14. Furthermore, for example, the voltage generation circuit 16 generates various voltages required for read operations and outputs these voltages to the read circuit 15.

[0043] Input / output circuit 17 controls communication with the outside of magnetic storage device 1. Input / output circuit 17 transmits address ADD from the outside of magnetic storage device 1 to decoding circuit 13. Input / output circuit 17 transmits command CMD from the outside of magnetic storage device 1 to control circuit 18. Input / output circuit 17 transmits various control signals CNT between the outside of magnetic storage device 1 and control circuit 18. Input / output circuit 17 transmits data DAT from the outside of magnetic storage device 1 to write circuit 14, and outputs data DAT transmitted from read circuit 15 to the outside of magnetic storage device 1.

[0044] The control circuit 18 includes, for example, a processor such as a central processing unit (CPU) and a read-only memory (ROM). The control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decoding circuit 13, writing circuit 14, reading circuit 15, voltage generation circuit 16, and input / output circuit 17 in the magnetic storage device 1 based on the control signal CNT and the command CMD.

[0045] 1.1.2 Memory Cell Array

[0046] Next, the configuration of the memory cell array of the magnetic memory device according to the first embodiment will be described.

[0047] Circuit configuration

[0048] Figure 2 This is a circuit diagram illustrating an example circuit configuration of a memory cell array according to the first embodiment. Figure 2 In the text, each of the word line WL, read bit line RBL, and write bit line WBL is categorized and shown by a suffix including an index ("<>").

[0049] The memory cell array 10 includes multiple memory cells MC, multiple word lines WL, multiple read bit lines RBL, and multiple write bit lines WBL. Figure 2 In the example, the multiple memory primitives MC include (M+1)×(N+1) memory primitives MC<0,0>, MC<0,1>, ..., MC<0,N>, MC<1,0>, ... and MC<0,N>.<M,N> (Where M and N are integers greater than or equal to 2). In Figure 2The example illustrates the case where M and N are integers greater than or equal to 2, but this disclosure is not limited thereto. M and N can be 0 or 1. Multiple word lines WL comprise (M+1) word lines WL. <0> WL <1> ... and WL <m>Multiple read bit lines RBL include (N+1) read bit lines RBL. <0> RBL <1> ...and RBL <n>Multiple write bit lines (WBL) include (N+1) write bit lines (WBL). <0> WBL <1> ...and WBL <n>.

[0050] Multiple memory cells (MCs) are arranged in a matrix within the memory cell array 10. Each memory cell (MC) is associated with a group comprising a set of read bit lines (RBLs) and write bit lines (WBLs) and a word line (WL) from a set of read bit lines (RBLs) and write bit lines (WBLs), respectively. In other words, the memory cells (MCs)<i,j> (0≤i≤M,0≤j≤N) Coupled to word line WL Read bit line RBL <j>and write bit line WBL <j>.

[0051] Memory primitive MC<i,j> It is a three-terminal memory cell, which includes a word line WL. The first end is coupled to the write bit line WBL <j>The second end is coupled to the read bit line RBL <j>The third end. Memory primitive MC<i,j> Including switching element SEL1<i,j> and SEL2<i,j> MTJ magnetoresistive element<i,j> and wiring SOTL<i,j> .

[0052] SOTL cabling<i,j> It includes a first part, a second part, and a third part located between the first and second parts. (SOTL wiring)<i,j> The first part is coupled to the word line WL SOTL cabling<i,j> The second part is coupled to the write bit line WBL <j>SOTL cabling<i,j> The third part is coupled to the read bit line RBL. <j>Switching element SEL1<i,j> Coupled to the SOTL wiring<i,j> The second part and the write bit line WBL <j>Between. Magnetoresistive element MTJ<i,j> Coupled to the SOTL wiring<i,j> The third part and the read bit line RBL <j>Between. Switching component SEL2<i,j> Coupled to the magnetoresistive element MTJ<i,j> and read bit line RBL <j>between.

[0053] Switching elements SEL1 and SEL2 are two-terminal switching elements. Two-terminal switching elements differ from three-terminal switching elements such as transistors. SEL1 and SEL2 have threshold voltages Vth1 and Vth2, respectively. When the voltages applied to SEL1 and SEL2 are less than the threshold voltages Vth1 and Vth2, respectively, switching elements SEL1 and SEL2 are in a "high resistance" state or a "off" state. As a result, SEL1 and SEL2 are not conductive. When the voltages applied to SEL1 and SEL2 are equal to or greater than the threshold voltages Vth1 and Vth2, respectively, SEL1 and SEL2 change to a "low resistance" state or a "conducting" state. As a result, SEL1 and SEL2 are conductive. More specifically, for example, when the voltage applied to the corresponding memory cell MC is lower than the threshold voltages Vth1 and Vth2, each of the switching elements SEL1 and SEL2 cuts off the current (enters the off state), acting as an insulator with a high resistance value. When the voltage applied to the corresponding memory cell MC exceeds the threshold voltages Vth1 and Vth2, each of the switching elements SEL1 and SEL2 allows current to flow (enters the conducting state), acting as a conductor with low resistance. Regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the flowing current), the switching elements SEL1 and SEL2 switch between allowing current to flow or cutting off current based on the magnitude of the voltage applied to the corresponding memory cell MC.

[0054] The SOTL (Site Layout Transmission Line) is a current path within a memory cell (MC). For example, when switching element SEL1 is on and switching element SEL2 is off, the SOTL serves as a current path between the word line WL and the write bit line WBL. Furthermore, for example, when switching element SEL1 is off and switching element SEL2 is on, a portion of the SOTL serves as a current path between the word line WL and the read bit line RBL.

[0055] The magnetoresistive element (MTJ) is a variable resistance element. The MTJ can switch its resistance value between a low-resistance state and a high-resistance state based on the current along its path, controlled by switching elements SEL1 and SEL2. The MTJ acts as a storage element, storing data in a non-volatile manner by changing its resistance state.

[0056] Floor plan

[0057] Next, the planar layout of the memory cell array according to the first embodiment will be described. Hereinafter, the plane parallel to the substrate surface will be referred to as the XY plane. The direction in which the magnetic memory device 1 is disposed relative to the substrate surface is the Z direction or the upward direction. The directions that intersect each other in the XY plane are the X direction and the Y direction.

[0058] Figure 3 This is a plan view illustrating an example of a planar layout of a memory cell array according to the first embodiment. Figure 3 In the text, structures such as the insulating layer are omitted.

[0059] The memory cell array 10 also includes multiple vertical structures V1, multiple vertical structures V2, and multiple vertical structures V3. Each of the multiple vertical structures V1 includes a switching element SEL1. Each of the multiple vertical structures V2 includes a magnetoresistive element MTJ and a switching element SEL2.

[0060] Multiple write bit lines (WBLs) are arranged in the X direction. Each of the multiple write bit lines (WBLs) extends in the Y direction.

[0061] Each of the multiple word lines (WL) is positioned above one of the multiple write bit lines (WBL). The multiple word lines (WL) are arranged in the Y direction. Each of the multiple word lines (WL) extends in the X direction.

[0062] Each of the multiple routing SOTLs is positioned above one of the multiple word lines WL. In a planar view, each of the multiple routing SOTLs has a rectangular shape that is longer in the Y direction than in the X direction. Each of the multiple routing SOTLs extends in the Y direction. In a planar view, each of the multiple routing SOTLs is arranged in a matrix form corresponding to the positions where it overlaps with a word line WL and a write bit line WBL.

[0063] Each of the multiple read bit lines RBL is positioned above one of the multiple routing SOTLs. The multiple read bit lines RBL are arranged in the X direction. Each of the multiple read bit lines RBL extends in the Y direction. In a plan view, each of the multiple read bit lines RBL is positioned at a location overlapping with the multiple write bit lines WBL.

[0064] Multiple vertical structures V1 extend in the Z direction. In the plan view, the multiple vertical structures V1 have a circular shape. Each of the multiple vertical structures V1 is located between a corresponding write bit line WBL and a corresponding routing SOTL. That is, each of the multiple vertical structures V1 is coupled to the second part of the corresponding routing SOTL.

[0065] Multiple vertical structures V2 extend in the Z direction. In the plan view, the multiple vertical structures V2 have a circular shape. Each of the multiple vertical structures V2 is located between a corresponding read bit line RBL and a corresponding routing SOTL. That is, each of the multiple vertical structures V2 is coupled to the third part of the corresponding routing SOTL.

[0066] Multiple vertical structures V3 extend in the Z direction. In the plan view, the multiple vertical structures V3 have a circular shape. Each of the multiple vertical structures V3 is located between a corresponding word line WL and a corresponding routing SOTL. That is, each of the multiple vertical structures V3 is coupled to the first part of the corresponding routing SOTL.

[0067] In the above configuration, a group consisting of a wiring SOTL, a vertical structure V1 coupled to the wiring SOTL, a vertical structure V2 and a vertical structure V3 is used as a memory primitive MC.

[0068] Cross-section structure

[0069] Next, the cross-sectional structure of the memory primitive array according to the first embodiment will be described.

[0070] Figure 4 It is along Figure 3 The cross-sectional view taken along line IV-IV shows an example of the cross-sectional structure of a memory primitive array according to the first embodiment. The memory primitive array 10 includes a semiconductor substrate 20 and hierarchical structures L1 and L2. Hierarchical structure L1 includes conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and element layers 22_1, 27_1, and 28_1. Hierarchical structure L2 includes conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and element layers 22_2, 27_2, and 28_2. Configurations with the suffix "_x" indicate that the configuration belongs to hierarchical structure Lx (x is an integer greater than or equal to 1).

[0071] Layered structures L1 and L2 are stacked in this order along the Z-direction above the semiconductor substrate 20. Each of the layered structures L1 and L2 corresponds to Figure 3 The plan layout shown.

[0072] Peripheral circuitry, such as row selection circuitry 11 and column selection circuitry 12, can be disposed between semiconductor substrate 20 and layered structure L1. Alternatively, no circuitry may be formed between semiconductor substrate 20 and layered structure L1. When no circuitry is formed between semiconductor substrate 20 and layered structure L1, shallow trench isolation (STI) may be formed in a portion of semiconductor substrate 20 located below layered structure L1.

[0073] The hierarchical structure L1 will be described.

[0074] Conductor layer 21_1 is disposed above semiconductor substrate 20. Conductor layer 21_2 serves as write bit line WBL. Conductor layer 21_1 extends in the Y direction.

[0075] Component layer 22_1 is disposed on the upper surface of conductor layer 21_1. Component layer 22_1 is used as switching component SEL1.

[0076] Conductor layer 23_1 is disposed on the upper surface of element layer 22_1. Conductor layer 23_1 serves as a contact. Element layer 22_1 and conductor layer 23_1 constitute a vertical structure V1.

[0077] Conductor layer 24_1 is disposed on the upper surface of conductor layer 23_1. Conductor layer 24_1 serves as a wiring SOTL. The portion of conductor layer 24_1 in contact with conductor layer 23_1 corresponds to the second portion of the wiring SOTL. Conductor layer 24_1 extends in the Y direction.

[0078] Conductor layer 25_1 is disposed on the lower surface of a portion of conductor layer 24_1 that is different from the portion where conductor layer 23_1 is disposed. The portion of conductor layer 24_1 that contacts conductor layer 25_1 corresponds to the first portion of wiring SOTL. Conductor layer 25_1 serves as a contact. Conductor layer 25_1 constitutes the vertical structure V3.

[0079] Conductor layer 26_1 is disposed on the lower surface of conductor layer 25_1. Conductor layer 26_1 serves as word line WL. Conductor layer 26_1 extends in the X direction.

[0080] Component layer 27_1 is disposed on the upper surface of a portion of conductor layer 24_1 located between the portion where conductor layer 23_1 is disposed and the portion where conductor layer 25_1 is disposed. The portion of conductor layer 24_1 in contact with component layer 27_1 corresponds to the third portion of the SOTL wiring. Component layer 27_1 serves as a magnetoresistive element MTJ.

[0081] Component layer 28_1 is disposed on the upper surface of component layer 27_1. Component layer 28_1 is used as a switching component SEL2. Component layers 27_1 and 28_1 constitute a vertical structure V2.

[0082] Conductor layer 29_1 is disposed on the upper surface of element layer 28_1. Conductor layer 29_1 serves as the read bit line RBL. Conductor layer 29_1 extends in the Y direction.

[0083] Using the above configuration, the group of conductor layers 24_1 in the layered structure L1 and the vertical structures V1, V2 and V3 are used as a memory cell MC, which has three terminals respectively coupled to conductor layers 21_1, 26_1 and 29_1.

[0084] Layered structure L2 has the same configuration as layered structure L1. That is, conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and element layers 22_2, 27_2, and 28_2 have the same structure and function as conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and element layers 21_1, 27_1, and 28_1, respectively. As a result, the group of conductor layer 24_2 in layered structure L2, as well as the vertical structures V1, V2, and V3, serve as a memory primitive MC, which has three terminals respectively coupled to conductor layers 21_2, 26_2, and 29_2.

[0085] 1.1.3 Magnetoresistive components and peripheral wiring

[0086] Next, the configuration of the magnetoresistive elements and peripheral wiring of the magnetic memory device according to the first embodiment will be described.

[0087] Figure 5 and Figure 6 yes Figure 4 A cross-sectional view of region V shows an example of the cross-sectional structure of the magnetoresistive element and peripheral wiring according to the first embodiment. Figure 5 This corresponds to the case where the SOTL wiring is at a low temperature. Figure 6 This corresponds to the situation where the SOTL wiring is at a high temperature.

[0088] The conductor layer 24, which serves as the SOTL wiring layer, includes a non-magnetic layer 24a, a magnetic layer 24b, and a non-magnetic layer 24c. The component layer 27 includes a ferromagnetic layer 27a, a non-magnetic layer 27b, a ferromagnetic layer 27c, a non-magnetic layer 27d, and a ferromagnetic layer 27e.

[0089] First, the structural details of conductor layer 24 will be described.

[0090] The non-magnetic layer 24a is a non-magnetic conductive film. The non-magnetic layer 24a serves as the substrate layer for the magnetic layer 24b. From the viewpoint of improving film adhesion, the non-magnetic layer 24a comprises tantalum (Ta), tungsten (W), titanium (Ti), titanium nitride (TiN), etc. The film thickness of the non-magnetic layer 24a is preferably greater than or equal to 0.5 nanometers and less than or equal to 5 nanometers. The lower limit of the film thickness of the non-magnetic layer 24a is determined from the viewpoint of film continuity in the conductive layer 24. Furthermore, from the viewpoint of preventing current shunting, the film thickness of the non-magnetic layer 24a is more preferably less than or equal to 3 nanometers.

[0091] The magnetic layer 24b is provided on the upper surface of the non-magnetic layer 24a. The magnetic layer 24b is a conductive film that exhibits a reversible magnetic phase transition or magnetic phase shift between an antiferromagnetic phase and a ferromagnetic phase. The magnetic layer 24b, for example, has an alloy (FeRh alloy) containing iron (Fe) and rhodium (Rh). In the FeRh alloy, the composition ratio (at%) of iron and rhodium is about 50:50, and a magnetic phase shift (magnetic phase transition) occurs. The composition ratio of iron in the FeRh alloy is preferably 50 ± 10 at% (greater than or equal to 40 at% and less than or equal to 60 at%). The composition of the magnetic layer 24b can be analyzed in a thin film state by energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), and X-ray fluorescence. From the viewpoint of preventing current shunting and generating Joule heat in the magnetic layer 24b, the non-magnetic layer 24a is preferably a thin film with high resistance. The film thickness of the magnetic layer 24b is preferably greater than or equal to 2 nm and less than or equal to 10 nm.

[0092] The magnetic phase transition of the magnetic layer 24b occurs with the threshold temperature TA as the boundary. That is, the threshold temperature TA is the phase transition temperature of the magnetic layer 24b. Specifically, as Figure 5 shown, when the temperature T of the magnetic layer 24b is lower than the threshold temperature TA (T < TA), the magnetic layer 24b exhibits antiferromagnetic characteristics. On the other hand, as Figure 6 shown, when the temperature T of the magnetic layer 24b exceeds the threshold temperature TA (T > TA), the magnetic layer 24b exhibits ferromagnetic characteristics.

[0093] When the magnetic layer 24b exhibits ferromagnetic characteristics, the saturation magnetization (Ms) of the non-magnetic layer 24a is significantly greater than zero. The magnetic layer 24b generates a leakage magnetic field SF outside the magnetic layer 24b. Due to, for example, shape anisotropy, the magnetization direction of the magnetic layer 24b is stable along the Y direction. The magnetization direction of the magnetic layer 24b is reversed according to the direction of the current flowing in the magnetic layer 24b. That is, the magnetic layer 24b has an axis easy to magnetize in the extending direction (±Y direction) of the magnetic layer 24b. On the other hand, when the magnetic layer 24b exhibits antiferromagnetic characteristics, the magnetic moments of the magnetic layer 24b are canceled inside. As a result, the saturation magnetization Ms of the magnetic layer 24b becomes zero. Therefore, the magnetic layer 24b does not generate a leakage magnetic field SF outside the magnetic layer 24b.

[0094] The magnetic layer 24b may further contain iridium (Ir), palladium (Pd), ruthenium (Ru), osmium (Os), platinum (Pt), gold (Au), silver (Ag), or copper (Cu) as additives. When the FeRh alloy is used for the magnetic layer 24b, these additives are preferably added by substituting rhodium (Rh). By including additives in the magnetic layer 24b, the threshold temperature TA can be adjusted to a desired value.

[0095] Furthermore, the magnetic layer 24b may contain cobalt (Co) or nickel (Ni) as additional additives. The additional additives are preferably added by replacing iron (Fe). With the inclusion of this additional additive, the magnetic layer 24b can be tuned in a ferromagnetic state to achieve a controlled saturation magnetization Ms. As a result, the strength of the leakage magnetic field SF from the magnetic layer 24b can be adjusted.

[0096] Figure 7 This is a view illustrating an example of the relationship between the temperature and saturation magnetization of the magnetic layer according to the first embodiment. Figure 7 The diagram shows the hysteresis H1 and H2 of the saturation magnetization Ms with respect to the temperature T of the magnetic layer 24b. The solid line hysteresis H1 corresponds to, for example, the case where the magnetic layer 24b does not contain any additives. The dashed line hysteresis H2 corresponds to, for example, the case where the magnetic layer 24b contains additives.

[0097] As shown by hysteresis H1, when the additive is absent, the magnetic layer 24b undergoes a phase transition at a threshold temperature TA1. On the other hand, as shown by hysteresis H2, when the additive is included, the magnetic layer 24b undergoes a phase transition at a threshold temperature TA2, which is higher than the threshold temperature TA1. By changing the composition ratio (at%) of the additive, the level of the threshold temperature TA2 and the saturation magnetization Ms after ferromagnetization can be adjusted. The composition of the magnetic layer 24b containing additive X is expressed as Fe... a (Rh (1-b) X b ) (100-a) When this is the case, the composition ratio b can be adjusted within a range of, for example, greater than or equal to 0 at% and less than or equal to 0.1 at%.

[0098] The structural details of conductor layer 24 will be referenced again. Figure 5 and Figure 6 Describe it.

[0099] A non-magnetic layer 24c is disposed on the upper surface of the magnetic layer 24b. The non-magnetic layer 24c is a conductive film made of a non-magnetic heavy metal. For example, the non-magnetic layer 24c contains at least one element selected from tantalum (Ta), tungsten (W), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).

[0100] The nonmagnetic layer 24c is the layer that generates spin-orbit torque (SOT), which is mainly caused by the spin-hole effect induced by the current flowing in the nonmagnetic layer 24c. To obtain a large SOT, it is necessary to increase the current flowing through the nonmagnetic layer 24c, that is, to increase the current density. Therefore, it is necessary to prevent current shunting to the other layers, the nonmagnetic layer 24a and the magnetic layer 24b. The SOT acts on the ferromagnetic layer 27a. The film thickness of the nonmagnetic layer 24c is preferably, for example, greater than or equal to 0.3 nanometers and less than or equal to 10 nanometers. From the viewpoint of film continuity in the conductor layer 24, the film thickness of the nonmagnetic layer 24c is preferably greater than or equal to 1 nanometer.

[0101] Next, the structural details of component layer 27 will be described.

[0102] A ferromagnetic layer 27a is disposed on the upper surface of the non-magnetic layer 24c. The ferromagnetic layer 27a is a conductive film with ferromagnetic properties. The ferromagnetic layer 27a serves as a storage layer. The ferromagnetic layer 27a has an axial direction that facilitates magnetization in a direction perpendicular to the film surface (Z direction).

[0103] When magnetic layer 24b exhibits antiferromagnetic properties, a leakage magnetic field SF is not applied to ferromagnetic layer 27a. That is, when magnetic layer 24b exhibits antiferromagnetic properties, a bias magnetic field is not applied to ferromagnetic layer 27a. On the other hand, when magnetic layer 24b exhibits ferromagnetic properties, a leakage magnetic field SF is applied to ferromagnetic layer 27a. That is, when magnetic layer 24b exhibits ferromagnetic properties, a bias magnetic field is applied to ferromagnetic layer 27a. The spin-orbit torque generated in the non-magnetic layer 24c acts on ferromagnetic layer 27a. When a predetermined leakage magnetic field SF and a predetermined spin-orbit torque are applied, the magnetization direction of ferromagnetic layer 27a is reversed.

[0104] The ferromagnetic layer 27a contains iron (Fe). The ferromagnetic layer 27a may also contain at least one element selected from cobalt (Co) and nickel (Ni). Furthermore, the ferromagnetic layer 27a may also contain boron (B). More specifically, for example, the ferromagnetic layer 27a contains cobalt-iron-boron (CoFeB) or iron boride (FeB).

[0105] From the viewpoint of increasing the retention energy ΔE of the storage layer used for data retention, the ferromagnetic layer 27a may comprise a stacked film of layers A and B. Layer A is a layer containing at least one element selected from cobalt (Co), iron (Fe), and nickel (Ni). Layer B is a layer containing at least one element selected from platinum (Pt), iridium (Ir), ruthenium (Ru), osmium (Os), palladium (Pd), and gold (Au). Examples of stacked films include Co / Pt stacked films, Co / Ir stacked films, Co / Pd stacked films, etc. When (001) oriented magnesium oxide (MgO) is used for the nonmagnetic layer 27b, the stacked film is also stacked with a layer C (interface layer) containing cobalt iron boron (CoFeB), etc. In this case, the stacked film is in contact with the nonmagnetic layer 24c, and layer C is in contact with the nonmagnetic layer 27b.

[0106] A nonmagnetic layer 27b is disposed on the upper surface of the ferromagnetic layer 27a. The nonmagnetic layer 27b is a nonmagnetic insulating film. The nonmagnetic layer 27b serves as a tunnel barrier layer. The nonmagnetic layer 27b is disposed between the ferromagnetic layers 27a and 27c, and together with these two ferromagnetic layers, forms a magnetic tunnel junction. Furthermore, when an initial amorphous layer such as cobalt-iron-boron (CoFeB) is used as the interface layer between the ferromagnetic layers 27a and 27c, the nonmagnetic layer 27b serves as a core seed material during the crystallization process of the ferromagnetic layer 27a, for growing a crystalline film from the interface with the ferromagnetic layer 17a. Here, the initial amorphous layer is immediately in an amorphous state after film deposition and crystallizes after annealing. The nonmagnetic layer 27b has a NaCl-type crystal structure with an orientation of (001). Examples of compounds used for the nonmagnetic layer 27b include magnesium oxide (MgO). When magnesium oxide (MgO) is used for the nonmagnetic layer 27b, the (001) interface of magnesium oxide (ZnO) and the (001) interface of cobalt iron boron (CoFeB) are grown aligned with each other. Therefore, cobalt iron boron (CoFeB) has a (100) oriented body-centered cubic (BCC) structure. When (001) oriented magnesium oxide (MgO), magnesium aluminum oxide (MgAlO), etc. are used, cobalt iron boron (CoFeB) etc. are not required as an interface layer.

[0107] A ferromagnetic layer 27c is disposed on the upper surface of the non-magnetic layer 27b. The ferromagnetic layer 27c is a conductive film with ferromagnetic properties. The ferromagnetic layer 27c serves as a reference layer. The ferromagnetic layer 27c has an axis that is easily magnetized in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic layer 27c is fixed. Figure 5 In the example, the magnetization direction of the ferromagnetic layer 27c points towards the ferromagnetic layer 27a. The phrase "the magnetization direction is fixed" means that the magnetization direction will not change due to a torque having a magnitude that can reverse the magnetization direction of the ferromagnetic layer 27a. The ferromagnetic layer 27c includes, for example, at least one alloy film selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). Stacked films such as Co / Pt stacked films or Co / Pd stacked films can also be used. When (001) oriented MgO is used for the nonmagnetic layer 27b, an initial amorphous layer (e.g., CoFeB, etc.) as an interface layer is used for the ferromagnetic layer 27c. The initial amorphous layer is used by stacking CoPt, CoPd, Co / Pt stacked films, Co / Pd stacked films, etc. In this case, the CoFeB-containing layer in the ferromagnetic layer 27c is formed on the nonmagnetic layer 27b side, and the nonmagnetic layer 27b side has a more (001) oriented MgO compared to the other layers.

[0108] A nonmagnetic layer 27d is disposed on the upper surface of the ferromagnetic layer 27c. The nonmagnetic layer 27d is a nonmagnetic conductive film. The nonmagnetic layer 27d serves as a spacer layer. For example, the nonmagnetic layer 27d is composed of elements selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr), or alloys thereof. For example, the film thickness of the nonmagnetic layer 27d is less than or equal to 2 nm.

[0109] A ferromagnetic layer 27e is disposed on the upper surface of the non-magnetic layer 27d. The ferromagnetic layer 27e is a conductive film with ferromagnetic properties. The ferromagnetic layer 27e serves as a shift cancelling layer. The ferromagnetic layer 27e has an axial direction that is readily magnetizable in a direction perpendicular to the film surface (Z direction). The ferromagnetic layer 27e may, for example, comprise at least one alloy layer selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). The ferromagnetic layer 27e may be a stacked film, such as a Co / Pt stacked film and a Co / Pd stacked film.

[0110] Ferromagnetic layers 27c and 27e are antiferromagnetically coupled by nonmagnetic layer 27d. That is, ferromagnetic layers 27c and 27e are coupled to have antiparallel magnetization directions. This coupling structure of ferromagnetic layer 27c, nonmagnetic layer 27d, and ferromagnetic layer 27e is called a synthetic antiferromagnetic (SAF) structure. Due to the SAF structure, ferromagnetic layer 27e cancels the effect of the leakage magnetic field of ferromagnetic layer 27c on the magnetization direction change of ferromagnetic layer 27a, and can reduce the leakage magnetic field of the substantial ferromagnetic layer 27c.

[0111] The magnetoresistive element (MTJ) can operate in a low-resistance or high-resistance state, depending on whether the magnetization directions of the storage layer and the reference layer are parallel or antiparallel. In this embodiment, the magnetization direction of the storage layer relative to the magnetization direction of the reference layer is controlled so that write current does not pass through the MTJ. Specifically, a write method using spin-track torque generated by passing current through the SOTL wiring is employed.

[0112] When a write current Ic0 of a certain magnitude passes through the SOTL wiring in the Y direction, the relative relationship between the magnetization directions of the storage layer and the reference layer becomes parallel. In this parallel state, the resistance of the magnetoresistive element MTJ is at its lowest, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "P (parallel) state" and is defined, for example, as the state of data "0".

[0113] Furthermore, when a write current Ic1 greater than the write current Ic0 passes through the SOTL wiring in the opposite direction to the write current Ic0, the relative relationship between the magnetization directions of the memory layer and the reference layer becomes antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ is at its highest, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (antiparallel) state" and is defined, for example, as the state of data "1".

[0114] The methods for defining data "1" and data "0" are not limited to the examples above. For example, the P state can be defined as data "1" and the AP state can be defined as data "0".

[0115] The shape of the magnetoresistive element (MTJ) seen in the Z-direction is elliptical or circular. From the viewpoint of high-density integration of the memory cell (MC), the shape of the magnetoresistive element (MTJ) seen in the Z-direction is preferably circular. From the viewpoint of reducing area and power consumption, the short side length when the magnetoresistive element (MTJ) is elliptical and the diameter when the magnetoresistive element (MTJ) is circular are preferably less than or equal to 100 nanometers. When performing a high-speed magnetization reversal of less than or equal to 5 nsec relative to the ferromagnetic layer 27a, the diameter of the magnetoresistive element (MTJ) is preferably less than or equal to 30 nanometers. When the diameter of the magnetoresistive element (MTJ) is less than or equal to 30 nm, the magnetization reversal mode approximately becomes a single-domain mode or a magnetization reversal mode that does not form a defined magnetic wall. Thus, high-speed magnetization reversal is achieved.

[0116] 1.2 Operation

[0117] Next, the operation of the magnetic storage device according to the first embodiment will be described.

[0118] 1.2.1 Relationship between various operations and magnetic layer temperature

[0119] Figure 8 This is a view illustrating an example of the relationship between various operations and the temperature of the magnetic layer in a magnetic storage device according to a first embodiment.

[0120] The magnetic storage device 1 is divided into states such as a write state, a read state, and a standby state. The write state is the state where data is being written to the memory cell array 10 (a write operation is being performed). The read state is the state where data is being read from the memory cell array 10 (a read operation is being performed). The standby state is the state where neither a write operation nor a read operation is being performed.

[0121] In standby or read mode, the temperature T of the magnetic layer 24b is designed to be below the threshold temperature TA. Conversely, in write mode, the temperature T of the magnetic layer 24b is designed to exceed the threshold temperature TA. Therefore, the magnetic properties of the magnetic layer 24b can be changed depending on whether a write operation is in progress. Specifically, when no write operation is being performed, the magnetic layer 24b exhibits antiferromagnetic properties. Conversely, when a write operation is being performed, the magnetic layer 24b exhibits ferromagnetic properties.

[0122] 1.2.2 Write Operation

[0123] Figure 9 This is a circuit diagram illustrating an example of a write operation in a magnetic storage device according to a first embodiment. Figure 9 The example shows data being written to multiple memory primitives MC.<m,n> Case (0) <m<M,0<n<N)。

[0124] When data is written to the memory primitive MC<m,n> At that time, voltage VDD or VSS is applied to word line WL <m>and write bit line WBL <n>Each of them. When voltage VDD is applied to word line WL <m>At that time, voltage VSS is applied to the write bit line WBL. <n>When voltage VSS is applied to word line WL <m>At that time, voltage VDD is applied to the write bit line WBL. <n>Voltage VDD / 2 is applied to word line WL. <m>All other word lines WL and write bit lines WBL <n>All write bit lines WBL and all read bit lines RBL except for the write bit line WBL.

[0125] Voltage VSS is the reference voltage. For example, voltage VSS is 0V. Voltage VDD (representing the voltage difference between voltage VDD and voltage VSS) is the voltage that turns on switching elements SEL1 and SEL2. Furthermore, the voltage difference VDD is the voltage that allows current to flow, changing the resistance state of the magnetoresistive element MTJ. The voltage difference VDD / 2 is the voltage that turns off switching elements SEL1 and SEL2.

[0126] As a result, in the word line WL <m>and write bit line WBL <n>A voltage difference VDD is generated between them. This occurs on the word line WL. <m>and write bit line WBL <n>Any write operation other than the word line WBL will generate a voltage difference of VDD / 2 between them. <m>A voltage difference of VDD / 2 is generated between the read bit line RBL and any read bit line RBL.

[0127] In addition, in the word line WL <m>Any word line WL and write bit line WBL other than <n>A voltage difference of VDD / 2 is generated between them. This occurs on the word line WL. <m>Any word line WL and write bit line WBL other than <n>No voltage difference is generated between any write bit lines WBL other than the word line WL. <m>No voltage difference is generated between any word line WL and any read bit line RBL other than the word line WL.

[0128] Write bit line WBL <n>and read bit line RBL <n>A voltage difference of VDD / 2 is generated between them. This occurs when writing to the bit line WBL. <n>No voltage difference is generated between any write bit line WBL and the corresponding read bit line RBL other than the write bit line WBL.

[0129] Therefore, switching element SEL1<m,n> The circuit is activated. Switching element SEL<m,n> All switching elements SEL1 except for SEL1 are turned off. Furthermore, all switching elements SEL2 are turned off.

[0130] Therefore, current can pass through the wiring SOTL<m,n> Without allowing current to flow through the wiring SOTL<m,n> All wiring SOTL and all magnetoresistive elements MTJ except for SOTL.

[0131] In the above write operation, the memory primitive MC<m,n> The state is also called the selected state. Memory primitives MC<0,n> to MCn<m-1,n> MC<m+1,n> To MC<M,n> MC<m,0> To MC<m,n-1> and MC<m,n+1> To MC<m,N> The state of a memory cell (MC) that is not in a selected or semi-selected state is also called a semi-selected state. The state of all memory cells (MCs) that are not in a selected or semi-selected state is also called a non-selected state.

[0132] Figure 10 and Figure 11 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a first embodiment. Figure 10 and Figure 11 The diagram schematically illustrates the current flowing through a selected memory cell MC and the magnetization direction of the magnetoresistive element MTJ. Figure 10 This corresponds to the write operation when writing the data "1". Figure 11 This corresponds to the write operation when writing data "0".

[0133] First, refer to Figure 10 Describe the operation of writing the data "1". Figure 10 The example shows the write current Ic1 flowing from word line WL (right side of the paper) to write bit line WBL (left side of the paper).

[0134] As described above, a VDD voltage difference is generated across the conductor layer 24 to turn on the switching element SEL1. By controlling the VDD voltage difference, a write current Ic1 flows through the conductor layer 24. When the write current Ic1 flows through the conductor layer 24, particularly in the non-magnetic layer 24c, a spin-orbit torque is generated that attempts to make the magnetization direction of the ferromagnetic layer 27a antiparallel to the magnetization direction of the ferromagnetic layer 27c. The spin-orbit torque acts on the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0135] Furthermore, due to the write current Ic1 flowing in the conductor layer 24, the temperature T of the magnetic layer 24b exceeds the threshold temperature TA. As a result, the magnetic layer 24b undergoes a phase transition from antiferromagnetic to ferromagnetic. Therefore, the magnetic layer 24b becomes magnetized, and a leakage magnetic field SF is also generated outside the magnetic layer 24b. The magnetization direction of the magnetic layer 24b does not depend on the direction of the write current Ic1 flow. Figure 10 In the example, the leakage magnetic field SF is applied to the ferromagnetic layer 27a in the +Y direction, which is antiparallel to the magnetization direction inside the magnetic layer 24b.

[0136] As a result, the magnetization direction of ferromagnetic layer 27a is reversed in a direction antiparallel to the magnetization direction of ferromagnetic layer 27c by the assistance of the leakage magnetic field SF and the spin-orbit torque. Through the above operations, the writing operation of data "1" is completed.

[0137] Next, we will refer to Figure 11 Describe the operation of writing the data "0". Figure 11 The example shows the write current Ic0 flowing from the write bit line WBL (left side of the paper) to the word line WL (right side of the paper).

[0138] As described above, a VDD voltage difference is generated across the conductor layer 24 to turn on the switching element SEL1. By controlling the VDD voltage difference, a write current Ic0 flows in the conductor layer 24. When the write current Ic0 flows in the conductor layer 24, especially in the non-magnetic layer 24c, a spin-orbit torque is generated that attempts to make the magnetization direction of the ferromagnetic layer 27a parallel to the magnetization direction of the ferromagnetic layer 27c. This spin-orbit torque acts on the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0139] Furthermore, due to the write current Ic0 flowing in the conductor layer 24, the temperature T of the magnetic layer 24b exceeds the threshold temperature TA. As a result, the magnetic layer 24b undergoes a phase transition from antiferromagnetic to ferromagnetic. Therefore, the magnetic layer 24b becomes magnetized, and a leakage magnetic field SF is also generated outside the magnetic layer 24b. The magnetization direction of the magnetic layer 24b does not depend on the direction of the write current Ic0 flow. Figure 11 In the example shown, similar to Figure 10 The leakage magnetic field SF is applied to the ferromagnetic layer 27a in the +Y direction, which is antiparallel to the magnetization direction inside the magnetic layer 24b.

[0140] As a result, the magnetization direction of ferromagnetic layer 27a is reversed in the direction parallel to the magnetization direction of ferromagnetic layer 27c by the assistance of the leakage magnetic field SF and the spin-orbit torque. Through the above operations, the writing operation of data "0" is completed.

[0141] 1.3 Effects related to the first embodiment

[0142] In a first embodiment, a write method utilizing spin-orbit torque is applied in an MRAM including a magnetoresistive element (MTJ) with vertical magnetization. In this case, a bias magnetic field is required to act on the magnetoresistive element (MTJ). The configuration used to generate the bias magnetic field can be a cause of complex device structures. According to the first embodiment, the load on the write operation can be reduced by generating a bias magnetic field while avoiding the complexity of the device structure. This effect according to the first embodiment will be described below.

[0143] The SOTL (Spin-Orbit Torque Transmission Line) consists of a first portion coupled to the word line WL, a second portion coupled to the write bit line WBL, and a third portion coupled to the read bit line RBL. A magnetoresistive element MTJ is coupled between the third portion of the SOTL and the read bit line RBL. A switching element SEL1 is coupled between the second portion of the SOTL and the write bit line WBL. A switching element SEL2 is coupled between the magnetoresistive element MTJ and the read bit line RBL. This allows for the configuration of a memory cell MC using a spin-orbit torque write method.

[0144] The SOTL wiring includes a magnetic layer 24b. The magnetic layer 24b has an alloy comprising iron (Fe) and rhodium (Rh). As a result, the magnetic layer 24b can have magnetic properties that exhibit antiferromagnetic characteristics below a threshold temperature TA and ferromagnetic characteristics above the threshold temperature TA.

[0145] The magnetic layer 24b also contains at least one element selected from iridium (Ir), ruthenium (Ru), palladium (Pd), osmium (Os), platinum (Pt), gold (Au), silver (Ag) and copper (Cu) as an additive, thereby adjusting the threshold temperature TA of the magnetic layer 24b to a desired temperature level.

[0146] Specifically, due to the heat generated by each of the currents Ic0 and Ic1 flowing through the magnetic layer 24b in the write state, the temperature T of the magnetic layer 24b is designed to exceed the threshold temperature TA. As a result, a leakage magnetic field SF can be generated as a bias magnetic field in the write state. Therefore, the magnetic layer 24b can assist in the reversal of the magnetization direction of the ferromagnetic layer 27a caused by the spin-orbit torque.

[0147] On the other hand, the temperature T of the magnetic layer 24b is designed to be below the threshold temperature TA in standby or read states. This prevents the generation of a leakage magnetic field SF, which acts as a bias magnetic field, in standby or read states. Therefore, the magnetic layer 24b prevents the application of unnecessary external magnetic fields to the magnetoresistive element MTJ. Thus, by avoiding the application of unnecessary bias magnetic fields, the degradation of the storage layer retention characteristics of the magnetoresistive element MTJ during standby can be prevented.

[0148] 2. Second Embodiment

[0149] Next, a second embodiment will be described. In the second embodiment, the mechanism for generating magnetization in the wiring SOTL differs from that in the first embodiment. The following description primarily describes the configurations and operations that differ from the first embodiment. Configurations and operations equivalent to those in the first embodiment have been appropriately omitted from the description.

[0150] 2.1 Configuration of magnetoresistive effect components and peripheral wiring

[0151] Figure 12 and Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element and the peripheral wiring according to the second embodiment. Figure 12 and Figure 13 Corresponding to the first embodiment Figure 5 and Figure 6 . Specifically, Figure 12 This corresponds to the case where the SOTL wiring is at a low temperature. Figure 13 This corresponds to the situation where the SOTL wiring is at a high temperature.

[0152] In the second embodiment, a conductor layer 24' is provided instead of conductor layer 24 for wiring SOTL. That is, conductor layer 24' includes a non-magnetic layer 24a, a magnetic layer 24b', and a non-magnetic layer 24c. The configuration of the non-magnetic layers 24a and 24c is the same as that in the first embodiment. The configuration of component layer 27 is the same as that in the first embodiment.

[0153] A magnetic layer 24b' is disposed between a non-magnetic layer 24a and a non-magnetic layer 24c. The magnetic layer 24b' is a conductive film comprising a ferromagnetic alloy. The magnetic layer 24b' contains at least one magnetic element (a 3d transition metal ferromagnetic element) selected from iron (Fe), cobalt (Co), and nickel (Ni). The magnetic layer 24b' contains at least one rare earth element selected from lanthanum (La), cesium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), yttrium (Yb), and lutetium (Lu). The magnetic layer 24b' can be a single-layer film of an alloy containing both magnetic elements and rare earth elements.

[0154] When the magnetic layer 24b' is a single-layer film, it has an amorphous structure. The magnetic layer 24b' can also be a stacked film in which layers containing magnetic elements and layers containing rare earth elements are stacked sequentially. When the magnetic layer 24b' is a stacked film, at least the layers containing rare earth elements in the magnetic layer 24b' have an amorphous structure. As described above, by having an amorphous structure, the magnetic layer 24b' is designed to have high resistance. From the viewpoint of preventing current shunting, the magnetic layer 24b' preferably has a thin film with high resistance. The film thickness of the magnetic layer 24b' is preferably greater than or equal to 2 nanometers and less than or equal to 10 nanometers.

[0155] The magnetic properties of magnetic layer 24b' vary around a threshold temperature TB. In other words, the threshold temperature TB is the compensation temperature of magnetic layer 24b'. Specifically, as... Figure 12 As shown, when the temperature T of the magnetic layer 24b' is below the threshold temperature TB (T < TB), the net saturation magnetization Ms of the magnetic layer 24b' becomes almost zero. Consequently, the magnetic layer 24b' does not generate a leakage magnetic field SF outside the magnetic layer 24b. Therefore, no leakage magnetic field SF is applied to the ferromagnetic layer 27a.

[0156] On the other hand, such as Figure 13 As shown, when the temperature T of the magnetic layer 24b' exceeds the threshold temperature TB (T > TB), the net saturation magnetization Ms of the magnetic layer 24b' is significantly greater than zero. Due to, for example, shape anisotropy, the magnetization direction of the magnetic layer 24b' is stable along the Y direction. The magnetization direction of the magnetic layer 24b' is reversed depending on the direction of the current flowing in the magnetic layer 24b'. That is, the magnetic layer 24b' has an axis that is easy to magnetize in the extension direction (Y direction) of the magnetic layer 24b'. A leakage magnetic field SF is generated outside the magnetic layer 24b'. Therefore, the leakage magnetic field SF is applied to the ferromagnetic layer 27a.

[0157] The direction of the leakage magnetic field SF applied to the ferromagnetic layer 27a is antiparallel to the magnetization direction of the magnetic layer 24b'. The spin-orbit torque generated in the nonmagnetic layer 24c acts on the ferromagnetic layer 27a. When a predetermined size of leakage magnetic field SF is applied and a predetermined size of spin-orbit torque is applied, the magnetization direction of the ferromagnetic layer 27a is configured to be reversed, as in the first embodiment.

[0158] The magnetic properties of the magnetic layer 24b' are achieved by adjusting the composition of the magnetic layer 24b'.

[0159] Figure 14 This is a view illustrating an example of the relationship between the composition of the magnetic layer and the saturation magnetization intensity according to the second embodiment. Figure 15 This is a view illustrating an example of the relationship between the composition of the magnetic layer and the coercivity according to the second embodiment. Figure 14 and Figure 15 In the case of magnetic layer 24b' containing magnetic element TM and rare earth element RE, the composition is determined by RE. x TM (100-x) When representing the composition ratio of rare earth elements, x is shown on the horizontal axis. Figure 14 In the figure, the change in net saturation magnetization Ms relative to the composition ratio x is represented by the line Le1. Figure 15 In the figure, the change in coercivity (Hc) relative to the composition ratio x is represented by lines Le2 and Le3.

[0160] As shown in line Le1, the net saturation magnetization Ms decreases as the rare earth element composition ratio x approaches x0. When the composition ratio x is x0, the net saturation magnetization Ms becomes zero.

[0161] As shown in lines Le2 and Le3, the coercivity Hc increases as the rare earth element composition ratio x approaches x0. When the composition ratio x is x0, the coercivity Hc diverges.

[0162] The composition of the magnetic layer 24b' with this composition ratio x0 is also called the compensation composition. The composition ratio x0 that makes the magnetic layer 24b' a compensation composition can be achieved, for example, in the range of greater than or equal to 20 at% and less than or equal to 30 at%. Conceptually, the compensation composition is better. However, from the point of view of controllability, the composition can be set such that the composition of the ferromagnetic element is slightly larger than the compensation composition.

[0163] 2.2 Relationship between various operations and the temperature of the magnetic layer

[0164] Figure 16 This is a view illustrating an example of the relationship between various operations and the temperature of the magnetic layer in a magnetic storage device according to a second embodiment. Figure 16 Corresponding to the first embodiment Figure 8 .

[0165] In standby or read mode, the temperature T of the magnetic layer 24b' is designed to be below the threshold temperature TB. Conversely, in write mode, the temperature T of the magnetic layer 24b' is designed to exceed the threshold temperature TB. As a result, the net saturation magnetization Ms of the magnetic layer 24b' can be adjusted depending on whether a write operation is being performed. Specifically, when no write operation is being performed, the net saturation magnetization Ms of the magnetic layer 24b' is almost zero. Conversely, when a write operation is being performed, the net saturation magnetization Ms of the magnetic layer 24b' is significantly greater than zero.

[0166] 2.3 Write Operation

[0167] Figure 17 and Figure 18 This is a cross-sectional view illustrating an example of a write operation in a magnetic storage device according to a second embodiment. Figure 17 and Figure 18 Corresponding to the first embodiment Figure 10 and Figure 11 . Specifically, Figure 17 This corresponds to the write operation when writing the data "1". Figure 18 This corresponds to the write operation when writing data "0".

[0168] First, refer to Figure 17 Describe the operation of writing the data "1". Figure 17 The example shows the write current Ic1 flowing from word line WL (right side of the paper) to write bit line WBL (left side of the paper).

[0169] As described above, a VDD voltage difference is generated across the conductor layer 24' to turn on the switching element SEL1. By controlling the VDD voltage difference, a write current Ic1 flows in the conductor layer 24'. When the write current Ic1 flows in the conductor layer 24', especially in the non-magnetic layer 24c, a spin-orbit torque is generated that attempts to make the magnetization direction of the ferromagnetic layer 27a antiparallel to the magnetization direction of the ferromagnetic layer 27c. This spin-orbit torque acts on the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0170] Furthermore, due to the write current Ic1 flowing in the conductor layer 24', the temperature T of the magnetic layer 24b' exceeds the threshold temperature TB. As a result, the net saturation magnetization Ms of the magnetic layer 24b' is significantly greater than zero. Therefore, a leakage magnetic field SF is generated outside the magnetic layer 24b'. The magnetization direction of the magnetic layer 24b' is independent of the direction of the write current Ic1 flow. Figure 17 In the example, the leakage magnetic field SF is applied to the ferromagnetic layer 27a in the +Y direction, which is antiparallel to the magnetization direction inside the magnetic layer 24b'.

[0171] As a result, the magnetization direction of ferromagnetic layer 27a is reversed in a direction antiparallel to the magnetization direction of ferromagnetic layer 27c by the assistance of the leakage magnetic field SF and the spin-orbit torque. Through the above operations, the writing operation of data "1" is completed.

[0172] Next, we will refer to Figure 18 Describe the operation of writing the data "0". Figure 18 The example shows the write current Ic0 flowing from the write bit line WBL (left side of the paper) to the word line WL (right side of the paper).

[0173] As described above, a VDD voltage difference is generated across the conductor layer 24 to turn on the switching element SEL1. By controlling the VDD voltage difference, a write current Ic0 flows in the conductor layer 24'. When the write current Ic0 flows in the conductor layer 24', especially in the non-magnetic layer 24c, a spin-orbit torque is generated that attempts to make the magnetization direction of the ferromagnetic layer 27a parallel to the magnetization direction of the ferromagnetic layer 27c. This spin-orbit torque acts on the ferromagnetic layer 27a near the non-magnetic layer 24c.

[0174] Furthermore, due to the write current Ic0 flowing in the conductor layer 24', the temperature T of the magnetic layer 24b' exceeds the threshold temperature TB. As a result, the net saturation magnetization Ms of the magnetic layer 24b' is significantly greater than zero. Therefore, the net saturation magnetization Ms of the magnetic layer 24b' generates a leakage magnetic field SF outside the magnetic layer 24b'. The magnetization direction of the magnetic layer 24b' is independent of the direction of the write current Ic0 flow. Figure 18 In the example shown, with Figure 17 Similarly, the leakage magnetic field SF is applied to the ferromagnetic layer 27a in the +Y direction, which is antiparallel to the magnetization direction inside the magnetic layer 24b'.

[0175] As a result, the magnetization direction of ferromagnetic layer 27a is reversed in the direction parallel to the magnetization direction of ferromagnetic layer 27c by the assistance of the leakage magnetic field SF and the spin-orbit torque. Through the above operations, the writing operation of data "0" is completed.

[0176] 2.4 Effects of the Second Embodiment

[0177] According to a second embodiment, the wiring SOTL includes a magnetic layer 24b'. The magnetic layer 24b' contains at least one magnetic element (a 3d transition metal ferromagnetic element) selected from iron (Fe), cobalt (Co), and nickel (Ni), and at least one rare earth element selected from lanthanum (La), cesium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), yttrium (Yb), and lutetium (Lu). As a result, the magnetic layer 24b' serves as a ferromagnetic material having a threshold temperature TB as a compensation temperature.

[0178] Here, the ferromagnetic material is a material composed of at least one rare earth element and at least one ferromagnetic element magnetically coupled such that their magnetization directions are opposite to each other. Specifically, when the net saturation magnetization Ms of the magnetic layer 24b' is below the threshold temperature TB, the saturation magnetization Ms can be set to a minimum value (almost zero) by controlling the composition. When the net saturation magnetization Ms of the magnetic layer 24b' exceeds the threshold temperature TB, the saturation magnetization Ms on the rare earth element side disappears due to temperature characteristics, and therefore a saturation magnetization Ms appears on the ferromagnetic element side. As a result, when the temperature exceeds the threshold temperature TB, the net saturation magnetization Ms of the magnetic layer 24b' has the characteristic of becoming significantly greater than the initial state. Magnetic materials with this characteristic are also called rare earth ferromagnetic materials. Rare earth ferromagnetic materials have a compensating composition in which the net saturation magnetization Ms becomes zero at room temperature, and the composition ratio of rare earth elements is greater than or equal to 20 at% and less than or equal to 30 at%. The composition of this rare earth ferromagnetic material is described as RE x TM 100-X (20≦X30 at%). Here, TM is a 3d ferromagnetic element, such as Co, Fe, and Ni. RE is a rare earth element. In practice, preferably, the composition of the rare earth ferromagnetic material in the initial state is selected such that the composition of TM is slightly larger than the compensation composition, and the net saturation magnetization Ms is slightly greater than or equal to zero.

[0179] The temperature T of the magnetic layer 24b' is designed to exceed the threshold temperature TB during the write state due to heat generation or current interference accompanying the current Ic0 or Ic1 flowing through the magnetic layer 24b'. As a result, a leakage magnetic field SF can be generated as a bias magnetic field during the write state. Therefore, the magnetic layer 24b' can assist in reversing the magnetization direction of the ferromagnetic layer 27a caused by the spin-orbit torque.

[0180] On the other hand, the temperature T of the magnetic layer 24b' is designed to be below the threshold temperature TB in standby or read states. This prevents the generation of a leakage magnetic field SF, which acts as a bias magnetic field, in standby or read states. Therefore, the magnetic layer 24b' prevents the application of unnecessary external magnetic fields to the magnetoresistive element MTJ. Thus, similar to the first embodiment, by avoiding the application of unnecessary bias magnetic fields, the degradation of the storage characteristics of the magnetoresistive element MTJ's storage layer during standby can be prevented.

[0181] 3. Variations

[0182] The first and second embodiments described above are not limited to the examples described above, and various variations can be applied.

[0183] In the first and second embodiments described above, the leakage magnetic field SF generated from magnetic layers 24b and 24b' has been described as being applied as a bias magnetic field to the ferromagnetic layer 27a. However, the bias magnetic field applied to the ferromagnetic layer 27a is not limited to the leakage magnetic field SF. For example, a bias magnetic field can be generated by utilizing the exchange coupling between magnetic layers 24b and 24b' and the ferromagnetic layer 27a. In this case, a bias magnetic field is generated at the interface between the ferromagnetic layer 27a and the non-magnetic layer 24c. Similar to the bias magnetic field utilizing the leakage magnetic field SF, the bias magnetic field utilizing the exchange coupling acts on the magnetoresistive element MTJ only when spontaneous magnetization occurs in magnetic layers 24b or 24b' due to the heat generated by the accompanying current. Therefore, when magnetic layer 24b does not heat up to the point where magnetic layer 24b exceeds the threshold temperature TA or magnetic layer 24b' exceeds the threshold temperature TB, as in the standby or readout state, it is possible to prevent the application of an unnecessary external magnetic field to the magnetoresistive element MTJ.

[0184] In the first and second embodiments described above, the case where the selector is applied as a two-terminal switching element to the switching element SEL2 is described, but it is not limited thereto. For example, a diode can be applied to the switching element SEL2.

[0185] In the first and second embodiments described above, the application of a two-terminal switching element to switching elements SEL1 and SEL2 was described, but the method is not limited thereto. For example, such as Figure 19 and Figure 20 As shown, a three-terminal switching element can be applied to switching elements SEL1 and SEL2. Specifically, for example, a transistor such as a gate-all-around transistor (SGT) can be applied to switching elements SEL1 and SEL2. In this case, the first portion of all wiring SOTL is connected to the source line SL. The source line SL is grounded, for example. Switching element SEL1<i,j> The gate is coupled to the word line WL1<i,j> Switching element SEL2<i,j> The gate is coupled to the word line WL2<i,j> Thus, when each switching element SEL1 and SEL2 is controlled by separate word lines WL1 and WL2, a memory primitive MC can be selected.

[0186] like Figure 19 As shown, when a three-terminal switching element is applied to switching elements SEL1 and SEL2, the switching elements SEL1 and SEL2 in the same memory cell MC can be coupled to the corresponding write bit line WBL and read bit line RBL, respectively. Figure 20 As shown, when a three-terminal switching element is applied to switching elements SEL1 and SEL2, the switching elements SEL2 and SEL1 in the same memory cell MC are coupled to the corresponding bit line BL.

[0187] In the first and second embodiments described above, the switching elements SEL1 and SEL2 are described as being either two-terminal or three-terminal, but are not limited to this. For example, as Figure 21 As shown, switching elements SEL1 and SEL2 can be three-terminal and two-terminal switching elements, respectively. In this case, the first part of all wiring SOTL is connected to the source line SL. The source line SL is grounded, for example. Switching element SEL1<i,j> The gate is coupled to the word line WL1<i,j> The switching elements SEL1 and SEL2 in the same memory cell MC are coupled to the corresponding write bit line WBL and read bit line RBL, respectively. As a result, a memory cell MC can be selected.

[0188] In the first and second embodiments described above, the case where two layered structures L1 and L2 are stacked on top of the semiconductor substrate 20 is illustrated, but the invention is not limited thereto. For example, three or more layered structures having the same structure may be stacked on the semiconductor substrate 20. Furthermore, for example, a single layered structure may be stacked on top of the semiconductor substrate 20.

[0189] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

[0190] Label Explanation

[0191] 1: Magnetic storage device

[0192] 10: Memory Primitive Array

[0193] 11: Row selection circuit

[0194] 12: Column Selection Circuit

[0195] 13: Decoding circuit

[0196] 14: Writing Circuit

[0197] 15: Reading circuit

[0198] 16: Voltage generation circuit

[0199] 17: Input / Output Circuit

[0200] 18: Control Circuit

[0201] 20: Semiconductor substrate

[0202] 21, 23, 24, 25, 26, 29: Conductor layer

[0203] 22, 27, 28: Component Layer

[0204] 24a, 24c, 24d, 27b, 27d: Non-magnetic layers

[0205] 24b: Magnetic layer

[0206] 27a, 27c, 27e: Ferromagnetic layers< / n> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / n> < / n> < / m>

Claims

1. A magnetic storage device, comprising: First conductor layer; Second conductor layer; Third conductor layer; as well as A three-terminal memory cell is coupled to the first conductor layer, the second conductor layer, and the third conductor layer, wherein... The memory primitive includes: A fourth conductor layer includes a first portion coupled to the first conductor layer, a second portion coupled to the second conductor layer, and a third portion coupled to the third conductor layer and located between the first and second portions. A magnetoresistive element coupled between the third conductor layer and the fourth conductor layer; The fourth conductor layer includes a magnetic layer exhibiting ferromagnetism and a first nonmagnetic layer disposed between the magnetic layer and the magnetoresistive element; and The magnetic layer has a temperature below a predetermined temperature and a first saturation magnetization during the standby or read state of the memory cell, and a temperature above the predetermined temperature and a second saturation magnetization greater than the first saturation magnetization during the write state of the memory cell.

2. The magnetic storage device according to claim 1, wherein The magnetic layer comprises at least one first element selected from lanthanum (La), cesium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), yttrium (Yb), and lutetium (Lu), and at least one second element selected from iron (Fe), cobalt (Co), and nickel (Ni).

3. The magnetic storage device according to claim 2, wherein... The magnetic layer comprises a first layer containing the first element and a second layer containing the second element.

4. The magnetic storage device according to claim 2, wherein The magnetic layer comprises an amorphous alloy containing the first element and the second element.

5. The magnetic storage device according to claim 1, wherein... The first non-magnetic layer contains at least one element selected from tantalum (Ta), tungsten (W), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).

6. The magnetic storage device according to claim 1, wherein... The thickness of the first non-magnetic layer is greater than or equal to 0.3 nanometers and less than or equal to 10 nanometers.

7. The magnetic storage device according to claim 1, wherein... The thickness of the magnetic layer is greater than or equal to 2 nanometers and less than or equal to 10 nanometers.

8. The magnetic storage device according to claim 1, wherein The fourth conductor layer further includes a second non-magnetic layer, which is disposed on the opposite side of the first non-magnetic layer relative to the magnetic layer.

9. The magnetic storage device according to claim 8, wherein The second nonmagnetic layer contains at least one element selected from tantalum (Ta), titanium (Ti), and tungsten (W).

10. The magnetic storage device according to claim 8, wherein The thickness of the second non-magnetic layer is greater than or equal to 0.5 nanometers and less than or equal to 5 nanometers.

11. The magnetic storage device according to claim 1, wherein During the write state of the memory cell, the magnetoresistive element has Based on the first resistance value of the first current flowing from the first portion to the second portion of the fourth conductor layer, and Based on a second resistance value that is different from the first resistance value, derived from a second current flowing from the second portion of the fourth conductor layer to the first portion.

12. The magnetic storage device according to claim 11, wherein The magnetoresistive effect element includes: First ferromagnetic layer, A second ferromagnetic layer is disposed on the opposite side of the fourth conductor layer relative to the first ferromagnetic layer, and A third non-magnetic layer is disposed between the first ferromagnetic layer and the second ferromagnetic layer, and The magnetization directions of the first ferromagnetic layer and the second ferromagnetic layer are along the stacking direction of the first ferromagnetic layer, the third nonmagnetic layer, and the second ferromagnetic layer.

13. The magnetic storage device according to claim 1, wherein The memory cell also includes A first switching element, coupled between the second conductor layer and the fourth conductor layer, and A second switching element is coupled between the first conductor layer and the third conductor layer.

14. The magnetic storage device according to claim 13, wherein The first switching element is a three-terminal switching element, and The second switching element is a two-terminal switching element.

Images