Method, apparatus and electronic device for detecting correctness of data transmission

Abstract

The application provides a data transmission correctness detection method and device and electronic equipment, wherein the method comprises the following steps: obtaining the operation sequence of a read operation and a write operation when the data transmission is performed on an axi bus; obtaining a read operation completion data packet and a write operation completion data packet of the axi bus when the read operation and the write operation are completed; and obtaining a detection result according to the operation sequence of the read operation and the write operation, the read operation completion data packet and the write operation completion data packet. In the technical solution, the occurrence sequence of the read operation and the write operation is obtained first, and then the read operation completion data packet when the read operation is completed and the write operation data packet when the write operation is completed are checked for data correctness when the occurrence sequence of the read operation and the write operation meets the requirements, and if the occurrence sequence of the read operation and the write operation does not meet the requirements, subsequent data correctness checking is not performed, so that the efficiency of data transmission correctness verification can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, and electronic device for detecting the correctness of data transmission. Background Technology

[0002] With the development of computer processing chip technology, chip processing speeds are getting faster and faster. The bus is the common communication trunk for transmitting information between various functional components of a computer. The bus bandwidth determines the chip's processing speed. As a high-speed on-chip bus, the AXI (Advanced Extensible Interface) bus has excellent performance and can well meet the needs of SoC (System on Chip) systems. Given the importance of the AXI bus to SoC systems, the correctness of data transmission is particularly important when internet devices designed with the AXI bus transmit data.

[0003] In existing technologies, Internet devices based on the AXI bus use a random verification method when transmitting data. This method requires verifying random data one by one during the data transmission correctness verification process, which results in low verification efficiency. Summary of the Invention

[0004] This application provides a method, apparatus, and electronic device for detecting the correctness of data transmission, which addresses the problem of low efficiency in existing data transmission correctness verification.

[0005] The first aspect of this application provides a method for detecting the correctness of data transmission, applied to an AXI bus device, the method comprising:

[0006] When data is transmitted on the AXI bus, the order of read and write operations is obtained. The order of operations includes write before read, read before write, and read and write occurring simultaneously.

[0007] When a read operation and a write operation are completed, the read operation completion data packet and the write operation completion data packet of the Axi bus are obtained. The read operation completion data packet includes at least the read address channel information and the read data channel information of the Axi bus, and the write operation completion data packet includes at least the write address channel information and the write data channel information of the Axi bus.

[0008] Based on the order of the read and write operations, the read operation completion data packet, and the write operation completion data packet, a detection result is obtained. The detection result indicates whether the read operation completion data and the write operation completion data are correct.

[0009] In one possible design of the first aspect, the order of the read and write operations includes:

[0010] When performing a read operation on the Axi bus, obtain the read address channel information of the Axi bus;

[0011] Based on the address in the read address channel information, the write address channel information of the AXI bus is searched to obtain the first search result;

[0012] Based on the first search result, determine the order of read and write operations.

[0013] In the above-described possible design of the first aspect, the step of searching for the write address channel information of the AXI bus based on the address in the read address channel information to obtain the first search result includes:

[0014] The write address channel information is parsed according to a preset data format to obtain the address in the write address channel information;

[0015] Using the address in the write address channel information as the index of the write operation association array, the parsed write address channel information is stored in the write operation association array;

[0016] Based on the address in the read address channel information and the index of the write operation association array, a first search result is obtained by searching the write operation association array.

[0017] In another possible design of the first aspect, the order of the read and write operations includes:

[0018] When performing a write operation on the Axi bus, obtain the write address channel information of the Axi bus;

[0019] Based on the address in the write address channel information, the read address channel information of the AXI bus is searched to obtain the second search result;

[0020] Based on the second search result, determine the order of read and write operations.

[0021] In the above possible design of the first aspect, the step of searching the read address channel information of the AXI bus based on the address in the write address channel information to obtain the second search result includes:

[0022] The read address channel information is parsed according to a preset data format to obtain the address in the read address channel information;

[0023] Using the address in the read address channel information as the index of the read operation association array, the parsed read address channel information is stored in the read operation association array;

[0024] Based on the address in the write address channel information and the index of the read operation association array, a second search result is obtained by searching the read operation association array.

[0025] In another possible design of the first aspect, after acquiring the read operation completion data packet and the write operation completion data packet of the AXI bus upon completion of the read and write operations, and before obtaining the detection result based on the operation order of the read and write operations, the read operation completion data packet, and the write operation completion data packet, the following steps are included:

[0026] The write operation completion data packet is parsed according to a preset data format, and the parsed write operation completion data packet is stored in the write completion associated array.

[0027] In the above-described possible design of the first aspect, obtaining the detection result based on the operation order of the read and write operations, the read operation completion data packet, and the write operation completion data packet includes:

[0028] The validity of the read operation is determined based on the order of the read and write operations.

[0029] When the read operation is valid, the read operation completion data packet is compared with the preset initialization data or the write operation completion data packet stored in the write completion association array to obtain the detection result.

[0030] In the above-described possible design of the first aspect, comparing the read operation completion data packet with the write operation completion data packet stored in the preset initialization data or the write operation completion association array to obtain the detection result includes:

[0031] Obtain the address of the read operation completion data packet, and search in the write completion association array for a corresponding write operation completion data packet based on the address. The address of the write operation completion data packet is the same as the address of the read operation completion data packet.

[0032] If a corresponding write operation completion data packet exists, the data in the write operation completion data packet is compared with the data in the read operation completion data packet to obtain the detection result;

[0033] If no corresponding write operation completion data packet exists, the data in the read operation completion data packet is compared with the preset initialization data to obtain the detection result.

[0034] A second aspect of this application provides a data transmission correctness detection device, comprising: a random read / write operation generator, a read / write operation driver, a read / write operation monitor, and a read / write operation correctness checker, wherein the read / write operation driver is connected to the read / write operation generator, the read / write operation monitor is connected to the read / write operation driver, and the read / write operation correctness checker is connected to the read / write operation monitor.

[0035] The random read / write operation generator is used to generate read operation packets when performing read operations and write operation packets when performing write operations.

[0036] The read / write operation driver is used to parse the read operation packet and write operation and drive them to the AXI bus;

[0037] The read / write operation monitor is used to acquire the parsed read and write operation packets and send them to the read / write operation correctness checker.

[0038] The read / write operation correctness checker is used to determine the operation order of the read and write operations, and obtain the detection result based on the operation order of the read and write operations and the parsed read and write operation packets. The detection result indicates whether the data completed by the read operation and the data completed by the write operation are correct.

[0039] A third aspect of this application provides an electronic device including at least one processor and a memory;

[0040] The memory stores computer-executed instructions;

[0041] The at least one processor executes the computer execution instructions stored in the memory, causing the at least one processor to perform the data transmission correctness detection method as described above.

[0042] A fourth aspect of this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the data transmission correctness detection method described above.

[0043] The data transmission correctness detection method, apparatus, and electronic device provided in this application, when performing data read and write operations via the AXI bus, first obtain the order of occurrence of read and write operations. If the order of occurrence of read and write operations meets the requirements, then the read operation completion data packet when the read operation is completed and the write operation data packet when the write operation is completed are checked for data correctness. If the order of occurrence of read and write operations does not meet the requirements, then no subsequent data correctness checks are performed. This effectively improves the efficiency of data transmission correctness verification. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the read operation data transmission structure of the AXI bus provided in an embodiment of this application;

[0045] Figure 2 This is a schematic diagram of the write operation data transmission structure of the AXI bus provided in an embodiment of this application;

[0046] Figure 3 A schematic flowchart of the data transmission correctness detection method provided in the embodiments of this application;

[0047] Figure 4 A flowchart illustrating the method for obtaining the operation sequence of read operations on the AXI bus according to an embodiment of this application;

[0048] Figure 5 A flowchart illustrating the method for obtaining the operation sequence of write operations on the AXI bus according to an embodiment of this application;

[0049] Figure 6 This is a schematic flowchart of a method for obtaining detection results provided in an embodiment of this application;

[0050] Figure 7 A schematic diagram of the structure of the data transmission correctness detection device provided in the embodiments of this application;

[0051] Figure 8 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0054] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise indicated. It should be understood that such terms can be used interchangeably where appropriate, for example, to implement the application in a sequence other than those given in the embodiments illustrated or described herein.

[0055] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0056] As used in this application, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0057] As computer processing speeds increase, the bandwidth requirements for buses also increase. When various functional components within a computer exchange and transmit data, the bus is used as the transmission channel. According to the types of information transmitted by the computer, the computer bus can be divided into a data bus, an address bus, and a control bus, which are used to transmit data, data addresses, and control signals, respectively. Various components within the computer are connected through the bus, and external devices can also be connected to the bus through corresponding interface circuits to form a hardware system. The AXI bus is a high-speed on-chip bus that achieves superior performance with a smaller area, lower power consumption, and lower latency, meeting the needs of existing high-performance computer systems. However, due to its high performance, the AXI bus handles large data transfer volumes and various data transmission scenarios, such as simultaneous read and write operations, read operations followed by write operations, and vice versa. For these scenarios, data integrity verification is necessary to prevent data mistransmission. Current technologies use random verification methods for data integrity verification. However, random verification does not generate simultaneous read and write operations during data transmission, making it impossible to determine the order of read and write operations or whether they are simultaneous. This random verification method increases the complexity of randomly generating stimuli, reduces verification noise, and is detrimental to verifying randomness, resulting in low data verification efficiency.

[0058] To address the aforementioned issues, this application provides a method, apparatus, and electronic device for detecting the correctness of data transmission. When data transmission occurs between components or between a component and a device via an AXI bus, the operation sequence of read and write operations on the AXI bus is obtained. After the data transmission is completed on the AXI bus, read operation completion data packets and write operation completion data packets are obtained. The sequence is first checked; if the sequence meets the requirements, the read operation is considered valid. Then, the read operation completion data packets and write operation completion data packets are checked for data correctness. If the sequence does not meet the requirements, the read operation is considered invalid. Subsequent checks on the read operation completion data packets and write operation completion data packets are no longer performed, saving time on data correctness checks and thus improving the efficiency of data correctness verification.

[0059] It is understood that the embodiments of this application are mainly used to detect the correctness of data transmission on the AXI bus. In practical applications, the data transmission correctness detection method, device, and electronic device can also be modified to other scenarios, and thus evolve into other data transmission correctness detection methods, devices, and electronic devices, which will not be described here.

[0060] Before introducing the data transmission correctness detection method of this application, the specific application scenarios to which this application is applicable will be described in detail.

[0061] The data transmission correctness detection method provided in this application can be applied to various devices that need to transmit data, such as between components inside a computer, between components inside a computer and external devices, etc.

[0062] Figure 1 This is a schematic diagram of the read operation data transmission structure of the AXI bus provided in the embodiments of this application, as shown below. Figure 1 As shown, the master device 11 and the slave device 13 communicate via the AXI bus to perform data reading operations. The reading operation process specifically includes a read address channel 12 (AR channel) and a read data channel 14 (R channel). The master device 11 first sends a signal to the slave device 13 through the read address channel 12. This signal includes address and control information. After receiving the information transmitted from the read address channel 12, the slave device 13 returns the data that the master device needs to read to the master device 11 through the read data channel 14. When the master device 11 receives the returned data, the entire reading operation process is completed.

[0063] Figure 2 This is a schematic diagram of the write operation data transmission structure of the AXI bus provided in the embodiments of this application, as shown below. Figure 2As shown, the write operation process specifically includes a master device 11, a write address channel 22 (WR channel), a slave device 13, a write data channel 24 (W channel), and a write response channel 25. The write operation process mainly involves the master device 11 sending a signal to the slave device 13 through the write address channel 22. This signal includes address and control information. Then, the master device 11 sends the data to be written to the slave device 13 through the write data channel 24. After receiving the data, the slave device 13 writes the data and replies with a write completion signal through the write response channel 25 to acknowledge the master device 11. The entire write operation process is then complete.

[0064] in, Figure 1 and Figure 2 The master device 11 and slave device 13 involved are virtual devices, such as virtual devices obtained through software simulation modeling, or they can be real physical devices.

[0065] The data transmission correctness detection method of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0066] Figure 3 This is a flowchart illustrating the data transmission correctness detection method provided in the embodiments of this application, as shown below. Figure 3 As shown, the method may include the following steps:

[0067] S301. When transmitting data on the AXI bus, obtain the order of read and write operations.

[0068] The operation sequence includes writing before reading, reading before writing, and reading and writing occurring simultaneously.

[0069] For example, in some implementations, a data transmission correctness detection device can be constructed through software simulation modeling, and this data transmission correctness detection device can serve as the execution subject of the embodiments of this application. Specifically, the data transmission correctness detection device may include a random read / write operation generator, a read / write operation driver, a read / write operation monitor, and a read / write operation correctness checker. The read / write operation driver is connected to the read / write operation generator, the read / write operation monitor is connected to the read / write operation driver, and the read / write operation correctness checker is connected to the read / write operation monitor.

[0070] The random read / write operation generator is used to generate read operation packets when performing read operations and write operation packets when performing write operations.

[0071] The read / write operation driver is used to parse read and write operation packets and drive them onto the AXI bus;

[0072] The read / write operation monitor is used to acquire the parsed read and write operation packets and send them to the read / write operation correctness checker.

[0073] The read / write operation correctness checker is used to determine the order of read and write operations, and obtain the detection result based on the order of read and write operations and the parsed read and write operation packets.

[0074] The detection results indicate whether the data completed during read operations and write operations are correct.

[0075] Among them, the random read / write operation generator, read / write operation driver, read / write operation monitor, and read / write operation correctness checker mentioned above can all be software simulation modules.

[0076] In this embodiment, during a read operation, data transmission is achieved through the read address channel and read data channel of the AXI bus. A read / write operation monitor connected to the read address channel and read data channel can be set up to collect signal information transmitted in these channels during a read operation. Similarly, the read / write operation monitor can also be connected to the write address channel, write data channel, and write response channel to collect signal information transmitted in these channels. It should be briefly noted that whether a read or write operation is in progress on the AXI bus can typically be determined by the high or low level of signals on the AXI bus.

[0077] Furthermore, the read / write operation monitor can be connected to the read / write operation correctness checker. During a read operation, the read / write operation monitor can simultaneously collect signal information transmitted in the read address channel, read data channel, write address channel, write data channel, and write response channel, and send it to the read / write operation correctness checker. The read / write operation correctness checker directly determines the order of read and write operations in the current data transmission process by analyzing the signal information transmitted in the read address channel and the write address channel.

[0078] It should be noted that, in the embodiments of this application, since the Axi bus has independent read address channel, read data channel, write address channel, write response channel and write data channel, when transmitting data, the Axi bus can perform read operation first, write operation first, or read operation and write operation simultaneously. The operation order of read operation and write operation of the Axi bus represents the relative order of read operation and write operation during data transmission.

[0079] For example, the order of read and write operations on the AXI bus can be any of the following: read before write, write before read, or read and write simultaneously.

[0080] Optionally, in this embodiment, when a write operation is performed, the read / write operation monitor can collect the signal information transmitted in the write address channel, write data channel, and write response channel. At the same time, the read / write operation monitor can also collect the signal information transmitted in the read address channel and read data channel at the current moment. The read / write operation correctness checker determines the operation order of the read and write operations at the current moment by using the signal information transmitted in the read address channel and the signal information transmitted in the write address channel.

[0081] S302. When the read operation and write operation are completed, obtain the read operation completion data packet and the write operation completion data packet of the AXI bus.

[0082] The read operation completion data packet includes at least the read address channel information and read data channel information of the AXI bus, and the write operation completion data packet includes at least the write address channel information and write data channel information of the AXI bus. Furthermore, the write operation completion data packet may also include write response channel information.

[0083] In this embodiment of the application, when the AXI bus data transmission ends, it indicates that both the read and write operations have been completed. The read / write operation monitor can collect the read address channel information and read data channel information of the AXI bus, as well as the write address channel information and write data channel information, and send them to the read / write operation correctness checker.

[0084] For example, the read address channel information includes various control information and data related to the AXI protocol read operation, the read data channel information includes the data read, the write address channel information includes various control information and data related to the AXI protocol write operation, the write data channel information includes the data written, and the write response channel information includes the corresponding information upon completion of the write operation.

[0085] S303. Based on the order of read and write operations, the data packet after the read operation is completed, and the data packet after the write operation is completed, the detection result is obtained.

[0086] The detection results indicate whether the data completed during read operations and write operations are correct.

[0087] In this embodiment of the application, during data transmission, if the read operation and the write operation of the data occur simultaneously, the read operation can be determined to be invalid (because data consistency cannot be guaranteed when reading and writing the data simultaneously), the transmitted data is directly discarded, no further data integrity checks are performed, and an invalid prompt can be directly output; if the read operation is completed before the write operation or the write operation is completed before the read operation, it indicates that the read operation is valid (i.e., there will be no data inconsistency), and subsequent data integrity checks will be performed. The data completed by the read operation and the data completed by the write operation will be subject to subsequent integrity checks to determine whether the data completed by the read operation and the data completed by the write operation are correct.

[0088] For example, when performing data correctness checks, the read / write operation correctness checker first obtains the address from the read address channel information in the read operation completion data packet and checks if there is a matching address in the write address channel information in the write operation completion data packet. If so, it compares the read data channel information in the read operation completion data packet with the write data channel information in the write operation completion data packet. When the comparison matches, it outputs the correct detection result. If not, it needs to determine whether the read operation data packet is the same as the preset initialization data. If they are the same, it also outputs the correct detection result. The preset initialization data can be user-preset data specifically used for data verification, which can be the initial data when performing the first read or write operation.

[0089] The data transmission correctness detection method provided in this application first detects the operation sequence to determine whether the read operation was completed before the write operation, thus determining whether the read operation is valid. Then, it further detects the completed data of the read and write operations to determine whether the data is correct. This method can improve the speed of data detection, quickly discover errors in the data transmission process, and improve the efficiency of data transmission correctness verification.

[0090] Figure 4 This is a flowchart illustrating the method for obtaining the operation sequence of read operations on the AXI bus according to an embodiment of this application. Figure 4 As shown, the method includes:

[0091] S401. When performing a read operation on the Axi bus, obtain the read address channel information of the Axi bus.

[0092] In this embodiment of the application, the read address channel information includes various control information and data during the read operation process. During data transmission, read and write operations can be performed. When a read operation is performed, the read / write operation monitor can collect the read address channel of the AXI bus to obtain the read address channel information.

[0093] For example, the read address channel information includes the address of the read operation.

[0094] S402. Based on the address in the read address channel information, search the write address channel information of the AXI bus to obtain the first search result.

[0095] In this embodiment, write address channel information refers to the information transmitted in the write address channel of the AXI bus. The write address channel information includes various control information and data during the write operation, such as the address of the write operation. Based on the address in the read address channel information, a search is performed on the address in the write address channel information. The first search result includes two possibilities: either the write address channel information contains the address from the read address channel information, or the write address channel information does not contain the address from the read address channel information.

[0096] It should be noted that the AXI bus can also perform write operations during read operations, transmitting write address channel information through the write address channel.

[0097] S403. Based on the first search result, determine the order of read and write operations.

[0098] In this embodiment of the application, when data transmission is performed, if the first search result is the first type of search result mentioned above, that is, an address containing the address in the read address channel information is found in the write address channel information, it means that while the read operation is in progress, a write operation with the same address is already in progress and has not yet been completed. That is, the operation order is that the read and write operations occur simultaneously. If no address containing the address in the read address channel information is found in the write address channel information, it means that while the read operation is in progress, no corresponding write operation has occurred or the write operation has been completed.

[0099] For example, the operation sequence also includes read operation first, write operation second, and read operation second, write operation first. Specifically, when the read address channel information contains the address, data, identifier, and transmission time of the read address channel information, and the write address channel information also contains the address, data, identifier, and transmission time of the write address channel information, the order of the read and write operations can be determined based on the order of their transmission times, provided that the read and write operations do not occur simultaneously.

[0100] If the first search result is another search result mentioned above, that is, the address containing the address in the read address channel information cannot be found in the write address channel information, it means that no corresponding write operation is performed when the read operation is performed, that is, the read operation and the write operation do not occur at the same time.

[0101] This application embodiment uses the address as an index to check whether the address in the write address channel information contains the address in the read address channel information. This allows it to determine whether a write operation with the same address is occurring simultaneously during a read operation on the AXI bus. If they are occurring simultaneously, it can be determined that the read-write relationship is out of order, eliminating the need for subsequent data transmission correctness checks and directly outputting a data invalidation message, thus effectively improving the efficiency of data transmission correctness detection.

[0102] Optionally, in one embodiment, the above-described data transmission correctness detection method may further include the following steps:

[0103] The write address channel information is parsed according to the preset data format to obtain the address in the write address channel information;

[0104] Using the address in the write address channel information as the index of the write operation associative array, the parsed write address channel information is stored in the write operation associative array;

[0105] Based on the address in the read address channel information and the index of the write operation associative array, the first search result is obtained by searching the write operation associative array.

[0106] In this embodiment of the application, the preset data format is shown in Table 1 below:

[0107] Addr Id Data Is_valid Sending_time

[0108] Table 1

[0109] In the table above, addr represents the address, id represents the ID number, data represents the data, is_valid takes a value of 1 or 0, when the value is 0 it means the operation is invalid, when the value is 1 it means the operation is valid, and Sending_time represents the sending time.

[0110] The write operation associative array stores write operation packets generated on the AXI bus. The write address channel information can be parsed according to a preset data format to extract the corresponding information (i.e., address, ID number, data, and transmission time). After assigning a value to Is_valid, the packets are integrated to form a write operation packet. The write operation packet can then be stored in the write operation associative array using the address within it as an index.

[0111] For example, taking a read operation on the AXI bus as an example, the read / write operation monitor collects the write address channel information, packages it, and sends it to the read / write operation correctness checker. The read / write operation correctness checker parses and packages the information into a correctness comparison packet aw_pkt (i.e., a write operation packet) according to the format in Table 1, sets the Is_valid value to 1, and then stores it in the write operation associative array using the address as an index. Afterwards, the address in the read address channel information can be used to check if there is a write operation packet with the same address in the write operation associative array. If so, it proves that when the read operation on the AXI bus occurs, a write operation with the same address has already occurred but has not yet been completed, meaning that read and write operations occur simultaneously. In this case, the Is_valid value in the write operation packet is set to 0 for identification.

[0112] This application embodiment parses and packages the write address channel information according to a preset format to form a write operation package, and stores it in the write operation association array with the address as the index. When determining the operation order of read and write operations, the address in the read address channel information can be used to search in the write operation association array to see if there are write operations with the same address occurring at the same time, which can conveniently and quickly determine the operation order of read and write operations.

[0113] Figure 5 This is a flowchart illustrating the method for obtaining the operation sequence of write operations on the AXI bus according to an embodiment of this application. Figure 5 As shown, the method includes:

[0114] S501. When performing a write operation on the Axi bus, obtain the write address channel information of the Axi bus.

[0115] In this embodiment, the write address channel information includes various control information and data during the write operation. For example, the write address channel information includes the address of the write operation. When the AXI bus performs a write operation, the read / write operation monitor can collect the write address channel of the AXI bus to obtain the write address channel information.

[0116] S502. Based on the address in the write address channel information, search the read address channel information of the AXI bus to obtain the second search result.

[0117] In this embodiment of the application, the second search result includes two types. The first type is that the address in the write address channel information is found in the read address channel information, and the second type is that the address in the write address channel information is not found in the read address channel information.

[0118] S503. Based on the second search result, determine the order of read and write operations.

[0119] In this embodiment of the application, during data transmission, if the second search result is the first one mentioned above, that is, an address containing the address in the write address channel information is found in the read address channel information, it indicates that while the write operation is in progress, a read operation with the same address is already occurring and has not yet been completed. In other words, the operation order is that read and write operations occur simultaneously. If the second search result is the other one mentioned above, that is, an address containing the address in the write address channel information is not found in the read address channel information, it indicates that while the write operation is in progress, no corresponding read operation has occurred or the read operation has already been completed.

[0120] This application embodiment uses the address as an index to check whether the address in the read address channel information contains the address in the write address channel information. This allows it to determine whether a read operation with the same address is occurring simultaneously while a write operation is in progress on the AXI bus. If they are occurring simultaneously, it can be determined that the read-write relationship is out of order, eliminating the need for subsequent data transmission correctness checks and directly outputting a data invalidation message, thus improving the efficiency of data transmission correctness checks.

[0121] Optionally, in one embodiment, the above-described data transmission correctness detection method may further include the following steps:

[0122] The address channel information is parsed according to the preset data format to obtain the address in the address channel information;

[0123] Using the address in the read address channel information as the index of the read operation associative array, the parsed read address channel information is stored in the read operation associative array;

[0124] Based on the address in the write address channel information and the index of the read operation associative array, the second search result is obtained by searching the read operation associative array.

[0125] In this embodiment, the preset data format can be found in Table 1 above. The read operation associative array stores the read operation packets generated on the AXI bus. The read address channel information is parsed using the data format in Table 1 to extract the address, ID number, data, and transmission time. Then, Is_valid is assigned a value, and finally, these are integrated to form the read operation packet. For example, if the read operation and write operation do not occur simultaneously, Is_valid can be assigned a value of 1; if a write operation occurs at the same address simultaneously with the read operation, Is_valid is assigned a value of 0. After obtaining the read operation packet, the address in the read operation packet is used as an index to store it in the read operation associative array.

[0126] For example, taking a write operation on the AXI bus as an example, the read / write operation monitor collects the read address channel information, packages it, and sends it to the read / write operation correctness checker. The read / write operation correctness checker parses it into a correctness comparison packet ar_pkt (i.e., a read operation packet) according to the format in Table 1, sets the Is_valid value in it to 1, and then stores it in the read operation associative array using the address as the index. Afterwards, the address in the correctness comparison packet ar_pkt can be used to check if there is a read operation packet with the same address in the read operation associative array. If so, it proves that when the write operation on the AXI bus occurs, a read operation with the same address has already occurred but has not yet been completed, meaning that read and write operations occur simultaneously. In this case, the Is_valid value in the read operation packet is set to 0 for identification.

[0127] This application embodiment parses and packages the read address channel information according to a preset format to form a read operation package, and stores it in the read operation association array with the address as the index. When determining the operation order of read and write operations, the information contained in the read operation package can be used to determine whether there are write operations at the same address occurring at the same time, and mark them, so as to conveniently and quickly determine the operation order of read and write operations.

[0128] In one embodiment, the above-mentioned data transmission correctness detection method may further include the following steps:

[0129] The write operation completion data packet is parsed according to the preset data format, and the parsed write operation completion data packet is stored in the write completion associated array.

[0130] In this embodiment, the write completion associative array stores the write operation completion data packets that have been completed on the AXI bus. The write operation completion data packets need to be parsed according to the data format in Table 1 above to obtain the address, ID number, data and sending time. Then, they are integrated to form a data correctness comparison packet w_pkt (i.e., the write operation completion data packet) and stored in the write completion associative array. For example, Is_valid can be left unassigned.

[0131] For example, before storing the write operation completion data packet into the write completion associative array, the address in the write operation completion data packet can be used as an index to check if a data packet with the same address has been previously stored in the write completion associative array. If so, the previously stored data packet needs to be deleted before storing the write operation completion data packet into the write completion associative array. The purpose of this step is mainly to update the write completion associative array. When a write operation is completed, it first checks if a write operation with the same address has already been completed. Now, if a new write operation needs to replace the old one, the data packet corresponding to the old write operation needs to be deleted before the new write operation completion data packet is stored.

[0132] In this embodiment, after the write operation completion data packet is stored in the write completion association array, the address in the write operation completion data packet can be used as an index to check if there is a data packet with the same address and ID number in the write operation association array. If so, it can be deleted.

[0133] This application embodiment uses a write-complete associative array to store write operation completion data packets. If subsequent read and write operations do not occur simultaneously and data correctness verification is required, the address of the read operation completion data packet can be used to search in the write-complete associative array for a write operation completion data packet with the same address to perform data correctness checks. That is, it is determined whether the data in the write operation completion data packet with the same address is consistent with the data in the read operation completion data packet, thereby quickly completing the data correctness check and improving data verification efficiency.

[0134] Figure 6 This is a schematic diagram of the method for obtaining detection results provided in the embodiments of this application, such as... Figure 6 As shown, the method includes the following steps:

[0135] S601. When transmitting data on the AXI bus, obtain the order of read and write operations.

[0136] S602. When the read operation and write operation are completed, obtain the read operation completion data packet and the write operation completion data packet of the AXI bus.

[0137] S603. Determine whether the read operation is valid based on the order of the read and write operations.

[0138] S604. When the read operation is valid, the read operation completion data packet is compared with the write operation completion data packet stored in the preset initialization data or the write completion association array to obtain the detection result.

[0139] In this embodiment, steps S601-S602 are similar to steps S301-S302 described above, and will not be repeated here. For example, the preset initialization data can be data pre-set before data transmission, specifically the initial data during the first read or write operation. The order of read and write operations includes at least the sequence of simultaneous read and write operations. When read and write occur simultaneously, the read operation is invalid; when read and write do not occur simultaneously, the read operation is valid.

[0140] In this embodiment, the validity of the read operation is first determined according to the order of the read and write operations. When the read operation is invalid, no subsequent data correctness check is performed, and an invalid read / write operation prompt is directly output. When the read operation is valid, the data correctness check is then performed.

[0141] This application embodiment obtains the order of read and write operations. When read and write operations do not occur simultaneously (i.e., when the read operation is valid), the read operation completion data packet is compared with preset initialization data or write operation completion data packet to obtain the detection result. If read and write operations occur simultaneously, no comparison is needed, and an invalid prompt is directly output, thus avoiding subsequent comparison operations, shortening the time spent on data verification, and improving the efficiency of data verification.

[0142] Furthermore, in some embodiments, the step S604 above, "comparing the read operation completion data packet with the write operation completion data packet stored in the preset initialization data or the write operation completion association array to obtain the detection result," can be specifically implemented through the following steps:

[0143] Get the address of the read operation completed data packet, and search in the write completed associated array for a corresponding write operation completed data packet based on the address;

[0144] If a corresponding write operation completion data packet exists, the data in the write operation completion data packet is compared with the data in the read operation completion data packet to obtain the detection result;

[0145] If no corresponding write operation completion data packet exists, the data in the read operation completion data packet is compared with the preset initialization data to obtain the detection result.

[0146] The address of the write operation completion data packet is the same as that of the read operation completion data packet.

[0147] For example, during data correctness checks, the read operation completion data packet includes the read address channel information and read data channel information of the AXI bus. The address in the read operation data packet is compared with the write operation completion data packets stored in the write completion associative array. If the write completion associative array stores a write operation completion data packet that matches the address in the read operation data packet, the data in the read operation completion data packet is then compared with the data in that write operation completion data packet. If they still match, the check result is that the data is correct and there is no problem with data transmission. If the write completion associative array does not store a write operation completion data packet that matches the address in the read operation data packet, the data in the read operation completion data packet is compared with the initialization data. If they match, the check result is still that the data is correct; if they do not match, it indicates that the read operation completion data is incorrect and there is a problem with data transmission.

[0148] This application embodiment checks whether a corresponding write operation completion data packet exists in the write completion association array. If found, it directly compares the data with that write operation completion data packet to obtain the detection result. If not found, it compares the data with preset initialization data to obtain the detection result. That is, multiple comparison and verification methods can be used to obtain a more accurate result.

[0149] Corresponding to the data transmission correctness detection method in the above embodiments, Figure 7 This is a schematic diagram of the data transmission correctness detection device provided in the embodiments of this application. For ease of explanation, only the parts related to the embodiments of this application are shown. Figure 7 As shown, the data transmission correctness detection device 70 includes a sequence acquisition module 701, a data acquisition module 702, and a detection module 703.

[0150] The sequence acquisition module 701 is used to acquire the operation sequence of read and write operations during data transmission on the AXI bus. The data acquisition module 702 is used to acquire the read operation completion data packet and the write operation completion data packet of the AXI bus when the read and write operations are completed. The detection module 703 is used to obtain the detection result based on the operation sequence of read and write operations, the read operation completion data packet, and the write operation completion data packet.

[0151] The read operation completion data packet includes at least the read address channel information and read data channel information of the AXI bus, and the write operation completion data packet includes at least the write address channel information and write data channel information of the AXI bus. Furthermore, the write operation completion data packet may also include write response channel information. The operation sequence includes write before read, read before write, and read and write occurring simultaneously. The detection result indicates whether the read operation completion data and the write operation completion data are correct.

[0152] Optionally, in one embodiment, the sequential acquisition module 701 is specifically used for:

[0153] When performing a read operation on the Axi bus, obtain the read address channel information of the Axi bus;

[0154] Based on the address in the read address channel information, the write address channel information of the AXI bus is searched to obtain the first search result;

[0155] Based on the first search result, determine the order of read and write operations.

[0156] Optionally, in one embodiment, the sequential acquisition module 701 further includes a read storage unit, which can be used for:

[0157] The write address channel information is parsed according to the preset data format to obtain the address in the write address channel information;

[0158] Using the address in the write address channel information as the index of the write operation associative array, the parsed write address channel information is stored in the write operation associative array;

[0159] Based on the address in the read address channel information and the index of the write operation associative array, the first search result is obtained by searching the write operation associative array.

[0160] Optionally, in one embodiment, the sequential acquisition module 701 is specifically used for:

[0161] When performing a write operation on the Axi bus, obtain the write address channel information of the Axi bus;

[0162] Based on the address in the write address channel information, the read address channel information of the AXI bus is searched to obtain the second search result;

[0163] Based on the second search result, determine the order of read and write operations.

[0164] Optionally, in one embodiment, the sequence acquisition module 701 further includes a write storage unit, which can be used for:

[0165] The address channel information is parsed according to the preset data format to obtain the address in the address channel information;

[0166] Using the address in the read address channel information as the index of the read operation associative array, the parsed read address channel information is stored in the read operation associative array;

[0167] Based on the address in the write address channel information and the index of the read operation associative array, the second search result is obtained by searching the read operation associative array.

[0168] Optionally, in one embodiment, the data transmission correctness detection device further includes a write-complete storage module, which is used to parse the write operation complete data packet according to a preset format and store the parsed write operation complete data packet into a write-complete association array.

[0169] Optionally, in one embodiment, the detection module 703 is specifically used for:

[0170] The validity of a read operation is determined based on the order of read and write operations.

[0171] When a read operation is valid, the read operation completion data packet is compared with the write operation completion data packet stored in the preset initialization data or the write operation completion association array to obtain the detection result.

[0172] Specific limitations regarding the data transmission correctness detection device can be found in the limitations of the data transmission correctness detection method described above, and will not be repeated here. Each module in the aforementioned data transmission correctness detection device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the display device, or stored in software in the memory of the display device, so that the processor can call and execute the corresponding operations of each module.

[0173] Optionally, in one embodiment, the detection module 703 may further be used for:

[0174] Get the address of the read operation completed data packet, and search in the write completed associated array for a corresponding write operation completed data packet based on the address;

[0175] If a corresponding write operation completion data packet exists, the data in the write operation completion data packet is compared with the data in the read operation completion data packet to obtain the detection result;

[0176] If no corresponding write operation completion data packet exists, the data in the read operation completion data packet is compared with the preset initialization data to obtain the detection result.

[0177] The address of the write operation completion data packet is the same as that of the read operation completion data packet.

[0178] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application, such as... Figure 8 As shown, the electronic device 80 includes at least one processor 801 and a memory 802; wherein

[0179] The 802 memory stores instructions executed by the computer;

[0180] At least one processor 801 executes computer execution instructions stored in memory 802, causing at least one processor 801 to perform the data transmission correctness detection method as described above.

[0181] Optionally, the memory 802 can be either standalone or integrated with the processor 801.

[0182] This application also provides a readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the various steps of the above-described data transmission correctness detection method.

[0183] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the preceding and following related objects; in formulas, the character " / " indicates a "division" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0184] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. In the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0185] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for detecting the correctness of data transmission, characterized in that, Applied to AXI bus devices, the method includes: When data is transmitted on the AXI bus, the order of read and write operations for the same address is obtained. The order of operations includes write before read, read before write, and read and write occurring simultaneously. When a read operation and a write operation are completed, the read operation completion data packet and the write operation completion data packet of the Axi bus are obtained. The read operation completion data packet includes at least the read address channel information and the read data channel information of the Axi bus, and the write operation completion data packet includes at least the write address channel information and the write data channel information of the Axi bus. Based on the order of the read and write operations, the read operation completion data packet, and the write operation completion data packet, a detection result is obtained. The detection result indicates whether the read operation completion data and the write operation completion data are correct.

2. The method according to claim 1, characterized in that, The order of operations for acquiring read and write operations includes: When performing a read operation on the Axi bus, obtain the read address channel information of the Axi bus; Based on the address in the read address channel information, the write address channel information of the AXI bus is searched to obtain the first search result; Based on the first search result, determine the order of read and write operations.

3. The data transmission correctness detection method according to claim 2, characterized in that, The step of searching for the write address channel information of the AXI bus based on the address in the read address channel information to obtain the first search result includes: The write address channel information is parsed according to a preset data format to obtain the address in the write address channel information; Using the address in the write address channel information as the index of the write operation association array, the parsed write address channel information is stored in the write operation association array; Based on the address in the read address channel information and the index of the write operation association array, a first search result is obtained by searching the write operation association array.

4. The method according to claim 1, characterized in that, The order of read and write operations is as follows: When performing a write operation on the Axi bus, obtain the write address channel information of the Axi bus; Based on the address in the write address channel information, the read address channel information of the AXI bus is searched to obtain the second search result; Based on the second search result, determine the order of read and write operations.

5. The method according to claim 4, characterized in that, The step of searching the read address channel information of the AXI bus based on the address in the write address channel information to obtain the second search result includes: The read address channel information is parsed according to a preset data format to obtain the address in the read address channel information; Using the address in the read address channel information as the index of the read operation association array, the parsed read address channel information is stored in the read operation association array; Based on the address in the write address channel information and the index of the read operation association array, a second search result is obtained by searching the read operation association array.

6. The method according to any one of claims 1-5, characterized in that, Upon completion of the read and write operations, after acquiring the read and write operation completion data packets from the AXI bus, and before obtaining the detection result based on the order of the read and write operations, the read and write operation completion data packets, and the write operation completion data packets, the following steps are included: The write operation completion data packet is parsed according to a preset data format, and the parsed write operation completion data packet is stored in the write completion associated array.

7. The method according to claim 6, characterized in that, The step of obtaining the detection result based on the order of the read and write operations, the read operation completion data packet, and the write operation completion data packet includes: The validity of the read operation is determined based on the order of the read and write operations. When the read operation is valid, the read operation completion data packet is compared with the preset initialization data or the write operation completion data packet stored in the write completion association array to obtain the detection result.

8. The method according to claim 7, characterized in that, The step of comparing the read operation completion data packet with the preset initialization data or the write operation completion data packet stored in the write completion association array to obtain the detection result includes: Obtain the address of the read operation completion data packet, and search in the write completion association array for a corresponding write operation completion data packet based on the address. The address of the write operation completion data packet is the same as the address of the read operation completion data packet. If it exists, the data in the write operation completion data packet is compared with the data in the read operation completion data packet to obtain the detection result; If it does not exist, the data in the read operation completed data packet is compared with the preset initialization data to obtain the detection result.

9. A data transmission correctness detection device, characterized in that, include: The system includes a random read / write operation generator, a read / write operation driver, a read / write operation monitor, and a read / write operation correctness checker. The read / write operation driver is connected to the read / write operation generator, the read / write operation monitor is connected to the read / write operation driver, and the read / write operation correctness checker is connected to the read / write operation monitor. The random read / write operation generator is used to generate read operation packets when performing read operations and write operation packets when performing write operations. The read / write operation driver is used to parse the read and write operation packets and drive them onto the AXI bus; The read / write operation monitor is used to acquire the parsed read and write operation packets and send them to the read / write operation correctness checker. The read / write operation correctness checker is used to determine the operation order of the read and write operations for the same address, and obtains the detection result based on the operation order of the read and write operations and the parsed read and write operation packets. The detection result indicates whether the read operation completion data and the write operation completion data are correct.

10. An electronic device, characterized in that, Includes at least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes the computer execution instructions stored in the memory, causing the at least one processor to perform the data transmission correctness detection method as described in any one of claims 1-8.

11. A readable storage medium, characterized in that, The readable storage medium stores computer-executable instructions, which, when executed by the processor, implement the data transmission correctness detection method as described in any one of claims 1-8.

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