Daisy chain SPI integrated circuit and method of operation thereof

Abstract

The present application provides a daisy chain serial peripheral interface (SPI) integrated circuit and an operating method thereof. The daisy chain SPI integrated circuit includes a first MISO interface circuit, a second MISO interface circuit, a first data enable interface circuit and a second data enable interface circuit. When the daisy chain SPI integrated circuit is a target slave circuit selected by a master circuit for reading target data, the first data enable interface circuit outputs a data enable signal to the master circuit, and the first MISO interface circuit returns the target data to the master circuit based on the timing of the data enable signal. When the daisy chain SPI integrated circuit is not the target slave circuit, a signal received by the second data enable interface circuit is transmitted to the first data enable interface circuit, and data received by the second MISO interface circuit is transmitted to the first MISO interface circuit. Embodiments of the present application enable the master circuit in the daisy chain SPI architecture to efficiently control multiple slave circuits.

Description

Technical Field

[0001] This invention relates to an integrated circuit, and more particularly to a daisy-chain sequence peripheral interface integrated circuit and its operation method. Background Technology

[0002] Some product applications may require multiple integrated circuits (ICs) to work collaboratively. For example, in large touch display IC (LTDI) applications, multiple (e.g., 30) driver ICs work together to drive the same large touch display panel. The Serial Peripheral Interface (SPI) architecture can provide a multi-drop driving architecture. In a multi-drop driving architecture, the master IC can connect to / drive multiple slave ICs through the same wire (channel). The larger the fan-out of the wire, the longer the signal transition time, resulting in poorer signal transmission efficiency. Furthermore, the master IC can only select one slave IC at a time in existing SPI protocols. Existing SPI protocols do not have broadcast functionality. How to efficiently control many slave ICs by the master IC is one of the many technical challenges in this field. Summary of the Invention

[0003] This invention provides a daisy-chain Serial Peripheral Interface (SPI) integrated circuit and its operation method, which enables the master integrated circuit in the daisy-chain SPI architecture to efficiently control multiple slave integrated circuits.

[0004] In one embodiment of the present invention, the daisy-chain SPI integrated circuit includes a first MISO (Master Input, Slave Output) interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, a second data enable interface circuit, a routing circuit, and a core circuit. The routing circuit is coupled to the input terminal of the first MISO interface circuit, the output terminal of the second MISO interface circuit, the input terminal of the first data enable interface circuit, and the output terminal of the second data enable interface circuit. The core circuit is coupled to the routing circuit. When the daisy-chain SPI integrated circuit is a slave IC in the daisy-chain SPI architecture and is the target slave circuit selected by the master IC in the daisy-chain SPI architecture to read target data, the core circuit outputs a data enable signal to the master IC through the routing circuit and the first data enable interface circuit, and the core circuit sends the target data back to the master IC through the routing circuit and the first MISO interface circuit based on the timing of the data enable signal. When the daisychain SPI integrated circuit is a slave integrated circuit of the daisychain SPI architecture and is not the target slave circuit, the routing circuit transmits the signal received by the second data enable interface circuit to the first data enable interface circuit, and the routing circuit transmits the data received by the second MISO interface circuit to the first MISO interface circuit.

[0005] In one embodiment of the present invention, the above-described operation method includes: defining a unique identifier for a daisy-chain SPI integrated circuit by at least one chip identification pin; when the unique identifier indicates that the daisy-chain SPI integrated circuit is a slave integrated circuit of the daisy-chain SPI architecture, determining by the core circuit of the daisy-chain SPI integrated circuit whether the daisy-chain SPI integrated circuit is the target slave circuit selected by the master integrated circuit of the daisy-chain SPI architecture; when the daisy-chain SPI integrated circuit is a slave integrated circuit of the daisy-chain SPI architecture and is the target slave circuit selected by the master integrated circuit for reading target data, the core circuit outputs a data enable signal to the master integrated circuit through the routing circuit and the first data enable interface circuit of the daisy-chain SPI integrated circuit, and the core circuit transmits the target data back to the master integrated circuit based on the timing of the data enable signal through the routing circuit and the first MISO interface circuit of the daisy-chain SPI integrated circuit; and when the daisy-chain SPI integrated circuit is a slave integrated circuit of the daisy-chain SPI architecture and is not the target slave circuit, the routing circuit transmits the signal received by the second data enable interface circuit of the daisy-chain SPI integrated circuit to the first data enable interface circuit, and the routing circuit transmits the data received by the second MISO interface circuit of the daisy-chain SPI integrated circuit to the first MISO interface circuit.

[0006] Based on the above, the daisy-chain SPI integrated circuits described in the embodiments of the present invention are suitable for daisy-chain SPI architectures. In a daisy-chain SPI architecture, that is, in a multi-chip cascaded architecture, multiple slave integrated circuits are interconnected to form a daisy chain, and the master integrated circuit is connected to the first slave integrated circuit in the daisy chain. The daisy-chain SPI integrated circuit can improve the multi-drop driving issue in multi-chip systems through the daisy-chain architecture. By adding a data enable (DE) signal through a custom SPI protocol, the master integrated circuit can know the timing of the data returned by any slave integrated circuit. Therefore, in a daisy-chain SPI architecture, the master integrated circuit can efficiently control multiple slave integrated circuits.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a daisy-chain serial peripheral interface (SPI) architecture according to an embodiment of the present invention.

[0009] Figure 2A and Figure 2B This is a circuit block diagram of a daisy-chain SPI integrated circuit according to an embodiment of the present invention.

[0010] Figure 3 This is a flowchart illustrating an operation method of a daisy-chain SPI integrated circuit according to an embodiment of the present invention.

[0011] Figure 4 This is a circuit block diagram of a daisy-chain SPI integrated circuit according to another embodiment of the present invention. Detailed Implementation

[0012] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0013] The existing standard Serial Peripheral Interface (SPI) protocol cannot meet the needs of applications with multiple integrated circuits connected in series. The existing standard SPI protocol stipulates that after the SPI master IC issues a read command, it must receive the data returned by the SPI slave IC within a fixed number of clock cycles, i.e., a fixed waiting time. In a structure where multiple integrated circuits are interconnected, if the number of connected integrated circuits is large, the slave IC that is farther from the master IC may not be able to send back data to the master IC within the waiting time specified by the existing standard SPI protocol, resulting in a standard SPI protocol violation. The following embodiments of the present invention will illustrate the solution. The custom SPI protocol proposed in the following embodiments adds a data enable (DE) signal. Based on the data enable signal, the master IC can know the timing of the data returned by any slave IC in the daisy-chain SPI architecture. After issuing a read command, the master IC does not need to idle and wait for the return data (at which time the master IC can perform other tasks) until the data enable signal indicates the arrival of the returned data (valid data).

[0014] Figure 1This is a schematic diagram of a daisy-chain SPI architecture 100 according to an embodiment of the present invention. The daisy-chain SPI architecture 100 includes multiple integrated circuits (ICs) connected in series, such as a master IC M1 and slave ICs S1, S2, S3, ..., Sn. The number n of slave ICs S1 to Sn can be determined according to the actual design. In the daisy-chain SPI architecture 100, slave ICs S1 to Sn are connected in series to form a daisy chain, and the master IC M1 is connected to the first slave IC S1 in the daisy chain. The master IC M1 and the slave ICs S1 to Sn are each given / defined with different unique identifiers. For example, the unique identifier of the master IC M1 is ID_M, the unique identifier of the slave IC S1 is ID_S1, the unique identifier of the slave IC S2 is ID_S2, the unique identifier of the slave IC S3 is ID_S3, and the unique identifier of the slave IC Sn is ID_Sn.

[0015] The master integrated circuit M1 can send commands (or data) MOSI, chip select signals CS, and clock signals SCL conforming to the SPI specification to the daisy chain. Any slave integrated circuit in the daisy chain can pass the commands (or data) MOSI, chip select signals CS, and clock signals SCL from the preceding integrated circuit to the following integrated circuit. Each slave integrated circuit S1 to Sn can decode the chip select signal CS to determine whether it is the target slave circuit selected by the master integrated circuit M1. For example, when the decoding result of the chip select signal CS by slave integrated circuit S3 matches the unique identifier ID_S3, slave integrated circuit S3 can determine that it is the target slave circuit selected by the master integrated circuit M1, and therefore slave integrated circuit S3 can execute (process) the commands (or data) MOSI of the master integrated circuit M1.

[0016] Furthermore, the main integrated circuit M1 and the slave integrated circuits S1 to Sn are also given / defined with one (or more) identical broadcast identification codes ID_CM. Each slave integrated circuit S1 to Sn can determine whether it is a broadcast target of the main integrated circuit M1 based on the relationship between the chip selection signal cs and the broadcast identification code ID_CM. For example, when the decoding result of the chip selection signal cs does not match the dedicated identification code ID_S3 of the slave integrated circuit S3, but matches the broadcast identification code ID_CM shared by the slave integrated circuits S1 to Sn, the slave integrated circuit S3 can determine that it is the target slave circuit (broadcast target) selected by the main integrated circuit M1, and therefore the slave integrated circuit S3 can execute (process) the command (or data) mosi of the main integrated circuit M1. Conversely, when the decoding result of the chip selection signal cs does not match the dedicated identification code ID_S3, nor does it match the broadcast identification code ID_CM, the slave integrated circuit S3 can determine that it is not the target slave circuit selected by the main integrated circuit M1, and therefore the slave integrated circuit S3 can ignore (not process) the command (or data) mosi of the main integrated circuit M1.

[0017] In a daisy-chain, any slave integrated circuit can transmit the data miso and data enable signal DE1 from the downstream integrated circuit to the upstream integrated circuit. Therefore, based on the execution (processing) result of the command (or data) mosi, each slave integrated circuit S1 to Sn can send the data miso and data enable signal DE1 back to the master integrated circuit M1. The data enable signal DE1 indicates the valid timing of the data miso. Based on the daisy-chain architecture, the time spent by the master integrated circuit M1 accessing different slave integrated circuits (the interval from issuing the command to receiving the returned data) varies. Based on the data enable signal DE1, the master integrated circuit M1 does not need to idle after issuing a command to wait for the returned data. After issuing the command, the master integrated circuit M1 can perform other tasks until the data enable signal DE1 indicates the arrival of the returned data (valid data).

[0018] In summary, in the daisy-chain SPI architecture 100, i.e., in a multi-chip cascaded architecture, multiple slave integrated circuits S1 to Sn are interconnected to form a daisy chain, and the master integrated circuit M1 is connected to the first slave integrated circuit S1 in the daisy chain. The daisy-chain SPI architecture 100 can improve the multi-drop driving issue in multi-chip systems. By adding a data enable signal DE1 through a custom SPI protocol, the master integrated circuit M1 can know the timing of the data returned by any of the slave integrated circuits S1 to Sn. Therefore, in the daisy-chain SPI architecture 100, the master integrated circuit M1 can efficiently control multiple slave integrated circuits S1 to Sn.

[0019] Figure 2A and Figure 2B This is a circuit block diagram of a daisy-chain SPI integrated circuit 200 according to an embodiment of the present invention. Figure 2A An example application scenario of the DaisyChain SPI integrated circuit 200 is illustrated. Figure 2A The daisy-chain SPI integrated circuit 200 shown can be referenced. Figure 1 The relevant descriptions of any one of the integrated circuits S1 to Sn are shown below. Figure 2B This illustrates another application scenario example of the DaisyChain SPI integrated circuit 200. Figure 2B The daisy-chain SPI integrated circuit 200 shown can be referenced. Figure 1 The relevant descriptions of the main integrated circuit M1 shown can be deduced by analogy.

[0020] Figure 2A The daisy-chain SPI integrated circuit 200 shown can be used as Figure 1 This is one of many embodiments of any of the integrated circuits S1 to Sn. The daisy-chain SPI integrated circuit 200 is coupled between the front-end integrated circuit 21 and the back-end integrated circuit 22. Assuming... Figure 2A The daisy-chain SPI integrated circuit 200 shown is Figure 1 As shown from integrated circuit S1, then Figure 2A The front-end integrated circuit 21 and the back-end integrated circuit 22 shown can be Figure 1 The master integrated circuit M1 and slave integrated circuit S2 are shown, and Figure 2A The unique identifier ID_200 shown can be Figure 1 The unique identifier shown is ID_S1. Assume... Figure 2A The daisy-chain SPI integrated circuit 200 shown is Figure 1 As shown from integrated circuit S2, then Figure 2A The front-end integrated circuit 21 and the back-end integrated circuit 22 shown can be Figure 1 The diagram shows integrated circuit S1 and integrated circuit S3, while... Figure 2A The unique identifier ID_200 shown can be Figure 1 The unique identification code shown is ID_S2.

[0021] Figure 2B The daisy-chain SPI integrated circuit 200 shown can be used as Figure 1 This is one of many embodiments of the main integrated circuit M1 shown. A daisy-chain SPI integrated circuit 200 is coupled to a subsequent integrated circuit 22. Assume... Figure 2B The daisy-chain SPI integrated circuit 200 shown is Figure 1 The main integrated circuit M1 shown is then Figure 2B The downstream integrated circuit 22 shown can be Figure 1 As shown, from integrated circuit S1, while Figure 2B The unique identifier ID_200 shown can be Figure 1 The unique identification code ID_M is shown.

[0022] Figure 2A and Figure 2B The daisy-chain SPI integrated circuit 200 shown includes data enable (DE) interface circuits DE21 and DE22, MOSI (Master Output, Slave Input) interface circuits MOSI21 and MOSI22, MISO (Master Input, Slave Output) interface circuits MISO21 and MISO22, chip select interface circuits CS21 and CS22, clock interface circuits SCL21 and SCL22, routing circuit 210, and core circuit 220. Each of these interface circuits may include a pin (or pad, or connector pad). Based on practical design, in some embodiments, each of these interface circuits may include a buffer circuit, a gain circuit, an electrostatic discharge (ESD) protection circuit, and / or other circuitry. Routing circuit 210 is coupled to the input of MISO interface circuit MISO21, the output of MISO interface circuit MISO22, the input of DE interface circuit DE21, and the output of DE interface circuit DE22. Core circuit 220 is coupled to routing circuit 210.

[0023] Figure 3 This is a flowchart illustrating an operation method of a daisy-chain SPI integrated circuit according to an embodiment of the present invention. Please refer to... Figure 2A (or Figure 2B )as well as Figure 3In step S310, at least one chip identification pin ID21 can define a unique identifier ID_200 for the daisy-chain SPI integrated circuit 200. Step S320 can determine whether the daisy-chain SPI integrated circuit 200 is a master integrated circuit or a slave integrated circuit. In some practical design examples, the core circuit 220 can check the unique identifier ID_200 of the chip identification pin ID21 to determine whether the daisy-chain SPI integrated circuit 200 is a master integrated circuit or a slave integrated circuit. For example, the identifier "0000 0000" can be defined as the "unique identifier of the master integrated circuit", the identifier "1111 1111" can be defined as the "broadcast identifier" (an identifier shared by multiple slave integrated circuits), and other identifiers "0000 0001" to "11111110" can be defined as "unique identifiers of different slave integrated circuits". Therefore, the core circuit 220 can check whether the unique identification code ID_200 of the chip identification pin ID21 is the identification code "0000 0000" or other identification codes "0000 0001" to "1111 1110" to determine whether the role of the daisy chain SPI integrated circuit 200 is the master integrated circuit or the slave integrated circuit in the daisy chain SPI architecture 100.

[0024] When the unique identification code ID_200 indicates that the daisy chain SPI integrated circuit 200 is a slave integrated circuit in the daisy chain SPI architecture 100 (the judgment result of step S320 is "slave integrated circuit"), the core circuit 220 of the daisy chain SPI integrated circuit 200 can perform step S330 to determine whether the daisy chain SPI integrated circuit 200 is the target slave circuit selected by the master integrated circuit M1 in the daisy chain SPI architecture 100. Figure 3 Steps S330, S340, and S350 shown can be referred to Figure 2A The application scenario is shown.

[0025] Please refer to Figure 2A and Figure 3 When the daisy-chain SPI integrated circuit 200 is a target slave circuit selected by the master integrated circuit M1 in the daisy-chain SPI architecture 100 to read target data (the judgment result of step S330 is "yes"), the core circuit 220 can perform step S340 to output a data enable signal Sde21 through the routing circuit 210 and the DE interface circuit DE21 as... Figure 1The data enable signal DE1 is sent to the main integrated circuit M1. Based on the timing of the data enable signal Sde21, the core circuit 220 can transmit the target data Smiso21 back to the main integrated circuit M1 through the routing circuit 210 and the MISO interface circuit MISO21 (step S340). When the daisy-chain SPI integrated circuit 200 is not the target slave circuit (the judgment result of step S330 is "No"), the core circuit 220 can perform step S350 to control the routing circuit 210 to transmit the signal Sde22 received by the DE interface circuit DE22 (second DE interface circuit) to the DE interface circuit DE21 (first DE interface circuit). In step S350, the routing circuit 210 can also transmit the data Smiso22 received by the MISO interface circuit MISO22 (second MISO interface circuit) to the MISO interface circuit MISO21 (first MISO interface circuit).

[0026] Please refer to Figure 2A Routing circuit 210 is also coupled to the output of clock interface circuit SCL21 and the input of clock interface circuit SCL22. When daisy-chain SPI integrated circuit 200 is one of the integrated circuits S1 to Sn in daisy-chain SPI architecture 100, routing circuit 210 can transmit the clock signal Ssc22 received by clock interface circuit SCL21 to clock interface circuit SCL22 and core circuit 220. Routing circuit 210 is also coupled to the output of chip select interface circuit CS21 and the input of chip select interface circuit CS22. When daisy-chain SPI integrated circuit 200 is one of the integrated circuits S1 to Sn in daisy-chain SPI architecture 100, routing circuit 210 can transmit the chip select signal Ssc22 received by chip select interface circuit CS21 to chip select interface circuit CS22 and core circuit 220. Routing circuit 210 is also coupled to the output of MOSI interface circuit MOSI21 and the input of MOSI interface circuit MOSI22. When the daisy-chain SPI integrated circuit 200 is one of the integrated circuits S1 to Sn in the daisy-chain SPI architecture 100, the routing circuit 210 can transmit the main circuit data Smosi22 received by the MOSI interface circuit MOSI21 to the MOSI interface circuit MOSI22 and the core circuit 220.

[0027] In the daisy-chain SPI architecture 100, the master integrated circuit M1 can issue a chip select signal cs (chip select signal SCS22) to designate the daisy-chain SPI integrated circuit 200 as the target slave circuit, and issue a command mosi (master circuit data Smosi22) to the target slave circuit to read target data. The core circuit 220 can decode the chip select signal SCS22 to determine whether the daisy-chain SPI integrated circuit 200 is the target slave circuit selected by the master integrated circuit M1. When the decoding result of the chip select signal SCS22 by the core circuit 220 matches the unique identifier ID_200 of the daisy-chain SPI integrated circuit 200, the core circuit 220 can determine that the daisy-chain SPI integrated circuit 200 is the target slave circuit selected by the master integrated circuit M1. When the decoding result does not match the unique identifier ID_200 of the daisy-chain SPI integrated circuit 200 but matches the broadcast identifier ID_CM shared by the slave integrated circuits S1 to Sn, the core circuit 220 can determine that the daisy-chain SPI integrated circuit 200 is the target slave circuit selected by the master integrated circuit M1.

[0028] If the core circuit 220 can determine that the daisy-chain SPI integrated circuit 200 is the target slave circuit selected by the master integrated circuit M1, the core circuit 220 can execute (process) the master circuit data Smiso22 (e.g., commands or data) issued by the master integrated circuit M1. Assume that the master circuit data Smiso22 contains a data read command. Based on the data read command issued by the master integrated circuit M1, the core circuit 220 can send the target data Smiso21 and the data enable signal Sde21 back to the master integrated circuit M1 through the routing circuit 210, the MISO interface circuit MISO21, and the DE interface circuit DE21. The data enable signal Sde21 can indicate the valid timing of the target data Smiso21.

[0029] When the decoding result does not match the daisy-chain SPI integrated circuit 200's unique identifier ID_200 or the broadcast identifier ID_CM, the core circuit 220 can determine that the daisy-chain SPI integrated circuit 200 is not the target slave circuit selected by the master integrated circuit M1. Therefore, the core circuit 220 can ignore (not process) the master circuit data Smiso22 (e.g., commands or data) sent by the master integrated circuit M1. In this case, the routing circuit 210 can, based on the control of the core circuit 220, transmit the data Smiso22 received by the MISO interface circuit MISO22 to the MISO interface circuit MISO21, and transmit the signal Sde22 received by the DE interface circuit DE22 to the DE interface circuit DE21.

[0030] Please refer to Figure 2B and Figure 3When the unique identification code ID_200 indicates that the daisychain SPI integrated circuit 200 is the main integrated circuit M1 in the daisychain SPI architecture 100 (the judgment result of step S320 is "main integrated circuit"), the core circuit 220 of the daisychain SPI integrated circuit 200 can perform steps S360 and S370. Figure 3 Steps S360 and S370 shown can be referred to Figure 2B The application scenario is shown. Figure 2B In the scenario shown, that is, when the daisy-chain SPI integrated circuit 200 is the master integrated circuit M1 in the daisy-chain SPI architecture 100, the core circuit 220 can output the clock signal Ssc21 to the slave integrated circuits S1 to Sn in the daisy-chain SPI architecture 100 through the routing circuit 210 and the clock interface circuit SCL22.

[0031] In step S360, the core circuit 220 can output a chip selection signal Scs21 (chip selection signal cs) to the slave integrated circuits S1 to Sn in the daisy-chain SPI architecture 100 via the routing circuit 210 and the chip selection interface circuit CS22 to specify / select the target slave circuit. Furthermore, the core circuit 220 can output master circuit data Smosi21 (command mosi) to the target slave circuit via the routing circuit 210 and the MOSI interface circuit MOSI22 to read the target data. In response to the command (master circuit data Smosi21) from the core circuit 220, the target slave circuit will send back a signal Sde22 (data enable signal) and data Smiso22 (target data) to the daisy-chain SPI integrated circuit 200.

[0032] In step S370, the core circuit 220 can receive the signal Sde22 (data enable signal) and data Smiso22 (target data) from the target slave circuit through the routing circuit 210, the DE interface circuit DE22, and the MISO interface circuit MISO22. The target slave circuit corresponds to the chip select signal Scs21. By adding the signal Sde22 (data enable signal) through a custom SPI protocol, the core circuit 220 can know the timing of the data returned by any of the slave integrated circuits S1 to Sn. Based on the signal Sde22 (data enable signal), the core circuit 220 does not need to idle to wait for the data Smiso22 (target data) after issuing a command. After issuing the command, the core circuit 220 can perform other tasks until the signal Sde22 (data enable signal) indicates the arrival of valid data Smiso22 (target data). Therefore, the core circuit 220 can efficiently control multiple slave integrated circuits S1 to Sn.

[0033] Figure 4 This is a circuit block diagram of a daisy-chain SPI integrated circuit 400 according to another embodiment of the present invention. Figure 4 The daisy-chain SPI integrated circuit 400 shown includes DE interface circuits DE21, DE interface circuit DE22, MOSI interface circuits MOSI21, MOSI22, MOSI23, MOSI24, MISO interface circuits MISO21, MISO22, MISO23, MISO24, chip select interface circuits CS21 and CS22, clock interface circuits SCL21 and SCL22, routing circuit 210, and core circuit 220. Figure 4 The daisy-chain SPI integrated circuit 400, DE interface circuits DE21 and DE22, MOSI interface circuits MOSI21 and MOSI22, MISO interface circuits MISO21 and MISO22, chip selection interface circuits CS21 and CS22, clock interface circuits SCL21 and SCL22, routing circuit 210, and core circuit 220 shown can be referenced. Figure 2A and Figure 2B The descriptions of the daisy-chain SPI integrated circuit 200, DE interface circuits DE21 and DE22, MOSI interface circuits MOSI21 and MOSI22, MISO interface circuits MISO21 and MISO22, chip selection interface circuits CS21 and CS22, clock interface circuits SCL21 and SCL22, routing circuit 210, and core circuit 220 shown are analogous and will not be repeated here. Based on actual design, in some embodiments, Figure 2A and Figure 2B The implementation details of the routing circuit 210 and the core circuit 220 shown can be found in [reference]. Figure 4 The descriptions of the routing circuit 210 and the core circuit 220 shown can be extrapolated.

[0034] exist Figure 4In the illustrated embodiment, the core circuit 220 includes a master-mode core circuit 221 and a slave-mode core circuit 222. The master-mode core circuit 221 and the slave-mode core circuit 222 are coupled to the routing circuit 210. Based on the unique identification code of the chip identification pin ID 21, when the daisy-chain SPI integrated circuit 400 acts as the master integrated circuit M1, the master-mode core circuit 221 can be enabled, while the slave-mode core circuit 222 can be disabled. When the daisy-chain SPI integrated circuit 400 acts as one of the slave integrated circuits S1 to Sn, the master-mode core circuit 221 can be disabled, while the slave-mode core circuit 222 can be enabled.

[0035] exist Figure 4 In the illustrated embodiment, the routing circuit 210 includes a latching circuit L1, a multiplexer Mux1, a latching circuit L3, and a multiplexer Mux3. The input of the latching circuit L1 is coupled to the output of the DE interface circuit DE22. The first input of the multiplexer Mux1 is coupled to the slave mode core circuit 222 of the core circuit 220. The second input of the multiplexer Mux1 is coupled to the output of the latching circuit L1. The output of the multiplexer Mux1 is coupled to the input of the DE interface circuit DE21. When the daisy-chain SPI integrated circuit 400 is one of the slave integrated circuits S1 to Sn, when the daisy-chain SPI integrated circuit 400 is the target slave circuit selected by the master integrated circuit M1, the output of the multiplexer Mux1 is selectively coupled to the first input of the multiplexer Mux1, that is, the slave mode core circuit 222 is selectively coupled to the input of the DE interface circuit DE21. When the daisy-chain SPI integrated circuit 400 is not the target slave circuit, the output of the multiplexer Mux1 is selectively coupled to the second input of the multiplexer Mux1, that is, the output of the latch circuit L1 is selectively coupled to the input of the DE interface circuit DE21.

[0036] The input of latch circuit L3 is coupled to the output of MISO interface circuit MISO22. The first input of multiplexer Mux3 is coupled to slave mode core circuit 222 of core circuit 220. The second input of multiplexer Mux3 is coupled to the output of latch circuit L3. The output of multiplexer Mux3 is coupled to the input of MISO interface circuit MISO21. When daisy-chain SPI integrated circuit 400 is one of the slave integrated circuits S1 to Sn, when daisy-chain SPI integrated circuit 400 is the target slave circuit selected by master integrated circuit M1, the output of multiplexer Mux3 is selectively coupled to the first input of multiplexer Mux3, that is, slave mode core circuit 222 is selectively coupled to the input of MISO interface circuit MISO21. When the daisy-chain SPI integrated circuit 400 is not the target slave circuit, the output of the multiplexer Mux3 is selectively coupled to the second input of the multiplexer Mux3, that is, the output of the latch circuit L3 is selectively coupled to the input of the MISO interface circuit MISO21.

[0037] exist Figure 4 In the illustrated embodiment, the routing circuit 210 further includes a latching circuit L5 and a multiplexer Mux5. The input of the latching circuit L5 is coupled to the output of the MISO interface circuit MISO23. The first input of the multiplexer Mux5 is coupled to the master mode core circuit 221 of the core circuit 220. The second input of the multiplexer Mux5 is coupled to the output of the latching circuit L5. The output of the multiplexer Mux5 is coupled to the input of the MISO interface circuit MISO24. When the daisy-chain SPI integrated circuit 400 is the master integrated circuit M1, the output of the multiplexer Mux5 is selectively coupled to the first input of the multiplexer Mux5, that is, the master mode core circuit 221 is selectively coupled to the input of the MISO interface circuit MISO24. When the daisy-chain SPI integrated circuit 400 is not the master integrated circuit M1, the output of the multiplexer Mux5 is selectively coupled to the second input of the multiplexer Mux5, that is, the output of the latching circuit L5 is selectively coupled to the input of the MISO interface circuit MISO24.

[0038] exist Figure 4In the illustrated embodiment, the routing circuit 210 further includes a latching circuit L4 and a multiplexer Mux4. The input of the latching circuit L4 is coupled to the output of the MOSI interface circuit MOSI21. The first input of the multiplexer Mux4 is coupled to the master mode core circuit 221 of the core circuit 220. The second input of the multiplexer Mux4 is coupled to the output of the latching circuit L4. The output of the multiplexer Mux4 is coupled to the input of the MOSI interface circuit MOSI22. When the daisy-chain SPI integrated circuit 400 is the master integrated circuit M1 in the daisy-chain SPI architecture 100, the output of the multiplexer Mux4 is selectively coupled to the first input of the multiplexer Mux4, that is, the master mode core circuit 221 is selectively coupled to the input of the MOSI interface circuit MOSI22. When the daisy-chain SPI integrated circuit 400 is not the main integrated circuit M1, the output of the multiplexer Mux4 is selectively coupled to the second input of the multiplexer Mux4, that is, the output of the latch circuit L4 is selectively coupled to the input of the MOSI interface circuit MOSI22.

[0039] exist Figure 4 In the illustrated embodiment, the routing circuit 210 further includes a latching circuit L2 and a multiplexer Mux2. The input of the latching circuit L2 is coupled to the output of the MOSI interface circuit MOSI24. The first input of the multiplexer Mux2 is coupled to the slave-mode core circuit 222 of the core circuit 220. The second input of the multiplexer Mux2 is coupled to the output of the latching circuit L2. The output of the multiplexer Mux2 is coupled to the input of the MOSI interface circuit MOSI23. When the daisy-chain SPI integrated circuit 400 is one of the slave integrated circuits S1 to Sn, and the daisy-chain SPI integrated circuit 400 is the target slave circuit selected by the master integrated circuit M1, the output of the multiplexer Mux2 is selectively coupled to the first input of the multiplexer Mux2, that is, the slave-mode core circuit 222 is selectively coupled to the input of the MOSI interface circuit MOSI23. When the daisy-chain SPI integrated circuit 400 is not the target slave circuit, the output of the multiplexer Mux2 is selectively coupled to the second input of the multiplexer Mux2, that is, the output of the latch circuit L2 is selectively coupled to the input of the MOSI interface circuit MOSI23.

[0040] exist Figure 4In the illustrated embodiment, the routing circuit 210 further includes a latching circuit L6 and a multiplexer Mux6. The input of the latching circuit L6 is coupled to the output of the chip selection interface circuit CS21. The first input of the multiplexer Mux6 is coupled to the master mode core circuit 221 of the core circuit 220. The second input of the multiplexer Mux6 is coupled to the output of the latching circuit L6. The output of the multiplexer Mux6 is coupled to the input of the chip selection interface circuit CS22. When the daisy-chain SPI integrated circuit 400 is the master integrated circuit M1, the output of the multiplexer Mux6 is selectively coupled to the first input of the multiplexer Mux6, that is, the master mode core circuit 221 is selectively coupled to the input of the chip selection interface circuit CS22. When the daisy-chain SPI integrated circuit 400 is not the master integrated circuit M1, the output of the multiplexer Mux6 is selectively coupled to the second input of the multiplexer Mux6, that is, the output of the latching circuit L6 is selectively coupled to the input of the chip selection interface circuit CS22.

[0041] exist Figure 4 In the illustrated embodiment, the routing circuit 210 further includes a multiplexer Mux7. The first input of the multiplexer Mux7 is coupled to the master mode core circuit 221 of the core circuit 220. The second input of the multiplexer Mux7 is coupled to the output of the clock interface circuit SCL21. The output of the multiplexer Mux7 is coupled to the input of the clock interface circuit SCL22. When the daisy-chain SPI integrated circuit 400 is the master integrated circuit M1, the output of the multiplexer Mux7 is selectively coupled to its input, meaning the master mode core circuit 221 is selectively coupled to the input of the clock interface circuit SCL22. When the daisy-chain SPI integrated circuit 400 is not the master integrated circuit M1, the output of the multiplexer Mux7 is selectively coupled to its second input, meaning the output of the clock interface circuit SCL21 is selectively coupled to the input of the clock interface circuit SCL22.

[0042] When the daisy-chain SPI integrated circuit 400 is the master integrated circuit M1 of the daisy-chain SPI architecture 100, the master mode core circuit 221 can output the chip selection signal Scs21 to the slave integrated circuits S1 to Sn of the daisy-chain SPI architecture 100 through the multiplexer Mux6 of the routing circuit 210 and the chip selection interface circuit CS22. The master mode core circuit 221 can also read the target data of the target slave circuit corresponding to the chip selection signal Scs21 through the routing circuit 210 and the MISO interface circuit MISO22. When the daisy-chain SPI integrated circuit 400 is one of the slave integrated circuits S1 to Sn of the daisy-chain SPI architecture 100, and the daisy-chain SPI integrated circuit 400 is the target slave circuit selected by the master integrated circuit M1, the slave mode core circuit 222 can output a data enable signal Sde21 to the master integrated circuit M1 of the daisy-chain SPI architecture 100 through the multiplexer Mux1 of the routing circuit 210 and the DE interface circuit DE21. The slave mode core circuit 222 can also transmit the target data Smiso21 back to the master integrated circuit M1 through the routing circuit and the first MISO interface circuit based on the timing of the data enable signal Sde21.

[0043] The daisy-chain SPI integrated circuit 400 described in this embodiment is suitable for... Figure 1 The diagram shows a daisy-chain SPI architecture 100. In the daisy-chain SPI architecture 100, that is, in a multi-chip cascaded architecture, multiple slave integrated circuits S1 to Sn are interconnected to form a daisy chain, and the master integrated circuit M1 is connected to the first slave integrated circuit S1 in the daisy chain. Based on the actual design, the daisy-chain SPI integrated circuit 400 can be used as either the master integrated circuit M1 or one of the slave integrated circuits S1 to Sn. The daisy-chain SPI integrated circuit 400 can improve the multi-drop driving issue in multi-chip systems through the daisy-chain architecture. In addition, slave integrated circuits S1 to Sn can be additionally given / defined one (or more) identical broadcast identifiers ID_CM. The master integrated circuit M1 can use the broadcast identifier ID_CM to broadcast common data to slave integrated circuits S1 to Sn. Through broadcast operation, the transmission performance from the master integrated circuit M1 to the slave integrated circuits S1 to Sn can be effectively improved. Furthermore, slave integrated circuits S1 to Sn can transmit data enable signals to the master integrated circuit M1. By adding a data enable signal path through a custom SPI protocol, the DaisyChain SPI IC 400 can effectively solve the problem of different data return times from different ICs.

[0044] Depending on different design requirements, the aforementioned core circuit 220, master-mode core circuit 221, and / or slave-mode core circuit 222 can be implemented in hardware, firmware, software (i.e., programs), or a combination of these three methods. In hardware form, the aforementioned core circuit 220, master-mode core circuit 221, and / or slave-mode core circuit 222 can be implemented as logic circuits on an integrated circuit. The related functions of the aforementioned core circuit 220, master-mode core circuit 221, and / or slave-mode core circuit 222 can be implemented as hardware using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages. For example, the functions of the aforementioned core circuit 220, master mode core circuit 221, and / or slave mode core circuit 222 can be implemented in various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or other processing units.

[0045] In software and / or firmware form, the functions of the core circuit 220, the master-mode core circuit 221, and / or the slave-mode core circuit 222 can be implemented as programming codes. For example, the core circuit 220, the master-mode core circuit 221, and / or the slave-mode core circuit 222 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory computer-readable medium. In some embodiments, the non-transitory computer-readable medium includes, for example, read-only memory (ROM), semiconductor memory, programmable logic circuits, and / or storage devices. The storage device includes a hard disk drive (HDD), a solid-state drive (SSD), or other storage devices. A central processing unit (CPU), controller, microcontroller, or microprocessor can read and execute the programming code from the non-transitory computer-readable medium to realize the relevant functions of the core circuit 220, the master-mode core circuit 221, and / or the slave-mode core circuit 222.

[0046] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A daisy-chain sequence peripheral interface integrated circuit (200, 400), characterized in that, The daisy-chain sequence peripheral interface integrated circuit (200, 400) includes: First MISO interface circuit (MISO21); Second MISO interface circuit (MISO22); First data enable interface circuit (DE21); Second data enable interface circuit (DE22); The routing circuit (210) is coupled to the input of the first MISO interface circuit (MISO21), the output of the second MISO interface circuit (MISO22), the input of the first data enable interface circuit (DE21), and the output of the second data enable interface circuit (DE22); and The core circuit (220) is coupled to the routing circuit (210), wherein, When the daisy-chain peripheral interface integrated circuit (200, 400) is a slave integrated circuit of the daisy-chain peripheral interface architecture (100) and is the target slave circuit selected by the master integrated circuit (M1) of the daisy-chain peripheral interface architecture (100) to read target data, the core circuit (220) outputs a data enable signal to the master integrated circuit (M1) through the routing circuit (210) and the first data enable interface circuit (DE21), and the core circuit (220) transmits the target data back to the master integrated circuit (M1) through the routing circuit (210) and the first MISO interface circuit (MISO21) based on the timing of the data enable signal; and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy chain sequence peripheral interface architecture (100) and not the target slave circuit, the routing circuit (210) transmits the signal received by the second data enable interface circuit (DE22) to the first data enable interface circuit (DE21), and the routing circuit (210) transmits the data received by the second MISO interface circuit (MISO22) to the first MISO interface circuit (MISO21).

2. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 1, characterized in that, The routing circuit (210) includes: The first latch circuit (L1) has an input terminal coupled to the output terminal of the second data enable interface circuit (DE22); A first multiplexer (Mux1) has a first input terminal coupled to the core circuit (220), wherein a second input terminal of the first multiplexer (Mux1) is coupled to the output terminal of the first latch circuit (L1), and the output terminal of the first multiplexer (Mux1) is coupled to the input terminal of the first data enable interface circuit (DE21). When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the target slave circuit, the output terminal of the first multiplexer (Mux1) is selectively coupled to the first input terminal of the first multiplexer (Mux1), and when the daisy chain sequence peripheral interface integrated circuit (200, 400) is not the target slave circuit, the output terminal of the first multiplexer (Mux1) is selectively coupled to the second input terminal of the first multiplexer (Mux1). The second latching circuit (L3) has an input terminal coupled to the output terminal of the second MISO interface circuit (MISO22); and The second multiplexer (Mux3) has a first input coupled to the core circuit (220), wherein the second input of the second multiplexer is coupled to the output of the second latch circuit (L3), and the output of the second multiplexer (Mux3) is coupled to the input of the first MISO interface circuit (MISO21). When the daisy chain peripheral interface integrated circuit (200, 400) is the target slave circuit, the output of the second multiplexer (Mux3) is selectively coupled to the first input of the second multiplexer (Mux3), and when the daisy chain peripheral interface integrated circuit (200, 400) is not the target slave circuit, the output of the second multiplexer (Mux3) is selectively coupled to the second input of the second multiplexer (Mux3).

3. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 2, characterized in that, The daisy-chain peripheral interface integrated circuit (400) further includes a third MISO interface circuit (MISO23) and a fourth MISO interface circuit (MISO24), and the routing circuit (210) further includes: The third latching circuit (L5) has an input terminal coupled to the output terminal of the third MISO interface circuit (MISO23); and The third multiplexer (Mux5) has a first input coupled to the core circuit (220), wherein the second input of the third multiplexer (Mux5) is coupled to the output of the third latch circuit (L5), and the output of the third multiplexer (Mux5) is coupled to the input of the fourth MISO interface circuit (MISO24). When the daisy chain peripheral interface integrated circuit (400) is the main integrated circuit (M1), the output of the third multiplexer (Mux5) is selectively coupled to the first input of the third multiplexer (Mux5), and when the daisy chain peripheral interface integrated circuit (400) is not the main integrated circuit (M1), the output of the third multiplexer (Mux5) is selectively coupled to the second input of the third multiplexer (Mux5).

4. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 1, characterized in that, The daisy-chain sequence peripheral interface integrated circuit (200, 400) also includes: First MOSI interface circuit (MOSI21): and The second MOSI interface circuit (MOSI22), wherein the routing circuit (210) is also coupled to the output of the first MOSI interface circuit and the input of the second MOSI interface circuit (MOSI22). When the daisy-chain peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain peripheral interface architecture (100), the routing circuit (210) transmits the master circuit data received by the first MOSI interface circuit (MOSI21) to the second MOSI interface circuit (MOSI22) and the core circuit (220); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1) of the daisy chain sequence peripheral interface architecture (100), the core circuit (220) outputs the main circuit data to multiple slave integrated circuits of the daisy chain sequence peripheral interface architecture (100) through the routing circuit (210) and the second MOSI interface circuit (MOSI22).

5. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 4, characterized in that, The routing circuit (210) includes: The first latching circuit (L1) has an input terminal coupled to the output terminal of the first MOSI interface circuit (MOSI21); and A first multiplexer (Mux1) has a first input terminal coupled to the core circuit (220), wherein a second input terminal of the first multiplexer (Mux1) is coupled to the output terminal of the first latch circuit (L1), and the output terminal of the first multiplexer (Mux1) is coupled to the input terminal of the second MOSI interface circuit (MOSI22). When the daisy-chain peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1), the output terminal of the first multiplexer (Mux1) is selectively coupled to the first input terminal of the first multiplexer (Mux1), and when the daisy-chain peripheral interface integrated circuit (200, 400) is not the main integrated circuit (M1), the output terminal of the first multiplexer (Mux1) is selectively coupled to the second input terminal of the first multiplexer (Mux1).

6. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 5, characterized in that, The daisy-chain peripheral interface integrated circuit (400) further includes a third MOSI interface circuit (MOSI23) and a fourth MOSI interface circuit (MOSI24), and the routing circuit (210) further includes: The second latching circuit (L3) has an input terminal coupled to the output terminal of the fourth MOSI interface circuit (MOSI24); and The second multiplexer (Mux3) has a first input terminal coupled to the core circuit (220), wherein the second input terminal of the second multiplexer (Mux3) is coupled to the output terminal of the second latch circuit (L3), and the output terminal of the second multiplexer (Mux3) is coupled to the input terminal of the third MOSI interface circuit (MOSI23). When the daisy-chain peripheral interface integrated circuit (400) is the target slave circuit, the output terminal of the second multiplexer (Mux3) is selectively coupled to the first input terminal of the second multiplexer (Mux3); and when the daisy-chain peripheral interface integrated circuit (400) is not the target slave circuit, the output terminal of the second multiplexer (Mux3) is selectively coupled to the second input terminal of the second multiplexer (Mux3).

7. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 1, characterized in that, The daisy-chain sequence peripheral interface integrated circuit (200, 400) also includes: First chip selection interface circuit (CS21): and The second chip selection interface circuit (CS22), wherein the routing circuit (210) is also coupled to the output of the first chip selection interface circuit (CS21) and the input of the second chip selection interface circuit (CS22). When the daisy-chain peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain peripheral interface architecture (100), the routing circuit (210) transmits the chip selection signal received by the first chip selection interface circuit (CS21) to the second chip selection interface circuit (CS22) and the core circuit (220), and the core circuit (220) decodes the chip selection signal to determine whether the daisy-chain peripheral interface integrated circuit (200, 400) is the target slave circuit selected by the master integrated circuit (M1); and When the daisy-chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1) of the daisy-chain sequence peripheral interface architecture (100), the core circuit (220) outputs the chip selection signal to multiple slave integrated circuits of the daisy-chain sequence peripheral interface architecture (100) through the routing circuit (210) and the second chip selection interface circuit (CS22), and the core circuit (220) reads the target data of the target slave circuit corresponding to the chip selection signal through the routing circuit (210) and the second MISO interface circuit (MISO22).

8. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 7, characterized in that, When the decoding result of the core circuit (220) of the chip selection signal matches the unique identification code of the daisy chain sequence peripheral interface integrated circuit (200, 400), the core circuit (220) determines that the daisy chain sequence peripheral interface integrated circuit (200, 400) is the target slave circuit selected by the master integrated circuit (M1); When the decoding result does not match the unique identification code of the daisy chain sequence peripheral interface integrated circuit (200, 400), but matches the broadcast identification code shared by the multiple slave integrated circuits of the daisy chain sequence peripheral interface architecture (100), the core circuit (220) determines that the daisy chain sequence peripheral interface integrated circuit (200, 400) is the target slave circuit selected by the master integrated circuit (M1); as well as When the decoding result does not match the unique identification code of the daisy chain sequence peripheral interface integrated circuit (200, 400) or the broadcast identification code, the core circuit (220) determines that the daisy chain sequence peripheral interface integrated circuit (200, 400) is not the target slave circuit selected by the master integrated circuit (M1).

9. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 7, characterized in that, The routing circuit (210) includes: A latching circuit (L6) has an input terminal coupled to the output terminal of the first chip select interface circuit (CS21); and A multiplexer (Mux6) has a first input terminal coupled to the core circuit (220), wherein a second input terminal of the multiplexer (Mux6) is coupled to the output terminal of the latch circuit (L6), and the output terminal of the multiplexer (Mux6) is coupled to the input terminal of the second chip selection interface circuit (CS22). When the daisy-chain peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1), the output terminal of the multiplexer (Mux6) is selectively coupled to the first input terminal of the multiplexer (Mux6), and when the daisy-chain peripheral interface integrated circuit (200, 400) is not the main integrated circuit (M1), the output terminal of the multiplexer (Mux6) is selectively coupled to the second input terminal of the multiplexer (Mux6).

10. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 7, characterized in that, The core circuit (220) includes: The master mode core circuit (221) is coupled to the routing circuit (210). When the daisy-chain sequence peripheral interface integrated circuit (200, 400) is the master integrated circuit (M1) of the daisy-chain sequence peripheral interface architecture (100), the master mode core circuit (221) outputs the chip selection signal to the plurality of slave integrated circuits of the daisy-chain sequence peripheral interface architecture (100) through the routing circuit (210) and the second chip selection interface circuit (CS22). The master mode core circuit (221) reads the target data of the target slave circuit corresponding to the chip selection signal through the routing circuit (210) and the second MISO interface circuit (MISO22). The slave mode core circuit (222) is coupled to the routing circuit (210), wherein when the daisy chain sequence peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy chain sequence peripheral interface architecture (100) and the daisy chain sequence peripheral interface integrated circuit (200, 400) is the target slave circuit, the slave mode core circuit (222) outputs the data enable signal to the master integrated circuit (M1) of the daisy chain sequence peripheral interface architecture (100) through the routing circuit (210) and the first data enable interface circuit (DE21), and the slave mode core circuit (222) transmits the target data back to the master integrated circuit (M1) through the routing circuit (210) and the first MISO interface circuit (MISO21) based on the timing of the data enable signal.

11. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 1, characterized in that, The daisy-chain sequence peripheral interface integrated circuit (200, 400) also includes: First clock interface circuit (SCL21): and The second clock interface circuit (SCL22), wherein the routing circuit (210) is also coupled to the output of the first clock interface circuit and the input of the second clock interface circuit (SCL22), When the daisy-chain peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain peripheral interface architecture (100), the routing circuit (210) transmits the clock signal received by the first clock interface circuit (SCL21) to the second clock interface circuit (SCL22) and the core circuit (220); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1) of the daisy chain sequence peripheral interface architecture (100), the core circuit (220) outputs the clock signal to multiple slave integrated circuits of the daisy chain sequence peripheral interface architecture (100) through the routing circuit (210) and the second clock interface circuit (SCL22).

12. The daisy-chain sequence peripheral interface integrated circuit (200, 400) according to claim 11, characterized in that, The routing circuit (210) includes: A multiplexer (Mux7) has a first input terminal coupled to the core circuit (220), wherein a second input terminal of the multiplexer (Mux7) is coupled to the output terminal of the first clock interface circuit (SCL21), and the output terminal of the multiplexer (Mux7) is coupled to the input terminal of the second clock interface circuit (SCL22). When the daisy-chain peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1), the output terminal of the multiplexer (Mux7) is selectively coupled to the first input terminal of the multiplexer (Mux7), and when the daisy-chain peripheral interface integrated circuit (200, 400) is not the main integrated circuit (M1), the output terminal of the multiplexer (Mux7) is selectively coupled to the second input terminal of the multiplexer (Mux7).

13. A method for operating a daisy-chain sequence peripheral interface integrated circuit (200, 400), characterized in that, The operation method includes: The unique identification code of the daisy chain sequence peripheral interface integrated circuit (200, 400) is defined by at least one chip identification pin of the daisy chain sequence peripheral interface integrated circuit (200, 400). When the unique identification code indicates that the daisy chain sequence peripheral interface integrated circuit (200, 400) is a slave integrated circuit of the daisy chain sequence peripheral interface architecture (100), the core circuit (220) of the daisy chain sequence peripheral interface integrated circuit (200, 400) determines whether the daisy chain sequence peripheral interface integrated circuit (200, 400) is the target slave circuit selected by the master integrated circuit (M1) of the daisy chain sequence peripheral interface architecture (100); When the daisy-chain peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain peripheral interface architecture (100) and the target slave circuit selected by the master integrated circuit (M1) for reading target data, the core circuit (220) outputs a data enable signal to the master integrated circuit (M1) through the routing circuit (210) of the daisy-chain peripheral interface integrated circuit (200, 400) and the first data enable interface circuit (DE21) of the daisy-chain peripheral interface integrated circuit (200, 400), and the core circuit (220) returns the target data to the master integrated circuit (M1) based on the timing of the data enable signal through the routing circuit (210) and the first MISO interface circuit (MISO21) of the daisy-chain peripheral interface integrated circuit (200, 400); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy chain sequence peripheral interface architecture (100) and not the target slave circuit, the routing circuit (210) transmits the signal received by the second data enable interface circuit (DE22) of the daisy chain sequence peripheral interface integrated circuit (200, 400) to the first data enable interface circuit (DE21), and the routing circuit (210) transmits the data received by the second MISO interface circuit (MISO22) of the daisy chain sequence peripheral interface integrated circuit (200, 400) to the first MISO interface circuit (MISO21).

14. The operating method according to claim 13, characterized in that, The routing circuit (210) includes a first latching circuit (L1), a second latching circuit (L3), a first multiplexer (Mux1), and a second multiplexer (Mux3). The input terminal of the first latching circuit (L1) is coupled to the second data enable interface circuit (DE22). The first input terminal of the first multiplexer (Mux1) is coupled to the core circuit (220). The second input terminal of the first multiplexer (Mux1) is coupled to the output terminal of the first latching circuit (L1). The output terminal of the first multiplexer (Mux1)... The operation method further includes: a first input terminal of the second latch circuit (L3) coupled to the first data enable interface circuit (DE21), an input terminal of the second latch circuit (L3) coupled to the second MISO interface circuit (MISO22), a first input terminal of the second multiplexer (Mux3) coupled to the core circuit (220), a second input terminal of the second multiplexer (Mux3) coupled to the output terminal of the second latch circuit (L3), and an output terminal of the second multiplexer (Mux3) coupled to the first MISO interface circuit (MISO21); and the operation method further includes: When the daisy-chain sequence peripheral interface integrated circuit (200, 400) is the target slave circuit, the output terminal of the first multiplexer (Mux1) is selectively coupled to the first input terminal of the first multiplexer (Mux1), and the output terminal of the second multiplexer (Mux3) is selectively coupled to the first input terminal of the second multiplexer (Mux3); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is not the target slave circuit, the output terminal of the first multiplexer (Mux1) is selectively coupled to the second input terminal of the first multiplexer (Mux1), and the output terminal of the second multiplexer (Mux3) is selectively coupled to the second input terminal of the second multiplexer (Mux3).

15. The operating method according to claim 14, characterized in that, The daisy-chain peripheral interface integrated circuit (400) further includes a third MISO interface circuit (MISO23) and a fourth MISO interface circuit (MISO24). The routing circuit (210) further includes a third latch circuit (L5) and a third multiplexer (Mux5). The input terminal of the third latch circuit (L5) is coupled to the output terminal of the third MISO interface circuit (MISO23). The first input terminal of the third multiplexer (Mux5) is coupled to the core circuit (220). The second input terminal of the third multiplexer (Mux5) is coupled to the output terminal of the third latch circuit (L5). The output terminal of the third multiplexer (Mux5) is coupled to the input terminal of the fourth MISO interface circuit (MISO24). The operation method further includes: When the daisy-chain sequence peripheral interface integrated circuit (400) is the main integrated circuit (M1), the output terminal of the third multiplexer (Mux5) is selectively coupled to the first input terminal of the third multiplexer (Mux5); and When the daisy chain sequence peripheral interface integrated circuit (400) is not the main integrated circuit (M1), the output terminal of the third multiplexer (Mux5) is selectively coupled to the second input terminal of the third multiplexer (Mux5).

16. The operating method according to claim 13, characterized in that, The daisy-chain peripheral interface integrated circuit (200, 400) further includes a first MOSI interface circuit (MOSI21) and a second MOSI interface circuit (MOSI22). The routing circuit (210) is also coupled to the output terminal of the first MOSI interface circuit (MOSI21) and the input terminal of the second MOSI interface circuit (MOSI22). The operation method further includes: When the daisy-chain peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain peripheral interface architecture (100), the routing circuit (210) transmits the master circuit data received by the first MOSI interface circuit (MOSI21) to the second MOSI interface circuit (MOSI22) and the core circuit (220); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1) of the daisy chain sequence peripheral interface architecture (100), the core circuit (220) outputs the main circuit data to multiple slave integrated circuits of the daisy chain sequence peripheral interface architecture (100) through the routing circuit (210) and the second MOSI interface circuit (MOSI22).

17. The operating method according to claim 16, characterized in that, The routing circuit (210) includes a first latching circuit (L1) and a first multiplexer (Mux1). The input terminal of the first latching circuit (L1) is coupled to the output terminal of the first MOSI interface circuit (MOSI21). The first input terminal of the first multiplexer (Mux1) is coupled to the core circuit (220). The second input terminal of the first multiplexer (Mux1) is coupled to the output terminal of the first latching circuit (L1). The output terminal of the first multiplexer (Mux1) is coupled to the input terminal of the second MOSI interface circuit (MOSI22). The operation method further includes: When the daisy-chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1), the output terminal of the first multiplexer (Mux1) is selectively coupled to the first input terminal of the first multiplexer (Mux1); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is not the main integrated circuit (M1), the output terminal of the first multiplexer (Mux1) is selectively coupled to the second input terminal of the first multiplexer (Mux1).

18. The operating method according to claim 17, characterized in that, The daisy-chain peripheral interface integrated circuit (400) further includes a third MOSI interface circuit (MOSI23) and a fourth MOSI interface circuit (MOSI24). The routing circuit (210) further includes a second latching circuit (L3) and a second multiplexer (Mux3). The input terminal of the second latching circuit (L3) is coupled to the output terminal of the fourth MOSI interface circuit (MOSI24). The first input terminal of the second multiplexer (Mux3) is coupled to the core circuit (220). The second input terminal of the second multiplexer (Mux3) is coupled to the output terminal of the second latching circuit (L3). The output terminal of the second multiplexer (Mux3) is coupled to the input terminal of the third MOSI interface circuit (MOSI23). The operation method further includes: When the daisy-chain sequence peripheral interface integrated circuit (400) is the target slave circuit, the output terminal of the second multiplexer (Mux3) is selectively coupled to the first input terminal of the second multiplexer (Mux3); and When the daisy chain sequence peripheral interface integrated circuit (400) is not the target slave circuit, the output terminal of the second multiplexer (Mux3) is selectively coupled to the second input terminal of the second multiplexer (Mux3).

19. The operating method according to claim 13, characterized in that, The daisy-chain peripheral interface integrated circuit (200, 400) further includes a first chip selection interface circuit (CS21) and a second chip selection interface circuit (CS22). The routing circuit (210) is also coupled to the output of the first chip selection interface circuit (CS21) and the input of the second chip selection interface circuit (CS22). The operation method further includes: When the daisy-chain peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain peripheral interface architecture (100), the routing circuit (210) transmits the chip selection signal received by the first chip selection interface circuit (CS21) to the second chip selection interface circuit (CS22) and the core circuit (220), and the core circuit (220) decodes the chip selection signal to determine whether the daisy-chain peripheral interface integrated circuit (200, 400) is the target slave circuit selected by the master integrated circuit (M1); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1) of the daisy chain sequence peripheral interface architecture (100), the core circuit (220) outputs the chip selection signal to multiple slave integrated circuits of the daisy chain sequence peripheral interface architecture (100) through the routing circuit (210) and the second chip selection interface circuit (CS22), and the core circuit (220) reads the target data of the target slave circuit corresponding to the chip selection signal through the routing circuit (210) and the second MISO interface circuit (MISO22).

20. The operating method according to claim 19, characterized in that, The operation method further includes: When the decoding result of the core circuit (220) of the chip selection signal matches the unique identification code of the daisy chain sequence peripheral interface integrated circuit (200, 400), the daisy chain sequence peripheral interface integrated circuit (200, 400) is determined to be the target slave circuit selected by the master integrated circuit (M1). When the decoding result does not match the unique identifier of the daisy-chain sequence peripheral interface integrated circuit (200, 400), but matches the broadcast identifier shared by the multiple slave integrated circuits of the daisy-chain sequence peripheral interface architecture (100), the daisy-chain sequence peripheral interface integrated circuit (200, 400) is determined to be the target slave circuit selected by the master integrated circuit (M1); and When the decoding result does not match the unique identifier of the daisy chain sequence peripheral interface integrated circuit (200, 400) or the broadcast identifier, it is determined that the daisy chain sequence peripheral interface integrated circuit (200, 400) is not the target slave circuit selected by the master integrated circuit (M1).

21. The operating method according to claim 19, characterized in that, The routing circuit (210) includes a latching circuit (L6) and a multiplexer (Mux6). The input of the latching circuit (L6) is coupled to the output of the first chip selection interface circuit (CS21). The first input of the multiplexer (Mux6) is coupled to the core circuit (220). The second input of the multiplexer (Mux6) is coupled to the output of the latching circuit (L6). The output of the multiplexer (Mux6) is coupled to the input of the second chip selection interface circuit (CS22). The operation method further includes: When the daisy-chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1), the output terminal of the multiplexer (Mux6) is selectively coupled to the first input terminal of the multiplexer (Mux6); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is not the main integrated circuit (M1), the output terminal of the multiplexer (Mux6) is selectively coupled to the second input terminal of the multiplexer (Mux6).

22. The operating method according to claim 19, characterized in that, The core circuit (220) includes a master mode core circuit (221) and a slave mode core circuit (222), the master mode core circuit (221) and the slave mode core circuit (222) being coupled to the routing circuit (210), and the operation method further includes: When the daisy-chain peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1) of the daisy-chain peripheral interface architecture (100), the master mode core circuit (221) outputs the chip selection signal to the plurality of slave integrated circuits of the daisy-chain peripheral interface architecture (100) through the routing circuit (210) and the second chip selection interface circuit (CS22), and the master mode core circuit (221) reads the target data of the target slave circuit corresponding to the chip selection signal through the routing circuit (210) and the second MISO interface circuit (MISO22); and When the daisy-chain sequence peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain sequence peripheral interface architecture (100) and the daisy-chain sequence peripheral interface integrated circuit (200, 400) is the target slave circuit, the slave mode core circuit (222) outputs the data enable signal to the master integrated circuit (M1) of the daisy-chain sequence peripheral interface architecture (100) through the routing circuit (210) and the first data enable interface circuit (DE21), and the slave mode core circuit (222) transmits the target data back to the master integrated circuit (M1) through the routing circuit (210) and the first MISO interface circuit (MISO21) based on the timing of the data enable signal.

23. The operating method according to claim 13, characterized in that, The daisy-chain peripheral interface integrated circuit (200, 400) further includes a first clock interface circuit (SCL21) and a second clock interface circuit (SCL22). The routing circuit (210) is also coupled to the output of the first clock interface circuit (SCL21) and the input of the second clock interface circuit (SCL22). The operation method further includes: When the daisy-chain peripheral interface integrated circuit (200, 400) is the slave integrated circuit of the daisy-chain peripheral interface architecture (100), the routing circuit (210) transmits the clock signal received by the first clock interface circuit (SCL21) to the second clock interface circuit (SCL22) and the core circuit (220); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1) of the daisy chain sequence peripheral interface architecture (100), the core circuit (220) outputs the clock signal to the multiple slave integrated circuits of the daisy chain sequence peripheral interface architecture (100) through the routing circuit (210) and the second clock interface circuit (SCL22).

24. The operating method according to claim 23, characterized in that, The routing circuit (210) includes a multiplexer (Mux7), the first input of which is coupled to the core circuit (220), the second input of which is coupled to the output of the first clock interface circuit (SCL21), and the output of which is coupled to the input of the second clock interface circuit (SCL22). The operation method further includes: When the daisy-chain peripheral interface integrated circuit (200, 400) is the main integrated circuit (M1), the output terminal of the multiplexer (Mux7) is selectively coupled to the first input terminal of the multiplexer (Mux7); and When the daisy chain sequence peripheral interface integrated circuit (200, 400) is not the main integrated circuit (M1), the output terminal of the multiplexer (Mux7) is selectively coupled to the second input terminal of the multiplexer (Mux7).

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