Semiconductor memory device

Abstract

The present invention relates to a semiconductor storage device. A first transistor is connected to a capacitor at a first terminal. A first inverter circuit is connected between a first node and a second node, including a second transistor of p-type and a third transistor of n-type connected at a third node. A second inverter circuit is connected between the first node and the second node, including a fourth transistor of p-type and a fifth transistor of n-type connected at a fourth node. A gate of the fourth transistor and a gate of the fifth transistor are connected to a second terminal of the first transistor. A sixth transistor is connected between the gate of the fourth transistor and the third node and between the gate of the fifth transistor and the third node. A seventh transistor is connected between a gate of the second transistor and the fourth node and between a gate of the third transistor and the fourth node. An eighth transistor is connected between the gate of the second transistor and the third node. A ninth transistor is connected between the gate of the fourth transistor and the fourth node.

Description

[0001] This application is based on and asserts the priority of prior Japanese Patent Application No. 2021-205417, filed on December 17, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The implementation methods generally involve storage devices. Background Technology

[0003] As a storage device, DRAM (Dynamic Random Access Memory) is known. A DRAM memory cell includes a capacitor and a transistor. The memory cell retains data based on the charge stored in the capacitor. The voltage of the data in the memory cell from which data is read is amplified by a sense amplifier, thereby identifying the stored data. Summary of the Invention

[0004] One implementation provides a semiconductor memory device in which malfunctions are suppressed.

[0005] One embodiment of the storage device includes: a capacitor; a first transistor; a first inverter circuit connected between a first node and a second node, including a p-type second transistor and an n-type third transistor connected in series at a third node; a second inverter circuit, including a p-type fourth transistor and an n-type fifth transistor connected in series at a fourth node; a sixth transistor; a seventh transistor; an eighth transistor; and a ninth transistor.

[0006] The first transistor is connected to the capacitor at its first terminal. The second inverter circuit is connected between the first node and the second node. The gates of the fourth and fifth transistors are connected to the second terminal of the first transistor. The sixth transistor is connected between the gate of the fourth transistor and the third node, and between the gate of the fifth transistor and the third node. The seventh transistor is connected between the gate of the second transistor and the fourth node, and between the gate of the third transistor and the fourth node. The eighth transistor is connected between the gate of the second transistor and the third node. The ninth transistor is connected between the gate of the fourth transistor and the fourth node.

[0007] Based on the above structure, a semiconductor memory device in which malfunctions are suppressed can be provided. Attached Figure Description

[0008] Figure 1 The functional blocks and associated constituent elements of the storage device of the first embodiment are shown.

[0009] Figure 2 The components of the memory cell of the first embodiment and the connections between the components are shown.

[0010] Figure 3 The diagram shows the components of a portion of the sensing amplifier according to the first embodiment, as well as the connections between the components.

[0011] Figure 4 The potential during the data readout period of several elements of the semiconductor memory device of the first embodiment is shown in chronological order.

[0012] Figure 5 This schematically illustrates a state during the operation of the sensing amplifier circuit of the first embodiment.

[0013] Figure 6 This schematically illustrates a state during the operation of the sensing amplifier circuit of the first embodiment.

[0014] Figure 7 This schematically illustrates a state during the operation of the sensing amplifier circuit of the first embodiment.

[0015] Figure 8 The potential during the data readout period of several elements of the storage device of the first embodiment is shown in the time diagram.

[0016] Figure 9 The components of a reference sense amplifier circuit and the connections between them are shown.

[0017] Figure 10 The potential during the period of data readout of several elements of the reference storage device is shown according to time.

[0018] Figure 11 The layout of a portion of the storage device of the first embodiment and a reference storage device is shown.

[0019] Figure 12 The structure of a storage device according to a variation of the first embodiment is schematically shown. Detailed Implementation

[0020] In the following description, multiple components having substantially the same function and structure in one or different embodiments are sometimes further distinguished by appending numbers or characters to the end of the reference numerals. In embodiments following a described embodiment, the differences from the described embodiment are mainly described. Any description of a particular embodiment, unless explicitly stated or clearly excluded, is also applicable as a description of other embodiments.

[0021] In this specification and the patent claims, a first element being "connected" to other second elements includes the first element being directly or always or selectively connected to the second element via an element that is conductive.

[0022] 1. First Implementation Method

[0023] 1.1. Construction (Structure)

[0024] Figure 1 Functional blocks of the storage device according to the first embodiment are shown. The storage device 1 is a device for storing data. The storage device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a row selection circuit 15, a column selection circuit 16, a write circuit 17, a readout circuit 18, and a sense amplifier 19.

[0025] The memory cell array 11 includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL. Each memory cell MC can store 1 bit of data. Each memory cell MC is connected to one bit line BL and one word line WL. The memory cell MC is connected between the bit line BL and, for example, a board line (not shown). The word line WL is associated with a row. The bit line BL is associated with a column. A memory cell MC is determined by selecting one row and one column.

[0026] Input / output circuit 12 is a circuit for inputting and outputting data and signals. Input / output circuit 12 receives control signals CNT, commands CMD, address signals ADD, and data DAT from outside the storage device 1, such as from a memory controller. Input / output circuit 12 outputs data DAT. Data DAT is used to write data into the storage device 1. Data DAT is used to read data from the storage device 1.

[0027] Control circuit 13 is a circuit that controls the operation of storage device 1. Control circuit 13 receives command CMD and control signal CNT from input / output circuit 12. Control circuit 13 controls write circuit 17 and read circuit 18 according to the control indicated by command CMD and control signal CNT.

[0028] The voltage generation circuit 14 is a circuit that generates various voltages used in the storage device 1. The voltage generation circuit 14 generates multiple voltages of different magnitudes under the control of the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 17, the read circuit 18, and the sense amplifier 19.

[0029] Row selection circuit 15 is a circuit that selects a row of memory cell MC. Row selection circuit 15 receives address signal ADD from input / output circuit 12. Row selection circuit 15 uses the voltage received from voltage generation circuit 14 to make one word line WL associated with the row determined according to the received address signal ADD selected.

[0030] Column selection circuit 16 is a circuit that selects a column of memory cell MC. Column selection circuit 16 receives an address signal ADD from input / output circuit 12. Column selection circuit 16 uses a voltage received from voltage generation circuit 14 to make the bit line BL associated with the column determined according to the received address signal ADD into the selected state.

[0031] The write circuit 17 is a circuit that performs processing and control for writing data to the memory cell MC. The write circuit 17 receives data written from the input / output circuit 12. According to the control circuit 13 and the data, the write circuit 17 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16.

[0032] The readout circuit 18 is a circuit that performs processing and control for reading data from the memory cell MC. The readout circuit 18 determines the data stored in the memory cell MC according to the control circuit 13. The determined data is then supplied to the input / output circuit 12.

[0033] The sensing amplifier 19 is a circuit used to determine the data stored in the memory cell MC. The sensing amplifier 19 includes multiple sensing amplifier circuits SAC (not shown). The sensing amplifier 19 receives multiple voltages from the voltage generation circuit 14 and operates using the received voltages. During data readout, the sensing amplifier 19 amplifies the potential on the bit line BL in order to infer the data stored in the memory cell MC to be read out.

[0034] 1.1.1. Memory Unit

[0035] Figure 2 The constituent elements of the memory cell according to the first embodiment and the connections between these constituent elements are shown. Figure 2 As shown, each memory cell MC includes a cell capacitor CC and an n-type MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) CT. The cell capacitor CC is connected at one end to the board line PL and at the other end to one end of the transistor CT. The cell capacitor CC uses the charge accumulated at the node connected to the transistor CT to store data. The node connected to the transistor CT of the cell capacitor CC is sometimes referred to as the memory device node SN.

[0036] The state of whether a storage device node has accumulated charge corresponds to the state of the memory cell MC storing "1" data or storing "0" data. For example, the state of storage device node SN with a positive potential is treated as the state of memory cell MC storing "1" data, and the state of storage device node SN without a positive potential is treated as the state of memory cell MC storing "0" data.

[0037] The transistor CT is connected to a bit line BL at one end and to a word line WL at the gate.

[0038] 1.1.2. Sensing Amplifier

[0039] Figure 3 The diagram shows the components of a portion of the sensing amplifier 19 according to the first embodiment, as well as the connections between these components. As described above, the sensing amplifier 19 includes a plurality of sensing amplifier circuits SAC. Figure 3 A sense amplifier circuit SAC is shown.

[0040] like Figure 3 As shown, each sense amplifier circuit (SAC) is connected to a bit line BL and a node -BL. The part below node -BL is sometimes referred to as the complementary bit line -BL. The complementary bit line -BL functions as a node with a reference potential (or reference potential). The reference potential is used to determine the data stored in the memory cell MC of the data readout target.

[0041] The sense amplifier circuit SAC includes p-type MOSFETs TP1 to TP6 and n-type MOSFETs TN1 to TN6. The sense amplifier 19 also includes transistors TN11 and TN12.

[0042] Transistor TP1 is connected between node SAP and node N1. Node SAP receives voltage, for example, from voltage generation circuit 14. Node SAP receives one dynamically switching voltage from a plurality of voltages, including the power supply voltage Vddsa and voltage Vddsa / 2. The power supply voltage Vddsa may have the same magnitude as the power supply voltage Vdd used in storage device 1, or it may have a different magnitude. Transistor TP1 is connected to the complementary bit line -BL at its gate. Transistor TP1 has a resistance of a certain magnitude (on-resistance) during conduction.

[0043] Transistor TN1 is connected between node N1 and node SAN. Node SAN receives voltage, for example, from voltage generation circuit 14. Node SAN is supplied with one dynamically switching voltage from a plurality of voltages, including the power supply voltage Vddsa / 2 and the ground voltage (common voltage) Vss. The ground voltage Vss is, for example, 0V, and the following description is based on this example. Transistor TN1 is connected to the complementary bit line -BL at its gate. Transistor TN1 has a certain on-resistance.

[0044] Transistor TP2 is connected between node SAP and node N2. Transistor TP2 is connected to bit line BL at its gate. Transistor TP2 has an on-resistance substantially the same as that of transistor TP1. In this specification, "substantially the same" means that two elements may be formed with the same goal, but are not entirely identical due to unavoidable reasons such as limitations in the technology used to manufacture these elements.

[0045] Transistor TN2 is connected between node N2 and node SAN. Transistor TN2 is connected to bit line BL at its gate. Transistor TN2 has an on-resistance that is substantially the same as that of transistor TN1.

[0046] Transistor TP3 is connected between node N1 and the gate of transistor TP1. Transistor TP3 receives signal OC_p at its gate. Signal OC_p is supplied, for example, from readout circuit 18.

[0047] Transistor TP4 is connected between node N2 and the gate of transistor TP2. Transistor TP4 receives the signal OC_p at its gate.

[0048] Transistor TP5 is connected between node N1 and bit line BL. Transistor TP5 receives signal ISO_p at its gate. Signal ISO_p is supplied, for example, from readout circuit 18.

[0049] Transistor TP6 is connected between node N2 and complementary bit line -BL. Transistor TP6 receives signal ISO_p at its gate.

[0050] Transistor TN3 is connected between node N1 and the gate of transistor TN1. Transistor TN3 receives signal OC_n at its gate. Signal OC_n is supplied, for example, from readout circuit 18.

[0051] Transistor TN4 is connected between node N2 and the gate of transistor TN2. Transistor TN4 receives the signal OC_n at its gate.

[0052] Transistor TN5 is connected between node N1 and bit line BL. Transistor TN5 receives signal ISO_n at its gate. Signal ISO_n is supplied, for example, from readout circuit 18.

[0053] Transistor TN6 is connected between node N2 and complementary bit line -BL. Transistor TN6 receives signal ISO_n at its gate.

[0054] Transistor TN11 is connected between at least one bit line BL and node NBP. Node NBP receives a pre-charge voltage Vpc from voltage generation circuit 14. The pre-charge voltage Vpc is (Vddsa - Vss) / 2, or Vddsa / 2 when Vss is 0V, and also functions as a reference voltage. Transistor TN11 receives signal EQ at its gate. Signal EQ is supplied, for example, from readout circuit 18.

[0055] Transistor TN12 is connected between at least one complementary bit line -BL and node NBP. Transistor TN12 receives signal EQ at its gate.

[0056] Transistors TP1 and TN1 constitute inverter circuit IV1, and transistors TP2 and TN2 constitute inverter circuit IV2. During the conduction of transistors TP5, TP6, TN5, and TN6, inverter circuits IV1 and IV2 are cross-coupled. That is, the input and output nodes of inverter circuit IV1 are connected to the input and output nodes of inverter circuit IV2, respectively.

[0057] 1.2. Actions

[0058] Figure 4 The voltage levels during data readout of several elements of the storage device in the first embodiment are shown in chronological order. Hereinafter, the memory cell MC to which data is readout is sometimes referred to as the selected memory cell MC. Figure 4 The word line WL shown is the word line connected to the select memory cell MC, and is sometimes referred to below as the select word line WL. Figure 4 The bit line BL shown is the one connected to the select memory cell MC during data readout; hereinafter, it is sometimes referred to as the select bit line BL. The complementary bit line -BL connected to the sense amplifier circuit SAC connected to the select bit line BL is sometimes referred to as the select complementary bit line -BL. By applying a voltage to the wiring or signal wiring shown in the transmission diagram, the wiring has a potential substantially the same as the applied voltage. For example, a wiring has a potential Vdd, so a supply voltage Vdd is applied.

[0059] exist Figure 4At the start of the period, the potentials of each element are as follows. The select word line WL is asserted, i.e., it has a power supply potential Vpp. The power supply potential Vpp is an internal power supply potential, for example, having a different magnitude than the power supply voltage Vdd. With the select word line WL having the power supply potential Vpp, the transistor CT of the select memory cell MC is turned on, and the cell capacitor CC of the select memory cell MC is connected to the select bit line BL.

[0060] This negates the EQ signal, meaning it has a potential (ground potential) Vss with a ground voltage Vss. Therefore, transistors TN11 and TN12 are turned off, and both the select bit line BL and the select complementary bit line -BL are not connected to node NBP at the precharge potential Vpc.

[0061] Enable the signal ISO_p, i.e., have a ground potential Vss. With a ground potential Vss at the gate, transistor TP5 is turned on, and the select bit line BL is connected to node N1 via the turned-on transistor TP5. With a ground potential Vss at the gate, transistor TP6 is turned on, and the select complementary bit line -BL is connected to node N2 via the turned-on transistor TP6.

[0062] To enable the signal ISO_n, the power supply potential Vddiso is set. Vddiso is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. With Vddiso at the gate, transistor TN5 is turned on, and the select bit line BL is connected to node N1 via the turned-on transistor TN5. With Vddiso at the gate, transistor TN6 is turned on, and the complementary select bit line -BL is connected to node N2 via the turned-on transistor TN6.

[0063] This invalidates the signal OC_p, i.e., it has a power supply potential Vddoc. The power supply potential Vddoc is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. With a power supply potential Vddoc at the gate, transistor TP3 is turned off, and the gate of transistor TP1 is cut off from node N1. With a power supply potential Vddoc at the gate, transistor TP4 is turned off, and the gate of transistor TP2 is cut off from node N2.

[0064] The signal OC_n is invalidated, i.e., it has a ground potential Vss. With a ground potential Vss at the gate, transistor TN3 is turned off, and the gate of transistor TN1 is cut off from node N1. With a ground potential Vss at the gate, transistor TN4 is turned off, and the gate of transistor TN2 is cut off from node N2.

[0065] The SAP node has a power supply potential Vddsa, and the SAN node has a ground potential Vss. Therefore, the sense amplifier circuit SAC receives power and is in a state where it is turned on and can operate.

[0066] Based on the potential states as described above, one of the selected bit line BL and the selected complementary bit line -BL has a power supply potential Vddsa, and the other has a ground potential Vss. Which bit line BL or the selected complementary bit line -BL has the power supply potential Vddsa depends on whether the selected memory cell MC stores "0" data or "1" data.

[0067] When the selected memory cell MC stores "0" data, the select bit line BL has a ground potential Vss, and the memory device node SN has a ground potential Vss. On the other hand, when the selected memory cell MC stores "1" data, the select bit line BL has a power supply potential Vddsa, and the memory device node SN has a power supply potential Vddsa. Hereinafter, the case where the selected memory cell MC stores "0" data is sometimes referred to as the "0" data storage case, and the case where the selected memory cell MC stores "1" data is sometimes referred to as the "1" data storage case.

[0068] Accompanying the start of data readout, at time t0, the select word line WL is deactivated, meaning its potential is set to ground Vss. Consequently, the transistor CT of the select memory cell MC is turned off, and the cell capacitor CC of the select memory cell MC is disconnected from the select bit line BL. Alternatively, the select word line WL can be set to a negative potential instead of ground Vss.

[0069] Time t1 to time t2 is the equalization period. At time t1, the potential of node SAP is set to Vddsa / 2, and the potential of node SAN is also set to Vddsa / 2. Therefore, the sense amplifier circuit SAC does not receive a power supply and does not have the function of amplifying the potential. The voltage applied to node SAP and node SAN is (Vddsa + Vss) / 2. However, as mentioned above, based on the example where the ground voltage Vss is 0V, the applied voltage is Vddsa / 2.

[0070] At time t1, signal EQ is made active, i.e., the potential of signal EQ is set to the power supply potential Vddeq. The power supply potential Vddeq is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. With the application of the power supply potential Vddeq, transistors TN11 and TN12 are turned on, and the select bit line BL and the select complementary bit line -BL are connected to node NBP. As a result, the select bit line BL and the select complementary bit line -BL are equalized to the same potential. Specifically, the select bit line BL and the select complementary bit line -BL are pre-charged to the potential of the pre-charge voltage Vpc, i.e., potential Vddsa / 2.

[0071] The period from time t2 to time t3 is the offset cancellation period. At time t2, the signal EQ is disabled. This ends the pre-charging of the selected bit line BL and the selected complementary bit line -BL.

[0072] At time t2, signal OC_p is made active, meaning its potential is set to ground potential Vss. Transistors TP3 and TP4 are turned on. Signal OC_n is made active, meaning its potential is set to power supply potential Vddoc. Transistors TN3 and TN4 are turned on. Signal ISO_p is made inactive, meaning its potential is set to power supply potential Vddiso. Transistors TP5 and TP6 are turned off. Signal ISO_n is made inactive, meaning its potential is set to ground potential Vss. Transistors TN5 and TN6 are turned off. Figure 5 The connection of the constituent elements of the sense amplifier circuit SAC during the offset cancellation period is schematically shown. Figure 5 And the following Figure 6 and Figure 7 In the diagram, a portion of a conducting transistor is represented by wiring connecting its two ends. A portion of a closed transistor is shown by dashed lines or not shown at all.

[0073] With transistor TP3 turned on, transistor TP1 is connected as a diode. Node N1 is connected to the complementary bit line -BL via transistor TP3.

[0074] With transistor TP4 turned on, transistor TP2 is connected as a diode. Node N2 is connected to the select bit line BL via transistor TP4.

[0075] With transistor TN3 turned on, transistor TN1 is connected as a diode. Node N1 is connected to the complementary bit line -BL via transistor TN3.

[0076] With transistor TN4 turned on, transistor TN2 is connected as a diode. Node N2 is connected to the select bit line BL via transistor TN4.

[0077] With transistors TP5 and TN5 cut off, the select bit line BL is disconnected from node N1, i.e., insulated. With transistors TP6 and TN6 cut off, the complementary select bit line -BL is disconnected from node N2, i.e., insulated. Therefore, inverter circuit IV1 (transistors TP1 and TN1) and inverter circuit IV2 (transistors TP2 and TN2) are not cross-coupled.

[0078] On the other hand, as described above, node N1 is connected to the selected complementary bit line -BL using transistors TP3 and TN3. Therefore, the potential of node N1 is transferred to the selected complementary bit line -BL, and node N1 has a potential substantially the same as that of the selected complementary bit line -BL. Furthermore, node N2 is connected to the selected bit line BL using transistors TP4 and TN4. Therefore, the potential of node N2 is transferred to the selected bit line BL, and node N2 has a potential substantially the same as that of the selected bit line BL.

[0079] like Figure 4 As shown, at time t2, the potential of node SAP is set to the power supply potential Vddsa, and the potential of node SAN is set to the ground potential Vss. As a result, the sense amplifier circuit SAC becomes capable of amplifying the potential.

[0080] At time t2, with the end of pre-charge and the start of insulation, the potentials of the select bit line BL and the select complementary bit line -BL change from the pre-charge potential (Vddsa / 2). During this change, offset cancellation occurs through the action of the conducting transistors TP3, TP4, TN3, and TN4. That is, transistor TP1 is turned on due to transistor TP3, thus forming an on-resistance of transistor TP1 between node SAP and node N1. Additionally, transistor TN1 is turned on due to transistor TN3, thus forming an on-resistance of transistor TN1 between node N1 and node SAN. Therefore, a potential is generated at node N1 based on the ratio of the on-resistance of transistor TP1 to the on-resistance of transistor TN1. Generally, p-type MOSFETs and n-type MOSFETs have different on-resistances, with the on-resistance of an n-type MOSFET being smaller than that of a p-type MOSFET. Therefore, the potential at node N1 is not the midpoint of the difference between the potentials of node SAP and node SAN, but a potential lower than the midpoint.

[0081] Furthermore, transistor TP2 is turned on due to transistor TP4, thus forming an on-resistance of transistor TP2 between node SAP and node N2. Similarly, transistor TN2 is turned on due to transistor TN4, thus forming an on-resistance of transistor TN2 between node N2 and node SAN. Therefore, a potential is generated at node N2 based on the ratio of the on-resistance of transistor TP2 to the on-resistance of transistor TN2. Therefore, for the same reasons as described regarding node N1, the potential of node N2 is not the midpoint of the difference between the potentials of node SAP and node SAN, but a potential lower than the midpoint.

[0082] Due to the change in the potential of node N1 based on offset cancellation, the potential of the selected complementary bit line -BL, connected to node N1 via transistors TP3 and TN3, also changes. Similarly, due to the change in the potential of node N2 based on offset cancellation, the potential of the selected bit line BL, connected to node N2 via transistors TP4 and TN4, also changes. One of the potentials of the selected bit line BL and the selected complementary bit line -BL decreases by a positive magnitude ΔV1 from potential Vddsa / 2, and the other decreases by a positive magnitude ΔV2 from potential Vddsa / 2. The difference between ΔV1 and ΔV2 arises from the difference in on-resistance between transistors TP1 and TP2, and the difference in on-resistance between transistors TN1 and TN2 (offset).

[0083] As described above, the difference between ΔV1 and ΔV2 is based on the difference (offset) in the on-resistance between transistors TP1 and TP2, and the difference in the on-resistance between transistors TN1 and TN2. Therefore, at the start of subsequent charge sharing, node N1 has a potential based on the on-resistance of transistors TP1 and TN1, and node N2 has a potential based on the on-resistance of transistors TP2 and TN2. Then, the complementary bit line -BL and the selected bit line BL are charged using nodes N1 and N2 with such potentials. The potentials of the selected bit line BL and the complementary bit line -BL, which are charged to such potentials, are sensed. The difference between the potentials of node N1 and node N2, based on the difference in the on-resistance of transistors TP1 and TP2 and the difference in the on-resistance of transistors TN1 and TN2, causes a deviation between the potential of the selected bit line BL and the potential of the complementary bit line -BL. In contrast, due to offset cancellation, the potentials based on the difference in on-resistance between transistors TP1 and TP2 and the difference in on-resistance between transistors TN1 and TN2 are charged to the complementary selection bit line -BL and the selection bit line BL via nodes N1 and N2, respectively, before sensing. Therefore, during sensing, the difference in on-resistance between transistors TP1 and TP2 and the difference in on-resistance between transistors TN1 and TN2 can be equivalently canceled (compensated).

[0084] Time intervals t3 to t4 constitute the period of charge sharing and pre-sensing. At time t3, signals OC_p and OC_n are invalidated; that is, the potential of signal OC_p is set to the power supply potential Vddoc, and the potential of signal OC_n is set to the ground potential Vss. Thus, as... Figure 6 As shown, transistors TP3, TP4, TN3, and TN4 are turned off. As a result, the connection between node N1 and the select complementary bit line -BL, and the connection between node N2 and the select bit line BL, are severed. Therefore, node N1 and the select complementary bit line -BL have independent potentials. Additionally, node N2 and the select bit line BL have independent potentials.

[0085] like Figure 4 As shown, at time t3, the select word line WL is enabled. This initiates charge sharing. Through charge sharing, the charge accumulated on the select bit line BL is shared with the charge accumulated in the memory node SN of the select memory cell MC. As a result, the potential of the select bit line BL rises or falls depending on the data stored in the select memory cell MC. The potentials of the select bit line BL (and the memory node SN) become equal in magnitude to the potentials of the select bit line BL and the memory node SN.

[0086] In the "0" data storage scenario, the potential of the select bit line BL decreases towards the potential of the storage device node SN, and the potential of the storage device node SN increases towards the potential of the select bit line BL. The select bit line BL and the storage device node SN reach a state with a potential VB0 equal to the magnitude of the decreasing potential of the select bit line BL and the increasing potential of the storage device node SN. The potential of the select complementary bit line -BL is maintained.

[0087] On the other hand, in the "1" data storage case, the potential of the storage device node SN decreases towards the potential of the select bit line BL, and the potential of the select bit line BL increases towards the potential of the storage device node SN. The select bit line BL and the storage device node SN become a state with a potential VB1 equal to the magnitude of the rising potential of the select bit line BL and the falling potential of the storage device node SN. The potential of the complementary select bit line -BL is maintained.

[0088] As described above, the potential of node N1 varies independently from the potential of the selected complementary bit line -BL, and the potential of node N2 varies independently from the potential of the selected bit line BL. The potentials of nodes N1 and N2 vary in the following manner.

[0089] At the time immediately preceding time t3, the potential of node N1, due to offset cancellation, is the difference between the power supply potential Vddsa and the ground potential Vss, divided by the on-resistance of transistor TP1 and transistor TN1. Then, the capacitance based on the potential of node N1 is stored in the selected complementary bit line -BL, and the potential of the selected complementary bit line -BL is not affected by charge sharing. Therefore, from time t3 onwards, node N1 also maintains the potential based on the state formed immediately preceding time t3 due to offset cancellation.

[0090] Immediately before time t3, the potential of node N2, due to offset cancellation, is the difference between the power supply potential Vddsa and the ground potential Vss, divided by the on-resistance of transistors TP2 and TN2. Then, the potential of the selection bit line BL changes due to the effect of charge sharing. This change in the potential of the selection bit line BL causes changes in the states of transistors TP2 and TN2, and even the current flowing through them. Therefore, the potential of node N2 changes from time t3 onwards.

[0091] In the case of "0" data storage, the potential of node N2 rises from time t3, and according to the potential of the selected bit line BL, it becomes a potential slightly lower than the power supply potential Vddsa.

[0092] In the case of "1" data storage, the potential of node N2 decreases from time t3, and according to the potential of the selected bit line BL, it becomes a potential slightly higher than the ground potential Vss.

[0093] As described above regarding time t2, at time t3, inverter circuits IV1 and IV2 are not cross-coupled. Therefore, the potential of node N1 does not affect the operation of inverter circuit IV2 or even the potential of node N2. Furthermore, the potential of node N2 does not affect the operation of inverter circuit IV1 or even the potential of node N1.

[0094] The period after time t4 is the sensing and recovery period. At time t4, signal ISO_p is activated. This turns on transistors TP5 and TP6. Additionally, signal ISO_n is activated. This turns on transistors TN5 and TN6.

[0095] Transistors TP5, TP6, TN5, and TN6 are turned on, thus... Figure 7 As shown, node N1 is connected to the gates of transistors TP2 and TN2, and node N2 is connected to the gates of transistors TP1 and TN1. That is, inverter circuit IV1 and inverter circuit IV2 are cross-coupled. Therefore, as... Figure 4 As shown, the sensing amplifier circuit SAC amplifies one of the potentials of node N1 and node N2 into a power supply potential Vddsa, and the other into a ground potential Vss.

[0096] The potential of node N1 is transferred to the select bit line BL via transistors TP5 and TN5. The potential of node N2 is transferred to the select complementary bit line -BL via transistors TP6 and TN6. Therefore, the potentials of the select bit line BL and the select complementary bit line -BL rise or fall. In the "0" data storage case, the potential of the select bit line BL is lowered to the ground potential Vss, and the potential of the select complementary bit line -BL is raised to the power supply potential Vddsa. On the other hand, in the "1" data storage case, the potential of the select bit line BL is raised to the power supply potential Vddsa, and the potential of the select complementary bit line -BL is lowered to the ground potential Vss.

[0097] 1.2.1. Actions when data volume is small

[0098] Figure 8 The potential during the data readout period of several elements of the storage device of the first embodiment is shown in the time diagram. Figure 8 This illustrates a worst-case scenario. The worst-case scenario corresponds to a situation where there is little semaphore in the "0" data storage condition, and the threshold voltage of transistor TN2 is not intentionally low beyond the permissible range. The low threshold voltage of transistor TN2 may, for example, occur due to unavoidable deviations in the manufacturing process of memory device 1.

[0099] In the case of "0" data storage, the small amount of semaphore is equivalent to the potential of the storage device node SN of the selected memory cell MC being unintentionally high due to leakage current, exceeding the allowable range.

[0100] like Figure 8 As shown, relative to the ideal ground potential Vss, the storage device node SN has a potential Vsn that is a certain magnitude higher than the ground potential Vss. As described above regarding time 3, through charge sharing from time t3, the potential of the selection bit line BL becomes a state where the potential of the storage device node SN is equal to the potential of the selection bit line BL.

[0101] The following is referred to as the normal case, in the case of "0" data storage, where the storage device node SN has a potential within the allowable range (e.g., a potential close to the ground potential Vss) and the transistor TN2 has a threshold voltage within the allowable range. Figure 4 This is equivalent to a normal situation. Figure 8 In the example, at the start of charge sharing, the potential of the memory node SN is high. Therefore, the result of charge sharing is that the potential VB0A of the selection bit line BL is high, higher than the potential under normal circumstances. Figure 4 The potential VB0 in the middle is high.

[0102] With a high potential at bit line BL and a low threshold voltage at transistor TN2, transistor TN2 conducts more strongly than normal. Therefore, the potential at node N2 is lower than normal. When inverter circuits IV1 and IV2 are cross-coupled, i.e., when node N2 is connected to the gates of transistors TP1 and TN1, transistor TP1 conducts more strongly due to the lower potential of node N2. Consequently, the potential at node N1 can be higher than normal, and due to the amplification function of the sense amplifier circuit SAC, the potential at node N1 may be higher than that at node N2.

[0103] However, in the first embodiment, during charge sharing, inverter circuit IV1 and inverter circuit IV2 are not cross-coupled. Therefore, the conduction level of transistor TP1 is not affected by the potential of node N2. Thus, even if the potential of node N2 is lower than the normal potential, it is possible to avoid the potential of node N1 being amplified by transistor TP1 due to the potential of node N2, and the potential of node N1 being higher than the potential of node N2 due to amplification. Therefore, in the worst case, similar to the normal case, the potential of node N2 is higher than the potential of node N1 from time t3.

[0104] 1.3. Advantages (Effects)

[0105] According to the first embodiment, a storage device that suppresses malfunctions can be provided.

[0106] For comparison, a reference storage device 100 is described. The storage device 100 includes a sense amplifier circuit 200. Figure 9 The components of a reference sense amplifier circuit 200 and the connections of the components are shown.

[0107] The sensing amplifier circuit 200 has a structure obtained by removing transistors TP3, TP4, TP5, and TP6 from the sensing amplifier circuit SAC of the first embodiment. The gate of transistor TP1 is connected to node N2, and the gate of transistor TP2 is connected to node N1. Therefore, by using transistors TP1 and TP2, the potentials of nodes N1 and N2 are always in an amplifying state.

[0108] Figure 10 The potential during the period of data reading from the reference storage device 100 is displayed according to the time. Figure 10 This shows the normal and worst-case scenarios for data storage of "0". For example... Figure 10 As shown, compared with the first embodiment Figure 4 Unlike other nodes, at the start of charge sharing at time t3, the potential of node SAP is set to potential Vddsa / 2, and the potential of node SAN is also set to potential Vddsa / 2.

[0109] At time t11, between time t3 and time t4, the potential of node SAP is set to the power supply potential Vddsa, and the potential of node SAN is set to the ground potential Vss, thus initiating pre-sensing. Initially, the potential of the selection bit line BL is lower than the potential of node N1.

[0110] Under normal circumstances, the potential of node SN in the memory device is low enough. Therefore, the potential of the select bit line BL at the start of pre-sensing is low enough that transistor TN2 is not turned on. On the other hand, the potential of the select complementary bit line -BL is high, so transistor TN1 is turned on. Therefore, the potential of node N1 drops rapidly towards the ground potential Vss, which is lower than the potential of the select bit line BL. In the sense amplifier circuit 200, the gate of transistor TP1 is connected to node N2, and the gate of transistor TP2 is connected to node N1. Therefore, due to the drop in the potential of node N1, transistor TP2 is turned on. Therefore, the potential of node N2 rises rapidly towards the power supply potential Vddsa. Therefore, at the start of sensing, the potential of node N2 is higher than the potential of node N1, and thus, the potential of the select bit line BL, which is connected to node N1 through sensing, becomes the ground potential Vss through sensing. In this way, the "0" data stored in the select memory cell MC is correctly determined.

[0111] On the other hand, even in the worst-case scenario, similar to the normal scenario, the potential of the complementary bit line -BL is high, so transistor TN1 turns on, and the potential of node N1 drops towards the ground potential Vss. Then, due to the decrease in the potential of node N1, transistor TP2 turns on. Therefore, the potential of node N2 is adjusted upwards towards the power supply potential Vddsa via transistor TP2. However, in the worst-case scenario, the potential of the memory device node SN is high. Therefore, the potential of the selected bit line BL at the beginning of the pre-sensing is high, and thus, transistor TN2, which has a low threshold voltage, may be turned on unintentionally. Therefore, the potential of node N2 is adjusted downwards towards the ground potential Vss via transistor TN2. Generally, the current drive capability of an n-type MOSFET is higher than that of a p-type MOSFET. Therefore, the effect of adjusting the potential of point N2 on transistor TP2 is not as strong as the effect of adjusting the potential of point N2 below transistor TN2. As a result, the potential of node N2 drops towards the ground potential Vss. On the other hand, the gate of transistor TP1 is connected to node N2. As the potential of node N2 decreases, the current driving capability of transistor TP1 increases, causing the potential of node N1 to rise towards the power supply potential Vddsa due to the action of the sensing amplifier circuit 200. Therefore, at the start of sensing, the potential of node N1 is higher than that of node N2. Consequently, the potential of the select bit line BL, which is connected to node N1 through sensing, becomes the power supply potential Vddsa. That is, the "0" data stored in the select memory cell MC is incorrectly determined to be "1" data.

[0112] According to the first embodiment, the gate of p-type transistor TP1 of inverter circuit IV1 in the sense amplifier circuit SAC is connected to node N2 (output of inverter circuit IV2) via transistor TP6, and the gate of p-type transistor TP2 of inverter circuit IV2 is connected to node N1 (output of inverter circuit IV1) via transistor TP5. Therefore, the gate of transistor TP1 can be selectively connected to and disconnected from node N2, and the gate of transistor TP2 can be selectively connected to and disconnected from node N1. Thus, during the period when a potential based on the select bit line BL is generated at node N2 through charge sharing, the gate of node N2 can be disconnected from the gate of transistor TP1 by the cutoff of transistor TP6. This prevents the potential of node N1 from rising due to the unintended high potential of the select bit line BL at the memory device node SN of the select memory cell MC, thus preventing the potential of node N2 from changing in an unintended direction and causing it to change in the intended direction. Therefore, even if the potential of the storage device node SN of the selected memory cell MC does not intentionally become high, data can still be read correctly from the selected memory cell MC.

[0113] According to the first embodiment, the gate of p-type transistor TP1 in inverter circuit IV1 of the sense amplifier circuit SAC is connected to node N1 (drain of transistor TP1) via transistor TP3, and the gate of p-type transistor TP2 in inverter circuit IV2 is connected to node N2 (drain of transistor TP2) via transistor TP4. Therefore, by turning on transistor TP3, the gate and drain of transistor TP1 can be connected, and by turning on transistor TP4, the gate and drain of transistor TP2 can be connected. By turning on transistor TP3, node N1 can generate a potential based on the on-resistance of transistor TP1, and by turning on transistor TP4, node N2 can generate a potential based on the on-resistance of transistor TP2.

[0114] Thus, the potentials generated at nodes N1 and N2 are transferred to the complementary selection bit line -BL and the selection bit line BL via transistors TP3, TP4, TN3, and TN4, respectively. Therefore, the selection bit line BL has a potential based on the on-resistance of transistors TP2 and TN2, and the complementary selection bit line -BL has a potential based on the on-resistance of transistors TP1 and TN1. By initiating charge sharing from this state, the potentials of the selection bit line BL and the complementary selection bit line -BL reflect the magnitudes of the on-resistances of transistors TP1, TP2, TN1, and TN2. Therefore, the influence of deviations in the on-resistances of transistors TN1, TN2, TP1, and TP2 on the sensing of the sense amplifier circuit SAC can be suppressed. This allows the sense amplifier circuit SAC to have a large margin, at least larger than the margin of the sense amplifier circuit 200.

[0115] According to the first embodiment, the sense amplifier circuit SAC includes more transistors than the sense amplifier circuit 200, and therefore has a larger area than the sense amplifier circuit 200. However, since the sense amplifier circuit SAC has a large margin, even if the capacity of the bit line BL connected to the sense amplifier circuit SAC is higher than the capacity of the bit line BL connected to the sense amplifier circuit 200, data can still be read correctly. Therefore, more memory cells MC than the sense amplifier circuit 200 can be connected to the sense amplifier circuit SAC. This means that the number of sense amplifier circuits SAC that need to be connected to n memory cells MC is less than the number of sense amplifier circuits 200 that need to be connected to n memory cells MC. Therefore, when the memory device 1 of the first embodiment and the reference memory device 100 are chips of the same size, the memory device 1 of the first embodiment can be configured with more memory cells MC than the reference memory device 100. Therefore, even if the sense amplifier circuit SAC has a larger area than the sense amplifier circuit 200, the memory device 1 can have the same or larger storage capacity as the memory device 100 (number of memory cells MC). Figure 11 This situation is illustrated schematically, with storage device 100 shown on the upper side and storage device 1 shown on the lower side.

[0116] like Figure 11 As shown on the upper left side, the subarrays of memory cells (memory cell subarrays) MCSA1 are arranged along the x-axis. Each memory cell subarray MCSA1 has a width WM1 along the x-axis and includes a certain number of memory cells MC Nm1. Between adjacent memory cell subarrays MCSA1, groups of sense amplifier circuits 200 (sense amplifier circuit groups) SACS1 are arranged. The sense amplifier circuit groups SACS1 have a width WS1 along the x-axis.

[0117] like Figure 11 As shown on the lower left side, the memory cell subarrays MCSA2 are arranged along the x-axis. Each memory cell subarray MCSA2 has a width WM2 along the x-axis and includes a certain number of memory cells MCs of Nm2. Between adjacent memory cell subarrays MCSA2, groups of sense amplifier circuits SACs (sense amplifier circuit groups) SACS2 are arranged. The sense amplifier circuit groups SACS2 have a width WS2 along the x-axis. The width WS2 is larger than the width WS1. On the other hand, the number of memory cells MCs that can be connected to one sense amplifier circuit SAC is greater than the number of memory cells MCs that can be connected to one sense amplifier circuit 200. Therefore, the width WM2 is larger than the width WM1.

[0118] Regarding storage device 100, the sum of the width WM1 of the three memory cell subarrays MCSA1 and the width WS1 of the three sense amplifier circuit groups SACS1 is the width WA1. Regarding storage device 1, the sum of the width WM2 of the two memory cell subarrays MCSA2 and the width WS2 of the two sense amplifier circuit groups SACS2 is the width WA2. Width WA2 is narrower than width WA1. Then, as shown on the right, the number of memory cells MC included in width WA1 (=Nm1×3) is the same as the number of memory cells MC included in width WA2 (=Nm2×2). Therefore, in the first embodiment, the same number of memory cells MC as in the reference example can be arranged in a narrower width area.

[0119] 1.4. Variations

[0120] As one embodiment, a configuration of transistors TP5, TP6, TN5, and TN6 is described. However, it is also possible to configure only one of the groups of transistors TP5 and TP6 or TN5 and TN6. For example, transistors TP5 and TP6 may not be configured. The gates of transistors TP1 and TN1 are connected to node N2 via transistor TN6, and the gates of transistors TP2 and TN2 are connected to node N1 via transistor TN5. In this case, it is necessary for the n-type transistor TN5 to be able to transfer potential between node N1 and bit line BL, and for the n-type transistor TN6 to be able to transfer potential between node N2 and complementary bit line -BL. For this purpose, the effective signal ISO_n has a potential that is greater than or equal to the threshold voltage of transistor TN5 above the potential of the transferred node N1 and bit line BL, and greater than or equal to the threshold voltage of transistor TN6 above the potential of the transferred node N2 and complementary bit line -BL.

[0121] Similarly, instead of providing transistors TP3, TP4, TN3, and TN4, only one side of the group containing transistors TP3 and TP4 and the group containing transistors TN3 and TN3 can be provided. For example, transistors TP3 and TP4 can be omitted. In this case, the n-type transistor TN3 needs to be able to transfer potential between node N1 and the complementary bit line -BL, and the n-type transistor TN4 needs to be able to transfer potential between node N2 and the bit line BL. For this purpose, the effective signal OC_n has a potential that is greater than the threshold voltage of transistor TN3 by a factor of 1 compared to the potential of the transferred node N1 and the complementary bit line -BL, and greater than the threshold voltage of transistor TN4 by a factor of 1 compared to the potential of the transferred node N2 and the bit line BL.

[0122] The storage device 1 can also have a so-called 3D structure. That is, the circuitry other than the memory cell array 11, at least the sensing amplifier 19, is located below along the z-axis of the memory cell array 11. Figure 12 The following example is shown to schematically illustrate the structure of a storage device of a variation of the first embodiment. Figure 12 It shows the space formed by mutually orthogonal x-axis, y-axis, and z-axis.

[0123] like Figure 12 As shown, a sensing amplifier 19 is disposed on the upper surface of a semiconductor substrate 21. The upper surface of the substrate 21 extends along the xy plane.

[0124] Multiple conductors 22 are disposed on the sensing amplifier 19. The conductors 22 extend along the z-axis and are arranged along the x-axis. Each conductor 22 functions as part of a bit line BL. The portion of the bit line BL implemented by the conductors 22 is sometimes referred to as the global bit line GBL.

[0125] Each conductor 22 is connected to a conductor 23 on its upper surface. The conductors 23 extend along the y-axis and are arranged along the x-axis. Each conductor 23 functions as part of a bit line BL. The portion of the bit line BL implemented through the conductors 23 is sometimes referred to as the global bit line GBL.

[0126] The memory cell array 11 is located above the conductor 23 along the z-axis. The memory cell array 11 includes multiple groups (multiple memory cell sets) of memory cells MC. Each memory cell set MCS includes multiple memory cells MC arranged along the x-axis. The multiple memory cells MC of each memory cell set MCS are connected to one conductor 31. Each conductor 31 functions as part of a word line WL. Each conductor 31 extends along the x-axis. Several (three are illustrated in the figure) memory cell set MCSs are arranged along the z-axis. Furthermore, multiple groups of memory cell set MCSs arranged along the z-axis are arranged along the y-axis. The multiple memory cells MC of each of the multiple memory cell set MCSs arranged along the z-axis are arranged along the y-axis. Thus, the memory cells MC are arranged along the x-axis, y-axis, and z-axis.

[0127] Each memory cell group (MCS) has multiple memory cells (MCs) connected to a conductor 32. The conductor 32 extends along the x-axis and z-axis. The conductor 32 functions as part of the board trace.

[0128] Each memory cell MC is connected to a conductor 35. Each conductor 35 extends along the z-axis. Multiple conductors 35, each connected to multiple memory cells MC of each memory cell group MCS, are arranged along the x-axis. Multiple memory cells MC arranged along the z-axis are connected to a single conductor 35. Each conductor 35 functions as part of a bit line BL.

[0129] Each conductor 31 is connected at one end to one end of a switch SW1. The switch SW1 is, for example, an n-type MOSFET. Figure 12 Based on this example, multiple switches SW1, each connected to a group of memory cells (MCS) arranged along the z-axis, are arranged along the z-axis.

[0130] Each conductor 31 is connected at its other end to one end of a switch SW2. The switch SW2 is, for example, an n-type MOSFET. Figure 12 Based on this example, multiple switches SW2, each connected to a group of memory cells (MCS) arranged along the z-axis, are also arranged along the z-axis.

[0131] Each conductor 35 is connected to one end of a switch SW3. Switch SW3 is, for example, an n-type MOSFET. Figure 12 The following description is based on this example. Multiple switches SW3, each connected to a plurality of conductors 35 arranged along the x-axis, are arranged along the x-axis. The switches SW3 are located between the memory cell array MA and the conductors 23. Each of the multiple switches SW3 arranged along the x-axis is connected to a conductor 42 at its respective control terminal (or gate).

[0132] Each conductor 42 is connected at one end to one end of a switch SW4. The switch SW4 is, for example, an n-type MOSFET. Figure 12 Based on this example, each switch SW4 is located below a plurality of switches SW1 arranged along the z-axis; that is, the plurality of switches SW1 and one switch SW4 are arranged along the z-axis. The other end of each of the plurality of switches SW1 and one switch SW4 arranged along the z-axis is connected to a conductor 45. Each conductor 45 extends along the z-axis.

[0133] Each conductor 42 is connected at its other end to one end of a switch SW5. Switch SW5 is, for example, an n-type MOSFET. Figure 12 Based on this example, each switch SW5 is located below a plurality of switches SW2 arranged along the z-axis; that is, the plurality of switches SW2 and one switch SW5 are arranged along the z-axis. The other end of each of the plurality of switches SW2 and one switch SW5 arranged along the z-axis is connected to a conductor 46. Each conductor 46 extends along the z-axis.

[0134] Each switch SW3 is connected to a conductor 51 at its other end. Each conductor 51 extends along the z-axis. Each conductor 51 functions as part of a bit line BL. Each conductor 51 is connected at its lower surface to the upper surface of a conductor 23. Thus, each global bit line GBL, which is part of a conductor 22 and a conductor 23, is connected to multiple bit lines BL, which are part of conductors 51.

[0135] in the case of Figure 12 With this configuration, even if the area of ​​the sensing amplifier circuit SAC in the first embodiment is at least larger than that of the reference sensing amplifier circuit 200, the area of ​​the storage device 1 does not need to be larger than that of the reference storage device 100 to be configured with the sensing amplifier circuit SAC.

[0136] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as set forth in the patent claims and its equivalents.

Claims

1. A storage device comprising: Capacitor; The first transistor is connected to the capacitor at its first terminal; The first inverter circuit is connected between the first node and the second node, and includes a p-type second transistor and an n-type third transistor connected in series at the third node; The second inverter circuit is connected between the first node and the second node, and includes a p-type fourth transistor and an n-type fifth transistor connected in series at the fourth node, with the gate of the fourth transistor and the gate of the fifth transistor connected to the second terminal of the first transistor. The sixth transistor is connected between the gate of the fourth transistor and the third node, and between the gate of the fifth transistor and the third node; The 7th transistor is connected between the gate of the 2nd transistor and the 4th node, and between the gate of the 3rd transistor and the 4th node; The 8th transistor is connected between the gate of the 2nd transistor and the 3rd node; as well as The 9th transistor is connected between the gate of the 4th transistor and the 4th node.

2. The apparatus according to claim 1, further comprising: The 10th transistor is connected between the gate of the 3rd transistor and the 3rd node; and The 11th transistor is connected between the gate of the 5th transistor and the 4th node.

3. The apparatus according to claim 2, further comprising: The 12th transistor of type n is connected between the gate of the 4th transistor and the 3rd node, and between the gate of the 5th transistor and the 3rd node; and The n-type 13th transistor is connected between the gate of the 2nd transistor and the 4th node, and between the gate of the 3rd transistor and the 4th node. The 6th and 7th transistors are p-type.

4. The apparatus according to claim 3, wherein, The 8th and 9th transistors are p-type. The 10th transistor and the 11th transistor are n-type.

5. The apparatus according to claim 1, wherein, The gates of the 6th transistor and the 7th transistor receive the first signal. The gates of the 8th transistor and the 9th transistor receive the second signal. Invalidate the first signal throughout the first period. The second signal is made valid throughout the first period.

6. The apparatus according to claim 5, wherein, Throughout the first period, a first voltage is applied to the first node, and a second voltage is applied to the second node. The second voltage is lower than the first voltage.

7. The apparatus according to claim 6, wherein, The gate of the first transistor receives the third signal. The third signal is made valid during the second period following the first period.

8. The apparatus according to claim 7, wherein, During the second period, the second signal is invalidated.

9. The apparatus according to claim 8, wherein, During the second period, the first signal is invalidated.

10. The apparatus according to claim 9, wherein, During the third period following the second period, the second signal is invalidated. During the third period, the first signal is made valid.

11. The apparatus according to claim 10, wherein, The gate of the fourth transistor and the gate of the fifth transistor are connected to the first bit line. The gate of the second transistor and the gate of the third transistor are connected to the second bit line. During the fourth period preceding the first period, the first voltage is applied to the first node, and the second voltage is applied to the second node.

12. The apparatus according to claim 11, wherein, During the fifth period, between the fourth period and the first period, the first bit line and the second bit line are connected, a third voltage lower than the first voltage is applied to the first node, and a fourth voltage higher than the second voltage is applied to the second node.

13. The apparatus according to claim 9, further comprising: The 10th transistor is connected between the gate of the 3rd transistor and the 3rd node; and The 11th transistor is connected between the gate of the 5th transistor and the 4th node.

14. The apparatus according to claim 13, further comprising: The 12th transistor of type n is connected between the gate of the 4th transistor and the 3rd node, and between the gate of the 5th transistor and the 3rd node; and The 13th transistor of type n is connected between the gate of the 2nd transistor and the 4th node, and between the gate of the 3rd transistor and the 4th node. The sixth and seventh transistors are p-type.

15. The apparatus according to claim 14, wherein, The 8th and 9th transistors are p-type. The 10th transistor and the 11th transistor are n-type.

16. The apparatus according to claim 15, wherein, The gates of the 12th transistor and the 13th transistor receive the 4th signal. The gate of the 10th transistor and the gate of the 11th transistor receive the 5th signal. The fourth signal is disabled throughout the first period. The fifth signal is made valid throughout the first period.

17. The apparatus according to claim 16, wherein, The fifth signal is invalidated during the second period.

18. The apparatus according to claim 17, wherein, The fourth signal is invalidated during the second period.

19. The apparatus according to claim 18, wherein, During the third period following the second period, the fifth signal is invalidated. The fourth signal is made valid during the third period.

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