Method of determining bit state of bits stored in a memory circuit and memory circuit

Abstract

A method of determining a bit state of a bit stored in a memory circuit and a memory circuit are disclosed. In some embodiments, the memory circuit includes a storage cell configured to store a bit. A reference line is configured to receive a reference signal and a data line is configured to receive a data signal. The data line is configured to selectively couple to the storage cell. A charge voltage selection unit is configured to charge the reference line and the data line in response to a select signal being in a first select state and to discharge the reference line and the data line in response to the select signal being in a second select state. A sense amplifier is configured to compare the data signal to the reference signal to sense the bit state of the bit stored by the storage cell.

Description

Technical Field Background Technology

[0001] Magnetic random-access memory (MRAM) devices are memory devices that use spin torque transfer to change the resistance state between a high-resistance state and a low-resistance state. The advantage of MRAM is that it retains stored data even without electricity. Generally, MRAM consists of multiple memory cells in an array. Each cell typically stores one bit of data. Advantages of using MRAM include smaller cell size, fewer process steps compared to other technologies used for reading and writing memory cells, and scalability to large arrays. However, a disadvantage of MRAM is the amount of energy consumed when reading a memory cell. Summary of the Invention Attached Figure Description

[0002] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0003] Figure 1 This is a block diagram of a memory circuit according to some embodiments.

[0004] Figure 2 This is a block diagram of a memory circuit according to some embodiments.

[0005] Figure 3 It is a voltage diagram describing the operation of the memory circuit.

[0006] Figure 4 This is a circuit diagram of a charging voltage selection unit according to some embodiments.

[0007] Figure 5 This is a block diagram of a voltage sense amplifier (VSA) according to some embodiments.

[0008] Figure 6 This is a block diagram of a timing control circuit according to some embodiments.

[0009] Figure 7 This is a circuit diagram of a VSA according to some embodiments.

[0010] Figure 8 This is a flowchart of a method for determining the bit state of a bit stored in a memory circuit according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are expected to exist. For example, in the following description, forming a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. In addition to the orientations depicted in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0013] This disclosure describes a system and method for reading the bit state of a memory cell in a memory array. While this disclosure is applicable to other types of memory cells, it is particularly applicable to circuitry for reading the bit state of a resistive memory cell. In some embodiments, the memory circuitry includes a charging voltage selection unit that charges a data line connected to a selected memory cell with a first reference voltage and discharges the data line connected to the selected memory cell with a second reference voltage. A sensing amplifier is configured to sense the resistance state of the selected memory cell during both the charging and discharging of the data line. By sensing the bit state stored in the memory cell during both the charging and discharging of the data line, the energy consumed by the memory circuitry is reduced. In some embodiments, the energy consumption of a memory circuitry that reads the bit state during both the charging and discharging of the data line is reduced by up to 40% compared to a memory circuitry that reads the bit state only during the discharging of the data line.

[0014] Figure 1 This is a block diagram of a memory circuit 100 according to some embodiments.

[0015] The memory circuit 100 includes a memory array of memory cells 102. Each memory cell 102 stores a bit that is in a first state or a second state. Figure 1 In this context, each of the storage cells 102 is a magnetoresistive random access memory (MRAM) cell. MRAM is a non-volatile memory technology that uses magnetic elements. For example, a spin transfer torque magnetoresistive random access memory (STT-MRAM) cell uses electrons that become spin-polarized when they pass through a thin film (spin filter). STT-MRAM cells are also called spin transfer torque random access memory (STT-RAM) cells, spin torque transfer magnetization switching RAM (Spin-RAM) cells, and spin momentum transfer RAM (SMT-RAM) cells.

[0016] Each of the memory cells 102 includes a magnetic tunnel junction (MTJ) memory element. In some embodiments, the MTJ memory element is formed of at least two ferromagnetic layers (pinned and free layers) separated by a thin, nonmagnetic insulating layer (tunnel barrier), each of the ferromagnetic layers maintaining a magnetic field or polarization. Due to the tunneling effect under a bias voltage applied to the ferromagnetic layers, electrons from the two ferromagnetic layers can penetrate the tunnel barrier. The magnetic polarization of the free layer can be reversed so that the polarities of the pinned and free layers are substantially aligned (parallel) or opposite (antiparallel). The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variation in resistance can be used to program and read the memory cell. For example, in some embodiments, the memory cell is in a low-resistance state when the polarities of the pinned and free layers are parallel. In some embodiments, the memory cell is in a high-resistance state when the polarities of the pinned and free layers are antiparallel.

[0017] In some embodiments, during a read operation, the resistance of the MTJ element in memory cell 102 is represented as current or voltage. A current or voltage signal is applied to a bit line connected to the MTJ element. To select a specific bit line and thus a specific one of memory cells 102, memory circuitry 100 includes a multiplexer 104. In some embodiments, multiplexer 104 receives an address input and decodes the address input to select a bit line (and thus a one of memory cells 102). In some embodiments, the voltage has a voltage level that varies with resistance. A voltage is generated to charge the bit line and discharge the bit line of the selected memory cell 102, as described in further detail below. The voltage is input to a bidirectional voltage sense amplifier (VSA) 106. The bidirectional VSA 106 is configured to read the bit value of the selected memory cell 102 during both the charging and discharging phases of the bit line.

[0018] To properly read the stored bit value based on the (high or low) resistance state of the MTJ memory element in memory cell 102, appropriate reference voltages REF[2n] and REF[2n+1] are input to VSA 106. In some embodiments, reference voltage REF[2n] is input to VSA 106. In some embodiments, reference voltage REF[2n+1] is input to VSA 106. The voltage generated on the bit line is compared with one of the reference voltages REF[2n] and REF[2n+1] to distinguish the high resistance state and low resistance state of the selected MTJ memory element. The relatively high resistance state and the relatively low resistance state of the MTJ correspond to the logic 'zero' or logic 'one' binary value of the selected memory cell 102.

[0019] exist Figure 1 In this embodiment, dummy memory cell 108 is configured to generate a reference voltage REF[2n+1]. In some embodiments, dummy memory cell 108 has an MTJ memory element whose resistance is the average of the high-resistance and low-resistance states of the MTJ memory element of memory cell 102 (i.e., (RH+RL) / 2). Thus, the reference voltage REF[2n+1] is used as a reference for distinguishing between the high-resistance and low-resistance states of the MTJ of memory cell 102. In addition to the average value, other types of dummy reference MTJs or other elements provide different parameter values ​​known to fall at the midpoint, such as a parallel resistance value with an additional series resistance.

[0020] exist Figure 1In this embodiment, dummy memory cell 110 is configured to generate a reference voltage REF[2n]. In some embodiments, dummy memory cell 110 has an MTJ, the resistance of which is the average of the high resistance state and the low resistance state of the MTJ of memory cell 102 (i.e., (RH+RL) / 2). Thus, the reference voltage REF[2n] is used as a reference for distinguishing between the high resistance state and the low resistance state of the MTJ of memory cell 102.

[0021] In some embodiments, dummy memory cells 108 and dummy memory cells 110 have different resistance values ​​known to fall at the midpoint, such as parallel resistance values ​​with additional series resistance. Dummy memory cells 108 and dummy memory cells 110 are manufactured using the same process as memory cells 102 whose resistance states will be identified (e.g., located on the same circuit chip), and are therefore similarly affected by process variations in dummy memory cells 108 and dummy memory cells 110.

[0022] Figure 2 This is a block diagram of a memory circuit 200 according to some embodiments.

[0023] The memory circuit 200 includes a memory sub-circuit 201E and a memory sub-circuit 201O. The memory sub-circuit 201E and... Figure 1 This corresponds to memory circuit 100. Memory sub-circuit 201O also corresponds to... Figure 1 The memory circuit 100 corresponds to this. In some embodiments, the memory sub-circuit 201E is referred to as an even-numbered circuit, while the memory sub-circuit 201O is referred to as an odd-numbered circuit.

[0024] The memory sub-circuit 201E includes a memory array of memory cells 202E. The memory array of memory cells 202E is connected to... Figure 1 The memory array corresponds to the memory cell 102. In some embodiments, each of the memory cells 202E includes an MTJ. The MTJ is configured to have a variable resistance that can switch between a high resistance state and a low resistance state.

[0025] The array of memory cells 202E is arranged such that bit lines BL[31:0] and select lines SL[15:0] intersect with memory cells 202E in the grid array. The rows of memory cells 202E are each connected to different select lines SL[15:0] and the columns of memory cells are connected to different one or different pairs of bit lines BL[31:0].

[0026] The memory sub-circuit 201E includes a multiplexer 204E. The multiplexer 204E is connected to bit lines BL[31:0] and select lines SL[15:0]. To select a specific memory cell 202E, the multiplexer 204E is configured to select select lines SL[15:0] and bit lines BL[31:0]. The selected select line SL[15:0] is selectively coupled to data select lines DSL[2n] via the multiplexer 204E. The selected bit line BL[31:0] is selectively coupled to data bit lines DBL[2n]. Select line control signals on the selected select line SL[15:0] (e.g., as shown in the following reference) Figure 3 The selected line control signal (SL control) opens and closes the discharge path of the selected data bit line BL[31:0] and the selected memory cell 202E. When the selected line control signal is in the non-selected state, the charging and discharging paths are disabled, so the selected bit line BL[31:0] and the selected memory cell 202E will not reach the rail voltage (e.g., the first reference voltage Vread or the second reference voltage 0V). When the selected line control signal is in the selected state, the charging and discharging paths are enabled, so the selected bit line BL[31:0] and the selected memory cell 202E reach the rail voltage (e.g., the first reference voltage Vread or the second reference voltage 0V).

[0027] Data bit line DBL[2n] is connected to the input of VSA 206E, which corresponds to VSA 106 described above. Therefore, the selected bit lines BL[31:0] are selectively coupled to VSA 206E as inputs by multiplexer 204E. Data selection line DSL[2n] is connected to the output of charging voltage selection unit 205E. Therefore, data selection line DSL[2n] is coupled to data bit line DBL[2n] via the selected memory cell 202E and the selected bit lines BL[31:0]. Charging voltage selection unit 205E is configured to receive a first reference voltage (voltage Vread in this embodiment), a second reference voltage (ground voltage 0V in this embodiment), and a selection signal Sel_even as inputs. The selection signal Sel_even is a clock signal oscillating between a first selection state and a second selection state. In some embodiments, the selection signal Sel_even has a 50% duty cycle. The charging voltage selection unit 205E is configured to apply a first reference voltage Vread to the selected memory cell 202E, the selected bit line BL[31:0], and the data bit line DBL[2n] in response to the selection signal Sel_even being in a first selection state, and to apply a second reference voltage 0V to the selected memory cell 202E, the selected data bit line BL[31:0], and the data bit line DBL[2n] in response to the selection signal Sel_even being in a second selection state.

[0028] In some embodiments, the first reference voltage Vread has a direct current (DC) voltage level. The DC voltage level is constant or nearly constant (i.e., constant within an acceptable error range). In some embodiments, the DC voltage level of Vread is, for example, the DC voltage level of a DC power supply voltage such as VDD, or is proportional to the DC voltage level of a DC power supply voltage such as VDD. In some embodiments, the DC voltage level of the first reference voltage Vread is positive. In some embodiments, the second reference voltage has a DC voltage level of 0V. In some embodiments, the second reference voltage is ground. In some embodiments, the second reference voltage has a positive or negative DC voltage level. The first reference voltage has a voltage level greater than the voltage level of the second reference voltage.

[0029] The reference line REF[2n] is connected as an input to VSA 206E. VSA 206E is configured to compare the voltage applied to the reference line REF[2n] with the voltage applied to the data bit line DBL[2n] to determine whether the selected memory cell 202E is in a high-resistance state or a low-resistance state. The voltage output by the charging voltage selection unit 205E also charges and discharges the reference line REF[2n]. When the charging voltage selection unit 205E selects the first reference voltage Vread, the reference line REF[2n] is charged, and when the charging voltage selection unit 205E selects the second reference voltage 0V, the reference line REF[2n] is discharged.

[0030] When the reference line REF[2n] and data bit line DBL[2n] are being charged by the first reference voltage Vread and the selected memory cell 202E is in a high-resistance state, the data bit line DBL[2n] charges slower than the reference line REF[2n]. In this case, VSA 206E initially reads logic 0, but then inverts logic 0 to logic 1. VSA 206E is configured to invert the logic state in response to the selection signal Sel_even being in the first selection state. Therefore, VSA 206E generates an output voltage DOUT[2n] in the high-voltage state, which corresponds to logic 1 in this embodiment.

[0031] When the reference line REF[2n] and data bit line DBL[2n] are being charged by the first reference voltage Vread and the selected memory cell 202E is in a high-resistance state, the data bit line DBL[2n] charges faster than the reference line REF[2n]. In this case, VSA 206E initially reads logic 1, but then inverts logic 1 to logic 0. VSA 206E is configured to invert the logic state in response to the selection signal Sel_even being in the first selection state. Therefore, VSA 206E generates an output voltage DOUT[2n] in a low-voltage state, which in this embodiment corresponds to logic 0.

[0032] When the reference line REF[2n] and data bit line DBL[2n] are discharging from the second reference voltage 0V and the selected memory cell 202E is in a high-resistance state, the data bit line DBL[2n] discharges slower than the reference line REF[2n]. In this case, the VSA 206E reads logic 1 and does not invert logic 1. The VSA 206E is configured not to invert the logic state in response to the selection signal Sel_even being in the second selection state. Therefore, the VSA 206E generates an output voltage DOUT[2n] in a high-voltage state, which corresponds to logic 1 in this embodiment.

[0033] When the reference line REF[2n] and data bit line DBL[2n] are being discharged by the second reference voltage 0V and the selected memory cell 202E is in a low-resistance state, the data bit line DBL[2n] discharges faster than the reference line REF[2n]. In this case, the VSA 206E reads logic 0 and does not invert logic 0. The VSA 206E is configured not to invert the logic state in response to the selection signal Sel_even being in the second selection state. Therefore, the VSA 206E generates an output voltage DOUT[2n] in a low-voltage state, which corresponds to logic 0 in this embodiment.

[0034] The memory sub-circuit 201O includes a memory array of memory cells 202O. The memory array of memory cells 202O is connected to... Figure 1 The memory cell 102 corresponds to the memory array. In some embodiments, each of the memory cells 202O includes an MTJ. The MTJ is configured to have a variable resistance that can switch between a high resistance state and a low resistance state.

[0035] The array of memory cells 202O is arranged such that bit lines BL[63:32] and select lines SL[31:16] intersect with memory cells 202O in the grid array. The rows of memory cells 202O are each connected to different select lines SL[31:16] and the columns of memory cells are connected to different one or different pairs of bit lines BL[63:32].

[0036] The memory sub-circuit 201O includes a multiplexer 204O. The multiplexer 204O is connected to bit lines BL [63:32] and select lines SL [31:16]. To select a specific memory cell 202O, the multiplexer 204O is configured to select select lines SL [31:16] and bit lines BL [63:32]. The selected select line SL [31:16] is selectively coupled to data select line DSL [2n+1] via the multiplexer 204O. The selected bit line BL [63:32] is selectively coupled to data bit line DBL [2n+1]. When the select line control signal is in a non-selected state, the charging and discharging paths are disabled, therefore the selected bit line BL [63:32] and the selected memory cell 202E will not reach the rail voltage (e.g., the first reference voltage Vread or the second reference voltage 0V). When the select line control signal is in the select state, the charging path and the discharging path are enabled, so the selected bit line BL[63:32] and the selected memory cell 202E reach the rail voltage (e.g., the first reference voltage Vread or the second reference voltage 0V).

[0037] Data bit line DBL[2n+1] is connected to the input in VSA 206O corresponding to VSA 106 described above. Therefore, the selected bit line BL[63:32] is selectively coupled to VSA 206O as an input by multiplexer 204O. Data selection line DSL[2n+1] is connected to the output of charging voltage selection unit 205O. Therefore, data selection line DSL[2n+1] is coupled to data bit line DBL[2n+1] via selected memory cell 202O and selected bit line BL[63:32]. Charging voltage selection unit 205O is configured to receive a first reference voltage (voltage Vread in this embodiment), a second reference voltage (ground voltage 0V in this embodiment), and a selection signal Sel_odd as inputs. The selection signal Sel_odd is a clock signal oscillating between a first selection state and a second selection state. In some embodiments, the selection signal Sel_odd has a 50% duty cycle. The charging voltage selection unit 205O is configured to apply a first reference voltage Vread to the selected memory cell 202O, the selected bit line BL[63:32], and the data bit line DBL[2n+1] in response to the selection signal Sel_even being in a first selection state, and to apply a second reference voltage 0V to the selected memory cell 202O, the selected bit line BL[63:32], and the data bit line DBL[2n+1] in response to the selection signal Sel_odd being in a second selection state.

[0038] In some embodiments, the selection signal Sel_odd and the selection signal Sel_even are identical except that they have a 180-degree phase difference. Therefore, when the selection signal Sel_even is in the first selection state, the selection signal Sel_odd is in the second selection state, and when the selection signal Sel_even is in the second selection state, the selection signal Sel_odd is in the first selection state. Thus, when the charging voltage selection unit 205O discharges the selected memory cell 202O, the selected bit line BL[63:32], and the data bit line DBL[2n+1] with the second reference voltage 0V, the charging voltage selection unit 205E charges the selected memory cell 202E, the selected bit line BL[31:0], and the data bit line DBL[2n] with the first reference voltage Vread. When the charging voltage selection unit 205O charges the selected memory cell 202O, the selected bit line BL[63:32], and the data bit line DBL[2n+1] with the first reference voltage Vread, the charging voltage selection unit 205E discharges the selected memory cell 202E, the selected bit line BL[31:0], and the data bit line DBL[2n] with the second reference voltage 0V.

[0039] The reference line REF[2n+1] is connected as an input to VSA 206O. VSA 206O is configured to compare the voltage applied to the reference line REF[2n+1] with the voltage applied to the data bit line DBL[2n+1] to determine whether the selected memory cell 202O is in a high-resistance state or a low-resistance state. The voltage output by the charging voltage selection unit 205E also charges and discharges the reference line REF[2n+1]. When the charging voltage selection unit 205E selects the first reference voltage Vread, the reference line REF[2n+1] is charged, and when the charging voltage selection unit 205E selects the second reference voltage 0V, the reference line REF[2n+1] is discharged.

[0040] When the reference line REF[2n+1] and data bit line DBL[2n+1] are being charged by the first reference voltage Vread and the selected memory cell 202O is in a high-resistance state, the data bit line DBL[2n+1] charges slower than the reference line REF[2n+1]. In this case, VSA 206O initially reads logic 0, but then inverts logic 0 to logic 1. VSA 206O is configured to invert the logic state in response to the selection signal Sel_odd being in the first selection state. Therefore, VSA 206O generates an output voltage DOUT[2n+1] in a high-voltage state, which corresponds to logic 1 in this embodiment.

[0041] When the reference line REF[2n+1] and data bit line DBL[2n+1] are being charged by the first reference voltage Vread and the selected memory cell 202O is in a high-resistance state, the data bit line DBL[2n+1] charges faster than the reference line REF[2n+1]. In this case, VSA 206O initially reads logic 1, but then inverts logic 1 to logic 0. VSA 206O is configured to invert the logic state in response to the selection signal Sel_odd being in the first selection state. Therefore, VSA 206O generates an output voltage DOUT[2n+1] in a low-voltage state, which in this embodiment corresponds to logic 0.

[0042] When the reference line REF[2n+1] and data bit line DBL[2n+1] are discharging from the second reference voltage 0V and the selected memory cell 202O is in a high-resistance state, the data bit line DBL[2n+1] discharges slower than the reference line REF[2n+1]. In this case, VSA 206O reads logic 1 and does not invert logic 1. VSA 206O is configured not to invert the logic state in response to the selection signal Sel_odd being in the second selection state. Therefore, VSA 206O generates an output voltage DOUT[2n+1] in a high-voltage state, which corresponds to logic 1 in this embodiment.

[0043] When the reference line REF[2n+1] and the data bit line DBL[2n+1] are being discharged by the second reference voltage 0V and the selected memory cell 202O is in a low-resistance state, the data bit line DBL[2n+1] discharges faster than the reference line REF[2n+1]. In this case, VSA 206O reads logic 0 and does not invert logic 0. VSA 206O is configured not to invert the logic state in response to the selection signal Sel_odd being in the second selection state. Therefore, VSA 206O generates an output voltage DOUT[2n+1] in a low-voltage state, which corresponds to logic 0 in this embodiment.

[0044] The memory circuit 200 includes a timing control circuit 210. The timing control circuit 210 is configured to generate a selection signal Sel_even and a selection signal Sel_odd based on a clock signal CLK. The timing control circuit 210 is configured to receive a start signal Initial, which is configured to start the selection signal Sel_even in a first selection state and the selection signal Sel_odd in a second selection state. After starting the selection signals Sel_even and Sel_odd, the selection signals Sel_even and Sel_odd switch between the first and second selection states according to the clock signal CLK. In some embodiments, the selection signals Sel_odd and Sel_even are identical except that they have a 180-degree phase difference. Therefore, when the selection signal Sel_even is in the first selection state, the selection signal Sel_odd is in the second selection state, and when the selection signal Sel_even is in the second selection state, the selection signal Sel_odd is in the first selection state. Therefore, when the charging voltage selection unit 205O discharges the selected memory cell 202O, the selected bit line BL[63:32], the reference line REF[2n+1], and the data bit line DBL[2n+1] with the second reference voltage 0V, the charging voltage selection unit 205E charges the selected memory cell 202E, the selected bit line BL[31:0], the reference line REF[2n], and the data bit line DBL[2n] with the first reference voltage Vread. When the charging voltage selection unit 205O charges the selected memory cell 202O, the selected bit line BL[63:32], the reference line REF[2n+1], and the data bit line DBL[2n+1] with the first reference voltage Vread, the charging voltage selection unit 205E discharges the selected memory cell 202E, the selected bit line BL[31:0], the reference line REF[2n], and the data bit line DBL[2n] with the second reference voltage 0V.

[0045] Figure 3 This is a voltage diagram 300 describing the operation of memory circuit 200.

[0046] Voltage diagram 300 defines three time periods, including an initial period 302 from time ti to time ts1, a sensing period 304 from time ts1 to time ts2, and a sensing period 306 from time ts2 to time ts3.

[0047] The initial cycle 302 occurs during the start of the memory circuit 200. At time ti, the clock signal CLK and word line signal WL switch from a second clock state (e.g., a low-voltage clock state) to a first clock state (e.g., a high-voltage clock state). In response, the timing control circuit 210 generates a selection signal Sel_even, causing the selection signal Sel_even to switch from the first selection state (e.g., a high-voltage state) to a second selection state (e.g., a low-voltage state). The selection signal Sel_even remains in the second selection state throughout the initial cycle 302. Furthermore, in response, the timing control circuit 210 generates a selection signal Sel_odd, causing the selection signal Sel_even to switch from the second selection state to the first selection state. The selection signal Sel_odd remains in the first selection state throughout the initial cycle 302. Additionally, in response, the start signal Initial switches from a non-start state (e.g., a low-voltage state) to a start state (e.g., a high-voltage state) at time ti. The sense enable signal SAEN remains in a disabled state (e.g., a low-voltage state) throughout the initial cycle 302. The selection line control signal SLcontrol also remains in a non-selection state (e.g., high voltage state) throughout the entire initial cycle 302.

[0048] At time ti, the data bit line DBL[2n] and the reference line REF[2n] discharge from the first reference voltage Vread to the second reference voltage 0V. The data bit line DBL[2n+1] and the reference line REF[2n+1] maintain the first reference voltage Vread throughout the entire initial cycle 302. At time tie, the start signal Initial switches from the start state to the non-start state. At time tec, the clock signal CLK and the word line signal WL switch from the first clock state to the second clock state. The initial cycle 302 ends at time ts1 and the sensing cycle 304 begins at time ts1.

[0049] At time ts1, the clock signal CLK and word line signal WL switch from the second clock state to the first clock state. In response, the timing control circuit 210 is configured to switch the selection signal Sel_even from the second selection state to the first selection state and the selection signal Sel_odd from the first selection state to the second selection state. Furthermore, in response, the charging voltage selection unit 205E is configured to apply a first reference voltage Vread to charge the data bit line DBL[2n] and the reference line REF[2n]. Therefore, the sensing period 304 is the charging period of the memory sub-circuit 201E. Additionally, in response, the charging voltage selection unit 205O is configured to apply a second reference voltage 0V to charge the data bit line DBL[2n+1] and the reference line REF[2n+1]. Therefore, the sensing period 304 is the discharging period of the memory sub-circuit 201O.

[0050] At time tss1, the sensing enable signal SAEN switches from the disabled state to the enabled state. In response, the selection line control signal SL control switches from the selected state to the deselected state. In response, VSA 206E is configured to compare the data bit voltage on the data bit line DBL[2n] with the reference voltage on the reference line REF[2n] to generate an output voltage DOUT[2n] in a high voltage state or a low voltage state based on the comparison. Since the selected selection line SL[15:0] is in the deselected state, neither the data bit line DBL[2n] nor the reference line REF[2n] reaches the rail voltage (e.g., the first reference voltage Vread). Furthermore, in response, VSA 206O is configured to compare the data bit voltage on the data bit line DBL[2n+1] with the reference voltage on the reference line REF[2n] to generate an output voltage DOUT[2n+1] in a high voltage state or a low voltage state based on the comparison. Since the selected selection lines SL[31:16] are in the non-selected state, neither the data bit line DBL[2n+1] nor the reference line REF[2n+1] reaches the rail voltage (e.g., the second reference voltage 0V). At time tse1, the sense enable signal SAEN switches from the enabled state to the disabled state.

[0051] At time tsc1, the clock signal CLK and word line signal WL switch from the first clock state to the second clock state, wherein the clock signal CLK and word line signal WL remain unchanged for the remainder of the sensing period 304. In response, the select line control signal SL control switches from the non-selected state to the selected state. As a result, both the data bit line DBL[2n] and the reference line REF[2n] reach the rail voltage (e.g., the first reference voltage Vread). As a result, both the data bit line DBL[2n+1] and the reference line REF[2n+1] reach the rail voltage (e.g., the second reference voltage 0V). The sensing period 304 ends at time ts2 and the sensing period 306 begins at time ts2.

[0052] At time ts2, the clock signal CLK and word line signal WL switch from the second clock state to the first clock state. In response, the timing control circuit 210 is configured to switch the selection signal Sel_even from the first selection state to the second selection state and the selection signal Sel_odd from the second selection state to the first selection state. Furthermore, in response, the charging voltage selection unit 205E is configured to apply a second reference voltage 0V to discharge the data bit line DBL[2n] and the reference line REF[2n]. Therefore, the sensing period 306 is the discharge period of the memory sub-circuit 201E. Additionally, in response, the charging voltage selection unit 205O is configured to apply a first reference voltage Vread to charge the data bit line DBL[2n+1] and the reference line REF[2n+1]. Therefore, the sensing period 306 is the charging period of the memory sub-circuit 201O.

[0053] At time tss2, the sensing enable signal SAEN switches from the disabled state to the enabled state. In response, the selection line control signal SL control switches from the selected state to the deselected state. In response, VSA 206E is configured to compare the data bit voltage on the data bit line DBL[2n] with the reference voltage on the reference line REF[2n] to generate an output voltage DOUT[2n] in a high voltage state or a low voltage state based on the comparison. Since the selected selection line SL[15:0] is in the deselected state, neither the data bit line DBL[2n] nor the reference line REF[2n] reaches the rail voltage (e.g., the second reference voltage 0V). Furthermore, in response, VSA 206O is configured to compare the data bit voltage on the data bit line DBL[2n+1] with the reference voltage on the reference line REF[2n] to generate an output voltage DOUT[2n+1] in a high voltage state or a low voltage state based on the comparison. Since the selected selection lines SL[31:16] are in the non-selected state, neither the data bit line DBL[2n+1] nor the reference line REF[2n+1] reaches the rail voltage (e.g., the first reference voltage Vread). At time tse2, the sense enable signal SAEN switches from the enabled state to the disabled state.

[0054] At time tsc2, the clock signal CLK and word line signal WL switch from the first clock state to the second clock state, wherein the clock signal CLK and word line signal WL remain unchanged for the remainder of the sensing period 306. In response, the select line control signal switches from the non-select state to the select state. As a result, both the data bit line DBL[2n] and the reference line REF[2n] reach the rail voltage (e.g., the second reference voltage 0V). As a result, both the data bit line DBL[2n+1] and the reference line REF[2n+1] reach the rail voltage (e.g., the first reference voltage Vread). Furthermore, in response, VSA 206E becomes opaque.

[0055] The sensing cycle 304 is then repeated, followed by the sensing cycle 306. This repetition of sensing cycles 304 and 306 continues until the memory read cycle is interrupted. When the memory circuit 200 is restarted, the initial cycle 302 is executed, followed by the repetition sequence of sensing cycles 304 and 306, until the memory read cycle is interrupted again.

[0056] Figure 4 This is a circuit diagram of a charging voltage selection unit 400 according to some embodiments.

[0057] In some embodiments, the charging voltage selection unit 400 is Figure 2An example of a charging voltage selection unit 205E. In some embodiments, the charging voltage selection unit 400 is... Figure 2 An example of a charging voltage selection unit 205O.

[0058] The charging voltage selection circuit 400 includes an inverter 402. The input terminal of the inverter 402 is configured to receive a selection signal Sel Gen. In some embodiments, the selection signal Sel Gen is... Figure 2 The selection signal Sel_even. In some embodiments, the selection signal Sel_even is... Figure 2 The selection signal Sel_odd is used. Inverter 402 is configured to generate an inverted selection signal Sel Genb from the output terminal.

[0059] The charging voltage selection circuit 400 also includes two field-effect transistors (FETs) 404 and 406. Figure 2 In this configuration, each of FET 404 and FET 406 is an N-type FET. In some embodiments, one or more of FET 404 and FET 406 are P-type FETs.

[0060] The gate of FET 404 is configured to receive a select signal Sel Gen, and the gate of FET 406 is configured to receive an inverting select signal Sel Genb. One of the drain / source terminals of FET 404 is connected to one of the drain / source terminals of FET 406. The connected drain / source terminals of FET 404 and FET 406 are each connected to a data select line DSL. In some embodiments, the data select line DSL is... Figure 2 The data selection line DSL[2n]. In some embodiments, the data selection line DSL is Figure 2 The data selection line in the middle is DSL[2n+1].

[0061] The other drain / source terminal of FET 404 is configured to receive a first reference voltage Vread. The other drain / source terminal of FET 406 is configured to receive a second reference voltage 0V. Thus, FET 404 is configured to be turned on and apply the first reference voltage Vread to the data select line DSL in response to the select signal Sel Gen being in the first select state, while FET 406 is configured to be turned off in response to the select signal Sel Gen being in the first select state (because the inverting select signal is in the second select state). FET 406 is configured to be turned on and apply the second reference voltage 0V to the data select line DSL in response to the select signal Sel Gen being in the second select state (because the inverting select signal is in the first select state), while FET 404 is configured to be turned off in response to the select signal Sel Gen being in the second select state.

[0062] Figure 5 This is a block diagram of the VSA 500 according to some embodiments.

[0063] In some embodiments, VSA 500 is Figure 2 An instance of VSA 206E. In some embodiments, VSA 500 is... Figure 2 An instance of VSA 206O in the dataset.

[0064] VSA 500 includes a voltage comparator 502. The voltage comparator 502 is configured to receive a bit line voltage on the data bit line DBL, a reference voltage on the reference line REF, and a sense enable signal SAEN. In some embodiments, the data bit line DBL is... Figure 2 The data bit line DBL[2n]. In some embodiments, the data bit line DBL is... Figure 2 The data bit line DBL[2n+1]. In some embodiments, the reference line REF is... Figure 2 The reference line REF[2n]. In some embodiments, the reference line REF is... Figure 2 The reference line in the reference is REF[2n+1].

[0065] In response to the sensing enable signal SAEN being in an disabled state, voltage comparator 502 is opaque. Therefore, when the sensing enable signal SAEN is in an disabled state, voltage comparator 502 is unaffected by the bit line voltage on the data bit line DBL and the reference voltage on the reference line REF.

[0066] However, voltage comparator 502 is configured to compare the bit line voltage on the data bit line DBL with the reference voltage on the reference line REF in response to the sensing enable signal SAEN being enabled. In response to a bit line voltage higher than the reference voltage, voltage comparator 502 is configured to output the sensed voltage Q in a high-voltage state. In response to a bit line voltage lower than the reference voltage, voltage comparator 502 is configured to output the sensed voltage Q in a low-voltage state.

[0067] VSA 500 includes an XOR gate 504. The XOR gate 504 is configured to receive a sensed voltage Q and a selection signal Sel Gen. The XOR gate 504 is configured to output an output voltage DOUT. In some embodiments, the output voltage DOUT is... Figure 2 The output voltage DOUT[2n]. In some embodiments, the output voltage DOUT is Figure 2 The output voltage DOUT[2n+1].

[0068] XOR gate 504 is configured to invert the sensed voltage Q in response to the selection signal being in a first selection state. Therefore, XOR gate 504 is configured to generate an output voltage DOUT in a low voltage state in response to the sensed voltage Q being in a high voltage state and the selection signal being in the first selection state. XOR gate 504 is configured to generate an output voltage DOUT in a high voltage state in response to the sensed voltage Q being in a low voltage state and the selection signal being in the first selection state.

[0069] XOR gate 504 is configured not to invert the sensed voltage Q in response to the selection signal being in the second selection state. Therefore, XOR gate 504 is configured to generate a low-voltage output voltage DOUT in response to the sensed voltage Q being in a low-voltage state and the selection signal being in the second selection state. XOR gate 504 is also configured to generate a high-voltage output voltage DOUT in response to the sensed voltage Q being in a high-voltage state and the selection signal being in the second selection state.

[0070] Figure 6 This is a block diagram of a timing control circuit 600 according to some embodiments.

[0071] In some embodiments, the timing control circuit 600 is Figure 2 An example of the timing control circuit 210 in the example.

[0072] The timing control circuit 600 includes a D-type flip-flop 602, an inverter 604, and an inverter 606. The D-type flip-flop 602 receives a start signal Initial at its enable terminal and a clock signal CLK at its clock terminal. The non-inverting output of the D-type flip-flop 602 is not connected. The inverting output of the D-type flip-flop 602 is fed back to its data terminal.

[0073] The D-type flip-flop 602 is transparent in response to a high voltage state of the clock signal CLK and opaque in response to a low voltage state of the clock signal CLK. Therefore, the Initial signal activates the D-type flip-flop 602, causing its inverted output to be in a high voltage state. Since the D-type flip-flop 602 becomes opaque once the clock signal CLK is set to a low voltage state, its inverted output remains in a high voltage state for the remainder of the initial clock cycle.

[0074] Inverter 604 has an input terminal connected to the inverted output terminal of D-type flip-flop 602 and an output terminal connected to the input terminal of inverter 606. Inverter 604 generates a selection signal Sel_even from the inverted output of D-type flip-flop 602. Inverter 606 generates a selection signal Sel_odd from the selection signal Sel_even. Since the inverted output of D-type flip-flop 602 is fed back to the data terminal of D-type flip-flop 602, the selection signals Sel_even and Sel_odd switch voltage states (i.e., from high voltage state to low voltage state or from low voltage state to high voltage state) in response to each positive clock edge of clock signal CLK. In other embodiments, timing control circuitry 600 is configured such that the selection signals Sel_even and Sel_odd switch voltage states in response to the negative clock edge of clock signal CLK.

[0075] Figure 7 This is a circuit diagram of the VSA 700 according to some embodiments.

[0076] In some embodiments, VSA 700 is Figure 2 An example of VSA 206E. In some embodiments, VSA 700 is... Figure 2 An example of VSA 206O. In some embodiments, VSA 700 is... Figure 5 An instance of VSA 500 in [the context of the system].

[0077] VSA 700 includes a voltage comparator 702. The voltage comparator 702 is configured to receive a bit line voltage on the data bit line DBL[n], a reference voltage on the reference line REF, and a sense enable signal SAEN. In some embodiments, the data bit line DBL[n] is Figure 2 The data bit line DBL[2n]. In some embodiments, the data bit line DBL[n] is... Figure 2 The data bit line DBL[2n+1]. In some embodiments, the reference line REF is... Figure 2 The reference line REF[2n]. In some embodiments, the reference line REF is... Figure 2 The reference line in the reference is REF[2n+1].

[0078] VSA 700 includes an inverter 701 configured to invert the sense enable signal SAEN and generate an inverted sense enable signal SAENB.

[0079] Voltage comparator 702 includes a P-type field-effect transistor (PFET) 704. The source of PFET 704 is configured to receive a power supply voltage VDD. The drain of PFET 704 is connected to node 705. The gate of PFET 704 is configured to receive an inverting sense enable signal SAENB.

[0080] Voltage comparator 702 also includes PFETs 706, 708, 710, and 712. The sources of PFET 706 and PFET 708 are connected to node 705. The drain of PFET 706 is connected to the source of PFET 710. The drain of PFET 708 is connected to the source of PFET 712. The source of PFET 710 is connected to node 714, and the source of PFET 712 is connected to node 716. A sense voltage Q is generated from node 716. An inverting sense voltage QB is generated from node 714. The gate of PFET 706 is connected to the data bit line DBL[n]. The gate of PFET 706 is configured to receive the data bit line voltage of data bit line DBL[n]. The gate of PFET 708 is connected to the reference line REF. The gate of PFET 708 is configured to receive the reference voltage of reference line REF.

[0081] Voltage comparator 702 includes N-type field-effect transistors (NFETs) 718, NFET 720, NFET 722, and NFET 724. The drains of NFET 718 and NFET 720 are each connected to node 714. The drains of NFET 722 and NFET 724 are each connected to node 716. The sources of NFET 718, NFET 720, NFET 722, and NFET 724 are each grounded. The gates of PFET 710 and NFET 720 are connected to node 716 and thus receive a sense voltage Q. The gates of PFET 712 and NFET 722 are connected to node 714 and thus receive an inverted sense voltage QB. The gate of NFET 718 is configured to receive the inverted sense enable signal SAENB, and the gate of NFET 724 is configured to receive the sense enable signal SAEN.

[0082] In response to the sense enable signal SAEN being disabled, voltage comparator 702 is opaque. Therefore, when the sense enable signal SAEN is disabled, voltage comparator 702 is unaffected by the bit line voltage on data bit line DBL[n] and the reference voltage on reference line REF. In response to the sense enable signal SAEN being disabled, PFET 704 is turned off, and NFETs 718 and 724 are turned off. Both the sense voltage Q and the inverting sense voltage QB are driven to a low voltage state (e.g., ground voltage).

[0083] Voltage comparator 702 is configured to compare the bit line voltage on data bit line DBL[n] with a reference voltage on reference line REF in response to the sense enable signal SAEN being enabled. In response to the sense enable signal SAEN being enabled, PFET 704 is turned on and NFETs 718 and 724 are turned off. In response to the bit line voltage on data bit line DBL[n] being higher than the reference voltage on reference voltage line REF, PFETs 708 and 712 drive the sense voltage Q to a high voltage state (e.g., at or near the supply voltage VDD). Consequently, NFET 720 is turned on, and thus drives the inverted sense voltage QB to a low voltage state (e.g., at or near ground). Alternatively, in response to the bit line voltage on data bit line DBL[n] being lower than the reference voltage on reference voltage line REF, PFETs 706 and 710 drive the sense voltage Q to a low voltage state. As a result, the NFET722 is turned on, and thus the inverting sense voltage QB is driven to a high voltage state.

[0084] VSA 700 includes an XOR gate 726. The XOR gate 726 is configured to receive a sensed voltage Q and a selection signal Sel Gen. The XOR gate 726 is configured to output an output voltage DOUT. In some embodiments, the output voltage DOUT is... Figure 2 The output voltage DOUT[2n]. In some embodiments, the output voltage DOUT is Figure 2 The output voltage DOUT[2n+1].

[0085] XOR gate 726 is configured to invert the sensed voltage Q in response to the selection signal Sel Gen being in a first selection state. Therefore, XOR gate 726 is configured to generate an output voltage DOUT in a low voltage state in response to the sensed voltage Q being in a high voltage state and the selection signal Sel Gen being in the first selection state. XOR gate 726 is configured to generate an output voltage DOUT in a high voltage state in response to the sensed voltage Q being in a low voltage state and the selection signal Sel Gen being in the first selection state.

[0086] XOR gate 726 is configured not to invert the sensed voltage Q in response to the selection signal Sel Gen being in the second selection state. Therefore, XOR gate 726 is configured to generate a low-voltage output voltage DOUT in response to the sensed voltage Q being in a low-voltage state and the selection signal Sel Gen being in the second selection state. XOR gate 726 is also configured to generate a high-voltage output voltage DOUT in response to the sensed voltage Q being in a high-voltage state and the selection signal Sel Gen being in the second selection state.

[0087] Figure 8 This is a flowchart of a method 800 for determining the bit state of a bit stored in a memory circuit according to some embodiments. Method 800 can be used with a memory circuit (e.g., as described above regarding...). Figures 1 to 7 The memory circuit 100 and memory circuit 200 discussed herein are used together.

[0088] Figure 8 The operation sequence of method 800 shown in the diagram is for illustrative purposes only; the operation of method 800 can be performed in conjunction with... Figure 8 The different sequences of execution are illustrated in the figures. In some embodiments, in addition to Figure 8 All operations other than those shown in the drawing are in Figure 8 The operations illustrated are performed before, between, during, and / or after the operations. In some embodiments, the operations of method 800 are a subset of the operations of methods for operating memory circuitry.

[0089] Method 800 includes blocks 802 to 816. The process begins at block 802.

[0090] At block 802, a first memory cell of the memory array is selected such that the first memory cell is selectively coupled to a data line. According to some embodiments, memory cell 202E of the memory array in memory sub-circuit 201E and memory cell 202O of the memory array in memory sub-circuit 201O are examples of the first memory cell of the memory array. According to some embodiments, examples of the data line are data bit line DBL[2n] and data bit line DBL[2n+1]. In some embodiments, block 802 is implemented by multiplexer 204E or multiplexer 204O. The process proceeds to block 804.

[0091] At block 804, the data line and reference line are charged. According to some embodiments, examples of the reference lines are reference line REF[2n] and reference line REF[2n+1]. In some embodiments, block 804 is implemented by charging voltage selection unit 205E or charging voltage selection unit 205O. The process proceeds to block 806.

[0092] At block 806, during the charging of the data line and reference line, the data signal on the data line is compared with a reference signal. In some embodiments, the data signal is the data voltage on data bit line DBL[2n] or data bit line DBL[2n+1]. In some embodiments, the reference signal is the reference voltage on reference line REF[2n] or reference line REF[2n+1]. The process proceeds to block 808.

[0093] At block 808, the bit state of the output bit signal is set based on a comparison between the data signal and the reference signal during the charging of the data line and reference line. According to some embodiments, output voltage DOUT[2n] and output voltage DOUT[2n+1] are examples of the output bit signal. In some embodiments, the charging of the data line and reference line and... Figure 3 The data line DBL[2n] and reference line REF[2n] during sensing cycle 304 correspond to or correspond to the data line DBL[2n+1] and reference line REF[2n+1] during sensing cycle 306. The process proceeds to block 810.

[0094] At block 810, a second memory cell of the memory array is selected such that the second memory cell is selectively coupled to a data line. According to some embodiments, memory cell 202E of the memory array in memory sub-circuit 201E and memory cell 202O of the memory array in memory sub-circuit 201O are examples of the second memory cell of the memory array. The process proceeds to block 812.

[0095] At block 812, discharge the data line and reference line. The process proceeds to block 814.

[0096] At block 814, during the discharge of the data line and reference line, the data signal on the data line is compared with the reference signal. In some embodiments, the discharge of the data line and reference line is compared with... Figure 3 The data line DBL[2n+1] and reference line REF[2n+1] during sensing cycle 304 correspond to the data line DBL[2n] and reference line REF[2n] during sensing cycle 306. The process proceeds to block 816.

[0097] At block 816, the bit state of the output bit signal is set based on the comparison between the data signal and the reference signal during the discharge of the data line and the reference line.

[0098] In some embodiments, a memory circuit includes: a memory cell configured to store bits; a reference line configured to receive a reference signal; a data line configured to receive a data signal, wherein the data line is configured to selectively couple to the memory cell; a charging voltage selection unit configured to charge the reference line and the data line in response to a selection signal being in a first selection state, and to discharge the reference line and the data line in response to a selection signal being in a second selection state; and a sensing amplifier configured to compare the data signal and the reference signal to sense the bit state of the bits stored by the memory cell. In some embodiments, the sensing amplifier is configured to receive a sensing signal oscillating between an enabled state and a disabled state; the sensing amplifier is configured to compare the data signal with the reference signal in response to the sensing signal being in an enabled state; and the sensing signal oscillates between an enabled state and a disabled state such that the sensing signal is enabled when the selection signal is in the first selection state and when the selection signal is in the second selection state. In some embodiments, the memory cell includes a magnetic tunnel junction (MTJ) memory cell. In some embodiments, the memory cell includes a resistive memory cell. In some embodiments, the memory circuit further includes: a memory array of memory cells, the memory array including memory cells; a multiplexer configured to select one memory cell in the memory array such that a data line is selectively coupled to the selected memory cell; a second memory array of second memory cells; a second reference line configured to receive a second reference signal; a second data line configured to receive a second data signal; a second multiplexer configured to select one second memory cell in the second memory array such that the second data line is selectively coupled to the selected second memory cell; a second charging voltage selection unit configured to receive a first reference voltage, a second reference voltage, and a second selection signal, wherein the charging voltage selection unit is configured to apply the first reference voltage to the second reference line and the second data line in response to the second selection signal being in a first selection state, and to apply the second reference voltage to the second data line and the second reference line in response to the second selection signal being in a second selection state; and a second sensing amplifier configured to compare the second data signal with the second reference signal, and to generate a second output bit signal having a bit state based on the comparison between the second data signal and the second reference signal. In some embodiments, the timing control circuit is configured to generate a selection signal and a second selection signal, such that when the selection signal is in a first selection state, the second selection signal is in a second selection state, and when the selection signal is in the second selection state, the second selection signal is in the first selection state. In some embodiments, the timing control circuit includes a trigger having an output bit terminal, a data input terminal, and a clock terminal configured to receive a clock signal, wherein the output bit terminal is connected to be fed back to the data input terminal.

[0099] In some embodiments, a memory circuit includes: a memory array of memory cells; a reference line configured to receive a reference voltage; a data line configured to receive a data signal; a multiplexer configured to select one memory cell in the memory array such that the data line is selectively coupled to the selected memory cell; a charging voltage selection unit configured to receive a first reference signal, a second reference signal, and a second selection signal, wherein the first reference signal has a voltage level greater than that of the second reference signal, and wherein the charging voltage selection unit is configured to apply the first reference signal to the reference line and the data line in response to the selection signal being in a first selection state, and to apply the second reference signal to the data line and the reference line in response to the selection signal being in a second selection state; and a sense amplifier configured to compare the data signal with the reference voltage and generate an output bit signal having a bit state based on the comparison between the data signal and the reference signal. In some embodiments, the sense amplifier is configured to receive a sense signal oscillating between an enabled state and a disabled state; the sense amplifier is configured to compare a data signal with a reference signal in response to the sense signal being in an enabled state; and the sense signal oscillates between the enabled state and the disabled state such that the sense signal is in an enabled state when the selection signal is in a first selection state and when the selection signal is in a second selection state. In some embodiments, the memory cell includes a magnetic tunnel junction (MTJ) memory cell. In some embodiments, the memory cell includes a resistive memory cell. In some embodiments, the memory circuit further includes: a second memory array of second memory cells; a second reference line configured to receive a second reference voltage; a second data line configured to receive a second data signal; a second multiplexer configured to select one of the second memory cells in the second memory array such that the second data line is selectively coupled to the selected second memory cell; a second charging voltage selection unit configured to receive a first reference signal, a second reference signal, and a second selection signal, wherein the second charging voltage selection unit is configured to apply the first reference signal to the second reference line and the second data line in response to the second selection signal being in a first selection state, and to apply the second reference signal to the second data line and the second reference line in response to the second selection signal being in a second selection state; and a second sensing amplifier configured to compare the second data signal with the second reference voltage, and to generate a second output bit signal having a bit state based on the comparison between the second data signal and the second reference voltage. In some embodiments, the memory circuit further includes a timing control circuit configured to generate a selection signal and a second selection signal, such that when the selection signal is in a first selection state, the second selection signal is in a second selection state, and when the selection signal is in the second selection state, the second selection signal is in the first selection state.In some embodiments, the timing control circuit includes a trigger having an output bit terminal, a data input terminal, and a clock terminal configured to receive a clock signal, wherein the output bit terminal is connected to be fed back to the data input terminal.

[0100] In some embodiments, a method for determining the bit state of a bit stored in a memory circuit includes: selecting a first memory cell of a memory array such that the first memory cell is selectively coupled to a data line; charging the data line and a reference line; comparing a data signal on the data line with a reference signal during the charging of the data line and the reference line; setting a bit state of an output bit signal based on the comparison of the data signal with the reference signal during the charging of the data line and the reference line; selecting a second memory cell of the memory array such that the second memory cell is selectively coupled to a data line; discharging the data line and the reference line; comparing a data signal on the data line with the reference signal during the discharging of the data line and the reference line; and setting a bit state of the output bit signal based on the comparison of the data signal with the reference signal during the discharging of the data line and the reference line. In some embodiments, selecting the first memory cell and selecting the second memory cell each includes selecting a magnetic tunnel junction (MTJ) memory cell. In some embodiments, selecting the first memory cell and selecting the second memory cell each includes selecting a resistive memory cell. In some embodiments, selecting the first memory cell and selecting the second memory cell each includes using a multiplexer. In some embodiments, charging the data line and reference line includes using a charging voltage selection unit to select a first reference voltage, and discharging the data line and reference line includes using a charging voltage selection unit to select a second reference voltage. In some embodiments, comparing the data signal on the data line with a reference signal during each of the charging and discharging of the data line and reference line includes using a sensing amplifier.

[0101] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

[0102] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0103] [Explanation of Symbols]

[0104] 100, 200: Memory circuit

[0105] 102, 202E, 202O: Storage Units

[0106] 104, 204E, 204O: Multiplexers

[0107] 106: Bidirectional Voltage Sensing Amplifier (VSA)

[0108] 108, 110: Virtual storage units

[0109] 201E, 201O: Memory sub-circuit

[0110] 205E, 205O: Charging voltage selection unit

[0111] 206E, 206O, 500, 700: VSA

[0112] 210, 600: Timing control circuit

[0113] 300: Voltage Diagram

[0114] 302: Initial Period

[0115] 304, 306: Sensing cycle

[0116] 400: Charging voltage selection unit

[0117] 402, 604, 606, 701: Inverters

[0118] 404, 406: Field-Effect Transistor (FET)

[0119] 502, 702: Voltage comparators

[0120] 504: XOR gate

[0121] 602: D-type trigger

[0122] 704, 706, 708, 710, 712: PFET

[0123] 705, 714, 716: Nodes

[0124] 718, 720, 722, 724: NFET

[0125] 800: Method

[0126] 802, 804, 806, 808, 810, 812, 814, 816: Squares

[0127] BL[31:0], BL[63:32]: Bit lines

[0128] CLK: Clock signal

[0129] DBL: Data Bit Line

[0130] DBL[2n], DBL[2n+1]: Data bit lines

[0131] DSL: Data Selection Line

[0132] DSL[2n], DSL[2n+1]: Data selection line

[0133] DOUT, DOUT[2n], DOUT[2n+1]: Output voltage

[0134] Initial: Start signal

[0135] Q: Sensing voltage

[0136] QB: Inverting sensing voltage

[0137] REF: Reference Line

[0138] REF[2n], REF[2n+1]: Reference lines

[0139] SAEN: Sensing Enable Signal

[0140] SAENB: Inverting Sensing Enable Signal

[0141] Sel_even, Sel_Gen, Sel_odd: Selection signals

[0142] Sel Genb: Inverting selection signal

[0143] SL[15:0], SL[31:16]: Select lines

[0144] SL control: Select line control signal

[0145] tec, ti, tie, ts1, ts2, ts3, tsc1, tsc2, tse1, tse2, tss1, tss2: Time

[0146] VDD: Power supply voltage

[0147] Vread: Voltage

[0148] WL: Word line signal

Claims

1. A memory circuit, characterized in that, include: The storage unit is configured to store bits; The reference line is configured to receive a reference signal; A data line is configured to receive a data signal, wherein the data line is configured to be selectively coupled to the memory cell; A charging voltage selection unit is configured to charge the reference line and the data line in response to a selection signal being in a first selection state, and to discharge the reference line and the data line in response to the selection signal being in a second selection state; and The sensing amplifier is configured to: The data signal is compared with the reference signal to sense the bit state of the bit stored by the memory cell; When the charging voltage selection unit charges the reference line and the data line in response to the selection signal being in the first selection state, it inverts the logic state corresponding to the comparison in response to the selection signal being in the first selection state, and determines the bit state of the bit stored by the memory unit based on the inverted logic state. as well as When the charging voltage selection unit discharges the reference line and the data line in response to the selection signal being in the second selection state, it does not invert the logic state corresponding to the comparison in response to the selection signal being in the second selection state, and determines the bit state of the bit stored by the memory cell based on the uninverted logic state.

2. The memory circuit according to claim 1, wherein: The sensing amplifier is configured to receive a sensing signal that oscillates between an enabled state and a disabled state. The sensing amplifier is configured to compare the data signal with the reference signal in response to the sensing signal being in the enabled state; and The sensing signal oscillates between the enabled state and the disabled state, such that the sensing signal is in the enabled state when the selection signal is in the first selection state and when the selection signal is in the second selection state.

3. The memory circuit according to claim 1, wherein the memory cell comprises a magnetic tunnel junction (MTJ) memory cell.

4. The memory circuit according to claim 1, wherein the memory cell includes a resistive memory cell.

5. The memory circuit according to claim 1, further comprising: A storage array comprising multiple storage units; The multiplexer is configured to select one of the plurality of storage cells in the storage array, such that the data line is selectively coupled to the selected storage cell among the plurality of storage cells; A second storage array with multiple second storage units; The second reference line is configured to receive the second reference signal; The second data line is configured to receive a second data signal; The second multiplexer is configured to select one of the plurality of second storage cells in the second storage array, such that the second data line is selectively coupled to the selected second storage cell among the plurality of second storage cells; The second charging voltage selection unit is configured to receive a first reference voltage, a second reference voltage, and a second selection signal, wherein the charging voltage selection unit is configured to apply the first reference voltage to the second reference line and the second data line in response to the second selection signal being in the first selection state, and to apply the second reference voltage to the second data line and the second reference line in response to the second selection signal being in the second selection state. as well as A second sensing amplifier is configured to compare the second data signal with the second reference signal and generate a second output bit signal having a bit state based on the comparison between the second data signal and the second reference signal.

6. The memory circuit of claim 5 further includes a timing control circuit, the timing control circuit being configured to generate the selection signal and the second selection signal such that when the selection signal is in the first selection state, the second selection signal is in the second selection state, and when the selection signal is in the second selection state, the second selection signal is in the first selection state.

7. The memory circuit of claim 6, wherein the timing control circuit includes a flip-flop having an output bit terminal, a data input terminal and a clock terminal configured to receive a clock signal, wherein the output bit terminal is connected to be fed back to the data input terminal.

8. A memory circuit, characterized in that, include: A storage array with multiple storage units; The reference line is configured to receive a reference voltage; The data cable is configured to receive data signals; The multiplexer is configured to select one of the plurality of storage cells in the storage array, such that the data line is selectively coupled to the selected storage cell among the plurality of storage cells; A charging voltage selection unit is configured to receive a first reference signal, a second reference signal, and a second selection signal, wherein the first reference signal has a voltage level greater than that of the second reference signal, and wherein the charging voltage selection unit is configured to apply the first reference signal to the reference line and the data line to charge the reference line and the data line in response to the selection signal being in a first selection state, and to apply the second reference signal to the data line and the reference line to discharge the reference line and the data line in response to the selection signal being in a second selection state. as well as The sensing amplifier is configured to: The data signal is compared with the reference voltage, and an output bit signal having a bit state is generated based on the comparison between the data signal and the reference signal. When the charging voltage selection unit charges the reference line and the data line in response to the selection signal being in the first selection state, it inverts the logic state corresponding to the comparison in response to the selection signal being in the first selection state, and determines the bit state based on the inverted logic state. as well as When the charging voltage selection unit discharges the reference line and the data line in response to the selection signal being in the second selection state, it does not invert the logic state corresponding to the comparison in response to the selection signal being in the second selection state, and determines the bit state based on the uninverted logic state.

9. The memory circuit according to claim 8, wherein: The sensing amplifier is configured to receive a sensing signal that oscillates between an enabled state and a disabled state. The sensing amplifier is configured to compare the data signal with the reference signal in response to the sensing signal being in the enabled state; and The sensing signal oscillates between the enabled state and the disabled state, such that the sensing signal is in the enabled state when the selection signal is in the first selection state and when the selection signal is in the second selection state.

10. The memory circuit of claim 8, wherein the memory cell comprises a magnetic tunnel junction (MTJ) memory cell.

11. The memory circuit according to claim 8, wherein the memory cell comprises a resistive memory cell.

12. The memory circuit according to claim 8, further comprising: A second storage array with multiple second storage units; The second reference line is configured to receive a second reference voltage; The second data line is configured to receive a second data signal; The second multiplexer is configured to select one of the plurality of second storage cells in the second storage array, such that the second data line is selectively coupled to the selected second storage cell among the plurality of second storage cells; The second charging voltage selection unit is configured to receive the first reference signal, the second reference signal, and the second selection signal, wherein the second charging voltage selection unit is configured to apply the first reference signal to the second reference line and the second data line in response to the second selection signal being in the first selection state, and to apply the second reference signal to the second data line and the second reference line in response to the second selection signal being in the second selection state. as well as A second sensing amplifier is configured to compare the second data signal with the second reference voltage, and generate a second output bit signal having the bit state based on the comparison between the second data signal and the second reference voltage.

13. The memory circuit of claim 12, further comprising a timing control circuit configured to generate the selection signal and the second selection signal such that when the selection signal is in the first selection state, the second selection signal is in the second selection state, and when the selection signal is in the second selection state, the second selection signal is in the first selection state.

14. The memory circuit of claim 13, wherein the timing control circuit includes a flip-flop having an output bit terminal, a data input terminal and a clock terminal configured to receive a clock signal, wherein the output bit terminal is connected to be fed back to the data input terminal.

15. A method for determining the bit state of a bit stored in a memory circuit, characterized in that, The method includes: Select a first storage cell in the storage array such that the first storage cell is selectively coupled to a data line; Charge the data line and reference line; During the charging process of the data line and the reference line, the data signal on the data line is compared with the reference signal. Setting the bit state of the output bit signal based on the comparison between the data signal and the reference signal during the charging of the data line and the reference line includes: The logic state corresponding to the comparison is inverted, and the bit state of the bit signal is determined based on the inverted logic state. Select a second storage cell in the storage array such that the second storage cell is selectively coupled to the data line; Discharge the data line and the reference line; During the discharge of the data line and the reference line, the data signal on the data line is compared with the reference signal; and Setting the bit state of the output bit signal based on the comparison between the data signal and the reference signal during the discharge of the data line and the reference line includes: The logic state corresponding to the comparison is not inverted, and the bit state of the bit signal is determined based on the uninverted logic state.

16. The method of claim 15, wherein each of selecting the first memory cell and selecting the second memory cell comprises selecting a magnetic tunnel junction (MTJ) memory cell.

17. The method of claim 15, wherein each of selecting the first memory cell and selecting the second memory cell comprises selecting a resistive memory cell.

18. The method of claim 15, wherein each of selecting the first storage unit and selecting the second storage unit includes using a multiplexer.

19. The method of claim 15, wherein Charging the data line and the reference line includes using a charging voltage selection unit to select a first reference voltage, and Discharging the data line and the reference line includes using the charging voltage selection unit to select a second reference voltage.

20. The method of claim 15, wherein comparing the data signal on the data line with the reference signal during each of the charging of the data line and the reference line and the discharging of the data line and the reference line comprises using a sense amplifier.

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