Adaptive control circuit

Abstract

The application provides an adaptive control circuit of a static random access memory (SRAM), comprising a switching circuit, a forward diode-connected transistor, a reverse diode-connected transistor and a first delay circuit. The switching circuit is powered by a power supply voltage and coupled to a first node. The reverse diode-connected transistor and the forward diode-connected transistor are coupled in parallel between the first node and a second node. The first delay circuit is coupled between the second node and a ground voltage. The adaptive control circuit of the application not only provides an acceptable operating speed, but also maintains sufficient read margin.

Description

Technical Field

[0001] This invention relates to control circuits, and more specifically, to adaptive control circuits for static random access memory (SRAM). Background Technology

[0002] In traditional designs, if the SRAM (Static Random Access Memory) control circuitry is powered by a variable supply voltage, the corresponding read margin may be insufficient. Furthermore, the control circuitry may be affected by slow operating speeds. Therefore, a novel solution is needed to address the problems of existing technologies. Summary of the Invention

[0003] In view of this, the present invention provides an adaptive control circuit for static random access memory (SRAM).

[0004] In an exemplary embodiment, the adaptive control circuit for SRAM includes a switching circuit, a forward diode-connected transistor, a reverse diode-connected transistor, and a first delay circuit. The switching circuit is powered by a supply voltage and coupled to a first node. The reverse diode-connected transistor and the forward diode-connected transistor are connected in parallel between the first node and a second node. The first delay circuit is coupled between the second node and ground.

[0005] The adaptive control circuit of this invention not only provides an acceptable operating speed, but also maintains sufficient read margin.

[0006] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments illustrated in the various accompanying drawings. Attached Figure Description

[0007] The invention will be more fully understood by referring to the following detailed description and embodiments, in which:

[0008] Figure 1 This is a schematic diagram of an adaptive control circuit for SRAM according to an embodiment of the present invention.

[0009] Figure 2 This is a circuit diagram of an adaptive control circuit for SRAM according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram of an adaptive control circuit for SRAM according to an embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram of the voltage waveform of the adaptive control circuit in an embodiment of the present invention.

[0012] Figure 5 This is a schematic diagram showing the relationship between the read margin and the power supply voltage of the adaptive control circuit in an embodiment of the present invention. Detailed Implementation

[0013] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by differences in name, but rather by differences in function. The term "comprising" throughout the specification and subsequent claims is an open-ended term and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if the text describes a first device electrically connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0014] Figure 1 This is a schematic diagram of an adaptive control circuit 100 for SRAM (Static Random Access Memory) according to an embodiment of the present invention. Figure 1 As shown, the adaptive control circuit 100 includes a switching circuit 110, a forward diode-connected transistor 120, a backward diode-connected transistor 130, and a first delay circuit 140. The switching circuit 110 is powered by a power supply voltage VCC and coupled to a first node N1. The power supply voltage VCC is variable. For example, the voltage level of the power supply voltage VCC can be greater than or equal to 0.4V, but is not limited thereto. The backward diode-connected transistor 130 is connected in parallel with the forward diode-connected transistor 120 between the first node N1 and the second node N2. The first delay circuit 140 is coupled between the second node N2 and a ground voltage VSS. For example, the ground voltage VSS can have a voltage level of 0V. The first delay circuit 140 can be a capacitive element or a resistive element, but is not limited thereto.

[0015] In some embodiments, if the power supply voltage VCC is below a threshold voltage, both the forward diode transistor 120 and the reverse diode transistor 130 are disabled. In an alternative embodiment, if the power supply voltage VCC is above or equal to the threshold voltage, the forward diode transistor 120 is enabled (the reverse diode transistor 130 may also be enabled). The adaptive control circuit 100 is inactive when the power supply voltage VCC is below the threshold voltage. For example, the threshold voltage may be equal to 0.6V, but is not limited thereto. For example, when the power supply voltage VCC is above or equal to the threshold voltage, the adaptive control circuit 100 is operational; when the switching circuit 110 is on, the forward diode transistor 120 is enabled (on), and the reverse diode transistor 130 is disabled (off); when the switching circuit 110 is off, the forward diode transistor 120 is disabled, and the reverse diode transistor 130 is enabled. The enabled forward diode transistor 120 can conduct the first current I1 from the first node N1 to the second node N2. On the other hand, if the reverse diode-connected transistor 130 is enabled, the second current I2 is conducted from the second node N2 to the first node N1 so that the first delay circuit 140 returns to its initial state.

[0016] Based on actual measurements, this design of the adaptive control circuit 100 not only provides an acceptable operating speed (different voltages charge the capacitor differently, thus adjusting the operating speed), but also maintains a sufficient read margin. For example, the operating speed of the adaptive control circuit 100 can be at least 100MHz, and the read margin can be at least 100mV, but is not limited to these. Therefore, the proposed adaptive control circuit 100 will have good operating performance even when powered by a variable supply voltage VCC.

[0017] The following embodiments will describe different configurations and detailed structural features of the adaptive control circuit 100. It should be understood that these figures and descriptions are merely exemplary and not intended to limit the invention.

[0018] Figure 2 This is a circuit diagram of an adaptive control circuit 200 for SRAM according to an embodiment of the present invention. Figure 2 In one embodiment, the adaptive control circuit 200 includes a switching circuit 210, a forward diode-connected transistor 220, a reverse diode-connected transistor 230, and a first delay circuit 240.

[0019] The switching circuit 210 includes a first transistor M1. The first transistor M1 has a control terminal (e.g., gate) for receiving a clock voltage VA, a first terminal (e.g., source / drain) coupled to a power supply voltage VCC, and a second terminal (e.g., the other of the source / drain) coupled to a first node N1. The first node N1 serves as the output node of the adaptive control circuit 200. A forward-biased diode transistor 220 is a second transistor M2, which has a control terminal (e.g., gate) coupled to the first node N1, a first terminal (e.g., one of the source / drain) coupled to a second node N2, and a second terminal (e.g., the other of the source / drain) coupled to the first node N1. A reverse-biased diode transistor 230 is a third transistor M3, which has a control terminal (e.g., gate) coupled to the second node N2, a first terminal (e.g., one of the source / drain) coupled to the first node N1, and a second terminal (e.g., the other of the source / drain) coupled to the second node N2. The first delay circuit 240 includes a fourth transistor M4. The fourth transistor M4 has a control terminal (e.g., gate) coupled to the second node N2, a first terminal (e.g., one of the source / drain) coupled to the ground voltage VSS, and a second terminal (e.g., the other of the source / drain) coupled to the ground voltage VSS. In some embodiments, the first transistor M1 is implemented using a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET), and each of the second transistor M2, the third transistor M3, and the fourth transistor M4 is implemented using an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET).

[0020] If the clock voltage VA is at a low logic level, the first transistor M1 is enabled to pre-charge the first node N1. Conversely, if the clock voltage VA is at a high logic level, the first transistor M1 stops pre-charging the first node N1. The second transistor M2 is configured to selectively conduct a first current I1 from the first node N1 to the second node N2. The third transistor M3 is configured to selectively conduct a second current I2 from the second node N2 to the first node N1. The fourth transistor M4 serves as a small-size chip capacitor. Figure 2 Other features of the adaptive control circuit 200 and Figure 1 The adaptive control circuit 100 is similar. Therefore, the two embodiments can achieve similar performance levels.

[0021] Figure 3 This is a circuit diagram of an adaptive control circuit 300 for SRAM according to an embodiment of the present invention. Figure 3 Similar to Figure 2 .exist Figure 3In this embodiment, the switching circuit 310 of the adaptive control circuit 300 further includes a fifth transistor M5, and the adaptive control circuit 300 also includes a second delay circuit 350, a third delay circuit 360, and an inverter 370. The second delay circuit 350, the third delay circuit 360, and the inverter 370 are all coupled to the first node N1.

[0022] The fifth transistor M5 has a control terminal (e.g., gate) for receiving a clock voltage VA, a first terminal (e.g., one of the source / drain terminals) coupled to a ground voltage VSS, and a second terminal (e.g., the other of the source / drain terminal) coupled to a first node N1. The second delay circuit 350 includes a sixth transistor M6. The sixth transistor M6 has a control terminal (e.g., gate) coupled to a ground voltage VSS, a first terminal (e.g., one of the source / drain terminals) coupled to a first node N1, and a second terminal (e.g., the other of the source / drain terminal) coupled to a ground voltage VSS. The third delay circuit 360 includes a seventh transistor M7. The seventh transistor M7 has a control terminal (e.g., gate) coupled to a first node N1, a first terminal (e.g., one of the source / drain terminals) coupled to a ground voltage VSS, and a second terminal (e.g., the other of the source / drain terminal) coupled to a ground voltage VSS. In some embodiments, each of the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 is implemented using an NMOSFET. The input terminal of the inverter 370 is coupled to the first node N1, and the second terminal is coupled to the output node NOUT. The fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are devices in the original SRAM charging and discharging circuit.

[0023] exist Figure 3 In one embodiment, the adaptive control circuit 300 is a tracking circuit for controlling the cell array (not shown) of the SRAM. If the clock voltage VA has a low logic level, the fifth transistor M5 is disabled and the first transistor M1 is enabled to charge the first node N1. Conversely, if the clock voltage VA has a high logic level, the first transistor M1 is disabled and the fifth transistor M5 is enabled to discharge the first node N1. In an alternative embodiment, each of the second delay circuit 350 and the third delay circuit 360 is a capacitive or resistive element with a different circuit design (e.g., the delay circuit may be a capacitor, a combination of a capacitor and a resistor, a combination of a capacitor and the transistor shown in the figure, a combination of a resistor and the transistor shown in the figure, a combination of a capacitor and a resistor and the transistor shown in the figure, etc.). The output node NOUT of the adaptive control circuit 300 is used to output a control voltage to control the associated circuitry of the SRAM (not shown). Figure 3 Other features of the adaptive control circuit 300 and Figure 2The adaptive control circuit 200 is similar. Therefore, the two embodiments can achieve similar performance levels.

[0024] Figure 4 This is a voltage waveform diagram of the adaptive control circuit 300 according to an embodiment of the present invention. The horizontal axis represents time, and the vertical axis represents the voltage levels of the clock voltage VA, the first voltage V1 at the first node N1, and the second voltage V2 at the second node N2. Figure 4 As shown, if the clock voltage VA rises to a logic high level, the first voltage V1 of the first node N1 will decrease; if the clock voltage VA falls to a logic low level, the first voltage V1 of the first node N1 will increase. It should be noted that the second voltage V2 at the second node N2 has a smaller variation due to the limitations imposed by the second transistor M2 and the third transistor M3 (for example, the second transistor M2 is turned on to charge the fourth transistor M4, which acts as a small-size chip capacitor, only when the difference between the first voltage V1 at the first node N1 and the second voltage V2 at the second node N2 is greater than the turn-on voltage of the diode-connected second transistor M2; the third transistor M3 is turned on to discharge the fourth transistor M4, which acts as a small-size chip capacitor, only when the difference between the second voltage V2 at the second node N2 and the first voltage V1 at the first node N1 is greater than the turn-on voltage of the diode-connected third transistor M3).

[0025] Figure 5 This is a schematic diagram illustrating the relationship between the read margin and the power supply voltage VCC in the adaptive control circuit 300 according to an embodiment of the present invention. The horizontal axis represents the voltage level of the power supply voltage VCC. The vertical axis represents the voltage level of the read margin. Figure 5 As shown, the read margin of the adaptive control circuit 300 is always greater than the minimum voltage level VL, regardless of changes in the supply voltage VCC. For example, the minimum voltage level VL can be equal to 100mV, but is not limited to this. Therefore, the adaptive control circuit 300 can maintain a sufficient read margin. It should be understood that the read margin of the adaptive control circuit 300 is also enhanced by the fourth transistor M4, which acts as a chip capacitor (the rise and fall times of the voltage at the first node N1 are increased due to the pre-charging and discharging of the fourth transistor M4, thereby increasing the read margin). Furthermore, due to the control circuit 200, the charging and discharging current of the capacitor can be adaptively limited according to the variable supply voltage VCC for operation over a wide voltage range. Therefore, the corresponding operating speed can achieve an acceptable target (e.g., faster than 100MHz).

[0026] This invention proposes an adaptive control circuit for SRAM. Compared with traditional designs, this invention has advantages such as adaptive power supply voltage, wide operating range, sufficient read margin, low leakage current, and fast operation speed, making it suitable for applications in various electronic devices.

[0027] It should be noted that the aforementioned component parameters such as voltage, current, resistance, inductance, and capacitance are not limitations of this invention. Designers can adjust these settings according to different requirements. The adaptive control circuit of this invention is not limited to... Figures 1 to 5 The configuration. This invention may include only... Figures 1 to 5 Any one or more features in any one or more embodiments. In other words, not all features shown in the figures should be implemented in the adaptive control circuit of the present invention. Although embodiments of the present invention use MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) as examples, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as BJTs (Bipolar Junction Transistors), JFETs (Junction-Gate Field-Effect Transistors), FinFETs (Fin Field-Effect Transistors), etc., without affecting the performance of the present invention.

[0028] The use of ordinal terms such as “first,” “second,” and “third” in claims to modify claim elements does not imply any priority, precedence, or order of one claim element relative to another claim element, or the chronological order of the method actions performed, but is merely used as labels to distinguish one claim element with a specific name from another element with the same name (used only as ordinal terms to distinguish claim elements).

[0029] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (which will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. An adaptive control circuit for a static random access memory (SRAM), the adaptive control circuit comprising: The switching circuit is powered by the power supply voltage and coupled to the first node; Forward diode-connected transistor; A reverse diode-connected transistor is coupled in parallel with the forward diode-connected transistor between the first node and the second node; as well as A first delay circuit is coupled between the second node and the ground voltage; The switching circuit includes: A first transistor, wherein the first transistor has a control terminal for receiving a clock voltage, a first terminal coupled to the power supply voltage, and a second terminal coupled to the first node; The power supply voltage is a variable power supply voltage.

2. The adaptive control circuit as described in claim 1, wherein, The forward diode-connected transistor is enabled when the power supply voltage is higher than or equal to the threshold voltage.

3. The adaptive control circuit as described in claim 1, wherein, The first transistor is implemented using a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET).

4. The adaptive control circuit as described in claim 1, wherein, The forward diode-connected transistor is a second transistor, which has a control terminal coupled to the first node, a first terminal coupled to the second node, and a second terminal coupled to the first node.

5. The adaptive control circuit as described in claim 4, wherein, The second transistor is implemented using an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET).

6. The adaptive control circuit as described in claim 1, wherein, The reverse diode-connected transistor is a third transistor, which has a control terminal coupled to the second node, a first terminal coupled to the first node, and a second terminal coupled to the second node.

7. The adaptive control circuit as described in claim 6, wherein, The third transistor is implemented using an NMOSFET.

8. The adaptive control circuit as described in claim 1, wherein, The first delay circuit is a capacitor or a resistor.

9. The adaptive control circuit as described in claim 1, wherein, The first delay circuit includes: A fourth transistor, wherein the fourth transistor has a control terminal coupled to the second node, a first terminal coupled to the ground voltage, and a second terminal coupled to the ground voltage.

10. The adaptive control circuit as described in claim 9, wherein, The fourth transistor is implemented using an NMOSFET.

11. The adaptive control circuit as described in claim 1, wherein, The switching circuit further includes: A fifth transistor, wherein the fifth transistor has a control terminal for receiving the clock voltage, a first terminal coupled to the ground voltage, and a second terminal coupled to the first node.

12. The adaptive control circuit as described in claim 11, wherein, The fifth transistor is implemented using an NMOSFET.

13. The adaptive control circuit as described in claim 1, further comprising: The second delay circuit is coupled to the first node.

14. The adaptive control circuit as described in claim 13, wherein, The second delay circuit includes: A sixth transistor, wherein the sixth transistor has a control terminal coupled to the ground voltage, a first terminal coupled to the first node, and a second terminal coupled to the ground voltage.

15. The adaptive control circuit as described in claim 14, wherein, The sixth transistor is implemented using an NMOSFET.

16. The adaptive control circuit of claim 13, further comprising: The third delay circuit is coupled to the first node.

17. The adaptive control circuit as described in claim 16, wherein, The third delay circuit includes: A seventh transistor, wherein the seventh transistor has a control terminal coupled to the first node, a first terminal coupled to the ground voltage, and a second terminal coupled to the ground voltage.

18. The adaptive control circuit as described in claim 17, wherein, The seventh transistor is implemented using an NMOSFET.

19. The adaptive control circuit as described in claim 1, further comprising: An inverter, wherein the inverter has an input terminal coupled to the first node and a second terminal coupled to the output node.

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