Semiconductor device

Abstract

A semiconductor device includes: a plurality of first conductors extending in a first direction different from a second direction, a third direction, and a fourth direction, wherein the first direction is perpendicular to the fourth direction; a plurality of second conductors extending in the fourth direction to intersect the plurality of first conductors to form an intersection region, and the plurality of second conductors being spaced apart from the plurality of first conductors; and a plurality of memory cells disposed relative to the first conductors and second conductors to overlap with the intersection regions of the first conductors and second conductors, respectively, and arranged along lines parallel to the first direction, the second direction, and the third direction, wherein the plurality of memory cells are respectively positioned at the vertices of an imaginary equilateral triangle having three sides parallel to the first direction, the second direction, and the third direction, wherein each first conductor overlaps with the plurality of memory cells arranged in the first direction, and each second conductor overlaps with the plurality of memory cells staggered from each other in the fourth direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0181364, filed on December 17, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The patent document relates to a storage circuit or storage device. Background Technology

[0004] In recent years, with the development of electronic devices towards miniaturization, low power consumption, high performance, and multifunctionality, there has been a need in this field for semiconductor devices capable of storing information in various electronic devices (such as computers, portable communication devices, etc.), and research on semiconductor devices has been conducted. Such semiconductor devices include those capable of storing data by utilizing their characteristic of switching between different resistance states according to applied voltage or current, such as RRAM (Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), and electric fuses. Summary of the Invention

[0005] The technology disclosed in this patent document includes various embodiments of semiconductor devices with excellent operating characteristics and prevention of process defects.

[0006] In one embodiment, a semiconductor device includes: a plurality of first conductors extending in a first direction different from a second direction, a third direction, and a fourth direction, wherein the first direction is perpendicular to the fourth direction; a plurality of second conductors extending in the fourth direction to intersect the plurality of first conductors to form an intersection region, and the plurality of second conductors being spaced apart from the plurality of first conductors; and a plurality of memory cells disposed relative to the first conductors and second conductors to overlap with the intersection regions of the first conductors and second conductors, respectively, and arranged along lines parallel to the first direction, the second direction, and the third direction, the plurality of memory cells being located at vertices of an imaginary equilateral triangle having three sides parallel to the first direction, the second direction, and the third direction, wherein each first conductor overlaps with a plurality of memory cells arranged in the first direction, and each second conductor overlaps with a plurality of memory cells staggered from each other in the fourth direction.

[0007] In another embodiment, a semiconductor device includes: a plurality of first conductors; a plurality of second conductors intersecting the plurality of first conductors to form an intersection region, and the plurality of second conductors being spaced apart from the plurality of first conductors; and a plurality of memory cells configured to overlap with the intersection region and arranged along lines parallel to a first direction, a second direction, and a third direction, the memory cells being positioned at vertices of an imaginary equilateral triangle having three sides parallel to the first direction, the second direction, and the third direction, wherein each first conductor extends in a fourth direction perpendicular to the first direction and overlaps with a memory cell arranged in the fourth direction, and each second conductor extends in a fifth direction perpendicular to the second direction and overlaps with a memory cell arranged in the fifth direction. Attached Figure Description

[0008] Figure 1A This is a plan view of a semiconductor memory showing a comparative example.

[0009] Figure 1B It is along Figure 1A The cross-sectional view taken by line A1-A1′.

[0010] Figure 1C It is along Figure 1A The cross-sectional view taken by line B1-B1′.

[0011] Figure 1D This is a plan view of a semiconductor memory that shows another comparative example.

[0012] Figure 2A This is a plan view illustrating a semiconductor memory according to an embodiment of the disclosed technology.

[0013] Figure 2B It is along Figure 2A The cross-sectional view taken from line A2-A2′.

[0014] Figure 2C It is along Figure 2A The cross-sectional view taken from line B2-B2′.

[0015] Figure 2D It is shown Figures 2A to 2C A view of a portion of the storage unit.

[0016] Figure 3 This is a plan view illustrating a semiconductor memory according to another embodiment of the disclosed technology.

[0017] Figure 4A This is a plan view illustrating a semiconductor memory according to another embodiment of the disclosed technology.

[0018] Figure 4B It is along Figure 4AThe cross-sectional view taken by line A4-A4′. Detailed Implementation

[0019] Various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0020] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated to clearly illustrate certain features of the described embodiments. When a particular example of a multi-layered structure with two or more layers is presented in the drawings or description, the order in which these layers are arranged or their relative positioning as shown reflects a particular implementation of the described or illustrated example, and different relative positioning or order in which these layers are arranged is possible.

[0021] Figure 1A This is a plan view showing a comparative example of a semiconductor memory. Figure 1B It is along Figure 1A The cross-sectional view taken by line A1-A1′, and Figure 1C It is along Figure 1A The cross-sectional view taken by line B1-B1′. Figure 1D This is a plan view of a semiconductor memory that shows another comparative example.

[0022] First, refer to Figures 1A to 1C A comparative example semiconductor memory may include: a substrate 100; a plurality of first conductors 110 formed on the substrate 100 and extending in a first direction; a plurality of second conductors 130 formed on the first conductors 110 and spaced apart from the first conductors 110 and extending in a second direction substantially perpendicular to the first direction; and a plurality of memory cells 120 overlapping the intersection regions of the first conductors 110 and the second conductors 130 between the first conductors 110 and the second conductors 130, respectively.

[0023] Storage cell 120 may have a cylindrical shape and function as a data storage unit. In one example, storage cell 120 may include a variable resistor element that stores different data by switching between different resistance states based on a voltage or current applied through its lower and upper ends. In another example, storage cell 120 may include a multilayer structure comprising a lower electrode layer 121, a selection element layer 123, an intermediate electrode layer 125, a variable resistor layer 127, and an upper electrode layer 129.

[0024] In this storage device, the spacing P1 of the storage cells 120 arranged in the first or second direction can be smaller than the spacing P1' of the storage cells 120 arranged in a direction diagonally opposite to the first or second direction (e.g., in the direction of line B1-B1'). For reference, spacing refers to the distance from one end of one component to one end of another adjacent component when multiple components are arranged in one direction, and it can correspond to the sum of the width of one component and the distance between one component and another adjacent component. Since the width of the storage cells 120 is substantially constant regardless of the direction, the distance between adjacent storage cells 120 in the first or second direction can be smaller than the distance between adjacent storage cells 120 in the diagonal direction.

[0025] To form the columnar memory cell 120, it may be necessary to deposit the material layers constituting the memory cell 120 by selectively etching the material layers. When the memory cell 120 has a multilayer structure (in which the variable resistance layer 127 has a multilayer structure such as a magnetic tunnel junction (MTJ) structure), the difficulty of finding a suitable etching process to etch such a multilayer structure into the desired shape may increase, and etching processes with excellent anisotropic etching characteristics (e.g., ion beam etching processes) can be used to achieve the desired etching results.

[0026] When the spacing between patterns is not constant, the ion beam etching process is affected by ion beam shadowing, in which the ion beam does not reach areas where the spacing between patterns is relatively narrow. Due to this ion beam shadowing, areas with relatively wide spacing between patterns can be sufficiently etched, while areas with relatively narrow spacing may be less etched. This difference in material removal due to the spacing between adjacent patterns using the same ion beam etching process is undesirable, as it can make it difficult to separate the patterns. Figure 1A In the comparative example of the storage device, adjacent storage cells 120 with a relatively wide distance in the diagonal direction may be sufficiently separated due to sufficient etching, while adjacent storage cells 120 with a relatively narrow distance in the first or second direction may not be separated from each other due to less etching.

[0027] Figure 1D The comparative example is designed to form memory cells 150 in different ways, such that there is a uniform distance between adjacent cells in different directions, that is, the memory cells 150 have a uniform spacing, which allows for the reduction of... Figure 1A The example uses an undesirable etching process with ion beam etching.

[0028] refer to Figure 1DAnother comparative example of a semiconductor memory may include: a plurality of first conductors 140 extending in a first direction; a plurality of second conductors 160 formed on the first conductors 140 to be spaced apart from the first conductors 140 and extending in a third direction and in a different direction forming an angle of 60 degrees or substantially about 60 degrees relative to the first direction; and a plurality of memory cells 150 overlapping with the intersection regions of the first conductors 140 and the second conductors 160, respectively. The line spacing and line width of the first conductor 140 and the line spacing and line width of the second conductor 160 are designed such that the spacing between adjacent memory cells 150 is placed at a uniform cell spacing in different directions, such that a memory cell 150 in a first conductor 140 and the two closest adjacent memory cells 150 in an adjacent first conductor 140 form the vertices of an equilateral triangle, and similarly, a memory cell 150 in a second conductor 160 and the two closest adjacent memory cells 150 in an adjacent second conductor 160 form the vertices of another equilateral triangle of the same or nearly the same size.

[0029] The above-mentioned equal unit spacing geometry is composed of Figure 1D The image shows imaginary dashed lines and multiple equilateral triangles formed by adjacent memory cells 150. These equilateral triangles are arranged such that six equilateral triangles form an equilateral hexagon, and the multiple memory cells 150 can be arranged to overlap with the vertices of the equilateral triangles respectively. Therefore, the multiple memory cells 150 can be arranged into a line along a first direction, a second direction, and a third direction parallel to the three sides of the equilateral triangles. The second direction can form an angle of approximately 60 degrees relative to each of the first and third directions. The multiple memory cells 150 arranged in the first direction can overlap with the first conductor 140, and the multiple memory cells 150 arranged in the third direction can overlap with the second conductor 160.

[0030] exist Figure 1D In the comparative example, the spacing P1″ (i.e., the interval between two adjacent cells) of the memory cells 150 in the first direction, the second direction, and the third direction can be substantially the same or constant. Therefore, the aforementioned problems caused by unequal spacing between adjacent cells during ion beam etching can be resolved. Figure 1A The problem lies in the comparison examples in the text.

[0031] Assuming in Figure 1A and Figure 1D The two examples in the text have the same wire structure, relative to Figure 1A In the comparison examples, the line spacings P11 and P12 are... Figure 1DIn the comparative example, the spacing P11″ of the first conductor 140 and the spacing P12″ of the second conductor 160 may be reduced. Therefore, in Figure 1D In the comparative example, the width of each of the first wire 140 and the second wire 160 can be reduced to achieve the same effect as... Figure 1A The comparison examples show identical or similar line spacing. When in Figure 1D In the comparative example, when the widths of the first wire 140 and the second wire 160 are reduced, the resistance of the first wire 140 and the second wire 160 with the reduced linewidth may increase, thus degrading the operating characteristics of the semiconductor memory. This will be described in more detail with the following example.

[0032] We can assume: Figure 1A In the comparison example, the spacing P1 of storage cell 120 in the first direction or the second direction and in Figure 1D In the comparison example, the storage cells 150 have the same value for the spacing P1″ in the first direction, the second direction, or the third direction, for example, 2F. In this case, Figure 1A In the comparative example, the spacing P11 of the first wire 110 can have the same value as the spacing P1 of the storage cell 120, i.e., 2F. On the other hand, in Figure 1D In the comparative example, the spacing P11′ of the first conductor 140 can have a value of 2F*√3 / 2, that is, approximately 1.732F. That is, in Figure 1D In the comparative example, the spacing P1″ of the first conductor 140 can be smaller than the spacing P1″ of the memory cell 150. A reduction in the spacing P11′ of the first conductor 140 may mean a reduction in the width of the first conductor 140 and an increase in its resistance. Similarly, in Figure 1A In the comparative example, the spacing P12 of the second wire 130 can have the same value as the spacing P1 of the storage cell 120, i.e., 2F. On the other hand, in Figure 1D In the comparative example, the spacing P12′ of the second conductor 160 can have a value of 2F*√3 / 2, that is, approximately 1.732F. That is, in Figure 1D In the comparative example, the spacing P12′ of the second conductor 160 can be smaller than the spacing P1″ of the memory cell 150. A reduction in the spacing P12′ of the second conductor 160 may mean a reduction in the width of the second conductor 160 and an increase in its resistance.

[0033] Recognizing reference Figure 1A and Figure 1D The issues discussed, and the disclosed technologies, include those capable of solving... Figure 1A The comparison example problem and Figure 1DThe comparative examples address various implementations of semiconductor memories. Implementations of the disclosed technology can be used to construct semiconductor memories capable of preventing and / or minimizing reductions in wire spacing and wire width / wire resistance, while maintaining constant spacing of memory cells in different directions to achieve relatively uniform etching during manufacturing.

[0034] Figure 2A This is a plan view illustrating a semiconductor memory according to an embodiment of the disclosed technology. Figure 2B It is along Figure 2A The cross-sectional view taken by line A2-A2′, and Figure 2C It is along Figure 2A The cross-sectional view taken from line B2-B2′.

[0035] refer to Figures 2A to 2C The semiconductor memory according to embodiments of the disclosed technology may include: a substrate 200; a plurality of first conductors 210 formed on the substrate 200 and extending in a first direction; a plurality of second conductors 230 formed on the first conductors 210 and spaced apart from the first conductors 210 and extending in a fourth direction substantially perpendicular to the first direction; and a plurality of memory cells 220 overlapping the intersection regions of the first conductors 210 and the second conductors 230 between the first conductors 210 and the second conductors 230, respectively.

[0036] The substrate 200 may include a semiconductor material such as silicon. A desired understructure (not shown) (e.g., a drive circuit) may be formed in the substrate 200, which is electrically connected to and drives the first wire 210 and / or the second wire 230.

[0037] Storage cell 220 can have a cylindrical shape and function as a data storage unit. In this embodiment, the storage cell 220 has been described as having a circular shape in a plan view, but other implementations are also possible. In a plan view, storage cell 220 can have various shapes, such as rectangular, elliptical, or others.

[0038] In the example, storage cell 220 may include a variable resistor element that switches between different resistance states based on a voltage or current applied via the lower end of the first conductor 210 and the upper end of the second conductor 230, for storing different data. In the example, storage cell 220 may include a multilayer structure comprising a lower electrode layer 221, a selection element layer 223, an intermediate electrode layer 225, a variable resistor layer 227, and an upper electrode layer 229.

[0039] The lower electrode layer 221 and the upper electrode layer 229 may be located at both ends of the memory cell 220, for example, at the lower end and the upper end of the memory cell 220, respectively, to transmit the voltage or current required to operate the memory cell 220. The intermediate electrode layer 225 may be located between the select element layer 223 and the variable resistor layer 227 to physically separate and electrically connect them. The lower electrode layer 221, the intermediate electrode layer 225, or the upper electrode layer 229 may comprise various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), and titanium (Ti); metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN); or combinations thereof. Alternatively, for example, at least one of the lower electrode layer 221, the intermediate electrode layer 225, and the upper electrode layer 229 may comprise a carbon electrode.

[0040] Selector layer 223 can function to reduce and / or suppress leakage current between memory cells MC sharing the first conductor 210 or the second conductor 230. In some embodiments, selector layer 223 may have threshold switching characteristics, for example, characteristics for blocking or substantially limiting current when the applied voltage amplitude is less than a predetermined threshold and characteristics for allowing a sudden increase in current when the applied voltage amplitude is higher than the threshold. This threshold may be referred to as the threshold voltage, and selector layer 223 may be implemented in an on or off state based on this threshold voltage. Selector layer 223 may include: diodes; bidirectional threshold switching (OTS) materials such as chalcogenide-based materials; mixed ion-electron conduction (MIEC) materials such as metal chalcogenide-based materials; metal-insulator transition (MIT) materials such as NbO2 and VO2; tunneling insulating layers with relatively wide band gaps such as SiO2 and Al2O3; or others.

[0041] The variable resistance layer 227 may be a portion of the storage cell 220 where data is stored. In some embodiments, the variable resistance layer 227 may have variable resistance characteristics that switch between different resistance states according to the applied voltage. The variable resistance layer 227 may have a single-layer or multi-layer structure, which includes at least one material used for RRAM, PRAM, MRAM, FRAM, or others. For example, the variable resistance layer 227 may include: metal oxides such as perovskite-based oxides and transition metal oxides, phase change materials such as chalcogenide-based materials, ferromagnetic materials, ferroelectric materials, or others.

[0042] Figure 2D It is shown Figures 2A to 2C A view of a portion of the storage cell, which includes a variable resistance layer 227, an upper electrode layer 229, and an intermediate electrode layer 225.

[0043] refer to Figure 2D The variable resistance layer 227 may include a fixed layer 227A, a free layer 227C, and a tunnel blocking layer 227B between the fixed layer 227A and the free layer 227C.

[0044] Fixed layer 227A may have a fixed magnetization direction. For example, as indicated by the arrow in fixed layer 227A, fixed layer 227A may have a magnetization direction perpendicular to the surface of fixed layer 227A from top to bottom. However, the disclosed technology is not limited to this, and in another embodiment, fixed layer 227A may have a magnetization direction from bottom to top. Alternatively, in another embodiment, fixed layer 227A may have a magnetization direction parallel to the surface of fixed layer 227A. That is, fixed layer 227A may have one of a right-to-left magnetization direction and a left-to-right magnetization direction. Free layer 227C may have a magnetization direction that can be changed. For example, as indicated by the arrow in free layer 227C, free layer 227C may have a magnetization direction perpendicular to the surface of free layer 227C from top to bottom or from bottom to top. However, when the fixed layer 227A has a magnetization direction parallel to its surface, the free layer 227C can also have a magnetization direction parallel to its surface, i.e., a right-to-left or left-to-right magnetization direction. The fixed layer 227A and the free layer 227C can have a single-layer or multi-layer structure, comprising various ferromagnetic materials, such as Fe-Pt alloys, Fe-Pd alloys, Co-Pd alloys, Co-Pt alloys, Fe-Ni-Pt alloys, Co-Fe-Pt alloys, Co-Ni-Pt alloys, or others. A tunneling barrier layer 227B can be located between the fixed layer 227A and the free layer 227C, and if needed, such as during programming operations that change the resistance state of the memory cell 220, the magnetization direction of the free layer 227C can be changed by allowing electron tunneling. The tunnel barrier layer 227B can have a single-layer or multi-layer structure, including oxides such as MgO, CaO, SrO, TiO, VO, and NbO. In this embodiment, although the fixed layer 227A is illustrated as being positioned below the tunnel barrier layer 227B and the free layer 227C as being positioned above the tunnel barrier layer 227B, the disclosed technology is not limited thereto. In another embodiment, the positions of the fixed layer 227A and the free layer 227C can be changed. For example, the fixed layer 227A can be positioned above the tunnel barrier layer 227B, while the free layer 227C can be positioned below the tunnel barrier layer 227B.

[0045] In the variable resistance layer 227, the magnetization direction of the free layer 227C can be changed by a program current passing through the variable resistance layer 227. Therefore, the magnetization direction of the free layer 227C and the magnetization direction of the fixed layer 227A can be parallel or antiparallel. When the magnetization direction of the free layer 227C and the magnetization direction of the fixed layer 227A are parallel, the memory cell 220 can have a low resistance state. Conversely, when the magnetization direction of the free layer 227C and the magnetization direction of the fixed layer 227A are antiparallel, the memory cell 220 can have a high resistance state.

[0046] exist Figures 2A to 2C In the example described above, although memory cell 220 includes a lower electrode layer 221, a select element layer 223, an intermediate electrode layer 225, a variable resistance layer 227, and an upper electrode layer 229, the layer structure of memory cell 220 is not limited to the example described in the embodiments, and other embodiments of the layer structure of memory cell 220 are possible. For example, in one embodiment of memory cell 220 having a variable resistance layer 227 for data storage, the stacking order of the layers of memory cell 220 may be changed, or at least one stacked layer may be omitted. As an example, one or more of the lower electrode layer 221, intermediate electrode layer 225, and upper electrode layer 229 may be omitted, or the positions of select element layer 223 and variable resistance layer 227 may be reversed. Alternatively, one or more layers (not shown) may be added to memory cell 220 for process improvements or performance improvements of memory cell 220.

[0047] Suppose there exists an imaginary line in the planar diagram that forms multiple equilateral triangles (see...). Figure 2A (The dashed lines in the diagram represent the equilateral triangles.) If the equilateral triangles are arranged such that six equilateral triangles form an equilateral hexagon, then multiple storage cells 220 can be arranged to overlap with the vertices of the equilateral triangles respectively. Therefore, the multiple storage cells 220 can be arranged in a line along a first direction, a second direction, and a third direction parallel to the three sides of the equilateral triangles. The second direction can form an angle of approximately 60 degrees relative to the first direction, and the third direction can form an angle of approximately 60 degrees relative to the second direction. As a result, the spacing P2 of the storage cells 220 in the first direction, the second direction, and the third direction can have a constant value.

[0048] A first conductive line 210 may be disposed between the substrate 200 and the memory cell 220 to connect to the lower end of the memory cell 220. The first conductive line 210 may have a single-layer or multi-layer structure, comprising various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta); metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN); or combinations thereof. The first conductive line 210 may overlap with a plurality of memory cells 220 arranged in a first direction by extending in that direction. The plurality of first conductive lines 210 may be arranged to be spaced apart from each other in a fourth direction corresponding to the width direction of the first conductive lines 210. In the fourth direction, the centers of the first conductive lines 210 and the centers of the memory cells 220 may be arranged to substantially overlap. This overlap of the first conductive lines 210 and the memory cells 220 in the fourth direction may be referred to as an on-pitch shape. In this case, the pitch P21 of the first conductive lines 210 may be smaller than the pitch P2 of the memory cells 220. As an example, when the spacing P2 of the storage cell 220 is 2F, the spacing P21 of the first conductor 210 may have a value of 2F*√3 / 2, that is, about 1.732F.

[0049] The space between the first conductors 210 may be filled with a first interlayer insulating layer ILD1, and the space between the storage cells 220 may be filled with a second interlayer insulating layer ILD2. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may comprise various insulating materials, such as silicon oxide, silicon nitride, or combinations thereof.

[0050] The second conductor 230 can be disposed above the memory cell 220 and the second interlayer insulating layer ILD2 to be connected to the upper end of the memory cell 220. The second conductor 230 can have a single-layer or multi-layer structure, comprising various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta); metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN); or combinations thereof. The second conductor 230 can extend in a fourth direction to overlap with a plurality of memory cells 220 arranged in the fourth direction, and can be arranged to be spaced apart from each other in the first direction. In this case, the plurality of memory cells 220 arranged in the fourth direction can be arranged in a zigzag manner, rather than positioned in a straight line extending along the fourth direction. This is because, as described above, the plurality of memory cells 220 are arranged in a line along the first, second, and third directions. Therefore, the second conductor 230 can only partially overlap with each of the plurality of memory cells 220 arranged in the fourth direction. This will be described in more detail below.

[0051] When multiple storage cells 220 arranged in a line in a first direction are referred to as a column of storage cells 220, multiple columns of storage cells 220 can be arranged in a fourth direction. The multiple columns of storage cells 220 may include one or more even-numbered columns and one or more odd-numbered columns. Figure 2A In the plan view, the first and third columns of storage cells 220, starting from the top, can correspond to odd-numbered columns, and the second column of storage cells 220, starting from the top, can correspond to even-numbered columns. The first and third columns can overlap with the first and third first wires 210 from the top, and the second column can overlap with the second first wire 210 from the top. In this case, one of the second wires 230 can overlap with the first portion (e.g., the right side portion) of the storage cells 220 in the even-numbered columns and with the second portion (e.g., the left side portion) of the storage cells 220 in the odd-numbered columns. Therefore, when two storage cells in the odd and even-numbered columns overlap with the second wire 230, the left side portion of the storage cells in the odd-numbered columns overlaps with the second wire 230, while the right side portion of the storage cells in the even-numbered columns overlaps with the second wire 230. These right and left portions can be arranged to face each other. Therefore, in the plan view, the portion of the storage cell that does not overlap with the second wire 230 can be located outside the second wire 230. For example, the second portion (e.g., the left portion) of the storage cell 220 in the even-numbered column may protrude from the second conductor 230 without overlapping it. Furthermore, in a plan view, the first portion (e.g., the right portion) of the storage cell 220 in the odd-numbered column may protrude from the second conductor 230 without overlapping it. As an example, the second conductor 230 may overlap and connect with the right half of the storage cell 220 in the even-numbered column and the left half of the storage cell 220 in the odd-numbered column. However, other embodiments are possible besides the specific examples disclosed in this patent document. For example, in some embodiments, the second conductor 230 partially overlaps with the storage cell 220 arranged in a fourth direction, and the overlapping area of ​​the second conductor 230 and the storage cell 220 can be modified in various ways.

[0052] According to this embodiment, the spacing P22 of the second conductor 230 can be substantially the same as the spacing P2 of the storage cell 220. When the spacing P2 of the storage cell 220 is 2F, the spacing P22 of the second conductor 230 can also have a value of 2F. The center of the second conductor 230 and the center of the storage cell 220 can be offset from each other based on a first direction, for example, in an off-pitch shape.

[0053] The following describes an example of a method for manufacturing a semiconductor memory according to this embodiment.

[0054] First, the first conductive lines 210 can be formed by depositing a conductive material on the substrate 200 and selectively etching the conductive material. The spaces between the first conductive lines 210 can be filled with an insulating material to form a first interlayer insulating layer ILD1.

[0055] Next, a material layer for forming the memory cell 220 can be deposited on the first conductor 210 and the first interlayer insulating layer ILD1, and then the material layer can be selectively etched to form the memory cell 220. For example, selective etching of the material layer can be performed by an ion beam etching method. The space between the memory cells 220 can be filled with insulating material to form a second interlayer insulating layer ILD2.

[0056] Secondly, the second wire 230 can be formed by depositing a conductive material on the storage cell 220 and the second interlayer insulating layer ILD2 and selectively etching the conductive material.

[0057] According to the semiconductor memory described above, the reduction of the spacing P22 of the second conductive lines 230 can be prevented while keeping the spacing P2 of the memory cells 220 constant. Therefore, defects in the etching process can be eliminated and operating characteristics improved.

[0058] In the above embodiments, the case where the first wire 210 is located below the storage cell 220 and the second wire 230 is located above the storage cell 220 has been described. However, the upper and lower positions of the first wire 210 and the second wire 230 can be changed. For example, the second wire 230, which extends in the fourth direction and partially overlaps with the storage cell 220, can be positioned below the storage cell 220, while the first wire, which extends in the first direction, can be positioned above the storage cell 220.

[0059] In the above embodiment, the fourth direction is substantially perpendicular to the first direction, but other implementations are also possible. The fourth direction may be perpendicular to the second or a third direction. In this case, the second conductor 230 may extend along the fourth direction and partially overlap with the storage cell 220 arranged along the fourth direction.

[0060] In the above embodiments, the case where the first wire 210 extends in a first direction and overlaps with the storage cell 220 arranged in the first direction has been described, but other implementations are also possible. In another embodiment, the first wire 210 may extend upward in a second direction or a third direction. This will be referred to... Figure 3 Described exemplarily.

[0061] Figure 3 This is a plan view illustrating a semiconductor memory according to another embodiment of the disclosed technology. The main differences from the embodiments described above will be described.

[0062] refer to Figure 3 The semiconductor memory according to this embodiment may include: a plurality of first conductors 310 extending in a third direction; a plurality of second conductors 330 formed to be spaced apart from the first conductors 310 and extending in a fourth direction; and a plurality of memory cells 320 overlapping the intersection region of the first conductors 310 and the second conductors 330 between the first conductors 310 and the second conductors 330.

[0063] Suppose there exists an imaginary line in the planar diagram that forms multiple equilateral triangles (see...). Figure 3 (The dashed lines represent the equilateral triangles, and the equilateral triangles are arranged such that six equilateral triangles form an equilateral hexagon.) Then, multiple storage cells 320 can be arranged to overlap with the vertices of the equilateral triangles respectively. Therefore, the multiple storage cells 320 can be arranged in a line along a first direction, a second direction, and a third direction parallel to the three sides of the equilateral triangles. The second direction can form an angle of approximately 60 degrees relative to the first direction, and the third direction can also form an angle of approximately 60 degrees relative to the second direction. As a result, the spacing P3 of the storage cells 320 in the first direction, the second direction, and the third direction can have a constant value. The fourth direction can be substantially perpendicular to the first direction.

[0064] The first conductor 310 can be configured to be connected to one of the lower and upper ends of the memory cell 320. The first conductor 310 can extend in a third direction to overlap with a plurality of memory cells 320 arranged in the third direction. The plurality of first conductors 310 can be arranged to be spaced apart from each other in a direction perpendicular to the third direction, corresponding to the width direction of the first conductor 310. In the width direction of the first conductor 310, the center of the first conductor 310 and the center of the memory cell 320 can be arranged to substantially overlap, i.e., in an on-pitch shape. In this case, the pitch P31 of the first conductors 310 can be smaller than the pitch P3 of the memory cells 320. As an example, when the pitch P3 of the memory cells 320 is 2F, the pitch P31 of the first conductors 310 can have a value of 2F*√3 / 2, i.e., approximately 1.732F.

[0065] The second wire 330 may be configured to be connected to another of the lower and upper ends of the memory cell 320 (which is not connected to the first wire 310). The second wire 330 may extend in a fourth direction to overlap with the plurality of memory cells 320 arranged in the fourth direction, and may be arranged to be spaced apart from each other in the first direction. Since the plurality of memory cells 320 are not arranged in a line in the fourth direction, the second wire 330 may overlap only partially with each of the plurality of memory cells 320 arranged in the fourth direction. As an example, one of the second wires 330 may overlap with a first portion (e.g., the right portion) of the memory cells 320 in an even-numbered column, and may overlap with a second portion (e.g., the left portion) of the memory cells 320 in an odd-numbered column.

[0066] According to this embodiment, the spacing P32 of the second conductor 330 can be substantially the same as the spacing P3 of the storage cell 320. That is, when the spacing P3 of the storage cell 320 is 2F, the spacing P32 of the second conductor 330 can also have a value of 2F. The centers of the second conductor 330 and the centers of the storage cell 320 can be arranged to be offset from each other relative to the first direction. This offset arrangement of the two centers of the two elements (e.g., the center of the second conductor 330 and the center of the storage cell 320) can be referred to as a shape with offset spacing.

[0067] Unlike this embodiment, the first conductor 310 may extend in the second direction to overlap with a plurality of memory cells 320 arranged in the second direction. In this case, the plurality of first conductors 310 may be arranged to be spaced apart from each other in a direction perpendicular to the second direction and corresponding to the width direction of the first conductors 310, and the centers of the first conductors 310 and the centers of the memory cells 320 may be arranged to substantially overlap in the width direction of the first conductors 310, i.e., in a shape of spacing.

[0068] In the above embodiments, it has been described how to prevent pitch reduction by arranging one of the upper and lower conductors in a shape deviating from the pitch; however, the disclosed technology is not limited thereto. In another embodiment, both the upper and lower conductors can be arranged in a shape deviating from the pitch. This will be referred to... Figure 4A and Figure 4B Described exemplarily.

[0069] Figure 4A This is a plan view illustrating a semiconductor memory according to another embodiment of the disclosed technology, and Figure 4B It is along Figure 4A The cross-sectional view taken along line A4-A4′. The main differences from the embodiments described above will be described.

[0070] refer to Figures 4A to 4BThe semiconductor memory according to this embodiment may include: a substrate 400; a plurality of first conductors 410 formed on the substrate 400 and extending in a fifth direction; a plurality of second conductors 430 formed on the first conductors 410 and spaced apart from the first conductors 410 and extending in a fourth direction; and a plurality of memory cells 420 overlapping the intersection region of the first conductors 410 and the second conductors 430 between the first conductors 410 and the second conductors 430.

[0071] Storage unit 420 may include: conventional storage unit 420R, which performs the function of storing data; and dummy storage unit 420D, which does not perform any function electrically.

[0072] As an example, a conventional memory cell 420R may include a variable resistor element that switches between different resistance states based on a voltage or current applied via a lower end connected to a first conductor 410 and an upper end connected to a second conductor 430 to store different data. Furthermore, as an example, the conventional memory cell 420R may have a multi-layer structure including a lower electrode layer 421, a selection element layer 423, an intermediate electrode layer 425, a variable resistor layer 427, and an upper electrode layer 429. A dummy memory cell 420D may be disconnected from at least one of the first conductor 410 and the second conductor 430 to prevent the execution of electrical functions. For this purpose, the dummy memory cell 420D may have the same structure as the conventional memory cell 420R, omitting at least one of the lower electrode layer 421 and the upper electrode layer 429. As an example, as shown in the figure, the dummy memory cell 420D can have a structure that omits the upper electrode layer 429 from the conventional memory cell 420R, and therefore can have a lower electrode layer 421, a select element layer 423, an intermediate electrode layer 425, and a variable resistor layer 427. In this case, since the upper end of the dummy memory cell 420D is covered by the second interlayer insulating layer ILD2, the dummy memory cell 420D and the second conductor 430 can be electrically insulated. However, the disclosed technology is not limited to this, and in another embodiment, the dummy memory cell 420D can have a structure that omits the lower electrode layer 421 from the conventional memory cell 420R, or a structure that omits both the lower electrode layer 421 and the upper electrode layer 429 from the conventional memory cell 420R. When the dummy memory cell 420D has a structure that omits the lower electrode layer 421 from the conventional memory cell 420R, the dummy memory cell 420D can be electrically insulated from the first conductor 410. When the dummy storage cell 420D has a structure that omits the lower electrode layer 421 and the upper electrode layer 429 from the conventional storage cell 420R, the dummy storage cell 420D can be electrically insulated from the first wire 410 and the second wire 430.

[0073] Suppose there exists an imaginary line in the planar diagram that forms multiple equilateral triangles (see reference). Figure 4A (The dashed lines in the diagram represent the equilateral triangles.) If the equilateral triangles are arranged such that six equilateral triangles form an equilateral hexagon, then multiple storage cells 420 can be arranged to overlap with the vertices of the equilateral triangles, respectively. Therefore, the multiple storage cells 420 can be arranged along each of the first, second, and third directions parallel to the three sides of the equilateral triangles. The second direction can form an angle of approximately 60 degrees relative to the first direction, and the third direction can also form an angle of approximately 60 degrees relative to the second direction. As a result, the spacing P4 of the storage cells 420 in the first, second, and third directions can have a constant value. The fourth direction can be substantially perpendicular to the first direction, and the fifth direction can be substantially perpendicular to the second direction.

[0074] A first conductive line 410 may be disposed between the substrate 400 and the memory cell 420. The first conductive line 410 may comprise various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta); metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN); or combinations thereof, and may have a single-layer or multi-layer structure. The first conductive line 410 may extend in a fifth direction to overlap with a plurality of memory cells 420 arranged in the fifth direction, and may be arranged to be spaced apart from each other in a second direction (i.e., in the width direction of the first conductive line 410). In this case, the plurality of memory cells 420 arranged in the fifth direction may not be arranged in a straight line extending along the fifth direction, but may be arranged in a zigzag pattern. Therefore, the first conductive line 410 may only partially overlap with each of the plurality of memory cells 420 arranged in the fifth direction.

[0075] More specifically, when multiple storage cells 420 arranged in a line in the second direction are referred to as a column of storage cells 420, multiple columns of storage cells 420 may be arranged in the fifth direction. When the multiple columns of storage cells 420 include one or more even columns and one or more odd columns, one of the first conductors 410 may overlap with a first portion (e.g., the right side portion) of the storage cells 420 in the odd column and may overlap with a second portion (e.g., the left side portion) of the storage cells 420 in the even column. Therefore, the second portion (e.g., the left side portion) other than the first portion of the storage cells 420 in the odd column may protrude beyond the first conductor 410 without overlapping with the first conductor 410. Furthermore, the first portion (e.g., the right side portion) other than the second portion of the storage cells 420 in the even column may protrude beyond the first conductor 410 without overlapping with the first conductor 410.

[0076] According to this embodiment, the spacing P41 of the first conductor 410 can be substantially the same as the spacing P4 of the storage cell 420. That is, when the spacing P4 of the storage cell 420 is 2F, the spacing P41 of the first conductor 410 can also have a value of 2F. However, in the second direction, the center of the first conductor 410 and the center of the storage cell 420 can be arranged to be offset from each other, that is, in a shape that deviates from the spacing.

[0077] The space between the first conductors 410 can be filled with a first interlayer insulation layer ILD1, and the space between the storage cells 420 can be filled with a second interlayer insulation layer ILD2.

[0078] The second conductor 430 can be disposed above the memory cell 420 and the interlayer insulating layer ILD2. The second conductor 430 can comprise various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta); metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN); or combinations thereof, and can have a single-layer or multi-layer structure. The second conductor 430 can extend in a fourth direction to overlap with a plurality of memory cells 420 arranged in the fourth direction, and can be arranged to be spaced apart from each other in a first direction. In this case, the plurality of memory cells 420 arranged in the fourth direction may not be positioned in a straight line extending along the fourth direction, but may be arranged in a zigzag pattern. Therefore, the second conductor 430 may overlap only partially with each of the plurality of memory cells 420 arranged in the fourth direction.

[0079] More specifically, when a plurality of storage cells 420 arranged in a line in a first direction are referred to as a column of storage cells 420, a plurality of columns of storage cells 420 may be arranged in a fourth direction. When the plurality of columns of storage cells 420 includes one or more even columns and one or more odd columns, one of the second conductors 430 may overlap with a first portion (e.g., the right side portion) of the storage cells 420 in the even columns and may overlap with a second portion (e.g., the left side portion) of the storage cells 420 in the odd columns. Therefore, the second portion (e.g., the left side portion) other than the first portion of the storage cells 420 in the even columns may protrude beyond the second conductor 430 without overlapping with the second conductor 430, and the first portion (e.g., the right side portion) other than the second portion of the storage cells 420 in the odd columns may protrude beyond the second conductor 430 without overlapping with the second conductor 430.

[0080] According to this embodiment, the spacing P42 of the second conductor 430 can be substantially the same as the spacing P4 of the storage cell 420. That is, when the spacing P4 of the storage cell 420 is 2F, the spacing P42 of the second conductor 430 can also have a value of 2F. However, the center of the second conductor 430 and the center of the storage cell 420 can be arranged to be offset from each other in a first direction, that is, in a shape that deviates from the spacing.

[0081] That is, according to this embodiment, the reduction of the spacing P41 of the first conductor 410 and the spacing P42 of the second conductor 430 can be prevented.

[0082] However, in this case, since the two memory cells 420 are located at the intersection of one of the first wires 410 and one of the second wires 430, one of the two memory cells 420 can be used as a regular memory cell 420R, while the other of the two memory cells 420 can be used as a dummy memory cell 420D. In this case, since only the regular memory cell 420R of the two memory cells 420 operates, the operation of the semiconductor memory can proceed without problems.

[0083] The method for manufacturing a semiconductor memory according to this embodiment will be briefly described below.

[0084] First, the first conductive lines 410 can be formed by depositing a conductive material on the substrate 400 and selectively etching the conductive material. The spaces between the first conductive lines 410 can be filled with an insulating material to form a first interlayer insulating layer ILD1.

[0085] Secondly, a material layer for forming the memory cell 420 can be deposited on the first conductor 410 and the first interlayer insulating layer ILD1, and the material layer can be selectively etched to form the memory cell 420. For example, selective etching of the material layer can be performed by an ion beam etching method.

[0086] Secondly, after forming the insulating material to fill the space between the memory cells 420, at least one material layer, such as the conductive layer used to form the upper electrode layer 429, in the region where the dummy memory cells 420D are to be formed can be removed by a masking and etching process. Then, the space from which the conductive layer was removed can be filled with additional insulating material. The insulating material and the additional insulating material can form a second interlayer insulating layer ILD2.

[0087] Secondly, the second wire 430 can be formed by depositing a conductive material on the memory cell 420 and the second interlayer insulating layer ILD2 and selectively etching the conductive material.

[0088] In the above embodiment, the first wire 410 is positioned below the storage cell 420, while the second wire 430 is positioned above the storage cell 420. However, other embodiments are also possible, such that the upper and lower positions of the first wire 410 and the second wire 430 can be changed. For example, the second wire 430 extending in the fourth direction can be positioned below the storage cell 420, while the first wire 410 extending in the fifth direction can be positioned above the storage cell 420.

[0089] In the above embodiment, the fifth direction is substantially perpendicular to the second direction, but other implementations are also possible. For example, the fifth direction may be substantially perpendicular to a third direction. In this case, the first wire 410 may extend in the fifth direction and partially overlap with the storage cell 420 arranged in the fifth direction.

[0090] Although this patent document contains numerous details in the disclosed examples, these should not be construed as limiting the scope of any invention or the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in this patent document may also be implemented in combination in a single embodiment within the context of an individual embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features have been described above as being able to function in certain combinations and even initially claimed in this way, in some cases one or more features from the claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0091] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order, or requiring all illustrated operations to be performed to obtain the desired result. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0092] Only a few embodiments and examples have been described. Other embodiments, enhancements, and modifications can be made based on the description and illustrations in this patent document.

Claims

1. A semiconductor device, comprising: Multiple first conductors; A plurality of second conductors, the plurality of second conductors intersecting with the plurality of first conductors to form an intersection region, and the plurality of second conductors being spaced apart from the plurality of first conductors; as well as Multiple storage cells are arranged to overlap with the intersection region and along lines parallel to a first direction, a second direction, and a third direction. Each storage cell is positioned at a vertex of an imaginary equilateral triangle having three sides parallel to the first direction, the second direction, and the third direction. Each of the first wires extends in a fourth direction perpendicular to the first direction and overlaps with the memory cells arranged in the fourth direction. Each of the second wires extends in a fifth direction perpendicular to the second direction and overlaps with the storage cell arranged in the fifth direction. Wherein, the first wire partially overlaps with each of the memory cells arranged in the fourth direction, and The second conductor partially overlaps with each of the storage cells arranged in the fifth direction.

2. The semiconductor device according to claim 1, wherein, When the storage cells arranged in a line in the first direction are a column of storage cells, multiple columns of storage cells are arranged in the fourth direction. The first wire overlaps with a first portion of the storage cell in the odd-numbered columns and a second portion of the storage cell in the even-numbered columns of the plurality of storage cells. The first part and the second part face each other.

3. The semiconductor device according to claim 1, wherein, When the storage cells arranged in a line in the second direction are a column of storage cells, multiple columns of storage cells are arranged in the fifth direction. The second wire overlaps with the first portion of the storage cells in the odd-numbered columns and the second portion of the storage cells in the even-numbered columns of the plurality of storage cells. The first part and the second part face each other.

4. The semiconductor device according to claim 1, wherein, The spacing between the first conductor and the second conductor is the same.

5. The semiconductor device according to claim 4, wherein, The spacing between the first conductors is the same as the spacing between the storage cells, and the spacing between the second conductors is the same as the spacing between the storage cells.

6. The semiconductor device according to claim 1, wherein, In the first direction, the center of the first conductor and the center of the storage cell are misaligned, and In the second direction, the center of the second conductor and the center of the storage cell are misaligned.

7. The semiconductor device according to claim 1, wherein, The two memory cells that overlap with the intersection area of ​​one of the first wires and one of the second wires include a conventional memory cell and a dummy memory cell.

8. The semiconductor device according to claim 7, wherein, The conventional storage unit is electrically connected to one of the first wires and one of the second wires, and The dummy storage unit is electrically insulated from at least one of the first wire and the second wire.

9. The semiconductor device according to claim 7, wherein, The conventional memory cell includes a stacked structure of a lower electrode layer, a select element layer, an intermediate electrode layer, a variable resistance layer, and an upper electrode layer. The dummy storage cell has the same structure as the structure in which at least one of the lower electrode layer and the upper electrode layer is omitted from the conventional storage cell.

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