Power conversion circuit with short circuit detection function and short circuit detection method thereof

Abstract

A power conversion circuit with short-circuit detection function and a short-circuit detection method thereof. The power conversion circuit includes first and second power converters for generating first and second drive voltages, respectively. The second power converter is a switching converter. In a short-circuit detection mode, the first drive voltage is regulated to a first drive level, and the second power converter operates in a pulse frequency modulation mode to regulate the second drive voltage to a short-circuit detection level. When the switching frequency of the second power converter exceeds a frequency threshold, a short-circuit condition between the second drive voltage and the first drive voltage is determined.

Description

Technical Field

[0001] This invention relates to a power conversion circuit capable of detecting short-circuit conditions. The invention also relates to a short-circuit detection method for a power conversion circuit used for short-circuit detection. Background Technology

[0002] U.S. Patent No. 10,483,755 employs a method different from that of the present invention for short circuit detection.

[0003] In display panels, manufacturing defects or aging components on chips or printed circuit boards can cause short circuits or significant leakage current, which can severely damage the chips, printed circuit boards, or the entire display device. To prevent such problems, many known display panels incorporate short circuit detection and protection during the startup and normal operation phase of the display.

[0004] Figure 1A and 1B This shows a known power conversion circuit with short-circuit detection (short-circuit detection circuit 100) (US Patent No. 10,483,755) and its flowchart. Figure 1A and 1B As shown, in step S100, voltage converter 1 provides a first drive voltage DV1 to the first output node during the short-circuit detection period Tsd. In step S200, comparator 210 determines whether the amplitude of the second drive voltage DV2 at the second output node exceeds the amplitude of the reference voltage Vref. When the second drive voltage DV2 is higher than the reference voltage Vref, it indicates that the resistance between the first and second output nodes is lower than the short-circuit resistance threshold, and the system can be shut down. On the other hand, if the amplitude of the second drive voltage DV2 does not exceed the amplitude of the reference voltage Vref, after the short-circuit detection period Tsd, voltage converter 2 provides a second drive voltage DV2 with an operating level from the second output node. Summary of the Invention

[0005] From one perspective, the present invention provides a power conversion circuit comprising: a first power converter for generating a first drive voltage; and a second power converter including at least one switch for switching an inductor to generate a second drive voltage; wherein in an operating mode, the first drive voltage and the second drive voltage are respectively adjusted to a first drive level and a second drive level to serve as a supply voltage for driving a load; wherein in a short-circuit detection mode, the first drive voltage is adjusted to the first drive level, and the second power converter is configured to operate in a pulse frequency modulation mode to modulate the second drive voltage to a short-circuit detection level, wherein when all switching frequencies of the second power converter exceed a frequency threshold, a short circuit is determined to have occurred between the second drive voltage and the first drive voltage; wherein the switching frequency relates to a leakage current between the second drive voltage and the first drive voltage, and in the short-circuit detection mode, a load current consumed by the load is less than a predetermined level.

[0006] In a preferred embodiment, the switching frequency is proportional to the leakage current or proportional to the leakage current plus an offset current, wherein the offset current is the current consumed by the second power converter from the second drive voltage when the second drive voltage is generated.

[0007] In a preferred embodiment, in the short-circuit detection mode, the first switch of the at least one switch of the second power converter is switched in a fixed on-time switching manner.

[0008] In a preferred embodiment, in the short-circuit detection mode, the second power converter operates in a discontinuous conduction mode.

[0009] In a preferred embodiment, the second power converter includes: a power stage circuit including a first switch and a second switch for switching the inductor in the operating mode to generate the second drive voltage; a switching control circuit for generating a control signal to control the first switch and the second switch according to the difference between the second drive voltage and a reference voltage; and a frequency detection circuit for measuring the switching frequency of the control signal in the short-circuit detection mode to determine whether the switching frequency exceeds the frequency threshold, and thus determine whether the short-circuit state has occurred.

[0010] In a preferred embodiment, in the short-circuit detection mode, the second switch is controlled to be non-conducting, causing the second power converter to operate in an asynchronous mode, wherein at least a portion of a current in the inductor flows through an internal diode of the second switch.

[0011] In a preferred embodiment, the power stage circuit further includes a third switch, wherein in the short-circuit detection mode, the third switch is controlled to be non-conducting, wherein in the operation mode, the second switch and the third switch are used to switch the inductor to generate the second drive voltage and control the second drive voltage to the second drive level.

[0012] In a preferred embodiment, in the operating mode, the first switch is controlled to be off, wherein the second and third switches are controlled to switch by pulse width modulation to generate the second driving voltage and control the second driving voltage to the second driving level.

[0013] In a preferred embodiment, the first switch is connected between the first driving voltage and one end of the inductor, wherein in the short-circuit detection mode, the second driving voltage is generated by switching the first switch to convert the first driving voltage, wherein the second driving voltage is adjusted to the short-circuit detection level.

[0014] In a preferred embodiment, the first switch is connected between the first driving voltage and a switching node, the second switch is connected between the switching node and the second driving voltage, the third switch is connected between an input voltage and the switching node, and the inductor is connected between the switching node and a ground node, such that the second power converter is configured as a buck-boost DC-DC converter.

[0015] In a preferred embodiment, the switching control circuit includes: a comparison circuit for comparing the second driving voltage with a reference voltage to generate a comparison output signal; and a pulse frequency modulation circuit for modulating a clock signal with a constant pulse width using the comparison output signal in the short-circuit detection mode to generate the control signal, thereby controlling the first switch to operate in the pulse frequency modulation mode.

[0016] In a preferred embodiment, the frequency detection circuit counts the number of pulses of the control signal within a predetermined time period to measure the switching frequency of the control signal.

[0017] In a preferred embodiment, the amplitude of the short-circuit detection level is smaller than the amplitude of the second driving level.

[0018] From another perspective, the present invention provides a short-circuit detection method for detecting a short-circuit state between a first driving voltage and a second driving voltage, wherein the second driving voltage is generated by controlling at least one switch for switching an inductor; wherein in an operating mode, the first driving voltage and the second driving voltage are respectively adjusted to a first driving level and a second driving level as supply voltages for driving a load; wherein the short-circuit detection method is implemented in a short-circuit detection mode, the short-circuit detection method comprising: adjusting the first driving voltage to the first driving level; controlling the at least one switch to operate in a pulse frequency modulation mode to adjust the second driving voltage to a short-circuit detection level; and detecting the short-circuit state by determining whether the switching frequency of the at least one switch exceeds a frequency threshold; wherein the switching frequency is related to a leakage current between the second driving voltage and the first driving voltage, and in the short-circuit detection mode, a load current consumed by the load is less than a predetermined level.

[0019] In a preferred embodiment, the switching frequency is proportional to the leakage current or proportional to the leakage current plus an offset current, wherein the offset current is consumed from the second drive voltage by operating the at least one switch when the second drive voltage is generated.

[0020] In a preferred embodiment, in the short-circuit detection mode, a first switch of the at least one switch is switched using a fixed on-time switching method.

[0021] In a preferred embodiment, in the short-circuit detection mode, the at least one switch operates the inductor in a discontinuous conduction mode.

[0022] In a preferred embodiment, the at least one switch includes a first switch and a second switch for switching the inductor in the operating mode to generate the second driving voltage. The step of controlling the at least one switch includes: generating a control signal to control the first switch and the second switch according to the difference between the second driving voltage and a reference voltage; and measuring the switching frequency of the control signal in the short-circuit detection mode to determine whether the switching frequency exceeds the frequency threshold, thereby determining whether the short-circuit state has occurred.

[0023] In a preferred embodiment, the step of controlling the at least one switch further includes: operating the first switch and the second switch in an asynchronous mode by controlling the second switch to be non-conducting, wherein at least a portion of a current in the inductor flows through an internal diode of the second switch.

[0024] In a preferred embodiment, the at least one switch further includes a third switch, wherein in the short-circuit detection mode, the third switch is controlled to be non-conducting, wherein in the operation mode, the second switch and the third switch are used to switch the inductor to generate the second drive voltage and control the second drive voltage to the second drive level.

[0025] In a preferred embodiment, in the operating mode, the first switch is controlled to be off, wherein the second and third switches are controlled to switch by pulse width modulation to generate the second driving voltage and control the second driving voltage to the second driving level.

[0026] In a preferred embodiment, the step of generating the control signal includes: comparing the second driving voltage with a reference voltage to generate a comparison output signal; and using the comparison output signal to modulate a clock signal with a constant pulse width in the short-circuit detection mode to generate the control signal, thereby controlling the first switch to operate in the pulse frequency modulation mode.

[0027] In a preferred embodiment, the step of measuring the switching frequency includes: counting the number of pulses of the control signal within a predetermined time period to measure the switching frequency of the control signal.

[0028] In a preferred embodiment, the amplitude of the short-circuit detection level is smaller than the amplitude of the second driving level.

[0029] This invention proposes a novel short-circuit detection method that utilizes the characteristic that the operating frequency of the power supply circuit in a display panel is proportional to the leakage current relative to the supply voltage in the panel. By employing a simple digital circuit, the leakage current can be detected, and the power supply circuit can be shut down when necessary to prevent damage to the entire system.

[0030] This invention does not utilize analog circuitry for short-circuit detection; it can be implemented using a digital circuit employing a pulse counter and multiple digital gates. Therefore, it saves circuit space and improves reliability. Furthermore, the short-circuit detection level can be easily adjusted through simple digital programming.

[0031] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0032] Figure 1A Show the known short-circuit detection circuit.

[0033] Figure 1B Is it displayed corresponding to Figure 1A The flowchart of a known short-circuit detection circuit.

[0034] Figure 2This is a block diagram showing a power conversion circuit with short-circuit detection function according to an embodiment of the present invention.

[0035] Figure 3 This is a waveform diagram showing the operation according to an exemplary embodiment of the present invention.

[0036] Figure 4 This is a block diagram showing a power conversion circuit with short-circuit detection function according to an embodiment of the present invention.

[0037] Figure 5 This is according to the present invention, corresponding to Figures 2-4 Flowchart of short circuit detection.

[0038] Figures 6A-6K Various topologies suitable for implementing the power stage circuits of this invention are shown.

[0039] Figure 7 This is an operational waveform diagram showing an embodiment of a power converter operating in pulse frequency modulation (PFM) mode according to the present invention.

[0040] Figure 8 This is a characteristic graph showing the switching frequency versus leakage resistance according to an embodiment of the present invention.

[0041] Figure 9 This is a schematic diagram showing a power converter according to an embodiment of the present invention.

[0042] Figure 10 This is a schematic diagram showing a switching control circuit according to an embodiment of the present invention.

[0043] Figure 11 This is a schematic diagram illustrating a pulse frequency modulation circuit according to a specific embodiment of the present invention.

[0044] Figure 12 This is a schematic diagram of a frequency detection circuit according to a specific embodiment of the present invention.

[0045] Explanation of symbols in the diagram

[0046] 10: First power converter

[0047] 20,920: Second power converter

[0048] 21, 121: Switching control circuit

[0049] 22: Frequency Detection Circuit

[0050] 23: Power Stage Circuit

[0051] 30: Load

[0052] 100: Short circuit detection circuit

[0053] 200: Power conversion circuit

[0054] 210: Comparator Circuit

[0055] 220: Pulse Width Modulation Circuit

[0056] 230: Pulse frequency modulation circuit

[0057] 232: On-time generation circuit

[0058] 234: Multiplication Circuit

[0059] 236: Pulse Counter

[0060] 238: Logic Circuits

[0061] 240: Selection and drive circuit

[0062] 400: Power Conversion Circuit

[0063] CPO: Comparison output signal

[0064] Db: Internal diode

[0065] DV1: First driving voltage

[0066] DV2: Second driving voltage

[0067] ELVDD, ELVSS: Drive voltage

[0068] ENscd: Mode control signal

[0069] Fct: Fixed conduction time clock signal

[0070] Fref: Reference clock signal

[0071] Hdrv, Ldrv, Sdrv: Control signals

[0072] HSW: First upper bridge switch

[0073] ILD: Load Current

[0074] ILL: Inductor current

[0075] Ios: Offset current

[0076] Iref: Reference current

[0077] Iscd: Leakage current

[0078] Lbb: Inductor

[0079] LSW: Lower Bridge Switch

[0080] PFO: Pulse Frequency Modulation Signal

[0081] PWO: Pulse Width Modulation Signal

[0082] Rscd: Leakage resistance value

[0083] S1, S2: Slope

[0084] S10, S20, S30, S40, S50, S60, S100, S200: Steps

[0085] Sscd: Detection output signal

[0086] SSW: Second upper bridge switch

[0087] t1, t2, t3, t4: Time points

[0088] Toff: Non-conducting time

[0089] Ton: On-time

[0090] Topr: Operation Period

[0091] Tpf: Periodic Time

[0092] Tscd: Short circuit detection period

[0093] Tz: Time

[0094] Vdrvn, Vdrvp: Driver bits

[0095] Vdrvp': Level

[0096] Vin: Input voltage

[0097] Vout, Vout1, Vout2: Output power

[0098] Vref, Vsfr: Reference voltage

[0099] Vscd: Short Circuit Detection Position Detailed Implementation

[0100] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0101] Figure 2 This is a block diagram showing a power conversion circuit with short-circuit detection function according to an embodiment of the present invention. Figure 3This is a waveform diagram of operation according to an exemplary embodiment of the present invention. In one embodiment, the power conversion circuit 200 includes a first power converter 10 and a second power converter 20 for generating drive voltages ELVDD and ELVSS, respectively. In one embodiment, the drive voltages ELVDD and ELVSS can serve as the supply voltages for driving a load 30, which may be, for example, an organic light-emitting diode (OLED) display panel. The load current consumed by the load 30 is denoted as ILD. In a particular embodiment, during the operation period Topr, the drive voltage ELVDD is a positive voltage (e.g., Vdrvp), and the drive voltage ELVSS is a negative voltage (e.g., drive level Vdrvn). During the operation period Topr, the load current ILD may be a non-zero value.

[0102] In a non-limiting embodiment, such as Figure 3 As shown, after the drive voltage ELVDD startup procedure ends (e.g., at time t1) and the drive voltage ELVDD is adjusted to a predetermined drive level Vdrvp, during the short-circuit detection period Tscd, the drive voltage ELVSS is started and adjusted to a predetermined short-circuit detection level Vscd (e.g., at time t2) for short-circuit detection. In one embodiment, during the short-circuit detection period Tscd, the load 30 can be configured to not consume power. In other words, during the short-circuit detection period Tscd, the load current ILD can be zero.

[0103] In one embodiment, before the short-circuit detection period Tscd, the drive voltage ELVDD first rises slowly to level Vdrvp' and then slowly rises to the drive level Vdrvp.

[0104] like Figure 2 As shown, leakage resistance 40 is used to illustrate the equivalent resistance of any possible leakage current path between drive voltages ELVDD and ELVSS, excluding load 30, where the resistance value of leakage resistance 40 is Rscd. If there is a finite impedance between drive voltages ELVDD and ELVSS, leakage current flows from drive voltage ELVDD to drive voltage ELVSS, as... Figure 2 The Iscd annotation.

[0105] The second power converter 20 is a switching power converter according to the present invention. The second power converter 20 can be configured as follows: Figures 6A-6KAny of the power converter topologies shown, such as a buck converter, boost converter, buck-boost converter, inverting buck-boost converter, and flyback converter. The second power converter 20 includes at least one switch for switching an inductor to convert the input voltage Vin into an output power supply Vout (corresponding to the drive voltage ELVSS).

[0106] In one embodiment, during the short-circuit detection period Tscd, the second power converter 20 is operated in pulse frequency modulation mode (PFM), wherein the switching frequency of the second power converter 20 operating in pulse frequency modulation mode is called Fpf. The switching frequency Fpf is related to the magnitude of the leakage current Iscd.

[0107] In one particular embodiment, because the second power converter 20 must supply or draw a current equal to the leakage current Iscd to maintain its output voltage at the short-circuit detection level Vscd, the output current of the second power converter 20 is proportional to the magnitude of the leakage current Iscd. Therefore, the magnitude of the leakage resistance value Rscd can be estimated using a frequency detection circuit. From another perspective, in this embodiment, the switching frequency Fpf is inversely proportional to the leakage resistance value Rscd. Utilizing the characteristics described herein, a short-circuit state can be detected by comparing the switching frequency Fpf with a predetermined frequency threshold Fth.

[0108] Figure 4 This is a block diagram showing a power conversion circuit 400 with short-circuit detection function according to an embodiment of the present invention. In practice, the second power converter 20 can provide or consume a certain amount of current through its output terminal, such as... Figure 4 The term Ios is used to indicate this. More specifically, the offset current Ios is the current consumed by the internal circuitry of the second power converter 20 when operating to generate the drive voltage ELVSS. In this embodiment, the switching frequency Fpf of the second power converter 20, in addition to being inversely proportional to the leakage resistance value Rscd, also has an offset, which is proportional to the offset current Ios. Therefore, whether a short-circuit condition has occurred can still be detected by measuring and comparing the switching frequency Fpf with a frequency threshold Fth, which may correspond to a current threshold related to the sum of a predetermined leakage resistance value Rscd and the offset current Ios.

[0109] Figure 5 Is it displayed corresponding to Figure 2 and Figure 4The short-circuit detection flowchart is as follows. In one embodiment, during the short-circuit detection period Tscd, firstly, in step S10, the first power converter 10 is started; then, in step S20, the second power converter 20 is started and operates in pulse frequency modulation mode. Next, in step S30, the switching frequency Fpf is measured, and in step S40, the switching frequency Fpf is compared with a predetermined frequency threshold Fth. In step S50, if the measured switching frequency Fpf exceeds (e.g., is greater than) the frequency threshold Fth, a short-circuit state is detected. In step S60, if the measured switching frequency Fpf does not exceed the frequency threshold Fth, it is determined that the power conversion circuit is not short-circuited. In one embodiment, then in step S60, an operating mode can be further entered.

[0110] In one particular embodiment, the first power converter 10 is a boost DC-to-DC converter for generating the drive voltage ELVDD, while the second power converter 20 is an inverting buck DC-to-DC converter for generating the drive voltage ELVSS. Typical boost DC-to-DC converters and buck DC-to-DC converters can be found in reference to [reference needed]. Figure 6C and Figure 6E .

[0111] Figure 7 This is an operational waveform diagram illustrating an embodiment of a second power converter 20 operating in pulse frequency modulation mode (PFM) according to the present invention. Please also refer to... Figure 9 This is a schematic diagram illustrating a power converter according to an embodiment of the present invention. In one embodiment, in a short-circuit detection mode, the second power converter 20 operates in a discontinuous conduction mode with a fixed on-time Ton. It should be noted that when operating in the discontinuous conduction mode with a fixed on-time Ton, the switching frequency is proportional to the average inductor current, which is equal to the output current of the second power converter 20 (i.e., the load current ILD plus the leakage current Iscd). Figure 7 As shown, during the on-time Ton, the inductor current ILL rises gradually with a slope S1, which is equal to Vins / L. During the off-time Toff, the inductor current ILL decreases gradually with a slope S2, which is equal to |Vscd| / L. During time Tz, the inductor current ILL is zero. The period corresponding to the switching frequency is Tpf = 1 / Fpf = Ton + Toff + Tz.

[0112] Therefore, the mathematical equation 1 for the switching frequency Fpf of the second power converter 20 is derived as follows:

[0113] Where L is the inductance Lbb of the second power converter 20 (e.g., Figure 9 The inductance value (shown) is Ton, where Ton is the pulse width of the pulse frequency modulation (PFM) pulse of the second power converter 20, and Vins is the power supply voltage of the second power converter 20.

[0114] In a preferred embodiment, the drive voltage ELVDD is used as the supply voltage for the second power converter 20, such as... Figure 9 As shown, this allows the supply voltage of the second power converter 20 to be a fixed value. Therefore, Vins can be replaced by Vdrvp, resulting in the following equation 2:

[0115] Assuming all variables on the right-hand side of Equation 2 are constant except for Rscd, the switching frequency Fpf will depend solely on the leakage resistance value Rscd. As described above, in this embodiment, Equation 2 indicates that the switching frequency Fpf is inversely proportional to the leakage resistance value Rscd.

[0116] Therefore, the frequency threshold Fth of the switching frequency Fpf can be derived from the leakage resistance threshold of the leakage resistance value Rscd, and can be used to detect short circuit conditions.

[0117] Figure 8 This is a graph showing the switching frequency Fpf as a function of the leakage resistance value Rscd. In this embodiment, the variables Vdrv, Vscd, L, Ton, and Ios are configured as 4.6V, -0.8V, 2.2nH, 35ns, and 2mA, respectively. Figure 8 As shown, the switching frequency Fpf is clearly inversely proportional to the leakage resistance value Rscd, and its sensitivity to the leakage resistance value Rscd is quite significant. This phenomenon helps to achieve high short-circuit detection accuracy. As a non-limiting and exemplary embodiment, the target leakage resistance value Rscd for short-circuit detection can be selected as 1.8 kOhm, and the corresponding frequency threshold Fth is 679 kHz. Therefore, when the measured switching frequency Fpf is higher than the frequency threshold Fth (679 kHz), the outputs of the first power converter 10 and the second power converter 20, i.e., the drive voltages ELVDD and ELVSS, will be judged as short circuits.

[0118] Reference Figure 9 The second power converter 920 corresponds, for example, to Figure 2 The second power converter 20 is shown. In one embodiment, the second power converter 920 includes a switching control circuit 21, a frequency detection circuit 22, and a power stage circuit 23.

[0119] Please refer to Figure 9 and Figure 3The reference voltage Vsfr can be adjusted by the mode control signal ENscd. More specifically, in short-circuit detection mode (e.g., corresponding to...) Figure 3 During the short-circuit detection period Tscd shown, when the mode control signal ENscd is enabled, the reference voltage Vsfr is configured to be equal to or related to the short-circuit detection level Vscd, while in the operating mode (e.g., corresponding to...) Figure 3 During the operation period Topr shown (when the mode control signal ENscd is disabled), the reference voltage Vsfr is configured to be equal to or related to the drive level Vdrvn. In one embodiment, the amplitude of the short-circuit detection level Vscd is smaller than the amplitude of the drive level Vdrvn, so that the aforementioned frequency threshold Fth can be lower (compared to if adjusted to the drive level Vdrvn), thereby improving the sensitivity to short-circuit detection.

[0120] In this embodiment, the power stage circuit 23 is configured as a buck-boost DC-DC converter and includes a first upper-bridge switch HSW, a second upper-bridge switch SSW, and a lower-bridge switch LSW. More specifically, the first upper-bridge switch HSW is connected between the input voltage Vin and the switching node LX. The lower-bridge switch LSW is connected between the switching node LX and the drive voltage ELVSS. The second upper-bridge switch SSW is connected between a regulated voltage and the switching node LX. An inductor Lbb is connected between the switching node LX and the ground node. In a non-limiting embodiment, these switches may be metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0121] In a preferred embodiment, in the short-circuit detection mode, one end of the second upper bridge switch SSW is connected to the drive voltage ELVDD (corresponding to the aforementioned regulated voltage) to adjust the drive voltage ELVSS to the short-circuit detection level Vscd, which will promote a more consistent dependence between the switching frequency Fpf and the leakage current Iscd.

[0122] The switching control circuit 21 is used to generate control signals Hdrv, Sdrv and Ldrv to control the first upper bridge switch HSW, the second upper bridge switch SSW and the lower bridge switch LSW according to the reference voltage Vsfr, the drive voltage ELVSS and the mode control signal ENscd.

[0123] In one embodiment, in the operating mode, the first upper bridge switch HSW and the lower bridge switch LSW are controlled to switch the inductor Lbb to generate a drive voltage ELVSS to reach the drive level Vdrvn, wherein the second upper bridge switch SSW is controlled to be non-conducting. In the short-circuit detection mode, the second upper bridge switch SSW is used to switch the inductor Lbb to generate a drive voltage ELVSS to reach the short-circuit detection level, wherein the first upper bridge switch HSW and the lower bridge switch LSW are controlled to be non-conducting, the details of which will be described later.

[0124] In the operating mode (Topr), i.e., when the mode control signal ENscd is disabled, the switching control circuit 21 controls the first upper bridge switch HSW and the lower bridge switch LSW to switch the inductor Lbb, thereby adjusting the drive voltage ELVSS to the drive level Vdrvn, which, together with the drive voltage ELVDD, is used to drive the load 30. In one embodiment, in the operating mode, the second upper bridge switch SSW may be non-conducting.

[0125] In short-circuit detection mode (Tscd), that is, when the mode control signal ENscd is enabled, the switching control circuit 21 controls the second upper bridge switch SSW to switch it to pulse frequency modulation (PFM) mode, so as to adjust the drive voltage ELVSS to the short-circuit detection level Vscd, wherein the switching frequency Fpf is proportional to the leakage current Iscd or proportional to the leakage current Iscd plus the offset current Ios, as previously described.

[0126] In one embodiment, the physical dimensions of the second upper-bridge switch SSW (e.g., the width-to-length ratio of a MOS transistor channel) are relatively smaller than those of the first upper-bridge switch HSW. Therefore, the switching losses of the second upper-bridge switch SSW are relatively low, especially when the output current of the drive voltage ELVSS is at a low level. In a preferred embodiment, in short-circuit detection mode, the first upper-bridge switch HSW is controlled to be non-conducting, thereby reducing power consumption due to the switching losses of the first upper-bridge switch HSW. Simultaneously, since not switching the first upper-bridge switch HSW also reduces the offset current Ios, it also promotes higher accuracy in short-circuit detection.

[0127] In one embodiment, the lower bridge switch LSW may also be non-conducting in the short-circuit detection mode. In this case, the internal diode Db of the lower bridge switch LSW operates together with the second upper bridge switch SSW as an asynchronous buck-boost DC-DC converter. This reduces switching power loss by not switching the lower bridge switch LSW, thereby enabling short-circuit detection to have lower power consumption and higher accuracy.

[0128] In one embodiment, in short-circuit detection mode, such as Figure 7 As shown, the second power converter 20 operates in discontinuous conduction mode when pulse frequency modulation is performed. Therefore, in addition to saving power, the second power converter 20 operates in asynchronous mode by not turning on the lower bridge switch LSW, thus eliminating the need for zero-crossing detection (ZCD) and further simplifying circuit design.

[0129] In the short-circuit detection mode, the frequency detection circuit 22 measures the pulse frequency modulation switching frequency Fpf according to the control signal Sdrv, and determines whether the measured switching frequency Fpf exceeds the frequency threshold Fth, in order to detect the short-circuit state. In one embodiment, the detection output signal Sscd being enabled indicates that a short-circuit state has occurred. In one embodiment, when a short-circuit state is detected, the detection output signal Sscd can control the shutdown of the first power converter 10, the second power converter 20, and other necessary circuits.

[0130] Figure 10 This is a schematic diagram showing a switching control circuit according to an embodiment of the present invention. The switching control circuit 121 corresponds, for example, to... Figure 9 The switching control circuit 21 is shown. In one embodiment, the switching control circuit 121 includes a comparator circuit 210, a pulse width modulation (PWM) circuit 220, a pulse frequency modulation circuit 230, and a selection and drive circuit 240. The comparator circuit 210 compares the drive voltage ELVSS with the reference voltage Vsfr to generate a comparator output signal CPO. In short-circuit detection mode, the pulse frequency modulation circuit 230 generates a pulse frequency modulation signal PFO based on the comparator output signal CPO, and the selection and drive circuit 240 generates a control signal Sdrv based on the pulse frequency modulation signal PFO to control the switching of the second upper bridge switch SSW. Furthermore, in short-circuit detection mode, the selection and drive circuit 240 also controls the first upper bridge switch HSW and the lower bridge switch LSW to be de-energized based on the generated control signals Hdrv and Ldrv.

[0131] In one embodiment, in the operating mode, the pulse width modulation circuit 220 generates a pulse width modulation signal PWO based on the comparison output signal CPO, and the selection and drive circuit 240 controls the control signals Hdrv and Ldrv based on the pulse width modulation signal PWO to control the switching of the first upper bridge switch HSW and the lower bridge switch LSW, respectively. Furthermore, in the operating mode, the selection and drive circuit 240 also controls the control signal Sdrv to keep the second upper bridge switch SSW off.

[0132] Figure 11 This is a schematic diagram illustrating a pulse frequency modulation circuit according to a specific embodiment of the present invention. In one embodiment, the pulse frequency modulation circuit 230 includes an on-time (Ton) generation circuit 232 and a multiplication circuit 234. The on-time generation circuit 232 is used to generate a fixed on-time clock signal Fct based on a reference clock signal Fref, wherein the fixed on-time clock signal Fct has a fixed pulse width. In one embodiment, the reference clock signal Fref may have a fixed frequency, and the pulse width (i.e., the on-time Ton) may be adjusted to be fixed based on a reference current Iref.

[0133] Multiplication circuit 234 multiplies the fixed on-time clock signal Fct by the comparison output signal CPO to generate a pulse frequency modulated signal PFO. In one embodiment, multiplication circuit 234 includes an AND gate. In short-circuit detection mode, when the voltage level of the drive voltage ELVSS does not exceed the target short-circuit detection level Vscd (e.g., when the comparison output signal CPO is at a high level), the AND gate enables the fixed on-time clock signal Fct, thereby turning on the second upper bridge switch SSW to increase the inductor current ILL. On the other hand, when the voltage level of the drive voltage ELVSS exceeds the target short-circuit detection level Vscd (e.g., when the comparison output signal CPO is at a low level), the AND gate blocks the fixed on-time clock signal Fct, thereby not turning on the second upper bridge switch SSW to reduce the inductor current ILL. Therefore, in short-circuit detection mode, the drive voltage ELVSS will be adjusted to the short-circuit detection level Vscd, and the pulse frequency of the pulse frequency modulated signal PFO will be proportional to the leakage current Iscd.

[0134] Figure 12 This is a schematic diagram of a frequency detection circuit according to a specific embodiment of the present invention. In one embodiment, the frequency detection circuit 22 includes a pulse counter 236 and a logic circuit 238. In one embodiment, the pulse counter 236 counts the number of pulses of the pulse frequency modulation signal PFO over a predetermined time period. The ratio of the count generated by the pulse counter 236 to the predetermined time period indicates the average frequency of the switching frequency Fpf. The logic circuit 238 compares the count obtained by the pulse counter 236 with a counting threshold to determine whether a short circuit has occurred, wherein the counting threshold corresponds to the aforementioned frequency threshold Fth. Since short circuit detection is implemented in the digital domain, the frequency threshold Fth can be adjusted by software programming.

[0135] It is worth noting that, from one perspective, the frequency detection circuit 22 determines the switching frequency Fpf by measuring the pulse density within a predetermined time period.

[0136] In one embodiment, such as Figure 9 The power conversion circuit shown can be simplified by removing the second upper bridge switch SSW. In this alternative case, in short-circuit detection mode, the first upper bridge switch HSW can operate in pulse frequency modulation mode according to the control signal Hdrv to generate a drive voltage ELVSS with a short-circuit detection level Vscd, and the relationship between the frequency of the control signal Hdrv and the leakage current Iscd remains the same as previously described, wherein in this embodiment, the control signal Hdrv is controlled by the pulse frequency modulation signal PFO (e.g., ...). Figure 10 (as shown) is controlled by.

[0137] It is worth noting that, with Figure 3 and Figure 5 In contrast, the short-circuit detection concept proposed in this invention can be applied to situations where the driving voltage ELVSS is turned on first, followed by the driving voltage ELVDD being turned on to a predetermined target value. In this case, in the short-circuit detection mode, the first power converter 10 in the aforementioned pulse frequency modulation mode can detect the short-circuit state according to the switching frequency of the first power converter 10.

[0138] The concept of this invention is based on, for example Figure 9 The buck-boost converter shown is used for illustration; however, other converter topologies, such as... Figures 6A-6K The aforementioned short-circuit detection function can also be used. Considering the differences in current / voltage waveforms between different types of DC-DC converters, the equation for the pulse frequency modulation switching frequency Fpf will differ from the aforementioned equation. However, the characteristics of the pulse frequency modulation frequency and the leakage current are still correlated or proportional.

[0139] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the broadest scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many combinations, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A power conversion circuit, characterized in that, Include: A first power converter for generating a first drive voltage; and A second power converter includes at least one switch for switching an inductor to generate a second drive voltage; In one operating mode, the first driving voltage and the second driving voltage are respectively adjusted to a first driving level and a second driving level to serve as the supply voltage for driving a load. In a short-circuit detection mode, the first driving voltage is adjusted to the first driving level, and the second power converter is used to operate in a pulse frequency modulation mode to modulate the second driving voltage to a short-circuit detection level. When all switching frequencies of the second power converter exceed a frequency threshold, a short circuit is determined to occur between the second driving voltage and the first driving voltage. The switching frequency is related to a leakage current between the second drive voltage and the first drive voltage. In the short-circuit detection mode, the load current consumed by the load is less than a predetermined level. The switching frequency is proportional to the leakage current or proportional to the leakage current plus an offset current, wherein the offset current is the current consumed by the second power converter from the second drive voltage when the second drive voltage is generated.

2. The power conversion circuit as described in claim 1, wherein, In this short-circuit detection mode, one of the at least one switches of the second power converter is switched using a fixed on-time switching method.

3. The power conversion circuit as described in claim 1, wherein, In this short-circuit detection mode, the second power converter operates in a discontinuous conduction mode.

4. The power conversion circuit as described in claim 1, wherein, The second power converter includes: A power stage circuit includes at least one upper bridge switch and one lower bridge switch for switching the inductor to generate the second drive voltage; A switching control circuit is configured to generate a control signal to control at least one upper bridge switch and the lower bridge switch based on the difference between the second drive voltage and a reference voltage; and A frequency detection circuit is used to measure the switching frequency of the control signal in the short circuit detection mode to determine whether the switching frequency exceeds the frequency threshold, and then to determine whether the short circuit state has occurred.

5. The power conversion circuit as described in claim 4, wherein, In this short-circuit detection mode, the lower bridge switch is controlled to be non-conducting, so that the second power converter operates in an asynchronous mode, wherein at least a portion of the current of the inductor flows through an internal diode of the lower bridge switch.

6. The power conversion circuit as described in claim 4, wherein, The at least one upper bridge switch includes a first upper bridge switch and a second upper bridge switch, wherein in the short circuit detection mode, the first upper bridge switch is controlled to be non-conducting, and the second upper bridge switch and the lower bridge switch are used to switch the inductor to generate the second driving voltage and control the second driving voltage to the short circuit detection level.

7. The power conversion circuit as described in claim 6, wherein, In this operating mode, the second upper bridge switch is controlled to be non-conducting, wherein the first upper bridge switch and the lower bridge switch are controlled to switch by pulse width modulation to generate the second driving voltage and control the second driving voltage to the second driving level.

8. The power conversion circuit as described in claim 6, wherein, The second upper bridge switch is connected between the first driving voltage and one end of the inductor. In the short-circuit detection mode, the second driving voltage is generated by switching the second upper bridge switch to convert the first driving voltage. The second driving voltage is adjusted to the short-circuit detection level.

9. The power conversion circuit as described in claim 8, wherein, The second upper bridge switch is connected between the first driving voltage and a switching node, the lower bridge switch is connected between the switching node and the second driving voltage, the first upper bridge switch is connected between an input voltage and the switching node, and the inductor is connected between the switching node and a ground node, so that the second power converter is configured as a buck-boost DC-DC converter.

10. The power conversion circuit as described in claim 6, wherein, The switching control circuit includes: A comparator circuit is used to compare the second driving voltage with a reference voltage to generate a comparison output signal; and A pulse frequency modulation circuit, in the short-circuit detection mode, uses the comparison output signal to modulate a clock signal with a constant pulse width to generate the control signal, thereby controlling the second upper bridge switch to operate in the pulse frequency modulation mode.

11. The power conversion circuit as described in claim 10, wherein, The frequency detection circuit counts the number of pulses of the control signal within a predetermined time period to measure the switching frequency of the control signal.

12. The power conversion circuit as described in claim 1, wherein, The amplitude of the short-circuit detection level is smaller than the amplitude of the second driving level.

13. A short-circuit detection method, characterized in that, A method for detecting a short-circuit state between a first driving voltage and a second driving voltage, wherein the second driving voltage is generated by controlling at least one switch for switching an inductor; wherein in an operating mode, the first driving voltage and the second driving voltage are respectively adjusted to a first driving level and a second driving level as supply voltages for driving a load; wherein the short-circuit detection method is implemented in a short-circuit detection mode, the short-circuit detection method comprising: Adjust the first driving voltage to the first driving level; Control the at least one switch to operate in a pulse frequency modulation mode to adjust the second drive voltage to a short-circuit detection level; as well as The short circuit state is detected by determining whether the switching frequency of at least one switch exceeds a frequency threshold. The switching frequency is related to a leakage current between the second drive voltage and the first drive voltage. In the short-circuit detection mode, the load current consumed by the load is less than a predetermined level. The switching frequency is proportional to the leakage current or proportional to the leakage current plus an offset current, wherein the offset current is consumed from the second drive voltage by operating the at least one switch when the second drive voltage is generated.

14. The short-circuit detection method as described in claim 13, wherein, In this short-circuit detection mode, one of the at least one switches is switched using a fixed on-time switching method.

15. The short-circuit detection method as described in claim 13, wherein, In this short-circuit detection mode, the at least one switch operates the inductor in a discontinuous conduction mode.

16. The short-circuit detection method as described in claim 13, wherein, The at least one switch includes at least one upper bridge switch and a lower bridge switch, which are used to switch the inductor to generate the second driving voltage, wherein the steps of controlling the at least one upper bridge switch and the lower bridge switch include: Generate a control signal to control at least one upper bridge switch and the lower bridge switch based on the difference between the second drive voltage and a reference voltage; and In the short-circuit detection mode, the switching frequency of the control signal is measured to determine whether the switching frequency exceeds the frequency threshold, and then to determine whether the short-circuit state has occurred.

17. The short-circuit detection method as described in claim 16, wherein, The step of controlling the at least one switch further includes: operating the at least one upper bridge switch and the lower bridge switch in an asynchronous mode by controlling the lower bridge switch to be non-conducting, wherein at least a portion of a current in the inductor flows through an internal diode of the lower bridge switch.

18. The short-circuit detection method as described in claim 16, wherein, The at least one upper bridge switch includes a first upper bridge switch and a second upper bridge switch, wherein in the short circuit detection mode, the first upper bridge switch is controlled to be non-conducting, and the second upper bridge switch and the lower bridge switch are used to switch the inductor to generate the second driving voltage and control the second driving voltage to the short circuit detection level.

19. The short-circuit detection method as described in claim 18, wherein, In this operating mode, the second upper bridge switch is controlled to be non-conducting, wherein the first upper bridge switch and the lower bridge switch are controlled to switch by pulse width modulation to generate the second driving voltage and control the second driving voltage to the second driving level.

20. The short-circuit detection method as described in claim 18, wherein, The steps for generating this control signal include: The second driving voltage is compared with a reference voltage to generate a comparison output signal; and In the short-circuit detection mode, the comparison output signal is used to modulate a clock signal with a constant pulse width to generate the control signal, which in turn controls the second upper bridge switch to operate in the pulse frequency modulation mode.

21. The short-circuit detection method as described in claim 20, wherein, The steps for measuring this switching frequency include: The number of pulses of the control signal is counted within a predetermined time period to measure the switching frequency of the control signal.

22. The short-circuit detection method as described in claim 13, wherein, The amplitude of the short-circuit detection level is smaller than the amplitude of the second driving level.

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