System and method for stable intermediate node operation in series stacked phase dc-dc converter

Abstract

A power converter circuit. In one aspect, the power converter circuit includes a first buck converter coupled in series to a second buck converter at a junction, and a control circuit coupled to each of the first and second buck converters. In another aspect, the control circuit is arranged to continuously operate the first buck converter, sense a voltage at the junction, compare the sensed voltage to a first threshold voltage, and disable the second buck converter in response to the sensed voltage being at a voltage lower than the first threshold voltage. In yet another aspect, the control circuit is arranged to continuously operate the first buck converter, compare the sensed voltage to a second threshold voltage, and operate the second buck converter in response to the sensed voltage being at a voltage higher than the second threshold voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to the following commonly assigned U.S. provisional patent applications: No. 63 / 265,611, filed December 17, 2021, entitled “Systems and methods for stable intermediate node operation in series stacked phase DC-DC converters,” and No. 63 / 265,823, filed December 21, 2021, entitled “Phase multiplexed series stacked DC-DC converter,” both of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] The described embodiments generally relate to power converters, and more specifically, the embodiments of the invention relate to systems and methods for stable intermediate node operation in series-stacked phase DC-DC converter circuits. Background Technology

[0004] Today, consumers have access to a wide variety of electronic devices. Many of these devices feature integrated circuits powered by regulated low-voltage DC power supplies. These low-voltage supplies are often generated by dedicated power converter circuits that use a higher voltage input from a battery or other power source. In some applications, the dedicated power converter circuit can be one of the largest power dissipation components in an electronic device, and sometimes it consumes more space than the integrated circuit that powers it. As electronic devices become more complex and compact, there is a growing need for more efficient power converter circuits. Summary of the Invention

[0005] In some embodiments, a power converter circuit is disclosed. The power converter circuit includes: a first buck converter having a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; a second buck converter having a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is series-coupled to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal; An input terminal coupled to the first drain terminal; an output terminal coupled to the first switching node and the second switching node; and control circuitry coupled to each of the first buck converter and the second buck converter, and arranged to continuously operate the first buck converter, wherein the control circuitry is further arranged to: sense a voltage at the junction; compare the sensed voltage with a first threshold voltage, and disable the second buck converter in response to the sensed voltage being below the first threshold voltage; and compare the sensed voltage with a second threshold voltage, and operate the second buck converter in response to the sensed voltage being above the second threshold voltage.

[0006] In some embodiments, the first buck converter and the second buck converter are arranged to produce an output voltage at the output terminal that is lower than the input voltage at the input terminal.

[0007] In some embodiments, the first buck converter and the second buck converter are arranged to control power transfer from the input terminal to the output terminal.

[0008] In some embodiments, the control circuitry includes a window comparator, which includes a first comparator and a second comparator.

[0009] In some embodiments, the first comparator is arranged to receive a voltage at the junction and a first threshold voltage.

[0010] In some embodiments, the second comparator is arranged to receive the voltage at the junction and to receive a second threshold voltage.

[0011] In some embodiments, the output terminal is coupled to the first switching node via a first inductor.

[0012] In some embodiments, the output terminal is coupled to the second switching node via a second inductor.

[0013] In some embodiments, the first inductor is coupled to the first switching node via a first capacitor.

[0014] In some embodiments, the second capacitor is coupled to a junction at its first terminal and to ground at its second terminal.

[0015] In some embodiments, a method of operating a power converter circuit is disclosed. The method includes: providing a first buck converter, the first buck converter including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; providing a second buck converter, the second buck converter including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is series coupled to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal. The control circuit provides an input terminal coupled to the first drain terminal; an output terminal coupled to the first switching node and the second switching node; and a control circuit coupled to each of the first buck converter and the second buck converter; the control circuit continuously operates the first buck converter; the control circuit senses the voltage at the junction; the control circuit compares the sensed voltage with a first threshold voltage; the control circuit disables the second buck converter in response to the sensed voltage being below the first threshold voltage; the control circuit compares the sensed voltage with a second threshold voltage; and the control circuit operates the second buck converter in response to the sensed voltage being above the second threshold voltage.

[0016] In some embodiments, the method further includes generating an output voltage at the output terminal that is lower than the input voltage at the input terminal by a first buck converter and a second buck converter.

[0017] In some embodiments, the method further includes controlling the power transfer from the input terminal to the output terminal by a first buck converter and a second buck converter.

[0018] In some embodiments, a circuit is disclosed. The circuit includes: a first buck converter having a first switching node; a second buck converter having a second switching node and series-coupled to the first buck converter at a junction; an input terminal coupled to the first buck converter; an output terminal coupled to the first switching node and the second switching node; and control circuitry coupled to each of the first buck converter and the second buck converter and arranged to continuously operate the first buck converter, wherein the control circuitry is further arranged to: sense a voltage at the junction; compare the sensed voltage with a first threshold voltage, and disable the second buck converter in response to the sensed voltage being below the first threshold voltage; and compare the sensed voltage with a second threshold voltage, and operate the second buck converter in response to the sensed voltage being above the second threshold voltage. Attached Figure Description

[0019] Figure 1 This describes a series-stacked phase DC-DC power converter circuit with a stable intermediate node according to embodiments of the present disclosure; and

[0020] Figure 2 illustrate Figure 1 The switching sequence and timing diagram of the DC-DC power converter circuit. Detailed Implementation

[0021] The circuits and related techniques disclosed herein generally relate to power converters. More specifically, the circuits, apparatus, and related techniques disclosed herein relate to systems and methods for stable intermediate node operation in series-stacked phase DC-DC converters. In some embodiments, the series-stacked phase DC-DC converter may include a top-phase buck converter and a bottom-phase buck converter, wherein the bottom phase can be switched on and off to maintain the intermediate node of the series-stacked phase DC-DC converter within a preset range. By maintaining the intermediate node of the series-stacked phase DC-DC converter within a preset range, embodiments of this disclosure may be able to eliminate positive feedback loops that may exist in the series-stacked phase DC-DC converter. In this way, operational interruptions of the series-stacked phase DC-DC converter can be prevented, and continuous stable operation of the series-stacked phase DC-DC converter can be achieved.

[0022] In various embodiments, systems and methods for stable intermediate node operation in a series-stacked phase DC-DC converter eliminate the use of relatively high-voltage components in the series-stacked phase DC-DC converter. More specifically, embodiments of this disclosure eliminate positive feedback loops and maintain the intermediate node stability of the series-stacked phase DC-DC converter without using additional capacitors or power path switches. Furthermore, embodiments of this disclosure prevent operational interruptions of the series-stacked phase DC-DC power converter without affecting the efficiency of the power converter. In some embodiments, a series-stacked phase DC-DC converter with a stable intermediate node may have an improved electromagnetic interference (EMI) spectrum. Various inventive embodiments are described herein, including methods, processes, systems, apparatuses, etc.

[0023] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of this invention. The following description is merely illustrative and is not intended to limit the scope, applicability, or configuration of this disclosure. In fact, the following description of the embodiments will provide an enlightening description for those skilled in the art to implement one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments can be practiced without these specific details. The drawings and descriptions are not intended to be limiting. The terms “example” or “exemplary” are used herein to mean “serving as an example, illustration, or description.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous relative to other embodiments or designs.

[0024] Figure 1 This describes a series-stacked phase DC-DC power converter circuit 100 with a stable intermediate node according to an embodiment of the present disclosure. For example... Figure 1 As shown, the power converter circuit 100 may include a top buck converter stage 109 (top phase) and a bottom buck converter stage 111 (bottom phase). In the illustrated embodiment, the top phase 109 and bottom phase 111 buck converter stages may be arranged in series, wherein the top phase 109 is connected to the bottom phase 111 at an intermediate node 107 having a voltage VM. The intermediate node 107 may be coupled to a capacitor 115. The power converter circuit 100 may have an input terminal 110 arranged to receive input power (Vin).

[0025] The top-phase 109 buck converter stage may include a first switch 102 having a gate terminal 150, a drain terminal 157, and a source terminal 152, and a second switch 104 having a gate terminal 154, a drain terminal 155, and a source terminal 156. The first switch 102 and the second switch 104 may be coupled in series at a first switch node 175 having a voltage Vsw1. The bottom-phase 111 buck converter stage may include a third switch 106 having a gate terminal 160, a drain terminal 161, and a source terminal 162, and a fourth switch 108 having a gate terminal 167, a drain terminal 168, and a source terminal 169. The third switch 106 and the fourth switch 108 may be coupled in series at a second switch node 117 having a voltage Vsw2. The first switch node 175 may be coupled to a flying capacitor 112 coupled to an inductor 114. The second switch node 117 may be coupled to an inductor 116. Inductors 114 and 116 may be coupled together at an output terminal 118 having an output voltage Vout. Output terminal 118 may be coupled to capacitor 131 and load 135. Capacitor 131 and load 135 may be coupled to ground 120. In some embodiments, the power converter circuit 100 is arranged to deliver an output voltage Vout at output terminal 118 that is lower than the input voltage Vin at input terminal 110.

[0026] The power converter circuit 100 may include logic and control circuitry 158 coupled to the top phase 109 and the bottom phase 111. The logic and control circuitry 158 may be arranged to generate control signals that control the operation of the buck converter stages of the top phase 109 and the bottom phase 111 to control power delivery from input terminal 110 to output terminal 118. In some embodiments, the bottom phase 111 may be alternately turned on and off by the logic and control circuitry 158, while the top phase 109 continues to operate. In one embodiment, the logic and control circuitry 158 may include a window comparator 128 and a set-reset (S / R) latch 141. The window comparator 128 may sense the voltage VM at intermediate node 107 and compare it to a preset threshold, maintaining the voltage VM within a preset window, for example, within 100 mV below and 10 mV above an ideal value for VM. As will be understood by those skilled in the art to which this disclosure pertains, the value of the preset window may be set to any suitable value. In some embodiments, the ideal value for VM will be Vin / 2.

[0027] Window comparator 128 may include a first comparator 151 and a second comparator 153. The outputs of the first comparator 151 and the second comparator 153 may trigger an S / R latch 141, which may alternately enable / disable the operation of the bottom phase 111. A first input 121 of the first comparator 151 may be connected to an intermediate node 107. A second input 124 of the first comparator 151 may be connected to a first reference voltage, which may be set to a preset threshold, for example, equal to the ideal value of voltage VM plus 10mV. A first input 127 of the second comparator 153 may be connected to the intermediate node 107. A second input 126 of the second comparator 153 may be connected to a second reference voltage, which may be set to a preset threshold, for example, equal to the ideal value of VM minus 100mV. In this way, the intermediate node 107 may be kept within a preset window, for example, within 100mV below and 10mV above the ideal value of VM. In various embodiments, the first comparator 151 may have a hysteresis threshold, which is the same value as a preset threshold above the ideal value of VM. As will be understood by those skilled in the art to which this disclosure pertains, the first reference voltage and the second reference voltage can be set to any suitable value.

[0028] When intermediate node 107 rises above a preset threshold, for example, above Vin / 2 10mV, bottom phase 111 can be turned on and begin switching until intermediate node 107 (VM) drops below a preset threshold, for example, below Vin / 2 100mV, at which point bottom phase is turned off. In this way, intermediate node 107 (VM) may not drop below the preset threshold. This prevents positive feedback from being generated and disrupting the operation of the power converter circuit. Top phase 109 can continue to switch continuously, while bottom phase 111 alternately turns on and off. Although a specific embodiment of the window comparator circuit has been discussed above, those skilled in the art to which this disclosure pertains will understand that intermediate node 107 (VM) can be monitored directly, or a filtered version of intermediate node 107 (VM) can be monitored, or a digital filter can be applied to the comparator output, all within the scope of identifying degraded intermediate node voltages without erroneously triggering the comparator due to noise.

[0029] S / R latch 141 can generate a signal HiZ at node 136. Signal HiZ can enable / disable operation of the bottom phase 111. Power converter circuit 100 may include a first clock generator 142 capable of generating a first clock Φ1 146 and a second clock generator 144 capable of generating a second clock Φ2 148. The first clock 146 can be applied to the gate terminal 150 of the first switch 102, and the inverted version of the first clock 146 can be applied to the gate terminal 154 of the second switch 104. The second clock 148 can be applied to the gate terminal 160 of the third switch 106 via an OR gate 138, and the inverted version of the second clock 148 can be applied to the gate terminal 167 of the fourth switch 108 via an AND gate 140. Although a particular control circuit and algorithm have been discussed above, those skilled in the art to which this disclosure pertains will appreciate that other control circuit architectures and control algorithms can be used for the series-stacked phase DC-DC power converter circuit 100 and are within the scope of this disclosure.

[0030] Now refer to Figure 1 and 2 This illustrates an embodiment of the switching sequence and timing diagram of circuit 100. Figure 2 This describes the waveforms of the signal (Φ1) at the gate of the first switch 102, the signal at intermediate node 107 (VM), the signal HiZ at node 136, and the output voltage (Vout) at output terminal 118. During the first time period 216, where, as shown in Figure 208, the bottom phase 111 is switching, the signal HiZ is low, and therefore the bottom phase 111 is enabled and switchable, while the top phase 109 can switch simultaneously, as shown in Figure 202, where the clock Φ1 at the gate of the first switch 102 is switching. During the first time period 216, the voltage at intermediate node 107 (VM) is stable and then drops rapidly during time period 212 due to the onset of a positive feedback effect. During time period 212, VM continues to drop until it reaches below Vin / 2 100mV, as shown in Figure 206. Then, window comparator 128 triggers S / R latch 141. This causes the "bottom phase switching" period to end and the second time period 218 to begin, where the bottom phase 111 is disabled.

[0031] During the second time period 218, when the bottom phase 111 is disabled and the signal HiZ is high, the bottom phase 111 is disabled, while the top phase 109 continues to switch. During the second time period 218, VM may begin to recover and increase in value. VM continues to increase during the second time period 218 until it reaches 10mV above Vin / 2. Then the window comparator 128 triggers the S / R latch 141. This causes the second time period to end and a new "bottom phase switching" time period to begin. As those skilled in the art to which this disclosure pertains will understand, acceptable values ​​for voltage fluctuations at intermediate node 107 (VM) can be set based on the power converter specifications. Figure 210 shows the voltage (VOUT) at output terminal 118. As can be seen in Figure 210, VOUT is regulated during the first time period 216. During the second time period 218, when the top phase is switching and the bottom phase is disabled, VOUT may not be regulated within the set point. However, this situation is acceptable because the converter may be overloaded beyond its normally specified operating parameters.

[0032] As will be appreciated by those skilled in the art to which this disclosure pertains, the disclosed on / off switching technique for the bottom phase is a technique for reducing the current drawn from the intermediate node, thereby preventing its degradation. Other techniques may be used, such as blanking switching cycles (so that the bottom phase switches only, for example, every other cycle), or forcing the bottom phase's duty cycle to draw less current from the intermediate node, resulting in a lower high-side turn-on time. Furthermore, those skilled in the art to which this disclosure pertains will recognize that other techniques for monitoring the intermediate node and more than one set of comparator thresholds may be used; for example, a 'soft response' may be used to recover from slight degradation of the VM voltage, while a 'hard response' may be used for more significant VM degradation.

[0033] As will be appreciated by those skilled in the art who benefit from this disclosure, additional feedback loops for voltage and / or current at other nodes within the series-stacked phase DC-DC power converter circuit 100 can be used to monitor intermediate nodes. Those skilled in the art will understand that alternative methods exist for controlling the switches in circuit 100 in a manner that achieves overall loop control, and such methods are within the scope of this disclosure. Those skilled in the art will further understand that alternative methods for controlling the switches in circuit 100 can be used to optimize light-load efficiency, or minimize area, and / or minimize electromagnetic interference (EMI), and such methods are within the scope of this disclosure.

[0034] Although this document describes and illustrates systems and methods for stable intermediate node operation in a series-stacked phase DC-DC power converter with respect to a particular configuration of the series-stacked phase DC-DC power converter circuit, embodiments of this disclosure are suitable for use with other configurations of DC-DC power converters. For example, multiphase DC-DC power converter circuits may employ embodiments of this disclosure to alternately switch phases for more efficient operation.

[0035] In some embodiments, the described switch may be formed in silicon or any other suitable semiconductor material. In various embodiments, the described switch may be a transistor. In some embodiments, the described switch may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In various embodiments, the disclosed MOSFET may be entirely formed within a single die well. In some embodiments, the disclosed series-stacked phase DC-DC power converter circuit (including transistors and control circuitry) may be monolithically integrated onto a single die. In various embodiments, the top phase and bottom phase stages may be formed on separate individual dies. In some embodiments, the top phase, bottom phase, and logic and control circuitry, and any combination thereof, may be grouped and formed on separate dies; for example, the top phase and bottom phase may be formed on a single die, and the logic and control circuitry may be formed on a separate die, or the top phase and bottom phase may be formed on the same die as the logic and control circuitry. In various embodiments, the top phase, bottom phase, and logic and control circuitry can all be integrated into a single electronic package, such as, but not limited to, a quad flat no-lead (QFN) package, a dual flat no-lead (DFN) package, or a ball grid array (BGA) package. In some embodiments, the top phase and bottom phase can be individually packaged into an electronic package. In various embodiments, the controller circuitry and / or control logic circuitry can be integrated with the disclosed series-stacked phase DC-DC converter into a single die.

[0036] In the foregoing description, embodiments of this disclosure have been described with reference to numerous specific details that may vary with different implementations. Therefore, the description and drawings should be considered illustrative rather than restrictive. The unique and exclusive reference to the scope of this disclosure, and what the applicant intends to be the scope of this disclosure, is the literal and equivalent scope of the set of claims published in this application, including any subsequent corrections in the specific form of such claims. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of this disclosure.

[0037] Additionally, spatially relative terms such as “bottom” or “top” may be used to describe the relationship of an element and / or feature to another element(s) and / or feature, as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use and / or operation. For example, if the device in the figures is flipped, then an element described as the “bottom” surface may be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0038] The terms “and,” “or,” and “and / or” as used herein may have a variety of meanings, which are also expected to depend at least in part on the context in which such terms are used. Generally, when used to relate a list such as A, B, or C, “or” is intended to mean A, B, and C, used here in an inclusive sense, and A, B, or C, used here in an exclusive sense. Additionally, the term “one or more” as used herein may be used to describe any feature, structure, or property in the singular, or may be used to describe a combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Furthermore, when used to relate a list such as A, B, or C, the term “at least one of…” may be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0039] Throughout this specification, references to “an example,” “an instance,” “some instances,” or “exemplary embodiments” indicate that a particular feature, structure, or characteristic described in connection with a feature and / or instance may be included in at least one feature and / or instance of the claimed subject matter. Therefore, the appearance of the phrases “in an example,” “an instance,” “in some instances,” or “in some embodiments,” or other similar phrases throughout this specification, does not necessarily refer to the same feature, instance, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more instances and / or features.

[0040] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter be limited to the specific instances disclosed, but rather that such claimed subject matter may also encompass all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A power converter circuit, comprising: A first buck converter includes a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, wherein the first source terminal is coupled to the second drain terminal at a first switch node; The second buck converter includes a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the third source terminal is coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is coupled in series to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal. An input terminal, which is coupled to the first drain terminal; An output terminal, which is coupled to the first switch node and the second switch node; as well as A control circuit coupled to each of the first buck converter and the second buck converter, and arranged to operate the first buck converter continuously, wherein the control circuit is further arranged to: Sensing the voltage at the junction; The sensed voltage is compared with a first threshold voltage, and in response to the sensed voltage being below the first threshold voltage, the control circuit disables the second buck converter; as well as The sensed voltage is compared with a second threshold voltage, and the control circuit operates the second buck converter in response to the sensed voltage being above the second threshold voltage.

2. The power converter circuit of claim 1, wherein the first buck converter and the second buck converter are arranged to generate an output voltage at the output terminal that is lower than the input voltage at the input terminal.

3. The power converter circuit of claim 1, wherein the first buck converter and the second buck converter are arranged to control power transfer from the input terminal to the output terminal.

4. The power converter circuit according to claim 1, wherein the control circuit includes a window comparator, the window comparator comprising a first comparator and a second comparator.

5. The power converter circuit of claim 4, wherein the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

6. The power converter circuit of claim 5, wherein the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

7. The power converter circuit according to claim 5, wherein the output terminal is coupled to the first switching node via a first inductor.

8. The power converter circuit according to claim 5, wherein the output terminal is coupled to the second switching node via a second inductor.

9. The power converter circuit of claim 7, wherein the first inductor is coupled to the first switching node via a first capacitor.

10. The power converter circuit of claim 9, wherein the second capacitor is coupled to the junction at its first terminal and to ground at its second terminal.

11. A method of operating a power converter circuit, the method comprising: A first buck converter is provided, the first buck converter including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; A second buck converter is provided, the second buck converter including a third switch having a third gate terminal, a third drain terminal and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is coupled in series to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal; Provides an input terminal coupled to the first drain terminal; Provides output terminals coupled to the first switching node and the second switching node; as well as A control circuit is provided coupled to each of the first buck converter and the second buck converter; The first buck converter is continuously operated by the control circuit; The voltage at the junction is sensed by the control circuit; The control circuit compares the sensed voltage with a first threshold voltage. The second buck converter is disabled by the control circuit in response to the sensed voltage being below the first threshold voltage; The control circuit compares the sensed voltage with a second threshold voltage. as well as The second buck converter is operated by the control circuit in response to the sensed voltage being above the second threshold voltage.

12. The method of claim 11, further comprising generating an output voltage at the output terminal that is lower than the input voltage at the input terminal by the first buck converter and the second buck converter.

13. The method of claim 11, further comprising controlling the power transfer from the input terminal to the output terminal by the first buck converter and the second buck converter.

14. The method of claim 11, wherein the control circuitry includes a window comparator, the window comparator comprising a first comparator and a second comparator.

15. The method of claim 14, wherein the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

16. The method of claim 15, wherein the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

17. A circuit comprising: A first buck converter having a first switching node; A second buck converter has a second switching node and is coupled in series to the first buck converter at a junction; The input terminal is coupled to the first buck converter; An output terminal, which is coupled to the first switch node and the second switch node; as well as A control circuit coupled to each of the first buck converter and the second buck converter, and arranged to operate the first buck converter continuously, wherein the control circuit is further arranged to: Sensing the voltage at the junction; The sensed voltage is compared with a first threshold voltage, and the second buck converter is disabled in response to the sensed voltage being below the first threshold voltage. as well as The sensed voltage is compared with a second threshold voltage, and the control circuit operates the second buck converter in response to the sensed voltage being above the second threshold voltage.

18. The circuit of claim 17, wherein the first buck converter and the second buck converter are arranged to generate an output voltage at the output terminal that is lower than the input voltage at the input terminal.

19. The circuit of claim 17, wherein the first buck converter and the second buck converter are arranged to control power transfer from the input terminal to the output terminal.

20. The circuit of claim 17, wherein the control circuit includes a window comparator, the window comparator comprising a first comparator and a second comparator.

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