Semiconductor structure and method of forming the same

Abstract

This application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate, a bit line structure, a first conductive pillar, an interface layer, a second conductive pillar, and an interposer structure. The substrate has an active region and an isolation structure. The bit line structure is disposed on the active region. The first conductive pillar is disposed on the active region. The interface layer is disposed on the top surface of the first conductive pillar. The second conductive pillar is disposed on the interface layer. The interposer structure is disposed between the first conductive pillar and the bit line structure.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of forming them, and more particularly to semiconductor structures and methods of forming them that can be used as memory devices after processing. Background Technology

[0002] Dynamic Random Access Memory (DRAM), a type of volatile memory, has the advantages of high storage cell density, fast access speed and low cost, and is therefore widely used.

[0003] However, with the trend of semiconductor device miniaturization, the size of memory devices continues to shrink, which increases capacitive coupling between adjacent components or interconnect structures, causing leakage current and / or short circuits, thus adversely affecting the performance of memory devices.

[0004] Therefore, existing semiconductor structures and their fabrication methods do not yet fully meet the requirements in all aspects. Thus, there are still some problems to be overcome regarding semiconductor structures and their fabrication methods that can be further processed into memory devices. Summary of the Invention

[0005] In view of the above problems, the present invention uses a first conductive pillar, an interface layer, a second conductive pillar, and an intermediate structure to collectively form a dielectric plug, thereby reducing the short-circuit risk between the dielectric plug and the bit line structure and improving the electrical characteristics of the semiconductor structure. For example, the contact area between the first and second conductive pillars is increased by adjusting the relative positions, contact areas, and / or material types of the first conductive pillar, interface layer, second conductive pillar, and intermediate structure. For example, increasing the contact area changes the current path flowing through the dielectric plug, thus reducing the overall resistance of the dielectric plug. Accordingly, the parasitic capacitance between the bit line structure and the dielectric plug is effectively reduced, thereby lowering the short-circuit risk between the dielectric plug and the bit line structure.

[0006] According to some embodiments, a semiconductor structure is provided, including a substrate, a bit line structure, a first conductive pillar, an interface layer, a second conductive pillar, and an interposer structure. The substrate has an active region and an isolation structure. The bit line structure is disposed on the active region. The first conductive pillar is disposed on the active region. The interface layer is disposed on the top surface of the first conductive pillar. The second conductive pillar is disposed on the interface layer. The interposer structure is disposed between the first conductive pillar and the bit line structure.

[0007] According to some embodiments, a method for forming a semiconductor structure is provided, comprising: forming an active region in a substrate; forming a plurality of bit line structures on the active region; having an opening between adjacent bit line structures; forming a dielectric structure in the opening; etching the active region to form a recess in the opening; forming a first conductive pillar on the recess; forming an interface layer on the top surface of the first conductive pillar; and forming a second conductive pillar on the interface layer. Attached Figure Description

[0008] Figure 1 The present invention provides some embodiments thereof, which illustrate circuit layout diagrams of semiconductor structures.

[0009] Figures 2 to 14 The diagram illustrates cross-sectional views of the semiconductor structure being formed at various stages, according to some embodiments of the present invention. Detailed Implementation

[0010] Reference Figure 1 The semiconductor structure includes: a substrate 100, an isolation structure 110, an active area AA, a bit line BL, a word line WL, and a storage node contact CC. For ease of explanation, Figure 1 The aforementioned components are only briefly illustrated; however, the semiconductor structure of this application may further include other components. Furthermore, the shapes of the aforementioned components are not limited to the shapes shown. Figure 1 The shape shown is available, and the dimensions can be adjusted according to process or application requirements.

[0011] In some embodiments, the first direction D1 and the second direction D2 are different from each other; for example, the first direction D1 and the second direction D2 are perpendicular to each other, but this application is not limited thereto. For example, the first direction D1 and the second direction D2 may intersect at an angle.

[0012] There can be multiple bit lines BL, which can be disposed on the substrate 100. Each bit line BL can extend along a first direction D1. Adjacent bit lines BL are arranged at a distance in a second direction D2, which is different from the first direction D1. Adjacent bit lines BL can be spaced by the same distance.

[0013] Multiple word lines WL may be provided on the substrate 100. Each word line WL may extend along a second direction D2. Adjacent word lines WL are arranged at a distance in a first direction D1. Adjacent word lines WL may be spaced by the same distance. In some embodiments, the word lines WL may be buried word lines. For example, the gate structure of the word line WL may be lower than the top surface of the substrate 100. In other embodiments, the gate structure of the word line WL may not be lower than the top surface of the substrate 100.

[0014] An isolation structure 110 can be formed in the substrate 100 to define the extent of the active region AA and electrically separate two adjacent active regions AA from each other. Multiple active regions AA can be formed in the substrate 100. Each active region AA extends along a direction having an angle with the first direction D1. The shape of the active region AA is merely an example, and this application is not limited thereto.

[0015] like Figure 1 As shown, each active region AA spans two word lines WL and one bit line BL. Each active region AA and its corresponding bit line BL have an overlapping area and non-overlapping areas on either side of the overlapping area. In each active region AA, there is a bit line contact BC in the overlapping area and a storage node contact CC in the non-overlapping area. In some embodiments, two storage node contacts CC corresponding to an active region AA are respectively disposed outside the two word lines WL passing through this active region AA. The storage node contacts CC may contact a capacitor and are therefore also referred to as capacitor contacts. In some embodiments, the storage node contacts CC are located on the substrate 100, and each storage node contact CC is located between two adjacent bit lines BL and between two adjacent word lines WL. In some embodiments, each bit line BL, when crossing its corresponding word line WL, can be electrically connected to the corresponding area located between the two word lines WL using the bit line contact BC.

[0016] Figures 2 to 14 It is drawn along such Figure 1 The diagram shows a cross-sectional view of line segment XX'.

[0017] Reference Figure 2A substrate 100 is provided. The substrate 100 may be a wafer such as a silicon wafer, a semiconductor-on-insulation (SOI) substrate, or a bulk semiconductor substrate. The substrate 100 may be a multilayer substrate or a gradient substrate. In some embodiments, the substrate 100 may be an elemental semiconductor, including silicon and germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or any combination thereof, but this application is not limited thereto. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate.

[0018] like Figure 2 As shown, active regions AA and isolation structures 110 are formed in substrate 100. For example, active regions AA are first formed in the upper part of substrate 100, and then isolation structures 110 are formed between adjacent active regions AA. In some embodiments, isolation structures 110 may be formed first, and then active regions AA may be formed in substrate 100. Isolation structure 110 may be an oxide such as silicon oxide. In some embodiments, isolation structure 110 may be formed by etching and deposition processes.

[0019] The etching process may include dry etching, wet etching, or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using acidic solutions, alkaline solutions, or solvents to remove at least a portion of the structure to be removed. Furthermore, the etching process may also be purely chemical etching, purely physical etching, or a combination thereof. The deposition process may be chemical deposition, physical deposition, or a combination thereof. Deposition processes may include chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), combinations thereof, or similar processes, but are not limited to these. The isolation structure 110 may be a shallow trench isolation (STI) structure. Furthermore, the required doped regions may be further formed according to the electrical requirements of the semiconductor structure.

[0020] like Figure 2 As shown, in some embodiments, a bit line structure (BLS) is formed on the active region AA. Multiple bit line structures (BLS) may be formed. Each bit line structure (BLS) may include a first conductive layer 220, a second conductive layer 230, and a masking layer 240. The first conductive layer 220 is disposed on the active region AA; the second conductive layer 230 is disposed on the first conductive layer 220; and the masking layer 240 is disposed on the second conductive layer 230. The first conductive layer 220 and / or the second conductive layer 230 may be a single-layer or multi-layer structure. In some embodiments, the materials of the first conductive layer 220 and the second conductive layer 230 may be deposited sequentially on the substrate 100, and then a patterned masking layer 240 is formed on the second conductive layer 230. Subsequently, an etching process is performed to pattern the materials of the first conductive layer 220 and the second conductive layer 230 to obtain the first conductive layer 220 and the second conductive layer 230.

[0021] The first conductive layer 220 and / or the second conductive layer 230 may include a conductive material. The conductive material may include polycrystalline silicon, amorphous silicon, metals such as tungsten, gold, silver, copper, cobalt, or the like, metal nitrides, conductive metal oxides, other suitable materials, or combinations thereof. For example, the first conductive layer 220 may include polycrystalline silicon, and the second conductive layer 230 may include tungsten. In some embodiments, the masking layer 240 may be a hard masking layer. The material of the masking layer 240 may include oxides, nitrides, oxynitrides, carbides, or combinations thereof. In some embodiments, the masking layer 240 may be a nitride such as silicon nitride.

[0022] like Figure 2 As shown, in some embodiments, a bit line dielectric layer 210 is formed on the isolation structure 110. In some embodiments, the bit line dielectric layer 210 is formed on the isolation structure 110 before the first conductive layer 220 is formed on the substrate 100. It should be noted here that, due to Figure 2 Show along Figure 1 A cross-sectional schematic diagram of line segment XX' shows that a bit line dielectric layer 210 is formed on the isolation structure 110 between the two active regions AA in the middle. The bit line dielectric layer 210 may include oxides, nitrides, oxynitrides, high-k materials, or combinations thereof. In some embodiments, the bit line dielectric layer 210 may include an oxide such as silicon oxide. The bit line dielectric layer 210 may be an insulating layer. In some embodiments, the bit line dielectric layer 210 may be formed by a deposition process. In this embodiment, located on... Figure 2 The bitline structure BLS above the leftmost and rightmost active regions AA in the image can be compared with... Figure 1 The bit line contact BC shown is electrically connected, or the bit line structure BLS can be part of the bit line contact BC.

[0023] like Figure 2 As shown, spacer structures 250 can be further formed on the side and top surfaces of the bitline structure (BLS). The spacer structures 250 provide isolation characteristics for the bitline structure (BLS). The spacer structures 250 can be oxides, nitrides, or combinations thereof. For example, the spacer structures 250 can be silicon oxide or silicon nitride.

[0024] The spacer structure 250 can be a single-layer or multi-layer structure. For example, the spacer structure 250 may include a first spacer 251, a second spacer 252, and a third spacer 253. The first spacer 251 may be disposed on the side surface of the bit line structure BLS. Specifically, the first spacer 251 contacts the isolation structure 110, the first conductive layer 220, the second conductive layer 230, and the shielding layer 240. In some embodiments, the first spacer 251 contacts the bit line dielectric layer 210. The second spacer 252 may be disposed on the side surface of the first spacer 251, and the first spacer 251 is located between the second spacer 252 and the bit line structure BLS. The third spacer 253 may be disposed on the side surface of the second spacer 252, and the second spacer 252 is located between the first spacer 251 and the third spacer 253. In some embodiments, the third spacer 253 may be blanket-covered on the second spacer 252, the first spacer 251, and the shielding layer 240.

[0025] The aforementioned spacer structure 250 can be formed by the aforementioned deposition and etching processes. In some embodiments, the first spacer 251 and the third spacer 253 may include silicon nitride, and the second spacer 252 may include silicon oxide. Therefore, the spacer structure 250 may be a nitride-oxide-nitride (NON) structure, but this application is not limited thereto.

[0026] In some embodiments, a substrate 260 may be conformally formed on the active region AA, the isolation structure 110, the spacer structure 250, and the bit line structure BLS. The substrate 260 may be a nitride such as silicon nitride. In some embodiments, the substrate 260 may be a single-layer or multi-layer structure, or the substrate 260 may be omitted. The substrate 260 may be formed using a deposition process.

[0027] like Figure 2 As shown, adjacent bit line structures (BLS) have openings (OPs). The openings (OPs) can be formed on the substrate 260, and the shape of the substrate 260 can correspond to the shape of the openings (OPs). Figure 2 Is along such Figure 1 The diagram shows a cross-sectional view of line segment XX', which reveals two openings OP. However, the number of openings OP is merely an example, and the number of openings OP will vary along the line segment. Figure 1 The cross-sectional schematic diagrams taken from different line segments vary, therefore this application is not limited thereto. In some embodiments, the opening OP has a first height H1 and a first width W1.

[0028] The dielectric plug formed in the open OP and electrically connected to the capacitor is described in detail below.

[0029] Reference Figure 3 A dielectric material 270 is formed in the opening OP. The dielectric material 270 can be formed by a deposition process to fill the opening OP. In some embodiments, the dielectric material 270 completely fills the opening OP. The dielectric material 270 contacts the side and bottom surfaces of the opening OP. The dielectric material 270 may include oxides, nitrides, oxynitrides, carbides, or combinations thereof. In some embodiments, the dielectric material 270 may be silicon oxide.

[0030] Reference Figure 4 A photoresist layer PR is formed on the dielectric material 270. The photoresist layer PR covers the substrate 260 and the dielectric material 270. In some embodiments, the photoresist layer PR covers a portion of the dielectric material 270 and exposes another portion of the dielectric material 270. The width of the photoresist layer PR covering the dielectric material 270 is a second width W2. The second width W2 is smaller than the first width W1. In some embodiments, the area ratio of the top surface of the dielectric material 270 and the subsequently formed first conductive pillar is adjusted by the range of 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or any combination thereof of the total area of ​​the top surface of the dielectric material 270 covered by the photoresist layer PR. That is, the width of the subsequently formed intermediate structure can be adjusted by the coverage area of ​​the photoresist layer PR.

[0031] Reference Figure 5 Continuing from the above, an etching process is performed to pattern the dielectric material 270 using the photoresist layer PR as an etching mask, thereby forming a patterned dielectric material 271 and exposing the side surface S1 and bottom surface S2 of the opening OP. The dielectric material 271 covers one side surface of the opposite side surface of the opening OP and exposes the other side surface S1 of the opposite side surface. The dielectric material 271 exposes a portion of the bottom surface S2 of the opening OP. The width of the patterned dielectric material 271 is substantially the same as the second width W2. The width of the dielectric material 271 can be adjusted according to electrical requirements. The dielectric material 271 may cover the top surface of the isolation structure 110. In some embodiments, the dielectric material 271 may further cover the top surface of the active region AA. In some embodiments, removal processes such as ashing and / or wet stripping may be performed to remove the photoresist layer PR.

[0032] Reference Figure 6Continuing from the above, a first etching process is performed to reduce the height of the dielectric material 271, such that the top surface of the dielectric material 271 is lower than the top surface of the bit line structure BLS, thereby forming a dielectric structure 272 in the opening OP. In some embodiments, the dielectric structure 272 has a second height H2. The second height H2 is smaller than the first height H1. In some embodiments, the height of the dielectric structure 272 is substantially the same as the height of the second conductive layer 230. Since a large parasitic capacitance is easily generated near the second conductive layer 230, when the height of the dielectric structure 272 is substantially the same as the height of the second conductive layer 230, the parasitic capacitance can be reduced by the dielectric structure 272. In some embodiments, the second height H2 of the dielectric structure 272 can be adjusted according to electrical requirements. In some embodiments, the first etching process is an etch-back process. The depth of the etch-back process can be controlled by the etch-back process parameters, thereby controlling the height of the dielectric structure 272.

[0033] like Figure 6 As shown, a second etching process is performed on the active region AA to form a recess 273 in the opening OP. Specifically, the second etching process is performed on the active region AA and a portion of the substrate 260 to remove a portion of the substrate 260 and a portion of the active region AA, thereby forming a recess 273 with a depth D. In some embodiments, the recess 273 is located between adjacent isolation structures 110. After performing the second etching process, the active region AA is exposed. In some embodiments, the bottom surface of the recess 273 is lower than the top surface of the active region AA. In other embodiments, the second etching process is performed until the active region AA is exposed, in other words, only the active region AA is exposed without removing a portion of the active region AA.

[0034] It should be noted that performing a second etching process to remove a portion of the active region AA can increase the contact area between the subsequently formed dielectric plug and the active region AA. Specifically, the contact area between the dielectric plug and the active region AA may further include a portion of the side surface that contacts the active region AA. For example, the side surface of the recess 273 in the active region AA can also contact the subsequently formed dielectric plug. Therefore, by increasing the contact area between the dielectric plug and the active region AA, the current path flowing through the active region AA and the dielectric plug can be adjusted, thereby reducing the risk of short circuits between the dielectric plug and the bit line structure.

[0035] Furthermore, in some embodiments, the first etching process for reducing the height of the dielectric material 271 and the second etching process for forming the recess 273 can be performed in the same process step. For example, while performing the first etching process to reduce the height of the dielectric material 271, the substrate 260 and the active region AA can be etched simultaneously by controlling the etching selectivity ratio and etching parameters of the dielectric material 271 and the substrate 260 and the active region AA, thereby removing the substrate 260 exposed by the dielectric structure 272 and causing the active region AA to be recessed. Therefore, process costs can be reduced. In some embodiments, the first etching process for reducing the height of the dielectric material 271 and the second etching process for forming the recess 273 can be performed sequentially in different process steps.

[0036] Reference Figure 7 A first conductive post 300 is formed on the recess 273. In some embodiments, the material for forming the first conductive post 300 is blanket-formed in the opening OP, and then the material of the first conductive post 300 is removed by an etching process so that the top surface of the first conductive post 300 is flush with the top surface of the dielectric structure 272. The first conductive post 300 may include a conductive material. The conductive material may include polycrystalline silicon, amorphous silicon, metals such as tungsten, gold, silver, copper, cobalt or the like, metal nitrides, conductive metal oxides, other suitable materials or combinations thereof. In some embodiments, the first conductive post 300 may include polycrystalline silicon.

[0037] A first conductive post 300 is disposed on the active region AA. In some embodiments, the first conductive post 300 covers a portion of the side surface S1 of the exposed opening OP. For example, the first conductive post 300 covers the lower part of the side surface S1 of the opening OP and exposes the upper part of the side surface S1 of the opening OP. In some embodiments, the first conductive post 300 completely covers the bottom surface S2 of the exposed opening OP. In some embodiments, the first conductive post 300 contacts one of the opposite side surfaces S1 of the opening OP, the dielectric structure 272 contacts the other of the opposite side surfaces S1 of the opening OP, and the first conductive post 300 is in direct contact with the dielectric structure 272. In some embodiments, the first conductive post 300 contacts the liner 260, the dielectric structure 272, the isolation structure 110, and the active region AA. In some embodiments, the dielectric structure 272 is located between the first conductive post 300 and the bit line structure BLS. In some embodiments, the top surface of the first conductive post 300 is a flat surface, thereby improving the reliability of the first conductive post 300. In some embodiments, the shape of the first conductive post 300 is not limited to a columnar shape.

[0038] Reference Figure 8The dielectric structure 272 is removed by an etching process. In some embodiments, the first conductive post 300 can be used as an etching mask, and the dielectric structure 272 can be removed by a wet etching process. The dielectric structure 272 is removed to expose the side and bottom surfaces of the opening OP located between the first conductive post 300 and the bit line structure BLS.

[0039] Reference Figure 9 An interface layer 400 is formed on the top surface of the first conductive post 300. In some embodiments, the interface layer 400 is formed after the dielectric structure 272 is removed. In some embodiments, the interface layer 400 is compliantly formed on the top surface and side surface of the first conductive post 300. In other words, the interface layer 400 may include an extension 410. The extension 410 of the aforementioned interface layer 400 may be disposed on the side surface of the first conductive post 300. In some embodiments, the extension 410 of the aforementioned interface layer 400 may be located between the first conductive post 300 and the bit line structure BLS. In other embodiments, the interface layer 400 may be formed on the top surface of the first conductive post 300, and the interface layer 400 may at least cover a portion of the side surface of the first conductive post 300. In still other embodiments, the interface layer 400 may be formed on the top surface of the first conductive post 300, and the interface layer 400 may completely expose the side surface of the first conductive post 300. In the semiconductor structure of this application, the contact area between the first conductive pillar 300 and the active region AA has a significant impact on resistance. Therefore, the semiconductor structure of this application can be effectively operated when the interface layer 400 is formed at least on the top surface of the first conductive pillar 300. In some embodiments, the interface layer 400 may be cane-shaped, inverted L-shaped, or other suitable shapes.

[0040] Interface layer 400 can serve as a buffer layer to improve compatibility, thereby enhancing the reliability of the dielectric plug in the subsequently formed semiconductor structure. In some embodiments, interface layer 400 may include cobalt silicide. Because interface layer 400 includes cobalt silicide, it can improve the compatibility between the first conductive post 300 and the second conductive post subsequently formed on interface layer 400, thereby improving the overall reliability of the dielectric plug.

[0041] Reference Figure 10 A second conductive pillar 600 is formed on the interface layer 400 to obtain the semiconductor structure 1 of this application. In some embodiments, the material and formation method used to form the second conductive pillar 600 may be the same as or different from the material and formation method used to form the first conductive pillar 300. In some embodiments, the second conductive pillar 600 includes tungsten.

[0042] like Figure 10As shown, an intermediate structure 500 can be formed below the second conductive post 600. In some embodiments, the intermediate structure 500 is disposed between the first conductive post 300 and the bit line structure BLS. In some embodiments, the top surface of the intermediate structure 500 may be flush with the top surface of the interface layer 400. In some embodiments, the material and forming method used to form the intermediate structure 500 may be the same as or different from the material and forming method used to form the second conductive post 600.

[0043] In some embodiments, the material of the intermediate structure 500 is the same as the material of the second conductive pillar 600. In some embodiments, both the intermediate structure 500 and the second conductive pillar 600 are tungsten. For example, a material such as tungsten is deposited on the substrate 260 and the interface layer 400 in a blanket manner to simultaneously form the intermediate structure 500 and the second conductive pillar 600. Next, a planarization process is performed to make the top surface of the second conductive pillar 600 flush with the top surface of the substrate 260. In other words, the intermediate structure 500 and the second conductive pillar 600 can be formed integrally. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process, but this application is not limited thereto. In some embodiments, after removing the dielectric structure 272, the intermediate structure 500 and the second conductive pillar 600 are integrally formed on, for example... Figure 9 The opening OP shown.

[0044] In some embodiments, when the materials of the intermediate structure 500 and the second conductive pillar 600 are deposited in a blanket-like manner, adjustments can be made as follows: Figure 5 The second width W2 shown and as Figure 6 The second height H2 shown is used to change the aspect ratio of the trench between the liner 260 and the extension 410 of the interface layer 400. Therefore, the deposition parameters and deposition profile of the materials for the deposition intermediate structure 500 and the second conductive pillar 600 can be adjusted by adjusting the aspect ratio of the trench. In some embodiments, the materials of the intermediate structure 500 and the second conductive pillar 600 are deposited in a blanket manner so that the materials of the intermediate structure 500 and the second conductive pillar 600 completely fill the trench between the liner 260 and the extension 410 of the interface layer 400. In other words, the intermediate structure 500 is surrounded by the liner 260, the extension 410 of the interface layer 400, and the second conductive pillar 600. In some embodiments, when the central axis of the second conductive pillar 600 is taken as the axis of symmetry, this application provides a dielectric plug with an asymmetrical structure.

[0045] In this embodiment, the extension 410 of the interface layer 400 is located between the interposer 500 and the first conductive post 300. In some embodiments, the interposer 500 is located between the extension 410 and the bit line structure BLS. The interposer 500 is located between the extension 410 and the liner 260. The bottom surface of the first conductive post 300 is lower than the bottom surface of the interposer 500. Therefore, the contact area between the first conductive post 300 and the interposer 500 and the second conductive post 600 can be increased. Accordingly, by providing the interposer 500, the current path flowing through the integral dielectric plug is adjusted, thereby reducing the risk of short circuits between the dielectric plug and the bit line structure BLS. For example, the risk of short circuits between the first conductive post 300 and the first conductive layer 220 and / or the second conductive layer 230 in the bit line structure BLS is reduced.

[0046] In other embodiments, the material of the intermediate structure 500 is different from the material of the second conductive pillar 600. In this embodiment, the intermediate structure 500 may be formed first, and then the second conductive pillar 600 may be formed.

[0047] like Figure 10 As shown, it is along Figure 1 A schematic diagram of the cross-section captured by line segment XX'. In this cross-section, along as shown... Figure 1 The second direction D2 shown spans five isolation structures 110 and four active regions AA, wherein the four active regions AA are respectively located between the five isolation structures 110. In this case, a bit line dielectric layer 210 and a bit line structure BLS are provided on the central isolation structure 110, and the bit line dielectric layer 210 and the bit line structure BLS can be regarded as a dummy bit line structure. In other words, Figure 10 This shows a cross-sectional view of two adjacent BitLine Structures (BLS) with a dummy bitline structure between them. Figure 10 In this configuration, the intermediate structure 500 is disposed adjacent to the bit line structure BLS and away from the dummy bit line structure. In some embodiments, the intermediate structure 500 and the first conductive post 300 are located between the bit line structure BLS and the dummy bit line structure. Specifically, the intermediate structure 500 is closer to the bit line structure BLS than the first conductive post 300. With the central axis of the dummy bit line structure as the axis of symmetry, the first conductive post 300, the interface layer 400, the intermediate structure 500, and the second conductive post 600 can be symmetrically arranged. In other words, when the central axis of the dummy bit line structure is used as the axis of symmetry, this application provides a symmetrical structure.

[0048] Reference Figure 11 The image shows a cross-sectional schematic diagram of the semiconductor structure 2 of this application. For ease of explanation, similar and repetitive descriptions are omitted. Figure 11 To continue Figure 9 A cross-sectional view of the semiconductor structure shown undergoing further processing. (Continued) Figure 9 ,like Figure 11 As shown, a second conductive pillar 600 is formed on the interface layer 400 to obtain the semiconductor structure 2 of this application. In this embodiment, the deposition profile of the material of the blanket-deposited intermediate structure 500 is changed by adjusting the aspect ratio of the trench between the substrate 260 and the extension portion 410 of the interface layer 400.

[0049] In this embodiment, an intermediary member 510 is formed below the second conductive post 600, and an air gap AG is formed below the intermediary member 510. In some embodiments, the material of the deposited intermediary structure 500 is as follows: Figure 9 In the shown opening OP, the bottom surface of the material of the intermediate structure 500 is positioned between the top and bottom surfaces of the interface layer 400. For example, the bottom surface of the material of the intermediate structure 500 may be positioned between the top surface of the interface layer 400 and the bottom surface of the extension 410.

[0050] In some embodiments, the material of the intermediary member 510 and the material of the second conductive post 600 may be the same. In other words, the intermediary member 510 and the second conductive post 600 are integrally formed. For example, the material of the second conductive post 600 is deposited in a blanket manner to simultaneously form the second conductive post 600 and the intermediary structure 500 including the intermediary member 510 and the air gap AG. In other words, when depositing the material of the second conductive post 600 in a blanket manner, the material of the second conductive post 600 may be partially filled in the trench between the substrate 260 and the extension 410 of the interface layer 400 to form the air gap AG. In some embodiments, both the intermediary member 510 and the second conductive post 600 are made of tungsten.

[0051] In some embodiments, the intermediary component 510 and the air gap AG can be considered as an integral part of the intermediary structure 500. In some embodiments, the area occupied by the intermediary component 510 and the air gap AG in the intermediary structure 500 can be adjusted according to the aspect ratio of the trench and the parameters of the deposition process. In some embodiments, the area occupied by the intermediary component 510 in the intermediary structure 500 can be less than, substantially equal to or greater than the area occupied by the air gap AG in the intermediary structure 500. In some embodiments, the top surface of the air gap AG can be lower than or flush with the top surface of the first conductive post 300 or the interface layer 400. In some embodiments, the intermediary component 510 contacts the first conductive post 300, the interface layer 400 and the second conductive post 600.

[0052] In some embodiments, the air gap AG may include an inert gas, air, or a vacuum. In this embodiment, since the intermediary structure 500 may include the air gap AG disposed below the intermediary member 510, parasitic capacitance can be effectively reduced, thereby reducing the risk of short circuits between the dielectric plug and the bit line structure BLS.

[0053] Reference Figure 12 The image shows a cross-sectional schematic diagram of the semiconductor structure 3 of this application. For ease of explanation, similar and repetitive descriptions are omitted. Figure 12 To continue Figure 9 A cross-sectional view of the semiconductor structure shown undergoing further processing. (Continued) Figure 9 ,like Figure 12 As shown, a second conductive pillar 600 is formed on the interface layer 400 to obtain the semiconductor structure 3 of this application. Figure 12 As shown, the bottom surface of the second conductive post 600 is flush with the top surface of the interface layer 400, and an air gap AG is formed below the second conductive post 600. In some embodiments, the air gap AG directly contacts the second conductive post 600. In this embodiment, the air gap AG can be considered as an intermediate structure. Therefore, in the case where the intermediate structure is essentially the air gap AG, the parasitic capacitance between the first conductive post 300 and the bit line structure BLS can be effectively reduced, thereby reducing the risk of short circuit.

[0054] Reference Figure 13 This diagram shows a cross-sectional view of a semiconductor structure according to another embodiment of this application. For ease of explanation, similar and repetitive descriptions are omitted. Figure 13 To continue Figure 7 A cross-sectional view of the semiconductor structure shown undergoing further processing. (Continued) Figure 7 ,like Figure 13 As shown, an interface layer 400 is formed on the top surface of the first conductive pillar 300. In some embodiments, the interface layer 400 may include cobalt silicide, the first conductive pillar 300 may include polysilicon, and the dielectric structure 272 may include silicon oxide. Due to material compatibility issues, the interface layer 400 may be formed only on the top surface of the first conductive pillar 300. In this embodiment, the dielectric structure 272 is retained between the first conductive pillar 300 and the bit line structure BLS to omit the process steps of removing the dielectric structure 272 and / or further forming an intermediate structure, thereby reducing process costs. In some embodiments, since the interface layer 400 can be formed with the polysilicon in the first conductive pillar 300, the top surface of the interface layer 400 is flush with the top surface of the dielectric structure 272.

[0055] like Figure 14 As shown, a second conductive post 600 is formed in such a way as Figure 13The semiconductor structure 4 of this application is obtained by means of the structure shown. In some embodiments, the second conductive post 600 contacts the interface layer 400 and the dielectric structure 272. In some embodiments, the bottom surface of the second conductive post 600 is flush with the top surface of the interface layer 400 and the dielectric structure 272. In this embodiment, the dielectric structure 272 can be regarded as an intermediary structure. Since the dielectric structure 272 can be used as an etching mask in the aforementioned process and as an intermediary structure disposed between the first conductive post 300 and the bit line structure BLS, it is possible to reduce process steps and reduce process costs. In addition, since the dielectric structure 272 may include a dielectric material such as silicon oxide, parasitic capacitance can be reduced to reduce the risk of short circuit between the first conductive post 300 and the bit line structure BLS.

[0056] In some embodiments, further processes may be performed on the semiconductor structures 1, 2, 3 and / or 4 of this application to form a memory device. For example, in some embodiments, a doping process may be performed according to electrical requirements. In some embodiments, the dopant may be a P-type dopant such as boron or an N-type dopant such as phosphorus.

[0057] In summary, the semiconductor structure of this application includes a first conductive pillar, an interface layer, a second conductive pillar, and an intermediate structure, which together serve as a dielectric plug for connecting capacitors in a memory device.

[0058] This application reduces the short-circuit risk between the first conductive post and the bit line structure by setting an intermediary structure made of the same material as the second conductive post between them, treating the intermediary structure as an extension of the second conductive post. This increases the contact area between the second and first conductive posts. This application also reduces the short-circuit risk between the first conductive post and the bit line structure by setting an intermediary structure including an air gap or entirely consisting of an air gap between them, thereby reducing the parasitic capacitance of the dielectric plug. Finally, this application reduces the short-circuit risk between the first conductive post and the bit line structure and / or reduces the process cost by setting an intermediary structure comprising a dielectric material such as silicon oxide between them, thereby reducing the parasitic capacitance of the dielectric plug and / or reducing process steps.

[0059] Furthermore, this application increases the contact area between the first conductive post and the second conductive post and / or the intermediate structure by providing a first conductive post with a bottom surface lower than that of the second conductive post and the intermediate structure. Therefore, the risk of short circuits can be reduced by adjusting the current flowing through the first conductive post, the second conductive post, and the intermediate structure. Moreover, this application improves the compatibility of the first and second conductive posts by providing an inverted L-shaped interface layer, thereby improving their reliability. Simultaneously, this application provides a semiconductor structure with dummy bitline structures between adjacent bitline structures, so that a semiconductor structure symmetrical to the dummy bitline structures can be obtained when viewed in this cross-sectional direction. Accordingly, the risk of short circuits is reduced by providing an intermediate structure that is far from and adjacent to the dummy bitline structures.

[0060] The foregoing summary outlines components of several embodiments of this application, enabling those skilled in the art to better understand the nature of this application. Those skilled in the art should understand that they can readily use this application as a basis for changing, replacing, substituting, and / or modifying other processes and structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this application, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having multiple active regions and an isolation structure; Multiple bit line structures, each bit line structure including a first conductive layer disposed on the multiple active regions and a first conductive layer disposed on the isolation structure, wherein a bit line dielectric layer is disposed between the isolation structure and the first conductive layer; A first conductive post is disposed on the active region located between the first conductive layer and the bit line dielectric layer; An interface layer is disposed on the top surface of the first conductive pillar; A second conductive pillar is disposed on the interface layer; as well as An intermediary structure is disposed between the first conductive post and the first conductive layer on the plurality of active regions, but not between the bit line dielectric layer on the first conductive post and the isolation structure.

2. The semiconductor structure as described in claim 1, characterized in that, The bottom surface of the first conductive post is lower than the bottom surface of the intermediate structure.

3. The semiconductor structure as described in claim 1, characterized in that, The interface layer has an extension portion disposed on the side surface of the first conductive post.

4. The semiconductor structure as described in claim 1, characterized in that, The intermediary structure further includes: An intermediate component is disposed below the second conductive post; and An air gap is provided below the intermediate component.

5. The semiconductor structure as described in claim 1, characterized in that, The intermediate structure is an air gap.

6. A method for forming a semiconductor structure, characterized in that, include: Multiple active regions and an isolation structure are formed in a substrate; Multiple bit line structures are formed, each bit line structure including a first conductive layer disposed on the multiple active regions and a first conductive layer disposed on the isolation structure, a bit line dielectric layer is disposed between the isolation structure and the first conductive layer, and an opening is provided between adjacent bit line structures. A dielectric structure is formed in the opening; The active region is etched to form a recess in the opening; A first conductive post is formed on the recess, and the first conductive post is disposed on the active region located between the first conductive layer and the bit line dielectric layer; An interface layer is formed on the top surface of the first conductive pillar; A second conductive pillar is formed on the interface layer; as well as An intermediary structure is formed, wherein the intermediary structure is disposed between the first conductive pillar and the first conductive layer on the plurality of active regions, but not between the first conductive pillar and the bit line dielectric layer on the isolation structure.

7. The forming method as described in claim 6, characterized in that, Including: The dielectric structure is removed before the interface layer is formed.

8. The forming method as described in claim 7, characterized in that, Including: After the dielectric structure is removed, the intermediate structure is formed in the opening so that the intermediate structure contacts the interface layer and the second conductive pillar.

9. The forming method as described in claim 8, characterized in that, The intermediate structure formed in the opening further includes: The material of the intermediate structure is deposited in the opening such that the bottom surface of the material of the intermediate structure is between the top and bottom surfaces of the interface layer.

10. The forming method as described in claim 6, characterized in that, Forming the dielectric structure in the opening further includes: A dielectric material is filled into the opening; The dielectric material is patterned to expose the side and bottom surfaces of the opening; The dielectric material is etched so that the top surface of the dielectric material is lower than the top surface of the plurality of bit line structures, thereby forming the dielectric structure.

11. The forming method as described in claim 10, characterized in that, The step of etching the dielectric material and the step of etching the active region are performed in the same process.

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