Display device with light emitting device

Abstract

A display device can include a display panel which can include a display area provided with light emitting devices and a bezel area provided outside the display area. A device substrate can extend over the entire display area and the bezel area. An overcoat layer can be on the device substrate over the display area and the bezel area. The light emitting device can include a first electrode, a light emitting layer, and a second electrode. A bank insulating layer covering edges of the first electrode can extend on the overcoat layer of the bezel area. An opening penetrating the overcoat layer and the bank insulating layer can be on the bezel area of the device substrate. A sidewall of the opening can be covered by the second electrode. Thus, external moisture can be blocked or delayed from penetrating through the overcoat layer and the bank insulating layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0180747, filed on December 16, 2021, which is incorporated herein by reference as fully set forth herein. Technical Field

[0003] This disclosure relates to an apparatus and method, and in particular, for example, to a display apparatus having light-emitting devices disposed on a device substrate, but is not limited thereto. Background Technology

[0004] Typically, a display device provides an image to a user. For example, a display device may include multiple light-emitting devices. These light-emitting devices can emit light that displays a specific color. For example, each of the light-emitting devices may include a first electrode, a light-emitting layer, and a second electrode stacked sequentially.

[0005] The device substrate supporting the light-emitting devices may include a display area and a bezel area disposed outside the display area. Signal wiring and an insulating layer may be disposed on the bezel area of ​​the device substrate. Various signals for controlling the operation of each light-emitting device can be applied through the signal wiring. The signal wiring may be insulated from each other through the insulating layer. For example, an outer coating and a dam insulating layer covering the edge of the first electrode disposed between the device substrate and the light-emitting devices may extend on the bezel area of ​​the device substrate.

[0006] The outer coating and the dike insulation layer may include organic insulating materials. The light-emitting layer may be susceptible to moisture damage. Therefore, in a display device, the light-emitting layer may deteriorate due to external moisture penetration through the outer coating and dike insulation layer. Consequently, the quality of the image provided to the user in the display device may be degraded. Summary of the Invention

[0007] Therefore, this disclosure aims to provide a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0008] One object of this disclosure is to provide a display device that can minimize image quality degradation caused by external moisture.

[0009] Another object of this disclosure is to provide a display device capable of blocking or delaying the penetration of external moisture.

[0010] Other advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the written description and its claims, as well as the structures particularly pointed out in the accompanying drawings.

[0011] To achieve these and other advantages, and in accordance with the purposes of this disclosure, as embodied and generally described herein, a display device comprising a display area and a bezel area is provided. The bezel area is disposed outside the display area. A device substrate is disposed in both the display area and the bezel area. A light-emitting device is disposed on the display area of ​​the device substrate. The light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially. An outer coating is disposed between the device substrate and the light-emitting device. The outer coating extends on the bezel area of ​​the device substrate. A dam insulating layer covering the edge of the first electrode extends on the outer coating of the bezel area. A moisture-blocking hole is disposed on the bezel area of ​​the device substrate. The moisture-blocking hole penetrates the outer coating and the dam insulating layer. The second electrode of the light-emitting device extends on the sidewall of the moisture-blocking hole.

[0012] The second electrode of a light-emitting device may include metal.

[0013] The second light-emitting device can be disposed on the display area of ​​the device substrate. The second light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially. The second electrode of the light-emitting device and the second electrode of the second light-emitting device can be configured to receive the same voltage.

[0014] The second electrode of the light-emitting device can be connected to a node or line for engagement with a voltage power supply.

[0015] The first electrode can be closer to the outer coating than the second electrode. The second electrode of the light-emitting device can extend on the bottom surface of the moisture-blocking hole.

[0016] The pixel driving circuit can be disposed in the display area between the device substrate and the outer coating. The pixel driving circuit can be electrically connected to the first electrode of the light-emitting device and the signal wiring. The signal wiring can extend on the border area of ​​the device substrate. Moisture-blocking holes can be disposed between the signal wirings.

[0017] The display device may also include signal wiring and pixel driving circuitry electrically connected to the signal wiring. The signal wiring may extend on the border area of ​​the device substrate. Moisture-blocking holes may be disposed between the signal wirings.

[0018] Moisture-blocking holes can extend in the same direction as signal wiring.

[0019] A moisture-blocking pattern can be disposed between the sidewall of the moisture-blocking hole and the second electrode of the light-emitting device. The end of the moisture-blocking pattern can be disposed between the outer coating and the embankment insulating layer in the border area.

[0020] The moisture barrier pattern may include the same material as the first electrode of the light-emitting device. The moisture barrier pattern may be formed simultaneously with the first electrode of the light-emitting device.

[0021] The encapsulation element covering the light-emitting device can extend along the border area of ​​the device substrate. Moisture-barrier holes can be filled by the encapsulation element.

[0022] The encapsulation element may include moisture-absorbing particles.

[0023] In another embodiment, a display device is provided, including a device substrate. An outer coating is disposed on a display area and a bezel area of ​​the device substrate. A light-emitting device is disposed on the outer coating of the display area. The light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially. A dammed insulating layer covering the edge of the first electrode extends on the outer coating of the bezel area. Moisture-blocking trenches penetrating the outer coating and the dammed insulating layer in the bezel area extend along the edge of the display area. The inner sidewalls of the moisture-blocking trenches facing the display area are covered by the second electrode of the light-emitting device.

[0024] The second electrode of the light-emitting device can extend on the outer wall of the moisture-blocking trench opposite to the display area.

[0025] Moisture-blocking trenches may include a lower trench that penetrates the outer coating and an upper trench that penetrates the dike insulation layer. The upper trench may be located within the lower trench. The sidewalls of the lower trench may be covered by the dike insulation layer.

[0026] The insulation layer of the dike can have a lower water vapor permeability than the outer coating.

[0027] Pixel driving circuitry can be disposed in the display area between the device substrate and the outer coating. Pixel driving circuitry can be electrically connected to the light-emitting device and signal wiring. Signal wiring can extend on the border area of ​​the device substrate. Moisture-blocking trenches can be disposed on the outside of the signal wiring.

[0028] The display device may also include signal wiring and pixel driving circuitry electrically connected to the signal wiring. The signal wiring may extend on the bezel area of ​​the device substrate. Moisture-blocking trenches may be disposed outside the signal wiring.

[0029] Moisture-blocking holes can be placed between signal wirings. The sidewalls of the moisture-blocking holes can be covered by the second electrode of the light-emitting device.

[0030] A device passivation layer can be disposed between the device substrate and the outer coating. The device passivation layer can include a material different from the outer coating and the dike insulating layer. Moisture-barrier trenches can penetrate the device passivation layer.

[0031] The inner wall of the water-blocking trench can have a stepped shape.

[0032] In a plan view, the inner wall of the water-blocking trench can have an uneven shape. Attached Figure Description

[0033] This disclosure includes accompanying drawings to provide a further understanding of the disclosure, and the drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Figure 1 This is a schematic diagram illustrating a display device according to an example embodiment of the present disclosure; Figure 2 This is a diagram illustrating the configuration of pixel regions in a display device according to an example embodiment of the present disclosure; Figure 3 This is a diagram that partially shows a cross-section of a pixel region in a display device according to an example embodiment of the present disclosure; Figure 4 yes Figure 1 An example of a magnified view of region R in the image; Figure 5 It is along Figure 4 An example of a plot captured by I-I'; Figure 6 It is along Figure 4 Example of a plot taken from II-II'; Figures 7 to 19 This is a diagram illustrating a display device according to another exemplary embodiment of the present disclosure; and Figure 20 This is a diagram illustrating the configuration of a portion of a pixel region in a display device according to another exemplary embodiment of the present disclosure. Detailed Implementation

[0034] In the following detailed description, the details relating to the above-described objectives, technical configurations, and operational effects of embodiments of the present disclosure will become clear from the accompanying drawings, which illustrate some embodiments of the present disclosure. Embodiments of the present disclosure are provided here to satisfactorily convey the technical spirit of the present disclosure to those skilled in the art; therefore, the present disclosure may be implemented in other forms and is not limited to the embodiments described below.

[0035] Furthermore, throughout the specification and drawings, identical or very similar elements may be represented by the same reference numerals, and for convenience, the length and thickness of layers and regions may be exaggerated. It should be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element to contact it, a third element may be inserted between the first and second elements.

[0036] Here, terms such as “first” and “second” may be used to distinguish one element from another. However, without departing from the technical spirit of this disclosure, the first element and the second element may be named arbitrarily according to the convenience of those skilled in the art.

[0037] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. For example, elements described in the singular are intended to include multiple elements unless the context clearly indicates otherwise. Furthermore, it will be further understood in this disclosure that the terms “comprising” and “including” specify the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0039] (Example)

[0040] Figure 1 This is a diagram schematically illustrating a display device according to an example embodiment of the present disclosure. Figure 2 This is a diagram illustrating the configuration of pixel regions in a display device according to an example embodiment of the present disclosure. Figure 3 This is a diagram showing a cross-section of a pixel region in a display device according to an example embodiment of the present disclosure.

[0041] Reference Figures 1 to 3 The display device according to an example embodiment of the present disclosure may include a display panel 100, a data driver 200, a gate driver 300, a timing controller 400, and a power supply unit 500.

[0042] Display panel 100 can generate images for a user. For example, display panel 100 may include multiple pixel regions PA. Data driver 200, gate driver 300, timing controller 400, and power supply unit 500 can control the operation of each pixel region PA. For example, data driver 200 can apply data signals to each pixel region PA via data lines DL (e.g., one or more data lines DL), and gate driver 300 can apply gate signals to each pixel region PA via gate lines GL (e.g., one or more gate lines GL). Power supply unit 500 can supply power voltage to each pixel region PA via one or more power supply voltage lines PL, and supply reference voltage to each pixel region PA via one or more reference voltage supply lines RL. Timing controller 400 can control data driver 200 and gate driver 300. For example, data driver 200 can receive digital video data and source timing control signals from timing controller 400, and gate driver 300 can receive clock signals, reset clock signals, and start signals from timing controller 400.

[0043] Each pixel region PA can achieve a specific color. For example, a light-emitting device 150 supported by the device substrate 101 can be disposed in each pixel region PA. The display panel 100 may include the device substrate 101, which may include an insulating material. The device substrate 101 may include a transparent material. For example, the device substrate 101 may include glass or plastic. The light-emitting device 150 can emit light displaying a specific color. For example, the light-emitting device 150 may include a first electrode 151, a light-emitting layer 152, and a second electrode 153 sequentially stacked on the device substrate 101.

[0044] The first electrode 151 may include a conductive material. The first electrode 151 may have high transmittance. For example, the first electrode 151 may be a transparent electrode made of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0045] The light-emitting layer 152 can generate light with a brightness corresponding to the voltage difference between the first electrode 151 and the second electrode 153. For example, the light-emitting layer 152 may include a light-emitting material layer (EML) having a light-emitting material. The light-emitting material may include organic materials, inorganic materials, or mixed materials. For example, the display device according to an example embodiment of this disclosure may be an organic light-emitting display device including an organic light-emitting material.

[0046] The light-emitting layer 152 may have a multilayer structure. For example, the light-emitting layer 152 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, in the display device according to the exemplary embodiment of the present disclosure, the emission efficiency of the light-emitting layer 152 can be improved.

[0047] The second electrode 153 may include a conductive material. The second electrode 153 may include a material different from the first electrode 151. For example, the transmittance of the second electrode 153 may be lower than that of the first electrode 151. The second electrode 153 may have a higher reflectance than the first electrode 151. For example, the second electrode 153 may include a metal, such as aluminum (Al), silver (Ag), an alloy of any of the above, or a combination thereof. Therefore, in the display panel 100 of the display device according to an exemplary embodiment of the present disclosure, light generated by the light-emitting layer 152 can be emitted to the outside through the first electrode 151 and the device substrate 101.

[0048] Each pixel region PA may include a pixel driving circuit DC to control the operation of the light-emitting device 150. For example, the pixel driving circuit DC of each pixel region PA can generate a driving current corresponding to the data signal according to the gate signal. The driving current generated by the pixel driving circuit DC of each pixel region PA can be provided to the light-emitting device 150 of the corresponding pixel region PA in one frame. For example, the pixel driving circuit DC of each pixel region PA may include a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, and a storage capacitor Cst.

[0049] The first thin-film transistor T1 may include a first semiconductor pattern, a first gate, a first source, and a first drain. The second thin-film transistor T2 may have the same structure as the first thin-film transistor T1. For example, the second thin-film transistor T2 may include a second semiconductor pattern 121, a second gate 122, a second source 123, and a second drain 124.

[0050] The first semiconductor pattern and the second semiconductor pattern 121 may include semiconductor materials. For example, each of the first semiconductor pattern and the second semiconductor pattern 121 may include an oxide semiconductor, such as indium gallium zinc oxide (IGZO). The second semiconductor pattern 121 may include the same material as the first semiconductor pattern. The second semiconductor pattern 121 may be disposed on the same layer as the first semiconductor pattern. For example, the second semiconductor pattern 121 may be formed simultaneously with the first semiconductor pattern.

[0051] Each of the first semiconductor pattern and the second semiconductor pattern 121 may include a source region, a channel region, and a drain region. The channel region may be disposed between the source region and the drain region. The source region and the drain region may have a lower resistance than the channel region. For example, the source region and the drain region may include conductive regions of an oxide semiconductor. The channel region may be a non-conductive region of an oxide semiconductor.

[0052] Each of the first gate and the second gate 122 may include a conductive material. For example, each of the first gate and the second gate 122 may include a metal, such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys thereof. The second gate 122 may include the same material as the first gate. The second gate 122 may be disposed on the same layer as the first gate. For example, the second gate 122 may be formed simultaneously with the first gate.

[0053] A first gate may be disposed on a first semiconductor pattern. For example, the first gate may overlap with a channel region of the first semiconductor pattern. A second gate 122 may be disposed on a second semiconductor pattern 121. For example, the second gate 122 may overlap with a channel region of the second semiconductor pattern 121. The first gate may be insulated from the first semiconductor pattern, and the second gate 122 may be insulated from the second semiconductor pattern 121. For example, the channel region of the first semiconductor pattern may have a conductivity corresponding to a voltage applied to the first gate, and the channel region of the second semiconductor pattern 121 may have a conductivity corresponding to a voltage applied to the second gate 122.

[0054] The first source, first drain, second source 123, and second drain 124 may comprise conductive materials. For example, each of the first source, first drain, second source 123, and second drain 124 may comprise a metal, such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys thereof. The first drain may comprise the same material as the first source. For example, the first drain may be disposed on the same layer as the first source. The second drain 124 may comprise the same material as the second source 123. For example, the second drain 124 may be disposed on the same layer as the second source 123. The second drain 124 may comprise the same material as the first drain. For example, the second source 123 and the second drain 124 may be formed simultaneously with the first source and the first drain.

[0055] The first source can be electrically connected to the source region of the first semiconductor pattern. The first drain can be electrically connected to the drain region of the first semiconductor pattern. For example, the first drain can be spaced apart from the first source. The second source 123 can be electrically connected to the source region of the second semiconductor pattern 121. The second drain 124 can be electrically connected to the drain region of the second semiconductor pattern 121. For example, the second drain 124 can be spaced apart from the second source 123.

[0056] The third thin-film transistor T3 may have the same structure as the second thin-film transistor T2. For example, the third thin-film transistor T3 may include a third semiconductor pattern 131, a third gate 132, a third source 133, and a third drain 134.

[0057] The third semiconductor pattern 131 may include a semiconductor material. For example, the third semiconductor pattern 131 may include an oxide semiconductor, such as IGZO. The third semiconductor pattern 131 may include the same material as the second semiconductor pattern 121. The third semiconductor pattern 131 may be disposed on the same layer as the second semiconductor pattern 121. For example, the third semiconductor pattern 131 may be formed simultaneously with the second semiconductor pattern 121. The third semiconductor pattern 131 may have the same structure as the second semiconductor pattern 121. For example, the third semiconductor pattern 131 may include a channel region between the source region and the drain region.

[0058] The third gate 132 may include a conductive material. For example, the third gate 132 may include a metal, such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys thereof. The third gate 132 may include the same material as the second gate 122. The third gate 132 may be disposed on the same layer as the second gate 122. For example, the third gate 132 may be formed simultaneously with the second gate 122.

[0059] The third gate 132 may be disposed on the third semiconductor pattern 131. For example, the third gate 132 may overlap with the channel region of the third semiconductor pattern 131. The third gate 132 may be insulated from the third semiconductor pattern 131. For example, the channel region of the third semiconductor pattern 131 may have a conductivity corresponding to the voltage applied to the third gate 132.

[0060] The third source 133 and the third drain 134 may comprise conductive materials. For example, each of the third source 133 and the third drain 134 may comprise a metal, such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys thereof. The third drain 134 may comprise the same material as the third source 133. For example, the third drain 134 may be formed simultaneously with the third source 133. The third drain 134 may comprise the same material as the second drain 124. For example, the third source 133 and the third drain 134 may be formed simultaneously with the second source 123 and the second drain 124.

[0061] The third source 133 can be electrically connected to the source region of the third semiconductor pattern 131. The third drain 134 can be electrically connected to the drain region of the third semiconductor pattern 131. For example, the third drain 134 can be spaced apart from the third source 13.

[0062] Thin-film transistors T1, T2, and T3 for each pixel region PA can be disposed between the device substrate 101 of the corresponding pixel region PA and the light-emitting device 150. For example, at least one of insulating layers 111, 112, 113, 114, and 115 can be disposed on the device substrate 101 to prevent unnecessary connections between the thin-film transistors T1, T2, and T3 of each pixel region PA and the light-emitting device 150. For example, a device buffer layer 111, a gate insulating layer 112, a device passivation layer 113, an outer coating layer 114, and a dam insulating layer 115 can be disposed on the device substrate 101.

[0063] Device buffer layer 111 may include an insulating material. For example, device buffer layer 111 may include an inorganic insulating material, such as silicon oxide (SiO) and silicon nitride (SiN). Device buffer layer 111 may include a multilayer structure. For example, device buffer layer 111 may have a stacked structure of layers made of silicon nitride (SiN) and layers made of silicon oxide (SiO).

[0064] A device buffer layer 111 may be disposed between the device substrate 101 and the thin-film transistors T1, T2, and T3 of each pixel region PA. The device buffer layer 111 can prevent contamination caused by the device substrate 101 during the process of forming the thin-film transistors T1, T2, and T3. For example, the entire surface of the device substrate 101 facing each pixel region PA of the thin-film transistors T1, T2, and T3 may be covered by the device buffer layer 111.

[0065] The gate insulating layer 112 may include an insulating material. For example, the gate insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO) and silicon nitride (SiN). The gate insulating layer 112 may include a material having a high dielectric constant (K). For example, the gate insulating layer 112 may include a high-K material, such as hafnium oxide (HfO). The gate insulating layer 112 may have a multilayer structure.

[0066] A gate insulating layer 112 may be disposed on the device buffer layer 111. The gate insulating layer 112 may extend between the semiconductor patterns 121 and 131 and the gates 122 and 132 of each thin-film transistor T1, T2, and T3. For example, the gate insulating layer 112 may cover the first semiconductor pattern, the second semiconductor pattern 121, and the third semiconductor pattern 131 of each pixel region PA. The first gate, the second gate 122, and the third gate 132 of each pixel region PA may be disposed on the gate insulating layer 112. For example, the gates 122 and 132 of each thin-film transistor T1, T2, and T3 may be insulated from the semiconductor patterns 121 and 131 of the corresponding thin-film transistors T1, T2, and T3 through the gate insulating layer 112.

[0067] The sources 123 and 133 and the drains 124 and 134 of each thin-film transistor T1, T2, and T3 can be disposed on the gate insulating layer 112. For example, the gate insulating layer 112 may include source contact holes that partially expose the source regions of each semiconductor pattern 121 and 131, and drain contact holes that partially expose the drain regions of each semiconductor pattern 121 and 131. The sources 123 and 133 of each thin-film transistor T1, T2, and T3 can be connected to the source regions of the corresponding semiconductor patterns 121 and 131 through one of the source contact holes, and the drains 124 and 134 of each thin-film transistor T1, T2, and T3 can be connected to the drain regions of the corresponding semiconductor patterns 121 and 131 through one of the drain contact holes.

[0068] The device passivation layer 113 may include an insulating material. For example, the device passivation layer 113 may include an inorganic insulating material, such as silicon oxide (SiO) and silicon nitride (SiN).

[0069] A device passivation layer 113 may be disposed on the gate insulating layer 112. The device passivation layer 113 can prevent damage to the individual thin-film transistors T1, T2, and T3 due to external impacts and moisture. For example, the gates 122 and 132, sources 123 and 133, and drains 124 and 134 of each thin-film transistor T1, T2, and T3 may be covered by the device passivation layer 113. The device passivation layer 113 may extend along the surface of each thin-film transistor T1, T2, and T3 opposite to the device substrate 101. For example, the device passivation layer 113 covering each pixel region PA of thin-film transistors T1, T2, and T3 may be in direct contact with the device passivation layers 113 covering adjacent pixel regions PA of thin-film transistors T1, T2, and T3.

[0070] The device passivation layer 113 can be in direct contact with the gate insulating layer 112 on the outside of each thin-film transistor T1, T2, and T3. For example, the source 123 and 133 and the drain 124 and 134 of each thin-film transistor T1, T2, and T3 can be disposed on the same layer as the gate 122 and 132 of the corresponding thin-film transistor T1, T2, and T3. The source 123 and 133 and the drain 124 and 134 of each thin-film transistor T1, T2, and T3 can be formed simultaneously with the gate 122 and 132 of the corresponding thin-film transistor T1, T2, and T3. The source 123 and 133 and the drain 124 and 134 of each thin-film transistor T1, T2, and T3 can include the same material as the gate 122 and 132 of the corresponding thin-film transistor T1, T2, and T3. Therefore, in the display device according to the exemplary embodiment of the present disclosure, the process of forming thin-film transistors T1, T2, and T3 in each pixel region PA can be simplified.

[0071] The outer coating 114 may include an insulating material. The outer coating 114 may include a material different from the device passivation layer 113. For example, the outer coating 114 may include an organic insulating material.

[0072] An outer coating 114 may be disposed on the device passivation layer 113. The outer coating 114 can eliminate thickness differences caused by the thin-film transistors T1, T2, and T3 in each pixel region PA. For example, the upper surface of the outer coating 114 opposite to the device substrate 101 may be a flat surface. The first electrode 151, the light-emitting layer 152, and the second electrode 153 of the light-emitting device 150 may be sequentially stacked on the upper surface of the outer coating 114. Therefore, in the display device according to the exemplary embodiment of the present disclosure, phase deviation and brightness deviation based on the generation position of light emitted to the outside through the device substrate 101 can be prevented.

[0073] The dike insulation layer 115 may include an insulating material. For example, the dike insulation layer 115 may include an organic insulating material. The dike insulation layer 115 may include a material different from the outer coating 114.

[0074] A dam insulating layer 115 may be disposed on the outer coating layer 114. The first electrode 151 of each light-emitting device 150 may be insulated from the first electrode 151 of adjacent light-emitting devices 150 by the dam insulating layer 115. For example, the dam insulating layer 115 may cover the edge of the first electrode 151 in each pixel region PA. Therefore, in a display device according to an exemplary embodiment of the present disclosure, the light-emitting device 150 in each pixel region PA may be independently controlled by the dam insulating layer 115. The light-emitting layer 152 and the second electrode 153 of each light-emitting device 150 may be stacked on the portion of the corresponding first electrode 151 exposed by the dam insulating layer 115. For example, the dam insulating layer 115 may define a light-emitting region EA in each pixel region PA.

[0075] The light-emitting region EA of each pixel region PA defined by the insulating layer 115 may not overlap with the pixel driving circuit DC of the corresponding pixel region PA. For example, the thin-film transistors T1, T2, and T3 of each pixel region PA may be disposed outside the emission region EA of the corresponding pixel region PA. Therefore, in the display device according to the exemplary embodiment of the present disclosure, the light emitted from the light-emitting device 150 of each pixel region PA may not be blocked by the thin-film transistors T1, T2, and T3 of the corresponding pixel region PA.

[0076] The light-emitting layer 152 of each light-emitting device 150 can be connected to the light-emitting layer 152 of adjacent light-emitting devices 150. For example, the light-emitting layer 152 of each light-emitting device 150 can extend on the retaining layer 115. The light emitted from the light-emitting device 150 of each pixel region PA can display the same color as the light emitted from the light-emitting device 150 of the adjacent pixel region PA. For example, the light-emitting layer 152 of each pixel region PA can produce white light.

[0077] Each pixel region PA can achieve a different color than its adjacent pixel regions PA. For example, each pixel region PA may include a color filter 160 that overlaps with the light-emitting region EA of the corresponding pixel region PA. The color filter 160 can utilize light passing through the corresponding color filter 160 to achieve a specific color. For example, the color filter 160 of each pixel region PA can be positioned in the path of light emitted from the light-emitting device 150 in the corresponding pixel region PA. The color filter 160 of each pixel region PA can be positioned between the device substrate 101 and the light-emitting device 150 of the corresponding pixel region PA. For example, the color filter 160 of each pixel region PA can be positioned between the device passivation layer 113 and the outer coating layer 114. The thickness difference caused by the color filter 160 of each pixel region PA can be removed by the outer coating layer 114.

[0078] The voltage applied to the second electrode 153 of each light-emitting device 150 can be the same as the voltage applied to the second electrode 153 of an adjacent light-emitting device 150. For example, the second electrode 153 of each light-emitting device 150 can be electrically connected to the second electrode 153 of an adjacent light-emitting device 150. The second electrode 153 of each light-emitting device 150 can include the same material as the second electrode 153 of an adjacent light-emitting device 150. For example, the second electrode 153 of each light-emitting device 150 can be formed simultaneously with the second electrode 153 of an adjacent light-emitting device 150. Therefore, in the display device according to the exemplary embodiment of this disclosure, the process of forming the second electrode 153 of each light-emitting device 150 can be simplified.

[0079] In one or more examples, the second electrode 153 of the light-emitting device 150 can be connected to a voltage power supply (e.g., Figure 2 The nodes or lines that are joined together (as shown in the diagram).

[0080] A light-blocking pattern 140 may be disposed between the device substrate 101 and each of the thin-film transistors T1, T2, and T3. For example, the light-blocking pattern 140 may be disposed between the device substrate 101 and the device buffer layer 111. The light-blocking pattern 140 may include a material capable of absorbing or reflecting light. The light-blocking pattern 140 may include a conductive material. For example, the light-blocking pattern 140 may include a metal, such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys thereof.

[0081] External light propagating in the directions of the semiconductor patterns 121 and 131 of the respective thin-film transistors T1, T2, and T3 can be blocked by the light-blocking pattern 140. For example, the light-blocking pattern 140 may include portions overlapping with the channel regions of the respective semiconductor patterns 121 and 131. The gates 122 and 132 of the respective thin-film transistors T1, T2, and T3 may overlap with a portion of the light-blocking pattern 140. Therefore, in the display device according to an exemplary embodiment of the present disclosure, characteristic changes of the respective thin-film transistors T1, T2, and T3 due to external light can be prevented.

[0082] The first thin-film transistor T1 of each pixel driving circuit DC can transmit the data signal to the corresponding second thin-film transistor T2 of the pixel driving circuit DC. For example, the first gate of each pixel driving circuit DC can be electrically connected to one of the gate lines GL, and the first source of each pixel driving circuit DC can be electrically connected to one of the data lines DL. The second thin-film transistor T2 of each pixel driving circuit DC can generate a driving current corresponding to the data signal. For example, the second gate 122 of each pixel driving circuit DC can be electrically connected to the first drain of the corresponding pixel driving circuit DC, and the second source 123 of each pixel driving circuit DC can be electrically connected to one of the power supply voltage supply lines PL. The driving current generated by the second thin-film transistor T2 of each pixel region PA can be provided to the light-emitting device 150 of the corresponding pixel region PA. For example, the first electrode 151 of each pixel region PA can be electrically connected to the second drain 124 of the corresponding pixel region PA.

[0083] Data lines DL can intersect with gate lines GL. Data lines DL can be disposed on a different layer than gate lines GL. For example, data lines DL can be disposed between device substrate 101 and device buffer layer 111. Data lines DL can include the same material as light-blocking pattern 140. For example, data lines DL can be formed simultaneously with light-blocking pattern 140. Device buffer layer 111 and gate insulating layer 112 can include data contact holes exposing a portion of each data line DL. The first source of each pixel region PA can be connected to the corresponding data line DL through one of the data contact holes.

[0084] The power supply line PL can extend parallel to the data line DL. For example, the power supply line PL can intersect the gate line GL. The power supply line PL can be disposed on the same layer as the data line DL. For example, the power supply line PL can be disposed between the device substrate 101 and the device buffer layer 111. The power supply line PL can include the same material as the data line DL. For example, the power supply line PL can be formed simultaneously with the data line DL. The device buffer layer 111 and the gate insulating layer 112 can include power contact holes that expose a portion of each power supply line PL. The second source 123 of each pixel region PA can be connected to the corresponding power supply line PL through one of the power contact holes.

[0085] The storage capacitor Cst of each pixel driving circuit DC can hold the signal applied to the second gate 122 of the corresponding pixel driving circuit DC within a frame. For example, the storage capacitor Cst of each pixel driving circuit DC can be electrically connected between the second gate 122 and the second drain 124 of the corresponding pixel driving circuit DC. The storage capacitor Cst of each pixel driving circuit DC can have a stacked structure of at least two capacitor electrodes 171 and 172. For example, the storage capacitor Cst of each pixel driving circuit DC can have a stacked structure of a first capacitor electrode 171 and a second capacitor electrode 172. The second capacitor electrode 172 of each pixel driving circuit DC can be disposed on the first capacitor electrode 171 of the corresponding pixel driving circuit DC. The second capacitor electrode 172 of each pixel driving circuit DC can be insulated from the first capacitor electrode 171 of the corresponding pixel driving circuit DC. The storage capacitor Cst of each pixel driving circuit DC can be formed using a conductive layer disposed between the device substrate 101 and the outer coating 114. For example, the first capacitor electrode 171 of each pixel driving circuit DC can be disposed between the device substrate 101 and the device buffer layer 111, and the second capacitor electrode 172 of each pixel driving circuit DC can be disposed between the device buffer layer 111 and the gate insulating layer 112.

[0086] The first capacitor electrode 171 of each pixel driving circuit DC may include the same material as the light-blocking pattern 140. For example, the first capacitor electrode 171 of each pixel driving circuit DC may include a metal, such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys thereof. The first capacitor electrode 171 of each pixel driving circuit DC may be formed simultaneously with the light-blocking pattern 140. For example, the first capacitor electrode 171 of each pixel driving circuit DC may be in direct contact with the light-blocking pattern 140 disposed in the corresponding pixel region PA.

[0087] The first capacitor electrode 171 of each pixel driving circuit DC can be electrically connected to the second drain 124 of the corresponding pixel driving circuit DC. For example, the first capacitor electrode 171 of each pixel driving circuit DC can be connected to the second drain 124 of the corresponding pixel driving circuit DC through the drain area of ​​the light blocking pattern 140 and the second semiconductor pattern 121 disposed in the corresponding pixel region PA. The drain area of ​​the second semiconductor pattern 121 in each pixel region PA can be electrically connected to the light blocking pattern 140 in the corresponding pixel region PA. For example, the device buffer layer 111 can include a storage contact hole between the light blocking pattern 140 and the drain area of ​​the second semiconductor pattern 121 in each pixel region PA. The drain area of ​​the second semiconductor pattern 121 in each pixel region PA can be connected to the light blocking pattern 140 in the corresponding pixel region PA through one of the storage contact holes.

[0088] The second capacitor electrode 172 of each pixel driving circuit DC may include the same material as the semiconductor patterns 121 and 131 of the corresponding pixel driving circuit DC. For example, the second capacitor electrode 172 of each pixel driving circuit DC may include an oxide semiconductor, such as IGZO. The second capacitor electrode 172 of each pixel driving circuit DC may be formed simultaneously with the semiconductor patterns 121 and 131 of the corresponding pixel driving circuit DC. The second capacitor electrode 172 of each pixel driving circuit DC may have a resistance lower than that of the channel regions of the respective semiconductor patterns 121 and 131 in the corresponding pixel driving circuit DC. For example, the second capacitor electrode 172 of each pixel driving circuit DC may include a conductive region of an oxide semiconductor.

[0089] The third thin-film transistor T3 of each pixel driving circuit DC can reset the storage capacitor Cst of the corresponding pixel driving circuit DC according to the gate signal. For example, the third gate 132 of each pixel driving circuit DC can be electrically connected to one of the gate lines GL, the third source 133 of each pixel driving circuit DC can be electrically connected to one of the reference voltage supply lines RL, and the third drain 134 of each pixel driving circuit DC can be electrically connected to the storage capacitor Cst of the corresponding pixel driving circuit DC. The third gate 132 of each pixel driving circuit DC can be connected to one gate line GL, and the first gate of the corresponding pixel driving circuit DC can be connected to the same gate line GL. In other words, for each pixel driving circuit DC, the corresponding third gate 132 and the corresponding first gate can be connected to the same corresponding gate line GL. For example, the first thin-film transistor T1 and the third thin-film transistor T3 of each pixel driving circuit can be turned on / off simultaneously.

[0090] The reference voltage supply line RL may extend parallel to the power supply voltage supply line PL. For example, the reference voltage supply line RL may intersect with the gate line GL. The reference voltage supply line RL may be disposed on the same layer as the power supply voltage supply line PL. For example, the reference voltage supply line RL may be disposed between the device substrate 101 and the device buffer layer 111. The reference voltage supply line RL may include the same material as the power supply voltage supply line PL. For example, the reference voltage supply line RL may be formed simultaneously with the power supply voltage supply line PL. The device buffer layer 111 and the gate insulating layer 112 may include reference contact holes that expose a portion of each reference voltage supply line RL. The third source 133 of each pixel region PA may be connected to the corresponding reference voltage supply line RL through one of the reference contact holes.

[0091] The display panel 100 may include a display area AA with pixel areas PA and a bezel area BZ disposed outside the display area AA. For example, the bezel area BZ may surround the display area AA. Signal wirings DL, GL, PL, and RL may be disposed in the bezel area BZ to transmit various signals for controlling the light-emitting devices 150 of each pixel area PA. For example, data lines DL, gate lines GL, power supply lines PL, and reference voltage supply lines RL that are DC electrically connected to the pixel driving circuit of each pixel area PA may extend on the bezel area BZ of the device substrate 101. The device substrate 101 of the display panel 100 may be disposed in the display area AA and the bezel area BZ (or may extend in the display area AA and the bezel area BZ, or may extend throughout the entire display area AA and the bezel area BZ).

[0092] Figure 4 yes Figure 1 An example of a magnified view of the R region. Figure 5 It is along Figure 4 An example of a plot captured by I-I'. Figure 6 It is along Figure 4 Example of a plot taken from II-II'.

[0093] Reference Figures 1 to 6 In the display device according to an exemplary embodiment of the present disclosure, at least one of insulating layers 111, 112, 113, 114, and 115 may be disposed on the border region BZ of the device substrate 101. For example, the device buffer layer 111, the gate insulating layer 112, the device passivation layer 113, the outer coating layer 114, and the dam insulating layer 115 may extend on the border region BZ of the device substrate 101. The device buffer layer 111, the gate insulating layer 112, the device passivation layer 113, the outer coating layer 114, and the dam insulating layer 115 may be sequentially stacked on the border region BZ of the device substrate 101.

[0094] The end of each data line DL can be disposed on a border region BZ of the device substrate 101. For example, a separation groove cg can be provided in the border region BZ to separate each data line DL from adjacent data lines DL. The separation groove cg can be filled by insulating layers 112, 113, 114, and 115 stacked on the data lines DL. For example, the process of forming the data lines DL may include: forming conductors such that two adjacent lines are connected to each other in the border region BZ; testing the conductor state; forming the data lines DL by forming the separation groove cg in the border region BZ to cut a portion of each conductor; and filling the separation groove cg with a device buffer layer 111 formed by a subsequent process. Therefore, in the display device according to the exemplary embodiment of the present disclosure, the defect rate of the data lines DL can be significantly reduced.

[0095] At least one power supply voltage shorting bar SB may be disposed on the border region BZ of the device substrate 101. The power supply voltage shorting bar SB may be connected between power supply voltage supply lines PL. Therefore, in the display device according to the exemplary embodiment of the present disclosure, the power supply voltage applied through the power supply voltage supply line PL can be maintained constant. The power supply voltage shorting bar SB may intersect with the power supply voltage supply line PL. For example, the power supply voltage supply line PL may extend in a first direction, and the power supply voltage shorting bar SB may extend in a second direction perpendicular to the first direction.

[0096] The power supply voltage shorting bar SB may include a conductive material. The power supply voltage shorting bar SB may include a material with low resistance. For example, the power supply voltage shorting bar SB may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys of any of the above. The power supply voltage shorting bar SB may be disposed on a different layer than the power supply voltage supply line PL. For example, the power supply voltage shorting bar SB may be disposed between the gate insulating layer 112 and the device passivation layer 113. The power supply voltage shorting bar SB may include a material different from the power supply voltage supply line PL. The power supply voltage shorting bar SB may include the same material as the gates 122 and 132 of each pixel driving circuit DC. For example, the power supply voltage shorting bar SB may be formed simultaneously with the gates 122 and 132 of each pixel driving circuit DC.

[0097] The device buffer layer 111 and gate insulating layer 112 may include power connection holes that expose a portion of each power supply voltage line PL in the border region BZ. A power supply voltage shorting bar SB may be connected to each power supply voltage line PL through the power connection holes.

[0098] A moisture-blocking hole 170h can be provided on the border region BZ of the device substrate 101. The moisture-blocking hole 170h can penetrate insulating layers 114 and 115 made of organic insulating material. For example, the moisture-blocking hole 170h can penetrate the outer coating 114 and the embankment insulating layer 115 of the border region BZ. Each of the moisture-blocking holes 170h can penetrate the device passivation layer 113 that contacts the lower surface of the outer coating 114 towards the device substrate 101. In this regard, in an example, the outer coating 114 and the embankment insulating layer 115 can be etched so that the moisture-blocking hole 170h can penetrate them. Furthermore, the device passivation layer 113 can be etched so that the moisture-blocking hole 170h can penetrate it. Therefore, in a display device according to an exemplary embodiment of the present disclosure, a portion of the outer coating 114 and a portion of the embankment insulating layer 115 provided in the border region BZ can be completely removed to form the moisture-blocking hole 170h. For example, each of the moisture blocking holes 170h may include a lower blocking hole 171h that completely penetrates the outer coating 114 and an upper blocking hole 172h that completely penetrates the dike insulation layer 115.

[0099] The second electrode 153 of each light-emitting device 150 can be electrically connected to the power supply unit 500 in the bezel region BZ. For example, the light-emitting layer 152 and the second electrode 153 of each light-emitting device 150 can extend beyond the display region AA. The light-emitting layer 152 and the second electrode 153 can be sequentially stacked on the embankment insulating layer 115 of the bezel region BZ.

[0100] The second electrode 153 may extend on (or cover) the sidewalls 170hs of the moisture-blocking hole 170h. For example, the sidewalls 170hs of each moisture-blocking hole 170h may be completely covered by the second electrode 153. The sidewalls 170hs of each moisture-blocking hole 170h may include an upper sidewall 172hs and a lower sidewall 171hs. Furthermore, the second electrode 153 may extend to the bottom surface 170hb of the moisture-blocking hole 170h (or, may cover, completely cover, or directly contact the bottom surface 170hb of the moisture-blocking hole 170h). The second electrode 153 may be in direct contact with the gate insulating layer 112 in each moisture-blocking hole 170h. Therefore, in the display device according to the example embodiment of the present disclosure, external moisture that permeates through the outer coating 114 and the embankment insulation layer 115 of the frame region BZ can be blocked or delayed by the moisture blocking hole 170h and the second electrode 153.

[0101] The light-emitting layer 152 of the frame region BZ can be disposed only on the embankment insulating layer 115. For example, the sidewall 170hs of each moisture-blocking hole 170h can be in direct contact with (or covered by) the second electrode 153. Therefore, in the display device according to the exemplary embodiment of the present disclosure, the penetration of external moisture caused by the layer made of organic material can be effectively blocked or delayed.

[0102] A moisture-blocking hole 170h can be disposed between signal traces DL, GL, PL, and RL. For example, each moisture-blocking hole 170h can extend in the same direction as the signal traces DL, GL, PL, and RL. The moisture-blocking hole 170h can be disposed between the display area AA and the power supply voltage shorting bar SB. For example, the power supply voltage shorting bar SB may not overlap with the moisture-blocking hole 170h. Therefore, in the display device according to an exemplary embodiment of the present disclosure, short circuits between the signal traces DL, GL, PL, and RL and the power supply voltage shorting bar SB caused by the moisture-blocking hole 170h can be prevented.

[0103] The sensing line SL can be disposed on the border region BZ of the device substrate 101. The sensing line SL can detect short circuits in the signal wirings DL, GL, PL, and RL. For example, short circuits caused by cracks in at least a portion of the device substrate 101 and / or in the insulating layers 111, 112, 113, 114, and 115 disposed on the device substrate 101 due to external stress can be detected by the sensing line SL.

[0104] Sensing lines SL can be disposed between signal lines DL, GL, PL, and RL. For example, each sensing line SL can be disposed between data lines DL separated by the separation groove cg. Sensing lines SL can extend in the same direction as adjacent signal lines DL, GL, PL, and RL. For example, sensing lines SL can extend parallel to data lines DL. Moisture-blocking holes 170h can be disposed outside the sensing lines SL. For example, moisture-blocking holes 170h can be disposed between the sensing lines SL and the signal lines DL, GL, PL, and RL. Moisture-blocking holes 170h can be spaced apart from the separation groove cg. Therefore, the display device according to the exemplary embodiment of this disclosure can block or delay the penetration of external moisture without affecting short-circuit detection using sensing lines SL.

[0105] The sensing line SL may include a conductive material. The sensing line SL may include a material with low resistance. For example, the sensing line SL may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), and alloys of any of the above. Each sensing line SL may be electrically connected to one of the signal wirings DL, GL, PL, and RL electrically connected to each pixel region PA. The signal wirings DL, GL, PL, and RL electrically connected to the sensing line SL may provide a signal with a constant voltage to each pixel region PA. For example, the sensing line SL may be electrically connected to a reference voltage supply line RL. Therefore, a display device according to an exemplary embodiment of this disclosure can use the sensing line SL to detect short circuits in the signal wirings DL, GL, PL, and RL without changing the density of the signal wirings DL, GL, PL, and RL.

[0106] The sensing line SL can be disposed on a different layer than the reference voltage supply line RL. For example, the sensing line SL can be disposed between the gate insulating layer 112 and the device passivation layer 113. The device buffer layer 111 and the gate insulating layer 112 may include contact holes that partially expose the ends of each reference voltage supply line RL. Each sensing line SL can directly contact the corresponding reference voltage supply line RL through one of the contact holes. The sensing line SL can include the same material as the gates 122 and 132 of each pixel driving circuit DC. For example, the sensing line SL can be formed simultaneously with the gates 122 and 132 of each pixel driving circuit DC.

[0107] An encapsulation substrate 190 may be disposed on the second electrode 153 of each light-emitting device 150. The encapsulation substrate 190 can prevent the light-emitting device 150 from being damaged by external impact and moisture. For example, the encapsulation substrate 190 may include a material with a specific hardness. For example, the encapsulation substrate 190 may include a material with relatively high thermal conductivity. For example, the encapsulation substrate 190 may include metals such as aluminum (Al), nickel (Ni), iron (Fe), and alloys of any of the above. Therefore, in the display device according to the exemplary embodiment of this disclosure, the heat generated by the pixel driving circuit DC of each pixel region PA and the light-emitting device 150 can be dissipated through the encapsulation substrate 190. Therefore, in the display device according to the exemplary embodiment of this disclosure, the deterioration of the light-emitting layer 152 can be minimized.

[0108] The encapsulation substrate 190 can be attached to the device substrate 101 on which the light-emitting device 150 is formed. For example, the encapsulation element 180 can be disposed in the space between the light-emitting device 150 and the encapsulation substrate 190. The encapsulation element 180 may include an adhesive material. The encapsulation element 180 may include an insulating material. For example, the encapsulation element 180 may include an olefin-based material. The encapsulation element 180 may have a relatively low water vapor transmission rate (WVTR). Therefore, in the display device according to the embodiments of the present disclosure, external moisture can be prevented from penetrating through the encapsulation element 180.

[0109] The encapsulation element 180 and the encapsulation substrate 190 can extend on the border region BZ of the device substrate 101. For example, the encapsulation element 180 can fill the moisture-blocking hole 170h. Therefore, in the display device according to the embodiments of the present disclosure, the moisture-blocking hole 170h, the second electrode 153, and the encapsulation element 180 can block or delay external moisture from penetrating through the outer coating 114 and the embankment insulating layer 115 of the border region BZ.

[0110] Therefore, a display device according to an exemplary embodiment of the present disclosure may include a light-emitting device 150 on a display area AA of a device substrate 101, signal wirings DL, GL, PL, and RL between the device substrate 101 and the light-emitting device 150, and insulating layers 111, 112, 113, 114, and 115 insulating the signal wirings DL, GL, PL, and RL. The signal wirings DL, GL, PL, and RL, the insulating layers 111, 112, 113, 114, and 115, and the second electrode 153 of each light-emitting device 150 may extend on a border region BZ of the device substrate 101. Furthermore, the outer coating 114, comprising an organic insulating material, and the sidewalls of the embankment insulating layer 115 in the insulating layers 111, 112, 113, 114, and 115 of the border region BZ may be covered by the second electrode 153. Therefore, in the display device according to an exemplary embodiment of the present disclosure, external moisture can be blocked or delayed from penetrating through the insulating layers made of organic insulating material. Therefore, in the display device according to the example embodiment of the present disclosure, the degradation of the light-emitting layer 152 and the deterioration of the image quality provided to the user due to the penetration of external moisture can be minimized.

[0111] The example display device according to embodiments of the present disclosure assumes that the data driver 200, gate driver 300, timing controller 400, and power supply unit 500 are disposed outside the display panel 100. However, in a display device according to another example embodiment of the present disclosure, at least one of the data driver 200, gate driver 300, timing controller 400, and power supply unit 500 may be disposed on the bezel region BZ of the display panel 100. For example, the display device according to another example embodiment of the present disclosure may be a gate-in-panel (GIP) type display device in which the gate driver 300 is formed in the bezel region BZ of the display panel 100.

[0112] In a display device according to another example embodiment of the present disclosure, the encapsulation element 180 may include moisture-absorbing particles. Therefore, in the display device according to another embodiment of the present disclosure, external moisture that has permeated through the outer coating 114 and the embankment insulation layer 115 of the bezel region BZ can be collected in the encapsulation element 180. Thus, in the display device according to another example embodiment of the present disclosure, the permeation of external moisture can be effectively blocked or delayed.

[0113] The display device according to an example embodiment of the present disclosure assumes that the gate insulating layer 112 of the bezel region BZ can be partially exposed by the moisture-blocking hole 170h. However, in another example display device according to another embodiment of the present disclosure, as Figure 7 As shown, the moisture-blocking hole 170h can penetrate the device buffer layer 111, gate insulating layer 112, device passivation layer 113, outer coating layer 114, and embankment insulating layer 115 of the frame region BZ. For example, in a display device according to another exemplary embodiment of the present disclosure, the frame region BZ of the device substrate 101 can be partially exposed by the moisture-blocking hole 170h. Therefore, in a display device according to another exemplary embodiment of the present disclosure, the penetration of external moisture can be effectively blocked or delayed by the moisture-blocking hole 170h.

[0114] The display device according to an exemplary embodiment of the present disclosure assumes that a moisture-blocking hole 170h extending in the same direction as the signal wirings DL, GL, PL, and RL is provided on the border region BZ of the device substrate 101. However, the display device according to another exemplary embodiment of the present disclosure may use various openings to block or delay the penetration of external moisture through the outer coating 114 and the dam insulation layer 115 of the border region BZ. For example, in the display device according to an exemplary embodiment of the present disclosure, a moisture-blocking trench 170t penetrating the device passivation layer 113, the outer coating 114, and the dam insulation layer 115 of the border region BZ may be provided outside the power supply voltage shorting bar SB, wherein the moisture-blocking trench 170t may extend parallel to the power supply voltage shorting bar SB, and wherein, as Figure 8 and 9As shown, the inner sidewall 170tis of the moisture-blocking trench 170t facing the display area AA can be covered by the second electrode 153 of each light-emitting device 150. That is, in a display device according to another example embodiment of the present disclosure, the moisture-blocking trench 170t, including the lower trench 171t that completely penetrates the outer coating 114 and the upper trench 172t that completely penetrates the embankment insulating layer 115, can extend along the edge of the display area AA. For example, the outer coating 114 and the embankment insulating layer 115 in the frame area BZ can be completely separated from the outer coating 114 and the embankment insulating layer 115 in the display area AA by the moisture-blocking trench 170t. Therefore, in a display device according to another example embodiment of the present disclosure, external moisture that permeates through the outer coating 114 and the embankment insulating layer 115 in the frame area BZ can be blocked by the moisture-blocking trench 170t and the second electrode 153. Therefore, in a display device according to another example embodiment of the present disclosure, the degradation of the light-emitting layer 152 due to the penetration of external moisture can be minimized. In this respect, the inner wall 170tis of the water-blocking trench 170t may include an upper inner wall 172tis and a lower inner wall 171tis.

[0115] The second electrode 153 may extend on the outer wall 170tos of the moisture-blocking trench 170t opposite to the display area AA (or may cover or directly contact the outer wall 170tos). For example, the second electrode 153 may extend along the surface of the moisture-blocking trench 170t. Therefore, in a display device according to another exemplary embodiment of the present disclosure, image quality degradation due to external moisture can be minimized. In one or more examples, the outer wall 170tos of the moisture-blocking trench 170t may include an upper outer wall 172tos and a lower outer wall 171tos. In this regard, the second electrode 153 may extend on the bottom surface 170tb of the moisture-blocking trench 170t (or may cover or directly contact the bottom surface 170tb) to minimize the penetration of external moisture.

[0116] In a display device according to another exemplary embodiment of the present disclosure, the inner and outer walls of the moisture-blocking groove 170t can have various shapes. For example, in a display device according to another exemplary embodiment of the present disclosure, such as Figure 10 and Figure 11 As shown, the planar shape of each of the inner and outer sidewalls of the moisture-blocking groove 170t can be concave or convex. Therefore, in a display device according to another exemplary embodiment of this disclosure, the penetration of external moisture can be effectively blocked or delayed.

[0117] In a display device according to another exemplary embodiment of the present disclosure, each of the inner and outer sidewalls of the moisture-blocking trench 170t may have a stepped shape. For example, each of the inner and outer sidewalls of the moisture-blocking trench 170t may include a stepped portion 114f. The stepped portion 114f may be formed on the outer coating 114 of the bezel region BZ. The stepped portion 114f may be formed using a halftone mask. For example, in a display device according to another exemplary embodiment of the present disclosure, a method of forming the moisture-blocking trench 170t may include: placing a halftone mask including a transparent area corresponding to the bottom surface of the moisture-blocking trench 170t and a halftone area corresponding to the stepped portion 114f on the outer coating 114; exposing the outer coating 114 of the bezel region BZ using the halftone mask; forming the stepped portion 114f by removing the exposed portion of the outer coating 114; and forming a dam insulating layer 115 on the outer coating 114 including an opening exposing the stepped portion 114f. Therefore, in a display device according to another example embodiment of the present disclosure, the second electrode 153 can be continuously connected to the inner and / or outer walls of the moisture-blocking trench 170t. That is, in a display device according to another example embodiment of the present disclosure, the second electrode 153 can be prevented from being disconnected due to the moisture-blocking trench 170t. Therefore, in a display device according to another example embodiment of the present disclosure, the outer coating 114 and the embankment insulating layer 115 can be formed to a sufficient thickness, and the inner and outer walls of the moisture-blocking trench 170t can be completely covered by the second electrode 153.

[0118] like Figure 12 As shown, a display device according to another example embodiment of the present disclosure may include a moisture-blocking hole 170h between the signal wirings DL, PL, and RL and the sensing line SL, and a moisture-blocking trench 170t disposed outside the power supply voltage shorting bar SB. Therefore, in the display device according to another example embodiment of the present disclosure, the degradation of the light-emitting layer 152 due to external moisture can be significantly reduced.

[0119] like Figure 13 and Figure 14As shown, a display device according to another example embodiment of this disclosure may include a first blocking pattern 175a on the lower sidewall 171hs of each lower blocking hole 171h and a second blocking pattern 175b on the lower inner sidewall 171tis and lower outer sidewall 171tos of each lower trench 171t. The first blocking pattern 175a and the second blocking pattern 175b may include a material capable of blocking or delaying moisture. The first blocking pattern 175a and the second blocking pattern 175b may be formed using a process of forming a layer between the outer coating 114 and the second electrode 153. For example, the first blocking pattern 175a and the second blocking pattern 175b may be formed simultaneously with the first electrode 151 of each light-emitting device. The first blocking pattern 175a and the second blocking pattern 175b may include the same material as the first electrode of each light-emitting device. In one or more aspects, the first blocking pattern 175a and the second blocking pattern 175b may be examples of moisture-blocking patterns.

[0120] The first blocking pattern 175a and the second blocking pattern 175b may be spaced apart (or separated) from each other. For example, the end of each first blocking pattern 175a and the end of each second blocking pattern 175b may be disposed between the outer coating 114 of the frame region BZ and the embankment insulation layer 115. The second electrode 153 may be in direct contact with (or may cover) the sidewalls 172hs of each upper blocking hole 172h and the sidewalls 172ts of each upper trench 172t. The second electrode 153 may be in direct contact with (or may cover) the first blocking pattern 175a and the second blocking pattern 175b in the lower blocking hole 171h and the lower trench 171t, respectively. Therefore, in a display device according to another exemplary embodiment of the present disclosure, the penetration of external moisture can be effectively blocked or delayed.

[0121] In a display device according to another exemplary embodiment of the present disclosure, the first blocking pattern 175a (see reference) Figure 13 ) and the second electrode 153 (refer to) Figure 6 One of the following can be stacked on (or can cover) the lower sidewall 171hs of each lower blocking hole 171h penetrating the outer coating 114, and the second blocking pattern 175b (refer to) Figure 14 ) and the second electrode 153 (refer to) Figure 9 One of the following can be stacked on the lower inner wall 171tis and lower outer wall 171tos of the lower groove 171t penetrating the outer coating 114 (or can cover the lower inner wall 171tis and lower outer wall 171tos penetrating the outer coating 114). Therefore, in a display device according to another exemplary embodiment of this disclosure, for example, as... Figure 13 and Figure 14 As shown, external moisture can be blocked or delayed even without the second electrode 153 on the lower blocking hole 171h and lower trench 171t. For example, in a display device according to another exemplary embodiment of the present disclosure, external moisture can be blocked or delayed even when the second electrode 153 is partially disconnected in the lower blocking hole 171h and / or lower trench 171t (or does not cover the lower blocking hole 171h and / or lower trench 171t, or is not provided in the lower blocking hole 171h and / or lower trench 171t).

[0122] In a display device according to another exemplary embodiment of the present disclosure, such as Figure 15 and Figure 16 As shown, the upper blocking hole 172h of each moisture blocking hole 170h can be disposed in the lower blocking hole 171h of the corresponding moisture blocking hole 170h, and the upper groove 172t of each moisture blocking groove 170t can be disposed in the lower groove 171t of the corresponding moisture blocking groove 170t. In this respect, the upper blocking hole 172h of each moisture blocking hole 170h can extend into the region of the lower blocking hole 171h of the corresponding moisture blocking hole 170h, and the upper groove 172t of each moisture blocking groove 170t can extend into the region of the lower groove 171t of the corresponding moisture blocking groove 170t. For example, the sidewalls 114s of the outer coating 114 exposed by the lower blocking hole 171h and the lower groove 171t can be covered by the dike insulation layer 115. During the manufacturing process, after the outer coating 114 is formed (or deposited), the outer coating 114 can be etched to form sidewalls 114s to create lower blocking holes 171h and lower trenches 171t. Subsequently, a dam insulating layer 115 can be formed (or deposited) over the outer coating 114 and can cover the sidewalls 114s of the outer coating 114. Afterward, the dam insulating layer 114 can be etched to form sidewalls 115s, thus creating upper blocking holes 172h and upper trenches 172t. The dam insulating layer 115 can have a lower water vapor transmission rate (WVTR) than the outer coating 114. Therefore, in an example display device according to another embodiment of this disclosure, the degradation of the light-emitting layer 152 due to external moisture can be effectively improved.

[0123] A display device according to another exemplary embodiment of the present disclosure may include a packaged element 180 having a multilayer structure. For example, in a display device according to another exemplary embodiment of the present disclosure, such as Figures 17 to 19As shown, the encapsulation element 180 between the second electrode 153 and the encapsulation substrate 190 may have a stacked structure of a first encapsulation layer 181 and a second encapsulation layer 182. The second encapsulation layer 182 may be disposed between the first encapsulation layer 181 and the encapsulation substrate 190. For example, the encapsulation substrate 190 may be in direct contact with the second encapsulation layer 182. Moisture-absorbing particles 182p may be disposed in the second encapsulation layer 182. Therefore, in a display device according to another exemplary embodiment of the present disclosure, the stress applied to the light-emitting device 150 due to the expansion of the moisture-absorbing particles 182p can be alleviated by the first encapsulation layer 181.

[0124] The moisture-blocking holes 170h and moisture-blocking trenches 170t on the frame region BZ of the device substrate 101 can be filled by the first encapsulation layer 181. Therefore, in a display device according to another exemplary embodiment of the present disclosure, external moisture that permeates through the outer coating 114 and the embankment insulating layer 115 of the frame region BZ can be collected by moisture-absorbing particles 182p, and damage to the second electrode 153 due to the expansion of the moisture-absorbing particles 182p can be prevented by the first encapsulation layer 181. Therefore, in a display device according to another exemplary embodiment of the present disclosure, the deterioration of each light-emitting layer 152 due to the penetration of external moisture can be minimized.

[0125] Return to reference Figure 2 The light-emitting device 150 in this example embodiment has an anode connected to the second thin-film transistor T2 and the third thin-film transistor T3 (e.g., connected to the source or drain of each of the thin-film transistors T2 and T3) and a cathode connected to a node or line for engaging with a voltage power supply, such as a low-voltage power supply (e.g., ground). Figure 2 The anode and cathode of the light-emitting device 150 can respectively correspond to Figure 3 The light-emitting device 150 has a first electrode 151 and a second electrode 153. However, it should be noted that this technical solution is not limited to... Figure 2 The circuit configuration shown. For example, Figure 20 A circuit configuration in a portion of a pixel region according to another example embodiment of this disclosure is shown. Figure 20 In this example, the light-emitting device 150 can be positioned above the thin-film transistor T4 that can drive the light-emitting device 150. The anode of the light-emitting device 150 can be connected to a node or line for engagement with a voltage power supply (e.g., a high-voltage power supply EVDD), and the cathode of the light-emitting device 150 can be connected to the thin-film transistor T4 (e.g., connected to the source or drain of the thin-film transistor T4). Figure 20 The anode and cathode of the light-emitting device 150 can respectively correspond to Figure 3 The second electrode 153 and the first electrode 151 of the light-emitting device 150. Figure 20Only a portion of the pixel region PA is shown, and the pixel region PA may include other components. It should be noted that... Figure 2 and Figure 20 These are example circuit configurations, and the present invention is not limited to these configurations.

[0126] Based on the description provided herein, a display device according to embodiments of the present disclosure may include an outer coating on a display area and a bezel area of ​​a device substrate, a light-emitting device on the outer coating of the display area, a retaining layer covering the edge of a first electrode of the light-emitting device, and at least one opening (e.g., a moisture-blocking hole or a moisture-blocking trench) penetrating the outer coating and the retaining layer of the bezel area, wherein the sidewalls of the opening may be covered by a second electrode of the light-emitting device. Therefore, in the display device according to embodiments of the present disclosure, external moisture can be blocked or delayed from penetrating through the outer coating and the retaining layer. Consequently, in the display device according to embodiments of the present disclosure, image quality degradation due to external moisture can be minimized.

Claims

1. A display device, comprising: The display area and the border area are provided, wherein the border area is located outside the display area; A device substrate, wherein the device substrate is disposed in the display area and the bezel area; A light-emitting device is disposed on the display area of ​​the device substrate, and the light-emitting device includes a first electrode, a light-emitting layer and a second electrode stacked in sequence; An outer coating is disposed between the device substrate and the light-emitting device, and the outer coating extends on the border area of ​​the device substrate; A dike-like insulating layer covering the edge of the first electrode, the dike-like insulating layer extending over the outer coating of the frame region; and Moisture-blocking holes are disposed on the frame area of ​​the device substrate. The moisture-blocking pores penetrate the outer coating and the dike insulation layer. The second electrode of the light-emitting device extends on the sidewall of the moisture-blocking hole, and The second electrode is spaced apart from the signal wiring disposed in the frame area in a portion of the moisture blocking hole.

2. The display device according to claim 1, wherein, The second electrode of the light-emitting device comprises metal.

3. The display device according to claim 1, wherein, The first electrode is closer to the outer coating than the second electrode.

4. The display device according to claim 1, wherein, The second electrode of the light-emitting device extends on the bottom surface of the moisture-blocking hole.

5. The display device according to claim 1, further comprising: The pixel driving circuit is electrically connected to the signal wiring in the display area. The signal wiring extends on the display area of ​​the device substrate, and the moisture blocking holes are disposed between the signal wiring in the frame area.

6. The display device according to claim 5, wherein, The moisture-blocking hole extends in the same direction as the signal wiring.

7. The display device according to claim 1, further comprising: A moisture-blocking pattern is disposed between the sidewall of the moisture-blocking hole and the second electrode of the light-emitting device.

8. The display device according to claim 7, wherein, The end of the moisture-blocking pattern is located in the border area between the outer coating and the dike insulation layer.

9. The display device according to claim 7, wherein, The moisture-blocking pattern comprises the same material as the first electrode of the light-emitting device.

10. The display device according to claim 7, wherein, The moisture-blocking pattern is formed simultaneously with the first electrode of the light-emitting device.

11. The display device according to claim 1, further comprising: A packaging element that covers the light-emitting device and extends over the border region of the device substrate. The moisture-blocking holes are filled by the encapsulation element.

12. The display device according to claim 11, wherein, The encapsulation element includes moisture-absorbing particles.

13. A display device, comprising: Device substrate; An outer coating is disposed on the display area and the border area of ​​the device substrate; A light-emitting device is disposed on the outer coating of the display area, and the light-emitting device includes a first electrode, a light-emitting layer and a second electrode stacked in sequence. A dike insulating layer, the dike insulating layer covering the edge of the first electrode, the dike insulating layer extending on the outer coating of the frame region; as well as A moisture-blocking trench that penetrates the outer coating and the embankment insulation layer in the frame area. The moisture-blocking grooves extend along the edge of the display area. The inner wall of the moisture-blocking trench facing the display area is covered by the second electrode of the light-emitting device, and The second electrode is spaced apart from the signal wiring disposed in the frame area in a portion of the moisture barrier trench.

14. The display device according to claim 13, wherein, The second electrode of the light-emitting device extends on the outer wall of the moisture-blocking trench opposite to the display area.

15. The display device according to claim 13, wherein, The moisture-blocking trench includes a lower trench that penetrates the outer coating and an upper trench that penetrates the embankment insulation layer. The upper groove is disposed in the lower groove, and The sidewalls of the lower trench are covered by the embankment insulation layer.

16. The display device according to claim 13, wherein, The insulating layer of the dike has a lower water vapor permeability than the outer coating.

17. The display device according to claim 13, further comprising: A pixel driving circuit is electrically connected to the signal wiring in the display area, wherein the signal wiring extends on the display area of ​​the device substrate, and the moisture blocking trench is disposed on the outside of the signal wiring.

18. The display device according to claim 13, further comprising: Moisture-blocking holes are disposed between the signal wirings in the frame area. The sidewall of the moisture-blocking hole is covered by the second electrode of the light-emitting device.

19. The display device according to claim 13, further comprising: A device passivation layer is disposed between the device substrate and the outer coating layer. The device passivation layer comprises a material different from the outer coating and the dike insulation layer, and the moisture-blocking trench penetrates the device passivation layer.

20. The display device according to claim 13, wherein, The inner wall of the water-blocking trench has a stepped shape.

21. The display device according to claim 13, wherein, In the plan view, the inner wall of the water-blocking trench has an uneven shape.

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