Wafer cutting method and apparatus, electronic device

Abstract

The present disclosure provides a wafer cutting method and device, and electronic equipment, and belongs to the technical field of wafer cutting. The wafer cutting method comprises the following steps: providing a wafer to be cut, the wafer being provided with a plurality of chips to be separated and a cutting lane between the plurality of chips, the cutting lane having a test interconnection structure; using narrow-band laser to perform twice laser on the cutting lane at different angles to form two groups of narrow grooves in the length direction of the cutting lane; using wide-band laser to perform twice laser on the cutting lane at different angles to laser the two groups of narrow grooves into wide grooves, and the wide grooves are used as cutting grooves; and cutting the wafer along the cutting grooves to complete the separation of the plurality of chips. The present application optimizes the laser process, effectively shortens the cutting time on the basis of maintaining the original equipment, improves the production line capacity, and increases the stress of IC after laser.

Description

Technical Field

[0001] This disclosure relates to the field of wafer laser technology, and in particular to a wafer dicing method and apparatus, and electronic equipment. Background Technology

[0002] As semiconductor process requirements become increasingly stringent, chip design demands are also rising, leading to higher requirements for chip performance testing. Currently, chip performance testing typically requires the chip to be electrically conductive; therefore, dielectric materials are generally laid on the wafer dicing surfaces. Low-k dielectric materials are usually brittle and hard, and cutting wafers using blade dicing can cause them to break or even extend. Therefore, current technology typically uses laser technology to cut these wafers.

[0003] In existing technologies, wafer laser dicing technology separates integrated circuit (IC) chips from wafers. First, a three-pass dicing process is used to complete the transverse (CH2) dicing of the wafer. Then, the wafer's platform is rotated 90°, and a third three-pass dicing process is used to complete the longitudinal (CH1) dicing. In the three steps of the 3-pass dicing process, the first step involves laser-cutting two thin protective grooves within the dicing channel, known as dual-narrow grooving. The second step uses a wide-beam laser to create a wide groove between the two protective grooves, laser-cutting a portion of the metal within the dicing channel. The third step again uses a wide-beam laser to remove the low-dielectric-constant dielectric material layer from the dicing channel, aiming to achieve a smooth bottom surface and the required cutting depth.

[0004] The 3-pass cutting mode described above can generally meet user needs when cutting dielectric materials and small amounts of metal. However, if there is a large metal layer on the cutting path, cutting that metal layer will present many problems. For example, when using Dual Narrow grooving, the laser power is low and the laser area is small (10μm for single-point laser cutting), resulting in less heat-affected zone. However, when using Wide Beam laser cutting, the laser area is large and the energy is high, which can cause a large amount of metal on the cutting path to melt, resulting in slag splashing. This can damage products near the cutting path, and the damaged products can also affect subsequent circuit communication, causing abnormal conditions such as short circuits and open circuits.

[0005] To address this, existing technologies employ a 6-pass cutting pattern for cutting dielectric materials and metals. For example, the first step uses laser trench beam grooving; the second to fourth steps use laser trench beam grooving to continue grooving, but the grooving size decreases progressively; and the fifth and sixth steps use laser grooving to partially cut the metal, ensuring a smooth bottom and achieving the required cutting depth. However, this 6-pass cutting pattern requires multiple laser grooving operations to reach the desired depth, resulting in a lengthy and cumbersome process that impacts production efficiency. Summary of the Invention

[0006] This disclosure aims to address at least one of the problems existing in the prior art by providing a wafer dicing method, apparatus, and electronic device.

[0007] One aspect of this disclosure provides a wafer dicing method, the wafer dicing method comprising:

[0008] A wafer to be diced is provided, the wafer having a plurality of chips to be diced and dicing channels located between the plurality of chips, the dicing channels having a test interconnect structure;

[0009] The cutting path is lasered twice at different angles using a narrow-band laser to form two sets of narrow grooves along the length of the cutting path.

[0010] The cutting path is lasered twice at different angles using a broadband laser to laser the two sets of narrow grooves into wide grooves, which are then used as cutting grooves.

[0011] The wafer is cut along the cutting groove to complete the dicing of multiple chips.

[0012] Optionally, the step of using a narrow-band laser to laser the cutting path twice at different angles to form two sets of narrow grooves along the length of the cutting path includes:

[0013] At the first laser angle, the first set of laser spots is focused on the cutting track for the first laser to form the first set of narrow grooves in the length direction of the cutting track.

[0014] At the second laser angle, the second set of laser spots is focused on the cutting track for a second laser irradiation to form a second set of narrow grooves along the length of the cutting track.

[0015] Optionally, both the first laser angle and the second laser angle are in the range of 0-30°.

[0016] Optionally, the first set of light spots includes four first sub-light spots, and the distance between the four first sub-light spots along their width direction on the cutting track is the first narrow band laser width;

[0017] The second set of light spots includes four second sub-light spots. The distance between the four second sub-light spots along the width direction on the cutting path is the second narrow band laser width, which is smaller than the first narrow band laser width.

[0018] Optionally, both the first narrowband laser width and the second narrowband laser width are calculated using the following formula (I):

[0019] X = sin(90-θ)*(d+2r)(I)

[0020] Where X is the narrowband laser width, θ is the laser angle, d is the distance between the four sub-spots, and r is the radius of the sub-spot.

[0021] Optionally, the step of using a broadband laser to laser the cutting path twice at different angles to laser the two sets of narrow grooves into wide grooves includes:

[0022] The laser angles of three preset light spots are switched to form a main cutting light spot and a secondary cutting light spot, wherein the energy of the main cutting light spot is greater than the energy of the secondary cutting light spot;

[0023] The main cutting spot is focused in the central region of the cutting channel, and the secondary cutting spot is focused in the edge region of the cutting channel for a third laser lithography, so as to laser the two sets of narrow grooves into wide grooves.

[0024] Three preset laser spots are focused onto the cutting path for a fourth laser pass to achieve the preset laser depth.

[0025] Optionally, the laser angle range for switching the three sets of preset light spots is 0-1°.

[0026] Optionally, each set of preset light spots includes four sub-light spots;

[0027] The main cutting spot includes three sets of cutting spots, and the secondary cutting spot includes one set or one set of half-cutting spots.

[0028] In another aspect of this disclosure, a wafer dicing apparatus is provided, the wafer dicing apparatus comprising:

[0029] An enhancement module is used to provide a wafer to be diced, the wafer being provided with a plurality of chips to be diced and dicing channels located between the plurality of chips, the dicing channels having a test interconnect structure;

[0030] A narrow-band laser module is used to laser the cutting path twice at different angles using a narrow-band laser to form two sets of narrow grooves along the length of the cutting path.

[0031] A broadband laser module is used to laser the cutting path twice at different angles using a broadband laser to laser the two sets of narrow grooves into wide grooves, and use them as cutting grooves.

[0032] A cutting module is used to cut the wafer along the cutting groove to complete the slicing of multiple chips.

[0033] In another aspect of this disclosure, an electronic device is proposed, comprising:

[0034] At least one processor; and,

[0035] A memory communicatively connected to the at least one processor; wherein,

[0036] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the wafer dicing method described above.

[0037] This disclosure proposes a wafer dicing method, apparatus, and electronic device. By optimizing the laser process, this disclosure uses a narrow-band laser to perform two laser lithography operations at different angles on the dicing track, forming two sets of narrow trenches along the length of the dicing track. This allows for the segmented breaking of metal when testing interconnect layers containing a large amount of metal, reducing the risk of molten slag sputtering. Furthermore, by using a broadband laser to perform two laser lithography operations on the dicing track at different angles, the two sets of narrow trenches are laser-laid into wide trenches, which are then used as dicing grooves. This reduces the degree of melting at the edge region of the dicing track, increases IC stress, and prevents problems such as warping and cracking in chip products. The method of this disclosure requires only four laser lithography operations to achieve the user's required depth, shortening the dicing time, increasing the capacity of the wafer dicing production line, and simultaneously increasing the number of good chip products obtained from wafer dicing, reducing product loss, increasing the product yield of wafer dicing, and improving product quality. Attached Figure Description

[0038] One or more embodiments are illustrated by way of example with the corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0039] Figure 1 A flowchart illustrating a wafer dicing method according to one embodiment of this disclosure;

[0040] Figure 2 A schematic diagram of the structure of a wafer provided for another embodiment of this disclosure;

[0041] Figure 3A schematic diagram illustrating the first laser treatment of the cutting path using a narrow-band laser, provided as another embodiment of this disclosure;

[0042] Figure 4 A schematic diagram illustrating a second laser treatment of the cutting path using a narrow-band laser, provided as another embodiment of this disclosure;

[0043] Figure 5 A schematic diagram of the spot structure of a narrowband laser using 4UV50 is provided for another embodiment of this disclosure; wherein, Figure 5 In the diagram, A represents a laser spot with a laser angle of 0°. Figure 5 B in the diagram represents a laser spot with a laser angle of θ.

[0044] Figure 6 A schematic diagram illustrating laser engraving of a cutting track using a broadband laser, provided as another embodiment of this disclosure;

[0045] Figure 7 A schematic diagram of the beam structure of a broadband laser using 4UV10 / 3UV100 is provided for another embodiment of this disclosure; wherein, Figure 7 In the diagram, A represents a laser spot with a laser angle of 0°. Figure 7 B in the diagram represents a laser spot with a laser angle of α.

[0046] Figure 8 The depth measurement result is obtained after dicing a wafer using a wafer dicing method provided in another embodiment of this disclosure;

[0047] Figure 9 The width measurement result is obtained after the wafer is cut using the wafer cutting method provided in another embodiment of this disclosure;

[0048] Figure 10 This is a comparison diagram showing the effects of existing wafer dicing processes and the wafer dicing method provided in this disclosure; wherein... Figure 10 In this context, A represents the 6-pass laser cutting process used in existing technologies. Figure 10 In this disclosure, B represents the 4-pass laser cutting process used.

[0049] Figure 11 This is a comparison image showing the depth and width after laser etching using existing wafer dicing processes and the wafer dicing method provided in this disclosure; wherein... Figure 11 In the diagram, A represents the depth and width after using the 6-pass laser cutting process in the existing technology. Figure 11 B in the diagram represents the depth and width of the material after the 4-pass laser cutting process was used in this disclosure.

[0050] Figure 12This is a comparison chart of IC reliability data between existing wafer dicing processes and the wafer dicing method provided in this disclosure; wherein... Figure 12 In this context, A represents the IC reliability data corresponding to the 6-pass laser cutting process in existing technologies. Figure 12 In this disclosure, B represents the IC reliability data corresponding to the 4-pass laser cutting process.

[0051] Figure 13 A schematic diagram of the structure of a wafer dicing apparatus provided in another embodiment of this disclosure;

[0052] Figure 14 A schematic diagram of the structure of an electronic device provided in another embodiment of this disclosure. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and with various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0054] One embodiment of this disclosure relates to a wafer dicing method S100, the process of which is as follows: Figure 1 As shown, it includes:

[0055] Step S110: A wafer to be diced is provided. The wafer is provided with multiple chips to be diced and dicing channels located between the multiple chips. The dicing channels are provided with test interconnect structures.

[0056] Specifically, combined Figure 2 The wafer 100 may have multiple chips 110 and dicing channels 120 located between the multiple chips 110. The dicing channels 120 may have test interconnect structures, through which each chip 110 can be connected to perform performance testing. Therefore, in addition to having a dielectric material layer, the test interconnect structure may also have a metal layer on the dielectric material layer to connect each chip 110 through the metal layer.

[0057] It should be understood that before using laser technology to diced the wafer, the width and depth of the laser need to be determined. That is, before step S120, the method disclosed herein also includes: determining the broadband laser depth of the broadband laser based on the thickness of the wafer; and determining the narrowband laser width of the narrowband laser and the broadband laser width of the broadband laser based on the width of the dicing track.

[0058] Furthermore, based on the narrowband laser width obtained from the above steps, the laser angles in the following laser steps can also be determined.

[0059] Step S120: Use a narrow-band laser to laser the cutting path twice at different angles to form two sets of narrow grooves along the length of the cutting path.

[0060] Specifically, combined Figures 3 to 6 At a first laser angle, a first set of laser spots 130 is focused on the dicing track 120 for a first laser irradiation, forming a first set of narrow grooves 150 along the length of the dicing track 120. At a second laser angle, a second set of laser spots 140 is focused on the dicing track 120 for a second laser irradiation, forming a second set of narrow grooves 160 along the length of the dicing track 120. In other words, in this embodiment, a Trench Beam 4UV50 is used for one laser irradiation (X / Y direction), and after rotating the Trench Beam angle, a second laser irradiation (X / Y direction) is performed using the 4UV50. Only two laser irradiations are required to complete the process of breaking down the metal and dielectric materials on the test interconnect structure.

[0061] It should be noted that, since this embodiment uses a 4UV50 narrowband laser, the first group of light spots has four first sub-spots, and the second group of light spots has four second sub-spots, each forming four beams. When these beams are focused onto the cutting path, four cutting grooves are formed on the cutting path, as shown below. Figures 3 to 6 As shown, the distance between the four first sub-spots in the first group of light spots 130 along the width direction of the cutting path 120 is the first narrow-band laser width X1. That is, the first group of narrow grooves 150 includes four first sub-narrow grooves, and the distance between the four first sub-narrow grooves along the width direction of the cutting path 120 is the first narrow-band laser width X1. Similarly, the distance between the four second sub-spots in the second group of light spots 140 along the width direction of the cutting path 120 is the second narrow-band laser width X2. That is, the second group of narrow grooves 160 includes four second sub-narrow grooves, and the distance between the four second sub-narrow grooves along the width direction of the cutting path 120 is the second narrow-band laser width X2.

[0062] Furthermore, in order to break the metal in the test interconnect structure into segments, the width of the second narrow-band laser X2 is smaller than the width of the first narrow-band laser X1. In this way, when the test interconnect structure contains a large amount of metal, the metal can be broken into segments by two narrow-band lasers in this step, reducing the risk of slag sputtering caused by metal melting.

[0063] Furthermore, the first narrowband laser width X1 and the second narrowband laser width X2 are both calculated using the following formula (I): X=sin(90-θ)*(d+2r)(I);

[0064] Where X is the narrowband laser width, i.e., X1 is the first narrowband laser width, X2 is the second narrowband laser width, θ is the first laser angle or the second laser angle, d is the distance between the four sub-spots, and r is the radius of the sub-spot.

[0065] Specifically, such as Figure 5 As shown, when using 4UV50 for narrowband laser, Figure 5 In this equation, 'l' represents the vertical distance between two sub-spots, which is 40 μm, and the sub-spot radius 'r' is 5 μm. Thus, the spacing between each sub-spot is 50 μm, the spacing 'd' between the four sub-spots is 150 μm, and (d+2r) = 160°. Based on this data, the narrowband laser width can be determined according to the width of the kerf, and thus the laser angle can be obtained; conversely, the laser angle can be determined according to the width of the kerf, and thus the narrowband laser width can be obtained.

[0066] It should be noted that when the width of the cutting track is different, other laser angles can be selected to determine different narrow band laser widths, and no specific limitation is made in this regard.

[0067] In some preferred embodiments, the range of both the first laser angle and the second laser angle is 0-30°.

[0068] For example, combined Figures 2 to 6 As shown, when the width of the cutting channel 120 is 60 μm, the first laser angle θ is 16°, and based on the above formula, the first narrow-band laser width X1 is 47.83 μm. When the second laser angle θ is 13°, the second narrow-band laser width X2 is 40.22 μm.

[0069] The narrowband laser used in this step employs a 4UV50 with four sub-spots. When the four sub-spots are focused on the cutting path, four narrow sub-grooves can be formed, effectively shortening the laser time. Furthermore, by adjusting the laser angle, the metal segments in the test interconnect structure can be broken up.

[0070] Step S130: Use a broadband laser to laser the cutting path twice at different angles to laser the two sets of narrow grooves into wide grooves, and use them as cutting grooves.

[0071] Specifically, such as Figure 6 and Figure 7 As shown, the laser angles of three preset laser spots 170 are switched to form a main cutting laser spot and a secondary cutting laser spot. The energy of the main cutting laser spot is greater than that of the secondary cutting laser spot. The main cutting laser spot is focused on the central region of the cutting path, and the secondary cutting laser spot is focused on the edge region of the cutting path for a third laser treatment to laser the two narrow grooves into wide grooves. The three preset laser spots 170 are then focused on the cutting path for a fourth laser treatment to achieve the preset laser depth. That is, after completing the Trench Beam laser treatment in step S120, the laser is switched to a wideband laser with grooving (4UV10 / 3UV100). The laser is then performed once by micro-rotation angle (X / Y direction), and then the laser is switched to wideband laser with grooving (4UV10 / 3UV100) once (X / Y direction).

[0072] In this embodiment, by micro-switching the angle of the broadband laser, the three sets of laser spots form a main cutting spot with higher energy and a secondary cutting spot with lower energy. That is, the density of the secondary cutting spot is smaller. In this way, when the secondary cutting spot is focused on the edge area of ​​the cutting channel, the degree of melting of the metal at the edge of the cutting channel can be reduced, and the flatness of the bottom of the cutting groove can be improved.

[0073] It should be noted that in broadband laser engraving, this embodiment uses 4UV10 / 3UV100 lasers to perform broadband laser engraving on the cutting path, such as... Figure 7 As shown, 4UV10 / 3UV100 represents 4 sub-spots. The spacing between the 4 sub-spots is h1 = 10 μm. There are 3 rows with 4 sub-spots per row and the row spacing is h2 = 100 μm, which forms three sets of preset spots. Each set of preset spots includes four sub-spots.

[0074] It should be understood that when the laser angles of the three preset laser spots are switched, it is equivalent to focusing the three laser spots on the cutting track in the form of a parallelogram. In this way, the middle sub-spots of the three preset laser spots are all focused on the central area of ​​the cutting track, forming three main cutting laser spots. A sub-spot on the edge of the first preset laser spot and a sub-spot on the edge of the last preset laser spot form a set of secondary cutting laser spots, which are used to focus on the edge area of ​​the cutting track to reduce the degree of melting of the metal at the edge of the cutting track.

[0075] It should be noted that the edge sub-spots in the three sets of preset spots can form a set of sub-cutting spots or a set and a half of sub-cutting spots. For example, when the switching laser angle is small, in addition to a sub-spot at the edge of the first set of preset spots and a sub-spot at the edge of the last set of preset spots forming a set of sub-cutting spots, the two outermost sub-spots of the preset spots in the middle set form a half set of sub-cutting spots.

[0076] In some preferred embodiments, the laser angle α for switching the three preset light spots ranges from 0 to 1°.

[0077] Specific, specific, such as Figure 7 As shown in Figure B, by switching the laser angle α = 0.5° of the three preset laser spots, when focused on the wafer dicing track, the three preset laser spots are distributed in a parallelogram, forming three main dicing spots in the central region and one or one and a half secondary dicing spots in the edge region. At this time, the broadband laser width W2 of the third laser is 41.23 μm. That is to say, when switching the laser angle of the three preset laser spots, there are three main dicing spots in the middle part of the dicing track to laser the central region of the dicing track, and only one or one and a half secondary dicing spots in the edge part to laser the edge region of the dicing track. Thus, the energy of the main dicing spots is greater than that of the secondary dicing spots, thereby reducing the degree of melting of the metal at the edge of the dicing track.

[0078] Furthermore, such as Figure 7 As shown in Figure A, when performing the fourth laser lithography on the dicing track using a broadband laser, there is no need to switch the laser angle; lithography can be performed directly at 0°. The three sets of laser spots are distributed in a rectangular pattern, and the broadband laser width W1 of the fourth laser lithography is 39.80 μm. In other words, when using three sets of preset laser spots for the fourth laser lithography of the dicing track, there are three sets of laser spots at both the edge and the middle of the dicing track, with higher energy to achieve the preset laser depth, meet the user's needs, and complete the wafer lithography.

[0079] In this embodiment, based on switching the laser angle of three preset light spots, when cutting the edge area of ​​the cutting channel, the original three light spots are changed to one light spot. The one light spot is used to burn the metal in the test interconnect structure, which effectively reduces the burning temperature, reduces the melting degree of the metal, and improves the flatness of the bottom.

[0080] It should be noted that during laser cutting, at the location where the laser hits the cutting track, substances such as metal or dielectric materials can sublimate or evaporate under the action of the laser, thereby removing the metal and dielectric materials at the laser-hit location and forming a cutting groove at the laser-hit location.

[0081] In step S140, the wafer is cut along the cutting groove formed in step S130 to complete the dicing of multiple chips.

[0082] Specifically, combined Figure 2As shown, this step can be based on the wideband laser width Grooving beam (4UV10 / 3UV100) and wideband laser depth, and use a preset laser power to laser cut the cutting channel 120 along the length direction of the cutting channel 120 through a wide beam laser method to complete the division of each chip 110.

[0083] Specifically, such as Figure 8 and Figure 9 As shown, the depth of the laser-etched wafer using the embodiments of this disclosure is 8±3μm and the width is 49±3μm, which meets the user's requirements for laser depth and width.

[0084] like Figure 10 and Figure 11 As shown, when a large amount of metal is present in the test interconnect structure of the cutting channel, the laser cutting effect is consistent when the 6-pass laser cutting process in the prior art and the 4-pass laser cutting process in this embodiment are used to cut samples 1, 2, and 3. There are no defects such as metal slag splashing, abnormal laser depth, or abnormal laser width.

[0085] Furthermore, such as Figure 12 As shown, the stress test SPEC B10 for the two cutting methods is >350MPa, and the reliability value B10 of the IC cut by the 6-pass laser cutting process is 457.3, while the reliability value B10 of the IC cut by the 4-pass laser cutting process in this embodiment is 529. Compared with the cutting methods of the prior art, the IC reliability value of this embodiment is improved.

[0086] Furthermore, it takes 46 minutes to cut a wafer using the 6-pass laser cutting process, while it takes 36 minutes to cut a wafer using the 4-pass laser cutting process of this disclosure. It can be seen that, compared with the cutting methods of the prior art, the cutting time of this disclosure can be effectively reduced and the cutting efficiency can be improved. Under the premise of maintaining the original process, no new equipment is required, thus reducing equipment costs.

[0087] Specifically, based on the above method, the laser cutting process flow is as follows:

[0088] 1. Trench Beam laser CH2 (0°) & CH1 (90°), after laser treatment is complete, switch to Grooving laser CH2 (0°) & CH1 (90°) in the current process program settings;

[0089] 2. Laser mode Trench Beam & Grooving beam;

[0090] 3. Set product thickness, power, and speed;

[0091] 4. Start by selecting the Trench Beam width (4UV50), energy, and angle;

[0092] 5. Adjust and reduce the Trench Beam width (4UV50) and adjust the rotation angle;

[0093] 6. Start by selecting the Grooving beam width (4UV10 / 3UV100), energy, and angle;

[0094] 7. Create the main program, selecting the coating program, laser program, and cleaning program;

[0095] 8. Load the product coating and align it before placing it on the tray.

[0096] 9. Set up the light source, level the surface, and measure the grain size (lateral and longitudinal directions);

[0097] 10. Select feature points and adjust the image for comparison with the sample;

[0098] 11. Enter the confidence level trainer test image;

[0099] 12. Fully automatic laser cutting begins.

[0100] The method disclosed herein can break down metal segments by segment when testing interconnect structures containing a large amount of metal, reducing the risk of slag sputtering, thereby increasing the number of yield chips obtained from wafer dicing, reducing product loss, increasing the yield of wafer dicing products, and improving product quality. Simultaneously, this embodiment can also increase the stress of the chip products, improve their strength, and prevent problems such as warping and cracking. Secondly, this embodiment optimizes the wafer laser process flow, effectively shortening the wafer dicing time and improving dicing efficiency. It eliminates the need for high-magnification microscopes for wafer defect detection, thereby increasing the capacity of the wafer dicing production line.

[0101] Another embodiment of this disclosure relates to a wafer dicing apparatus, such as Figure 13 As shown, the wafer dicing apparatus includes:

[0102] A module 1001 is provided for providing a wafer to be diced, the wafer having a plurality of chips to be diced and dicing channels located between the plurality of chips, the dicing channels having a test interconnect structure;

[0103] Narrowband laser module 1002 is used to laser the cutting path twice at different angles using a narrowband laser to form two sets of narrow grooves in the length direction of the cutting path.

[0104] The broadband laser module 1003 is used to laser the cutting path twice at different angles using a broadband laser to laser the two sets of narrow grooves into wide grooves and use them as cutting grooves.

[0105] The dicing module 1004 is used to dice the wafer along the dicing groove to complete the dicing of multiple chips.

[0106] For a detailed implementation of the wafer dicing apparatus provided in this disclosure, please refer to the wafer dicing method provided in the embodiments described above, which will not be repeated here.

[0107] Compared to existing technologies, this disclosed embodiment can break down the metal segment by segment when testing interconnect layers containing a large amount of metal, reducing the risk of slag sputtering. This increases the number of good chip products obtained from wafer dicing, reduces product loss, increases the product yield of wafer dicing, and prevents problems such as warping and cracking in chip products. At the same time, it can also shorten dicing time and improve production line capacity.

[0108] Another embodiment of this disclosure relates to an electronic device, such as Figure 14 As shown, it includes:

[0109] At least one processor 1101; and,

[0110] Memory 1102 is communicatively connected to at least one processor 1101; wherein,

[0111] The memory 1102 stores instructions that can be executed by at least one processor 1101, which enables the at least one processor 1101 to perform the wafer dicing method proposed in the above embodiments.

[0112] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0113] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0114] This disclosure presents a wafer dicing method, apparatus, and electronic equipment, which have the following beneficial effects:

[0115] First, this disclosure optimizes the laser process and shortens the laser time while maintaining the original equipment. After the improvement, it only takes 36 minutes to laser a wafer.

[0116] Secondly, the method disclosed herein only requires four laser passes to achieve the laser depth required by the user, effectively improving production efficiency;

[0117] Third, by micro-switching the laser angle of the broadband laser, this disclosure can reduce the degree of melting of the metal at the edge of the cutting track, increase the IC stress after laser treatment, and improve the flatness of the bottom of the cutting groove.

[0118] Those skilled in the art will understand that the above embodiments are specific implementations of this disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this disclosure.

Claims

1. A wafer dicing method, characterized in that, The wafer dicing method includes: A wafer to be diced is provided, the wafer having a plurality of chips to be diced and dicing channels located between the plurality of chips, the dicing channels having a test interconnect structure; The cutting path is lasered twice at different angles using a narrow-band laser to form two sets of narrow grooves along the length of the cutting path. The cutting path is lasered twice at different angles using a broadband laser to laser the two sets of narrow grooves into wide grooves, which are then used as cutting grooves. The wafer is cut along the cutting groove to complete the dicing of multiple chips; The method of using broadband laser to perform two laser lithography operations at different angles on the cutting path to laser-transform the two sets of narrow grooves into wide grooves includes: The laser angles of three preset light spots are switched to form a main cutting light spot and a secondary cutting light spot, wherein the energy of the main cutting light spot is greater than the energy of the secondary cutting light spot; The main cutting spot is focused in the central region of the cutting channel, and the secondary cutting spot is focused in the edge region of the cutting channel for a third laser lithography, so as to laser the two sets of narrow grooves into wide grooves. Three preset laser spots are focused onto the cutting path for a fourth laser pass to achieve the preset laser depth.

2. The wafer dicing method according to claim 1, characterized in that, The method of using a narrow-band laser to perform two laser lithography operations at different angles on the cutting track to form two sets of narrow grooves along the length of the cutting track includes: At the first laser angle, the first set of laser spots is focused on the cutting track for the first laser to form the first set of narrow grooves along the length of the cutting track. At the second laser angle, the second set of laser spots is focused on the cutting path for a second laser irradiation to form a second set of narrow grooves along the length of the cutting path.

3. The wafer dicing method according to claim 2, characterized in that, The range of both the first laser angle and the second laser angle is 0-30°.

4. The wafer dicing method according to claim 3, characterized in that, The first set of light spots includes four first sub-light spots, and the distance between the four first sub-light spots along the width direction on the cutting track is the first narrow band laser width; The second set of light spots includes four second sub-light spots. The distance between the four second sub-light spots along the width direction on the cutting path is the second narrow band laser width, which is smaller than the first narrow band laser width.

5. The wafer dicing method according to claim 4, characterized in that, The width of the first narrowband laser and the width of the second narrowband laser are both calculated using the following formula (I): X=sin(90-θ)*(d+2r) (I) Where X is the narrowband laser width, θ is the laser angle, d is the distance between the four sub-spots, and r is the radius of the sub-spot.

6. The wafer dicing method according to claim 1, characterized in that, The laser angle range for switching the three preset light spots is 0-1°.

7. The wafer dicing method according to claim 6, characterized in that, Each set of preset light spots includes four sub-light spots; The main cutting spot includes three sets of cutting spots, and the secondary cutting spot includes one set or one set of half-cutting spots.

8. A wafer dicing apparatus, characterized in that, The wafer dicing apparatus includes: An enhancement module is used to provide a wafer to be diced, the wafer being provided with a plurality of chips to be diced and dicing channels located between the plurality of chips, the dicing channels having a test interconnect structure; A narrow-band laser module is used to laser the cutting path twice at different angles using a narrow-band laser to form two sets of narrow grooves along the length of the cutting path. A broadband laser module is used to laser the cutting path twice at different angles using a broadband laser to laser the two sets of narrow grooves into wide grooves, and use them as cutting grooves. A cutting module is used to cut the wafer along the cutting grooves to complete the slicing of multiple chips; The method of using broadband laser to perform two laser lithography operations at different angles on the cutting path to laser-transform the two sets of narrow grooves into wide grooves includes: The laser angles of three preset light spots are switched to form a main cutting light spot and a secondary cutting light spot, wherein the energy of the main cutting light spot is greater than the energy of the secondary cutting light spot; The main cutting spot is focused in the central region of the cutting channel, and the secondary cutting spot is focused in the edge region of the cutting channel for a third laser lithography, so as to laser the two sets of narrow grooves into wide grooves. Three preset laser spots are focused onto the cutting path for a fourth laser pass to achieve the preset laser depth.

9. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the wafer dicing method according to any one of claims 1 to 7.

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