A circuit for controlling quiescent power dissipation in high voltage ldo dropout state

Abstract

This invention provides a circuit for controlling the static power consumption of a high-voltage LDO under voltage drop conditions, applicable to the field of high-voltage LDO technology. It includes a feedback loop and a comparator circuit. The feedback loop includes components for adjusting the voltage magnitude to generate an output signal V. OUT And output signal V OUT A conventional high-voltage LDO circuit input to a comparator circuit and a comparison signal V used to control the current of the conventional high-voltage LDO circuit and receive the output of the comparator circuit. OCP The current limiting circuit; the comparator circuit includes a current mirror unit for providing appropriate current to various parts of the circuit and a current comparison unit for comparing the external high-voltage power supply V. IN and the output signal V of the feedback loop OUT Based on the comparison result, the voltage of the circuit components is isolated, and a comparison signal V is output. OCP2 An isolation comparator unit is provided to the current-limiting circuit. This circuit reduces the static power consumption of the high-voltage LDO under dropout conditions.

Description

Technical Field

[0001] This invention belongs to the field of high-voltage LDO technology, specifically relating to a circuit for controlling the static power consumption of a high-voltage LDO under voltage drop conditions. Background Technology

[0002] The invention patent CN113253792B is a circuit for controlling the static power consumption of low-voltage LDOs in the voltage drop state. Similarly, high-voltage LDOs also have the problem of large static power consumption in the voltage drop state.

[0003] In traditional high-voltage LDO structures ( Figure 1 When V IN <V OUT(NOM) +V DROP At that time, i.e., in the voltage drop state, V OUT <V OUT(NOM) V OUT(NOM) The normal output voltage of the LDO is V. DROP For a certain load condition V OuT The required source-drain voltage of the high-voltage P-type power transistor during normal output, and the feedback voltage V generated by the feedback resistor. FB <V REF When the output of operational amplifier EA is positive, the gate potential of the low-voltage N-type MOSFET N1 increases, and the current in the second stage of operational amplifier EA (the common-source amplifier formed by the low-voltage N-type MOSFET N1) is very large. This results in a very large quiescent current in the high-voltage LDO voltage drop state. Figure 3 Based on Figure 1 The static power consumption of the high-voltage LDO in the circuit varies with the external high-voltage power supply V. IN The voltage waveform clearly shows that the static power consumption of the high-voltage LDO under voltage drop conditions is higher than the static power consumption I during normal operation. Q(NOM) Much higher, possibly up to I Q(NOM) Hundreds of times.

[0004] To address this problem, this invention proposes a circuit for controlling the static power consumption of a high-voltage LDO under voltage drop conditions. Summary of the Invention

[0005] In view of the above-mentioned problems in the prior art, the purpose of the present invention is to provide a circuit for controlling the static power consumption of a high-voltage LDO in the voltage drop state, which can reduce the static power consumption of the high-voltage LDO in the voltage drop state.

[0006] A circuit for controlling the static power consumption of a high-voltage LDO under voltage drop conditions includes a feedback loop and a comparator circuit electrically connected to each other. The feedback loop includes:

[0007] Traditional high-voltage LDO circuits are used to regulate the voltage to generate the output signal V. OUT and output signal V OUTThe input is fed into the comparator circuit;

[0008] The current limiting circuit, electrically connected to the traditional high-voltage LDO circuit, is used to control the current of the traditional high-voltage LDO circuit and receive the comparison signal V output from the comparator circuit. OCP2 ;

[0009] The comparator circuit includes:

[0010] A current mirror unit is used to provide appropriate current to various parts of the circuit;

[0011] The isolated comparator unit, electrically connected to the current mirror unit, is used to compare the external high-voltage power supply V. IN and the output signal V of the feedback loop OUT Based on the comparison result, the voltage of the circuit components is isolated, and a comparison signal V is output. OCP2 To the current limiting circuit.

[0012] In a preferred embodiment of the present invention, the mirror current unit includes a power supply V DD Connected bias current source I B The bias current source I B The negative terminal is connected to the drain and gate of the low-voltage N-type MOSFET N3. The sources of the low-voltage N-type MOSFETs N3, N4, N5, and N6 are all grounded. The drain and gate of the low-voltage N-type MOSFET N3 are connected to the gates of the low-voltage N-type MOSFETs N4, N5, and N6, respectively.

[0013] In a preferred embodiment of the present invention, the isolation comparator unit includes a high-voltage N-type MOSFET two HN2, a high-voltage N-type MOSFET three HN3, and a high-voltage N-type MOSFET four HN4. The gates of the high-voltage N-type MOSFET two HN2, high-voltage N-type MOSFET three HN3, and high-voltage N-type MOSFET four HN4 are all connected to the power supply V. DD The source is connected to the drain of low-voltage N-type MOSFETs N4, N5, and N6, respectively.

[0014] The isolation comparison unit further includes high-voltage P-type MOSFETs HP2, HP3, HP4, Zener diode Z1, and Z2. The drain of high-voltage N-type MOSFET Z2 is connected to the positive terminal of Zener diode Z1 and the gate of high-voltage P-type MOSFET HP4. The negative terminal of Zener diode Z1 is connected to the external high-voltage power supply V. IN connect;

[0015] The drain of the high-voltage N-type MOSFET HN3 is connected to the gate and drain of the high-voltage P-type MOSFET HP2 and the drain of the high-voltage P-type MOSFET HP4. The source of the high-voltage P-type MOSFET HP2 has an output signal V. OUT ;

[0016] The drain of the high-voltage N-type MOSFET HN4 is connected to the drain of the high-voltage P-type MOSFET HP3. The gate of the high-voltage P-type MOSFET HP3 is connected to the source of the high-voltage P-type MOSFET HP4 and the positive terminal of the Zener diode Z2. The source of the high-voltage P-type MOSFET HP3 and the negative terminal of the Zener diode Z2 are both connected to the external high-voltage power supply V. IN connect;

[0017] The circuit between the source of the high-voltage N-type MOSFET quad HN4 and the drain of the low-voltage N-type MOSFET hex N6 outputs a comparison signal V. OCP2 .

[0018] In a preferred embodiment of the present invention, the conventional high-voltage LDO circuit includes an operational amplifier EA, the non-inverting input terminal of which is connected to a reference voltage V. REF The inverting input terminal is connected to the feedback signal V. FB The output terminal is connected to the gate of a low-voltage N-type MOSFET N1. The source of the low-voltage N-type MOSFET N1 is connected to a current-limiting circuit, which is connected to a comparator circuit. The drain of the low-voltage N-type MOSFET N1 is connected to the source of a high-voltage N-type MOSFET HN1. The gate of the high-voltage N-type MOSFET HN1 is connected to the power supply V. DD The drain is connected to the gate and drain of the high-voltage P-type MOSFET HP1. A resistor R3 is connected to the source of the high-voltage P-type MOSFET HP1. The other end of resistor R3 is connected to the external high-voltage power supply V. IN The circuit consists of four resistors (R4 and R2) connected to the source of a high-voltage P-type power transistor (Power). The other end of R4 is connected to the gate and drain of a high-voltage P-type MOSFET (HP1) and the gate of the high-voltage P-type power transistor (Power). The drain of the high-voltage P-type power transistor (Power) is connected in series with two resistors (R1 and R2). The other end of R2 is grounded. The circuit between R1 and the drain of the high-voltage P-type power transistor (Power) outputs an output signal V. OUT .

[0019] In a preferred embodiment of the present invention, the circuit between resistor R1 and resistor R2 outputs a feedback signal V. FB .

[0020] In a preferred embodiment of the present invention, the current limiting circuit 211 includes a low-voltage N-type MOSFET N2, the source of which is grounded and the gate of which is fed a comparison signal V. OCP2 Drain and capacitor C C The source of the low-voltage N-type MOSFET N1 is connected, and the capacitor C... C The other end is connected to a resistor R C The resistor R C The other end is connected to the gate of the low-voltage N-type MOSFET N2.

[0021] In a preferred embodiment of the present invention, the width-to-length ratios of the high-voltage P-type MOSFETs HP2 and HP3 are the same, and their number ratio is N:1. When V IN <V OUT When +ΔV, the comparator circuit outputs a comparison signal V. OCP2 The voltage decreases; where N is greater than 1, ΔV = |V TH(HP3) |-|V TH(HP2) |,V TH(HP2) V TH(HP3) These are the threshold voltages of high-voltage P-type MOSFETs HP2 and HP3, respectively.

[0022] In a preferred embodiment of the present invention, when V IN >V OUT +V z At this time, high-voltage P-type MOSFET HP4 isolates the gate voltage of high-voltage P-type MOSFET HP2 from the gate voltage of high-voltage P-type MOSFET HP3, ensuring that the gate-source voltage of high-voltage P-type MOSFET HP3 does not exceed V. z , where V z This is the reverse breakdown voltage of Zener diode Z2.

[0023] In a preferred embodiment of the present invention, the bias current source I B It is at the nA level.

[0024] The beneficial effect of this invention is that the circuit for controlling the static power consumption of the high-voltage LDO voltage drop state, when in use, when V IN -|V TH(HP3) |≥V OUT -|V TH(HP2) |, i.e., V IN ≥V OUT -|V TH(HP2) |+|V TH(HP3) | Let ΔV = |V TH(HP3) |-|V TH(HP2) |, then V IN ≥V OUT +ΔV, compare signal VOCP2 =V DD -V TH(HN4) The low-voltage N-type MOSFET N2 operates in the linear region and can be considered as a switching transistor in the on state, outputting a signal V. OUT Normal output;

[0025] V IN Gradually decrease, when V IN <V OUT When +AV, compare signal V OCP2 As the voltage gradually decreases, the low-voltage N-type MOSFET N2 operates in the subthreshold region, and the current in the branch where the low-voltage N-type MOSFET N2 is located decreases, thereby controlling the static power consumption of the LDO in the voltage drop state.

[0026] Among them, V TH(HP2) V TH(HP3) V TH(HN4) These are the threshold voltages of high-voltage P-type MOSFETs HP2, HP3, and HP4, respectively.

[0027] This method can control the static power consumption in the voltage drop region to the static power consumption I during normal operation of the high-voltage LDO. Q(NOM) The following solution addresses the issue of high static power consumption in the high voltage drop state of the LDO. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 This is the circuit diagram of a traditional high-voltage LDO;

[0030] Figure 2 This is the circuit diagram of the present invention;

[0031] Figure 3 This is a waveform diagram showing the static power consumption of a traditional high-voltage LDO as a function of input voltage.

[0032] Figure 4 This is a waveform diagram showing the static power consumption of the present invention as a function of input voltage.

[0033] The circuit diagram is labeled as follows: 210, feedback loop; 211, current limiting circuit; 220, comparator circuit. Detailed Implementation

[0034] Example 1

[0035] like Figure 2 As shown, a circuit for controlling the static power consumption of a high-voltage LDO voltage drop state includes a feedback loop 210 and a comparator circuit 220 that are electrically connected to each other.

[0036] The feedback loop 210 includes a traditional high-voltage LDO circuit and a current limiting circuit 211.

[0037] Specifically, such as Figure 1 , Figure 2 As shown, a traditional high-voltage LDO circuit is used to regulate the voltage to generate an output signal V. OUT and output signal V OUT The input is fed into comparator circuit 220. A conventional high-voltage LDO circuit includes operational amplifier EA, with the non-inverting input of operational amplifier EA connected to a reference voltage V. REF The inverting input terminal is connected to the feedback signal V. FB The output terminal is connected to the gate of a low-voltage N-type MOSFET, N1. The circuit between resistors R1 and R2 outputs a feedback signal V. FB .

[0038] The source of the low-voltage N-type MOSFET N1 is connected to the current limiting circuit 211, which is connected to the comparator circuit 220. The drain of the low-voltage N-type MOSFET N1 is connected to the source of the high-voltage N-type MOSFET HN1, and the gate of the high-voltage N-type MOSFET HN1 is connected to the power supply V. DD The drain is connected to the gate and drain of the high-voltage P-type MOSFET HP1. The source of the high-voltage P-type MOSFET HP1 is connected to a resistor R3. The other end of resistor R3 is connected to the external high-voltage power supply V. IN The circuit consists of four resistors (R4 and R2) connected to the source of a high-voltage P-type power transistor (Power). The other end of R4 is connected to the gate and drain of a high-voltage P-type MOSFET (HP1) and the gate of the high-voltage P-type power transistor (Power). The drain of Power is connected in series with two resistors (R1 and R2), the other end of which is grounded. The circuit between R1 and the drain of Power outputs an output signal V. OUT .

[0039] The reference voltage V is controlled by operational amplifier EA. REF and feedback signal V FB The comparison causes the output of operational amplifier EA to control the gate voltage of the low-voltage N-type MOSFET N1, which in turn transmits the signal to the gate of the high-voltage P-type power transistor Power via the high-voltage P-type MOSFET HP1, thereby adjusting the output signal V. OUT Make the output signal V OUT Stablize.

[0040] like Figure 2 As shown, the current limiting circuit 211 is used to control the current of a conventional high-voltage LDO circuit and to receive the comparison signal V output by the comparator circuit 220. OCP2The current limiting circuit 211 includes a low-voltage N-type MOSFET N2, the source of which is grounded and the gate of which is fed a comparison signal V. OCP2 Drain and capacitor C C The source of the low-voltage N-type MOSFET N1 is connected, and the capacitor C... C The other end is connected to a resistor R C resistance R C The other end is connected to the gate of the low-voltage N-type MOSFET N2.

[0041] The comparator circuit 220 includes a current mirror unit and an isolated comparator unit.

[0042] like Figure 2 As shown, specifically, the current mirror unit is used to provide appropriate current to various parts of the circuit. The current mirror unit includes components connected to the power supply V. DD Connected bias current source I B Bias current source I B In the nA range, bias current source I B The negative terminal is connected to the drain and gate of the low-voltage N-type MOSFET N3. The sources of the low-voltage N-type MOSFETs N3, N4, N5, and N6 are all grounded. The drain and gate of the low-voltage N-type MOSFET N3 are connected to the gates of the low-voltage N-type MOSFETs N4, N5, and N6, respectively.

[0043] Furthermore, since the width-to-length ratios and number of low-voltage N-type MOSFETs N5 and N6 are the same, their mirror currents are also the same. Therefore, the current in the branches containing both low-voltage N-type MOSFETs N5 and N6 is equal to I. B .

[0044] like Figure 2 As shown, specifically, the isolation comparator unit is used to compare the external high-voltage power supply V. IN and the output signal V of feedback loop 210 OUT Based on the comparison result, the voltage of the circuit components is isolated, and a comparison signal V is output. OCP2 To the current limiting circuit 211. The name of the isolation comparator unit is given because the unit has the functions of isolation and comparison, and has no special meaning.

[0045] The isolation comparator unit includes three high-voltage N-type MOSFETs: HN2 (two), HN3 (three), and HN4 (four). The gates of all three MOSFETs are connected to the power supply V. DDThe source of the transistor is connected to the drain of low-voltage N-type MOSFETs N4, N5, and N6, respectively. The isolation comparator unit also includes high-voltage P-type MOSFETs HP2, HP3, HP4, Zener diode Z1, and Z2. The drain of high-voltage N-type MOSFET Z2 is connected to the positive terminal of Zener diode Z1 and the gate of high-voltage P-type MOSFET HP4. The negative terminal of Zener diode Z1 is connected to the external high-voltage power supply V. IN connect.

[0046] The drain of high-voltage N-type MOSFET HN3 is connected to the gate and drain of high-voltage P-type MOSFET HP2 and the drain of high-voltage P-type MOSFET HP4. The source input of high-voltage P-type MOSFET HP2 has an output signal V. OUT The drain of high-voltage N-type MOSFET four HN4 is connected to the drain of high-voltage P-type MOSFET three HP3. The gate of high-voltage P-type MOSFET three HP3 is connected to the source of high-voltage P-type MOSFET four HP4 and the positive terminal of Zener diode two Z2. The source of high-voltage P-type MOSFET three HP3 and the negative terminal of Zener diode two Z2 are both connected to the external high-voltage power supply V. IN Connection; the circuit between the source of the high-voltage N-type MOSFET quad HN4 and the drain of the low-voltage N-type MOSFET hex N6 outputs a comparison signal V. OCP2 .

[0047] Furthermore, when V IN >V OUT +V z At this time, the high-voltage P-type MOSFET HP4 can isolate the gate voltage of the high-voltage P-type MOSFET HP2 from the gate voltage of the high-voltage P-type MOSFET HP3, ensuring that the gate-source voltage of the high-voltage P-type MOSFET HP3 does not exceed V. z , where V z This is the reverse breakdown voltage of Zener diode Z2.

[0048] In use, the width-to-length ratio of high-voltage P-type MOSFETs HP2 and HP3 is set to be the same, and the ratio of their numbers is N:1. V is defined as follows: TH(HP2) V TH(HP3) V TH(HN4) These are the threshold voltages of high-voltage P-type MOSFETs HP2, HP3, and HP4, respectively.

[0049] When V IN -|V TH(HP3) |≥V OUT -|V TH(HP2) |, i.e., V IN ≥V OUT -|V TH(HP2) |+|VTH(HP3) |, so that ΔV=|V TH(HP3) |-|V TH(HP2) |, then VI N ≥V OUT +ΔV, the comparison signal V output by comparator circuit 220. OCP2 At its highest point, V OCP2 =V DD -V TH(HN4) The low-voltage N-type MOSFET N2 operates in the linear region and can be considered as a switch in the on state. The output signal V from the feedback loop 210 is... OUT After voltage division by resistors R1 and R2, a feedback signal V is generated. FB and the feedback signal V FB The signal is fed into the inverting input of operational amplifier EA, making the feedback signal V... FB The reference voltage V input to the non-inverting input terminal REF In comparison, the output of operational amplifier EA controls the gate voltage of the low-voltage N-type MOSFET N1, which then transmits the signal to the gate of the high-voltage P-type power transistor Power via the high-voltage P-type MOSFET HP1, thereby adjusting the output signal V. OUT This ensures that the feedback loop 210 is unaffected by the low-voltage N-type MOSFET N2, and the output signal V OUT Stable output, at this point,

[0050]

[0051] When V IN <V OUT When +ΔV, the comparator circuit 220 outputs a comparison signal V. OCP2 As the voltage decreases, the low-voltage N-type MOSFET N2 operates in the subthreshold region. The current in the branch containing the low-voltage N-type MOSFET N2 is limited and reduced, causing the gate voltage of the high-voltage P-type power transistor Power to increase, and the output signal V... OUT Decrease, compare signal V OCP2 Increase, forming negative feedback, and achieving balance. Therefore, when V IN <V OUT When +ΔV, compare signal V OCP2 The value is not 0; it simply means that the low-voltage N-type MOSFET N2 has entered the subthreshold region, and the current in the branch where the low-voltage N-type MOSFET N2 is located has decreased.

[0052] like Figure 4 As shown, this circuit controls the static power consumption in the voltage drop region to the static power consumption I when the high voltage LD0 is operating normally. Q(NOM) The following solution addresses the issue of high static power consumption in the high voltage drop state of the LDO.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit for controlling the static power consumption of a high-voltage LDO under voltage drop conditions, characterized in that, It includes a feedback loop (210) and a comparator circuit (220) that are electrically connected to each other, wherein the feedback loop (210) includes: Traditional high-voltage LDO circuits are used to regulate the voltage to generate an output signal. and output signal The input is fed into the comparator circuit (220); The current limiting circuit (211) is electrically connected to the conventional high-voltage LDO circuit and is used to control the current of the conventional high-voltage LDO circuit and receive the comparison signal output by the comparator circuit (220). ; The comparator circuit (220) includes: A current mirror unit is used to provide appropriate current to various parts of the circuit; The isolated comparator unit, electrically connected to the current mirror unit, is used to compare external high-voltage power supplies. and the output signal of the feedback loop (210) The circuit components' voltages are isolated based on the comparison result, and a comparison signal is output. To the current limiting circuit (211); The conventional high-voltage LDO circuit includes an operational amplifier EA, the non-inverting input of which is connected to a reference voltage. The inverting input terminal is connected to the feedback signal. The output terminal is connected to the gate of the low-voltage N-type MOSFET N1. The source of the low-voltage N-type MOSFET N1 is connected to the current limiting circuit (211), which is connected to the comparator circuit (220). The drain of the low-voltage N-type MOSFET N1 is connected to the source of the high-voltage N-type MOSFET HN1. The gate of the high-voltage N-type MOSFET HN1 is connected to the power supply. The drain is connected to the gate and drain of the high-voltage P-type MOSFET HP1. The source of the high-voltage P-type MOSFET HP1 is connected to a resistor R3. The other end of the resistor R3 is connected to an external high-voltage power supply. A resistor R4 is connected to the source of a high-voltage P-type power transistor Power. The other end of resistor R4 is connected to the gate and drain of a high-voltage P-type MOSFET HP1, and the gate of the high-voltage P-type power transistor Power. The drain of the high-voltage P-type power transistor Power is connected to a series resistor R1 and a resistor R2. The other end of resistor R2 is grounded. The circuit between resistor R1 and the drain of the high-voltage P-type power transistor Power outputs an output signal. ; The current limiting circuit (211) includes a low-voltage N-type MOSFET N2, the source of which is grounded and a comparison signal is input to its gate. Drain and capacitor The source of the low-voltage N-type MOSFET N1 is connected, and the capacitor... The other end is connected to a resistor The resistor The other end is connected to the gate of the low-voltage N-type MOSFET N2.

2. The circuit for controlling the static power consumption of the high-voltage LDO voltage drop state according to claim 1, characterized in that, The mirror current unit includes a power supply. Connected bias current source The bias current source The negative terminal is connected to the drain and gate of the low-voltage N-type MOSFET N3. The sources of the low-voltage N-type MOSFETs N3, N4, N5, and N6 are all grounded. The drain and gate of the low-voltage N-type MOSFET N3 are connected to the gates of the low-voltage N-type MOSFETs N4, N5, and N6, respectively.

3. The circuit for controlling the static power consumption of the high-voltage LDO voltage drop state according to claim 1, characterized in that, The isolation comparison unit includes high-voltage N-type MOSFETs HN2, HN3, and HN4. The gates of HN2, HN3, and HN4 are all connected to the power supply. The high-voltage N-type MOSFET HN2 is connected to the drain of the low-voltage N-type MOSFET N4, the high-voltage N-type MOSFET HN3 is connected to the drain of the low-voltage N-type MOSFET N5, and the high-voltage N-type MOSFET HN4 is connected to the drain of the low-voltage N-type MOSFET N6. The isolation comparison unit further includes high-voltage P-type MOSFETs HP2, HP3, and HP4, Zener diode Z1, and Zener diode Z2. The drain of high-voltage N-type MOSFET Z2 is connected to the positive terminal of Zener diode Z1 and the gate of high-voltage P-type MOSFET HP4. The negative terminal of Zener diode Z1 is connected to an external high-voltage power supply. connect; The drain of the high-voltage N-type MOSFET HN3 is connected to the gate and drain of the high-voltage P-type MOSFET HP2 and the drain of the high-voltage P-type MOSFET HP4. The source of the high-voltage P-type MOSFET HP2 receives an output signal. ; The drain of the high-voltage N-type MOSFET HN4 is connected to the drain of the high-voltage P-type MOSFET HP3. The gate of the high-voltage P-type MOSFET HP3 is connected to the source of the high-voltage P-type MOSFET HP4 and the positive terminal of the Zener diode Z2. The source of the high-voltage P-type MOSFET HP3 and the negative terminal of the Zener diode Z2 are both connected to an external high-voltage power supply. connect; The circuit between the source of the high-voltage N-type MOSFET quad HN4 and the drain of the low-voltage N-type MOSFET hex N6 outputs a comparison signal. .

4. The circuit for controlling the static power consumption of the high-voltage LDO voltage drop state according to claim 1, characterized in that, The circuit between resistor R1 and resistor R2 outputs a feedback signal. .

5. The circuit for controlling the static power consumption of the high-voltage LDO voltage drop state according to claim 3, characterized in that, The high-voltage P-type MOSFETs HP2 and HP3 have the same width-to-length ratio, and their number ratio is N:

1. At that time, the comparator circuit (220) outputs a comparison signal. The voltage decreases; where N is greater than 1. , , These are the threshold voltages of high-voltage P-type MOSFETs HP2 and HP3, respectively.

6. The circuit for controlling the static power consumption of the high-voltage LDO voltage drop state according to claim 1, characterized in that, when At this time, high-voltage P-type MOSFET HP4 isolates the gate voltage of high-voltage P-type MOSFET HP2 from the gate voltage of high-voltage P-type MOSFET HP3, ensuring that the gate-source voltage of high-voltage P-type MOSFET HP3 does not exceed [the gate voltage of HP3]. ,in, This is the reverse breakdown voltage of Zener diode Z2.

7. The circuit for controlling the static power consumption of the high-voltage LDO voltage drop state according to claim 2, characterized in that, The bias current source It is at the nA level.

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