Floating power rail generation circuit and generation method

Abstract

The disclosure provides a floating power rail generating circuit and a generating method. The generating circuit comprises: a bias circuit configured to generate a bias current according to an external reference current, and determine a reference voltage in combination with a power supply to provide to a first input terminal of a high-voltage amplifier; the high-voltage amplifier is configured to generate a voltage amplification signal according to the bias circuit; a high-speed regulating circuit is configured to output an output terminal voltage of the floating power rail generating circuit according to the voltage amplification signal; a voltage dividing feedback circuit is configured to divide the collected output terminal voltage to generate a feedback voltage, and feed the feedback voltage back to a second input terminal of the high-voltage amplifier; the high-speed regulating circuit is further configured to self-regulate the output terminal voltage, so that the voltage of the first input terminal of the high-voltage amplifier is the same as the voltage of the second input terminal of the high-voltage amplifier. Through the processing scheme of the disclosure, the hardware resources are less, the accurate voltage is generated based on the high-voltage power supply, the regulating ability is strong, and the voltage offset is not generated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a floating power rail generation circuit and generation method. Background Technology

[0002] Low dropout regulators (LDOs) are essential modules in almost all analog integrated circuits, typically used to provide a stable supply voltage to other circuit modules within the chip. In high-voltage chip applications, a low LDO voltage needs to be generated from the high-voltage supply voltage to power other circuit modules. For example, if the chip's supply voltage is 40V, but the internal circuit modules need to operate in the 5V range, a high-voltage LDO is required to generate the 5V voltage.

[0003] Furthermore, in some more specialized applications, a floating low-voltage power rail is required based on the high-voltage domain. For example, in a half-bridge driver chip, the high-voltage power supply is 40V. If the high-side transistor is a PMOS, the driving voltage for the PMOS needs to be 35V to 40V, thus requiring a 35V to 40V power rail. Currently, in existing publicly available solutions, the floating rail circuit voltage is determined by the gate-source voltage of the MOS transistor, which results in a large voltage deviation, and the regulation capability of this floating rail circuit is relatively weak. Summary of the Invention

[0004] In view of this, the present disclosure provides a floating power rail generation circuit and generation method, which at least partially solves the problems existing in the prior art.

[0005] In a first aspect, embodiments of this disclosure provide a floating power rail generation circuit, including a bias circuit, a high-voltage amplifier, a high-speed regulation circuit, and a voltage divider feedback circuit; wherein... The bias circuit is connected to the first input terminal of the high-voltage amplifier and the high-speed adjustment circuit. It is used to generate a bias current based on the external reference current and determine the reference voltage in conjunction with the power supply so as to provide it to the first input terminal of the high-voltage amplifier. The high-voltage amplifier is used to generate a voltage amplification signal according to the bias circuit; The high-speed adjustment circuit is connected to the bias circuit and the high-voltage amplifier, and is used to output the output voltage of the floating power rail generation circuit according to the voltage amplification signal. The voltage divider feedback circuit is connected to both the high-speed adjustment circuit and the second input terminal of the high-voltage amplifier. It is used to divide the collected output voltage to generate a feedback voltage and feed the feedback voltage back to the second input terminal of the high-voltage amplifier. The high-speed adjustment circuit is also used to self-adjust the output voltage so that the voltage at the first input terminal of the high-voltage amplifier is the same as the voltage at the second input terminal of the high-voltage amplifier.

[0006] According to a specific implementation of an embodiment of this disclosure, the bias circuit includes: A common-source, common-gate current mirror, whose first terminal receives the external reference current and whose second terminal is grounded; A reference voltage generating resistor, the first end of which is connected to the power supply; A high-voltage bias transistor, the first end of which is connected to the second end of the reference voltage generating resistor, and its control end is connected to both its second end and the third end of the common-source cascode current mirror; The first copy current tube has its first end connected to the power supply, and its second end connected to its control terminal and the fourth end of the common source cascode current mirror.

[0007] According to a specific implementation of an embodiment of this disclosure, the common-source cascode current mirror includes: The first high-voltage isolation tube, both its first end and its control end are used to receive the external reference current; The first current mirror transistor has its first end connected to its control terminal and the second end of the first high-voltage isolation transistor, and its second end is grounded. The second high-voltage isolation tube has its first end connected to the second end of the high-voltage bias tube, and its control end connected to the control end of the first high-voltage isolation tube. The second current mirror has its first end connected to the second end of the second high-voltage isolation tube, its control end connected to the control end of the first current mirror, and its second end grounded. The third high-voltage isolation tube has its first end connected to the second end of the first copy current tube, and its control end connected to the control end of the first high-voltage isolation tube. The third current mirror transistor has its first end connected to the second end of the third high-voltage isolation transistor, its control end connected to the control end of the first current mirror transistor, and its second end grounded.

[0008] According to a specific implementation of this disclosure, the high-voltage amplifier includes: The second copy current transistor has its first end connected to the power supply and its control end connected to the control end of the first copy current transistor. The input transistor unit has its first terminal connected to the second terminal of the second copy current transistor, its second terminal connected to the second terminal of the reference voltage generating resistor, and its third terminal connected to the voltage divider feedback circuit. The high-voltage isolation unit is connected to the input pair transistors, the common-source cascode current mirror, the control terminal of the high-voltage bias transistor, and the high-speed regulation circuit. It is used to isolate the power supply and transmit the voltage amplification signal to the high-speed regulation circuit. The load-pair unit has its first and second ends connected to the high-voltage isolation unit, and its third end grounded.

[0009] According to a specific implementation of an embodiment of this disclosure, the input pair unit includes: The first input transistor has its first terminal connected to the second terminal of the second copy current transistor, and its control terminal connected to the second terminal of the reference voltage generating resistor. The second input transistor has its first terminal connected to the second terminal of the second copy current transistor, and its control terminal connected to the voltage divider feedback circuit.

[0010] According to a specific implementation of an embodiment of this disclosure, the high-voltage isolation unit includes: The fourth high-voltage isolation tube has its first end connected to the second end of the first input tube, and its control end connected to the control end of the high-voltage bias tube. The fifth high-voltage isolation tube has its first end connected to the second end of the second input tube, and its control end connected to the control end of the high-voltage bias tube. The sixth high-voltage isolation tube has its first end connected to the second end of the fourth high-voltage isolation tube, and its control end connected to the control end of the first high-voltage isolation tube. The seventh high-voltage isolation tube has its first end connected to the second end of the fifth high-voltage isolation tube, and its control end connected to the control end of the first high-voltage isolation tube.

[0011] According to a specific implementation of an embodiment of this disclosure, the load pair unit includes: The first load tube has its first end connected to its control end and the second end of the sixth high-voltage isolation tube, and its second end is grounded. The second load tube has its first end connected to the second end of the seventh high-voltage isolation tube, its control end connected to the control end of the first load tube, and its second end grounded.

[0012] According to a specific implementation of this disclosure, the high-speed adjustment circuit includes: The third copy current transistor has its first end connected to the power supply and its control end connected to the control end of the first copy current transistor. A fast-response transistor, the first end of which is connected to the second end of the third copy current transistor, and its control end is connected to the high-voltage bias transistor; An adjustable resistor is provided, with its first end connected to the second end of the fast response transistor, and the second end grounded. An output regulating tube, the first end of which is connected to the first end of the fast response tube, and its control end is connected to the output end of the high voltage amplifier; The power transistor has its first terminal connected to the second terminal of the output regulating transistor, its control terminal connected to the first terminal of the regulating resistor, and its second terminal grounded. The zero-point resistor has its first end connected to the second end of the output regulating tube, and its second end outputs the output voltage of the floating power rail generation circuit.

[0013] According to a specific implementation of an embodiment of this disclosure, the voltage divider feedback circuit includes: The first voltage divider resistor has its first end connected to the power supply. The second voltage divider resistor has its first end connected to the second end of the first voltage divider resistor and the second input terminal of the high-voltage amplifier, and its second end connected to the output terminal of the high-speed adjustment circuit.

[0014] Secondly, embodiments of this disclosure provide a method for generating floating power rails, including: The control bias circuit generates a bias current based on the received external reference current and determines the reference voltage in conjunction with the power supply to provide it to the first input terminal of the high voltage amplifier. The high-voltage amplifier is controlled to generate a voltage amplification signal according to the bias circuit; The high-speed adjustment circuit obtains the output voltage based on the voltage amplification signal. The control voltage divider feedback circuit divides the acquired output voltage to generate a feedback voltage, and feeds the feedback voltage back to the second input terminal of the high voltage amplifier; The high-speed adjustment circuit is controlled to self-adjust the output voltage so that the voltage at the first input terminal of the high-voltage amplifier is the same as the voltage at the second input terminal of the high-voltage amplifier.

[0015] In the floating power rail generation circuit and method of this disclosure, the generation circuit includes a bias circuit, a high-voltage amplifier, a high-speed adjustment circuit, and a voltage divider feedback circuit. The bias circuit is connected to both the first input terminal of the high-voltage amplifier and the high-speed adjustment circuit. It generates a bias current based on an external reference current and determines a reference voltage based on the power supply, which is then supplied to the first input terminal of the high-voltage amplifier. The high-voltage amplifier generates a voltage amplification signal based on the bias circuit. The high-speed adjustment circuit is connected to both the bias circuit and the high-voltage amplifier. It outputs the output voltage of the floating power rail generation circuit based on the voltage amplification signal. The voltage divider feedback circuit is connected to both the high-speed adjustment circuit and the second input terminal of the high-voltage amplifier. It performs voltage divider processing on the acquired output voltage to generate a feedback voltage and feeds the feedback voltage back to the second input terminal of the high-voltage amplifier. The high-speed adjustment circuit also self-adjusts the output voltage to ensure that the voltage at the first input terminal of the high-voltage amplifier is the same as the voltage at the second input terminal. This disclosure allows for the generation of a precise voltage from a high-voltage power supply with minimal hardware resources, exhibiting strong regulation capabilities and preventing voltage deviation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the circuit principle of a floating power rail generation circuit provided in an embodiment of this disclosure; Figure 2 A schematic diagram of the circuit structure of a floating power rail generation circuit provided in an embodiment of this disclosure; Figure 3 This is a flowchart illustrating a method for generating a floating power rail according to an embodiment of the present disclosure.

[0018] Explanation of reference numerals in the attached diagram: 10, bias circuit; 20, high-voltage amplifier; 30, high-speed adjustment circuit; 40, voltage divider feedback circuit; 11. Common source cascode current mirror; 21. Input transistor unit; 22. High voltage isolation unit; 23. Load transistor unit. Detailed Implementation

[0019] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0020] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0022] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0024] In one embodiment of this application, such as Figure 1 As shown, a floating power rail generation circuit for a high-voltage power supply is provided. The floating power rail generation circuit includes: a bias circuit 10, a high-voltage amplifier 20, a high-speed adjustment circuit 30, and a voltage divider feedback circuit 40; wherein, the bias circuit 10 is connected to the first input terminal 1 of the high-voltage amplifier 20 and the high-speed adjustment circuit 30, and is used to generate a power rail based on an external reference current I. REFA bias current is generated and a reference voltage is determined in conjunction with the power supply VDD to provide to the first input terminal 1 of the high-voltage amplifier 20. The high-voltage amplifier 20 is used to generate a voltage amplification signal according to the bias circuit. The high-speed adjustment circuit 30 is connected to both the bias circuit 10 and the high-voltage amplifier 20, and is used to output the output terminal voltage of the floating power rail generation circuit according to the voltage amplification signal. The voltage divider feedback circuit 40 is connected to both the high-speed adjustment circuit 30 and the second input terminal 2 of the high-voltage amplifier 20, and is used to divide the acquired output terminal voltage to generate a feedback voltage, and feed the feedback voltage back to the second input terminal 2 of the high-voltage amplifier 20. The high-speed adjustment circuit 30 is also used to self-adjust the output terminal voltage so that the voltage at the first input terminal 1 of the high-voltage amplifier 20 is the same as the voltage at the second input terminal 2 of the high-voltage amplifier 20.

[0025] The floating power rail generation circuit scheme provided in the above embodiments can match the resistance value in the voltage divider feedback circuit 40 with less hardware resources. The high-speed amplifier 20 determines the accurate output voltage VOUT based on the high-voltage power supply VDD through feedback. The high-speed adjustment circuit 30 provides faster load adjustment capability, reduces the impedance of the output node VOUT, and does not produce voltage deviation.

[0026] As an example, the power supply VDD is a high-voltage power supply.

[0027] In one embodiment, such as Figure 2 As shown, the bias circuit 10 includes: a cascode current mirror 11, a reference voltage generating resistor R1, a high-voltage bias transistor PM1, and a first copy current transistor PM2; specifically, the first terminal of the cascode current mirror 11 receives an external reference current I. REF The second terminal of the common-source cascode current mirror 11 is grounded to GND; the first terminal of the reference voltage generating resistor R1 is connected to the power supply VDD; the first terminal of the high-voltage bias transistor PM1 is connected to the second terminal of the reference voltage generating resistor R1, and the control terminal of the high-voltage bias transistor PM1 is connected to the second terminal of the high-voltage bias transistor PM1 and the third terminal of the common-source cascode current mirror 11; the first terminal of the first copy current transistor PM2 is connected to the power supply VDD, and the second terminal of the first copy current transistor PM2 is connected to the control terminal of the first copy current transistor PM2 and the fourth terminal of the common-source cascode current mirror 11.

[0028] In one embodiment, please refer to... Figure 2The common-source cascode current mirror 11 includes: a first high-voltage isolation transistor NM4, a first current mirror transistor NM1, a second high-voltage isolation transistor NM5, a second current mirror transistor NM2, a third high-voltage isolation transistor NM6, and a third current mirror transistor NM3; specifically, the first terminal and the control terminal of the first high-voltage isolation transistor NM4 are both used to receive the external reference current I. REF The first current mirror transistor NM1 has its first end connected to its control terminal and the second end of the first high-voltage isolation transistor NM4, and its second end is grounded. The second high-voltage isolation transistor NM5 has its first end connected to the second end of the high-voltage bias transistor PM1, and its control terminal connected to the control terminal of the first high-voltage isolation transistor NM4. The second current mirror transistor NM2 has its first end connected to the second end of the second high-voltage isolation transistor NM5, and its control terminal connected to the control terminal of the first current mirror transistor NM1, and its second end is grounded. The third high-voltage isolation transistor NM6 has its first end connected to the second end of the first copy current transistor PM2, and its control terminal connected to the control terminal of the first high-voltage isolation transistor NM4. The third current mirror transistor NM3 has its first end connected to the second end of the third high-voltage isolation transistor NM6, and its control terminal connected to the control terminal of the first current mirror transistor NM1, and its second end is grounded (GND).

[0029] Specifically, the current flowing through NM4 and NM1 is the external reference current I. REF NM2, NM5, NM3, and NM6 all copy the external reference current I proportionally. REF And flows through the reference voltage generating resistors R1 and PM1, generating I across the reference voltage generating resistor R1. REF The reference voltage of ×R1 is provided to the first input terminal of the high-voltage amplifier; VDD-I is generated at the gate of PM1. REF ×R1-Vgs_PM1, where Vgs_PM1 is the voltage drop from the source to the gate of PM1.

[0030] It should be noted that the ratio of the proportional copies of NM2, NM5, NM3 and NM6 can be determined by the engineer by adjusting the ratio of the bias current provided by the bias circuit, and this application does not impose any restrictions on this.

[0031] In one embodiment, please refer to... Figure 2The high-voltage amplifier 20 includes: a second copy current transistor PM3, an input transistor pair unit 21, a high-voltage isolation unit 22, and a load transistor pair unit 23. Specifically, the second copy current transistor PM3 has its first terminal connected to the power supply VDD and its control terminal connected to the control terminal of the first copy current transistor PM2. The input transistor pair unit 21 has its first terminal connected to the second terminal of the second copy current transistor PM3, its second terminal connected to the second terminal of the reference voltage generating resistor R1, and its third terminal connected to the voltage divider feedback circuit. The high-voltage isolation unit 22 is connected to the input transistor pair, the common-source common-gate current mirror 11, the control terminal of the high-voltage bias transistor PM1, and the high-speed adjustment circuit 30, and is used to isolate the power supply VDD and transmit the voltage amplification signal to the high-speed adjustment circuit. The load transistor pair unit 23 has its first and second terminals connected to the high-voltage isolation unit 22, and its third terminal grounded.

[0032] In one embodiment, please refer to... Figure 2 The input transistor unit 21 includes: a first input transistor PM4 and a second input transistor PM5; specifically, the first input transistor PM4 has its first end connected to the second end of the second copy current transistor PM3, and its control end connected to the second end of the reference voltage generating resistor R1; the second input transistor PM5 has its first end connected to the second end of the second copy current transistor PM3, and its control end connected to the voltage divider feedback circuit 40.

[0033] Specifically, the gate voltage of the first input transistor PM4 is the reference voltage I. REF ×R1 can remain fixed; the gate voltage of the second input transistor PM5 is the feedback voltage fed back by the voltage divider feedback circuit 40. Through feedback adjustment, the gate voltage of the first input transistor PM4 and the gate voltage of the second input transistor PM5 are finally the same, so as to stably generate the output voltage VOUT of the floating power rail.

[0034] In one embodiment, please refer to... Figure 2The high-voltage isolation unit 22 includes: a fourth high-voltage isolation tube PM6, a fifth high-voltage isolation tube PM7, a sixth high-voltage isolation tube NM9, and a seventh high-voltage isolation tube NM10; specifically, the first end of the fourth high-voltage isolation tube PM6 is connected to the second end of the first input tube PM4, and its control end is connected to the control end of the high-voltage bias tube PM1; the first end of the fifth high-voltage isolation tube PM7 is connected to the second end of the second input tube PM5, and its control end is connected to the control end of the high-voltage bias tube PM1; the first end of the sixth high-voltage isolation tube NM9 is connected to the second end of the fourth high-voltage isolation tube PM6, and its control end is connected to the control end of the first high-voltage isolation tube NM4; the first end of the seventh high-voltage isolation tube NM10 is connected to the second end of the fifth high-voltage isolation tube PM7, and its control end is connected to the control end of the first high-voltage isolation tube NM4.

[0035] In one embodiment, please refer to... Figure 2 The load tube unit 23 includes: a first load tube NM7 and a second load tube NM8; specifically, the first load tube NM7 has its first end connected to its control end and the second end of the sixth high-voltage isolation tube NM9, and its second end is grounded; the second load tube NM8 has its first end connected to the second end of the seventh high-voltage isolation tube NM10, its control end connected to the control end of the first load tube NM7, and its second end is grounded.

[0036] When the gate voltage of PM5 increases, VSG_PM5 decreases, the current flowing through PM5 decreases, the current of PM4 increases, the current of NM7 increases, the current of NM8 increases, and the gate voltage of NM12 decreases, thus completing the feedback regulation.

[0037] Since PM5 and PM7, NM10 and NM8 all form a common source and common gate structure, the output node of the high voltage amplifier has a large impedance, while the high-speed adjustment circuit can reduce the impedance brought by the output node of the high voltage amplifier.

[0038] In one embodiment, please refer to... Figure 2The high-speed regulation circuit 30 includes: a third copy current transistor PM9, a fast response transistor PM8, a regulating resistor R5, an output regulating transistor NM12, a power transistor NM11, and a zero-point resistor R4; specifically, the first terminal of the third copy current transistor PM9 is connected to the power supply VDD, and its control terminal is connected to the control terminal of the first copy current transistor PM2; the first terminal of the fast response transistor PM8 is connected to the second terminal of the third copy current transistor PM9, and its control terminal is connected to the high-voltage bias transistor PM1; the first terminal of the regulating resistor R5 is connected to the second terminal of the first copy current transistor PM2 .... The second terminal of the fast response transistor PM8 is connected to ground; the first terminal of the output regulating transistor NM12 is connected to the first terminal of the fast response transistor PM8, and its control terminal is connected to the output terminal of the high voltage amplifier 20; the first terminal of the power transistor NM11 is connected to the second terminal of the output regulating transistor NM12, and its control terminal is connected to the first terminal of the regulating resistor R5, with its second terminal grounded to GND; the zero-point resistor R4 is connected to the second terminal of the output regulating transistor NM12, and its second terminal outputs the output voltage VOUT of the floating power rail generation circuit.

[0039] It should be noted that PM6 is a proportional copy of the external reference current I flowing through NM4. REF PM2 is a proportional copy of the current flowing through PM6, and PM3 and PM9 are proportional copies of the current flowing through PM2. In other words, the current flowing through PM3 and PM9 is equal to the current flowing through the external reference current I. REF The gate voltage of the fast response transistor PM8 is an integer multiple of the bias voltage.

[0040] By setting the current of PM3, the current of PM6, PM7, and PM1 can be ensured to be proportional to their size. Since the gate-source voltages of PM6, PM7, and PM1 are approximately the same, the sum of the source-drain voltages of PM3 and PM4, and the sum of the source-drain voltages of PM3 and PM5, are approximately equal to I. REF ×R1 can be reasonably set to ensure that PM3, PM4, and PM5 all operate in the saturation region. The drain-source voltage of NM7 and NM8 is approximately equal to the drain-source voltage of NM1, which is its gate-source voltage, thus ensuring that NM7 and NM8 operate in the saturation region.

[0041] The zero-point resistor R4 and the output load capacitor (not shown in the figure) form a zero point to compensate for the poles of the loop in the high-speed regulation circuit 30, ensuring that the high-speed regulation circuit 30 can work stably.

[0042] As an example, in this scheme, the proportional current copy ratio can be assumed to be 1. All load current flows into NM11 through R4, and the gate of NM11 is grounded through R5. Therefore, the current through R5 is VGS_NM11 / R5. This current also flows through PM8, whose gate is connected to PM1. Therefore, the source-drain voltage of PM9 is approximately equal to I.REF ×R1.

[0043] Based on the signal path, the adjustment principle of the high-speed adjustment circuit 30 is as follows: the output voltage VOUT is connected to the source of NM12 through R4, and then to the source of PM8, thereby adjusting the voltage on R5, that is, adjusting the gate-source voltage of NM11, thus quickly adjusting the change of the output voltage VOUT.

[0044] The following example illustrates that if the current of R5 increases, the voltage of R5 increases, which means the gate voltage of NM11 increases, and the current of NM11 increases, thus pulling down the output voltage VOUT and completing the adjustment process of the high-speed adjustment circuit 30.

[0045] In one embodiment, please refer to... Figure 2 The voltage divider feedback circuit 40 includes: a first voltage divider resistor R2 and a second voltage divider resistor R3; specifically, the first voltage divider resistor has its first end connected to the power supply; the second voltage divider resistor has its first end connected to the second end of the first voltage divider resistor and the second input terminal of the high-voltage amplifier, and its second end connected to the output terminal of the high-speed adjustment circuit.

[0046] Specifically, R2 and R3 sample the output voltage VOUT and feed it back to the second input terminal of the high-voltage amplifier. Since the voltage at the first input terminal of the high-voltage amplifier is VDD - IREF × R1, the output voltage VOUT can be determined as VDD - (R2 + R3) / R2 × IREF × R1. In the circuit implementation, the resistors can be well matched, so the resulting floating power rail voltage VDD - VOUT = (R2 + R3) / R2 × IREF × R1 can be accurately determined.

[0047] Furthermore, it should be noted that the transistor types of the various current mirror transistors, high-voltage isolation transistors, current bias transistors, copy current transistors, input transistors, load transistors, output regulation transistors, and fast response transistors are not limited to NMOS and PMOS transistors. Other transistors capable of performing the functions of their respective device transistors are all within the scope of protection of this application. Moreover, the various current mirror transistors, high-voltage isolation transistors, current bias transistors, copy current transistors, input transistors, load transistors, output regulation transistors, and fast response transistors can be either NMOS or PMOS transistors. Figure 2 The illustration shows only one embodiment of the NMOS and PMOS transistors, but is not limited thereto.

[0048] It should be noted that, Figure 2 The MOSFETs highlighted in the dashed box are all high-voltage transistors, such as NM4, NM5, NM6, PM1, PM6, PM7, NM9, NM10, PM8, and NM11. They are used to withstand the high voltage on the power supply VDD and protect the safety of other low-voltage MOSFETs.

[0049] In one embodiment of this application, such as Figure 3 As shown, a method for generating a floating power rail is also provided, applied to the above-mentioned floating power rail generation circuit, comprising the following steps: Step S10: The bias circuit generates a bias current based on the received external reference current and determines the reference voltage in conjunction with the power supply to provide it to the first input terminal of the high voltage amplifier. Step S20: Control the high-voltage amplifier to generate a voltage amplification signal according to the bias circuit; Step S30: Control the high-speed adjustment circuit to obtain the output voltage according to the voltage amplification signal; Step S40: Control the voltage divider feedback circuit to divide the acquired output voltage to generate a feedback voltage, and feed the feedback voltage back to the second input terminal of the high voltage amplifier; Step S50: Control the high-speed adjustment circuit to self-adjust the output voltage so that the voltage at the first input terminal of the high-voltage amplifier is the same as the voltage at the second input terminal of the high-voltage amplifier.

[0050] The floating power rail generation method provided in the above embodiments can generate a precise voltage based on a high-voltage power supply with fewer hardware resources in the floating power rail generation circuit. It has strong regulation capability and will not produce voltage deviation. This generation method can accurately determine the output voltage of the floating power rail generation circuit.

[0051] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A floating power rail generation circuit, characterized in that, include: Bias circuit, high-voltage amplifier, high-speed regulation circuit, and voltage divider feedback circuit; among which, The bias circuit is connected to the first input terminal of the high-voltage amplifier and the high-speed adjustment circuit. It is used to generate a bias current based on the external reference current and determine the reference voltage in conjunction with the power supply so as to provide it to the first input terminal of the high-voltage amplifier. The high-voltage amplifier is used to generate a voltage amplification signal according to the bias circuit; The high-speed adjustment circuit is connected to the bias circuit and the high-voltage amplifier, and is used to output the output voltage of the floating power rail generation circuit according to the voltage amplification signal. The voltage divider feedback circuit is connected to both the high-speed adjustment circuit and the second input terminal of the high-voltage amplifier. It is used to divide the collected output voltage to generate a feedback voltage and feed the feedback voltage back to the second input terminal of the high-voltage amplifier. The high-speed adjustment circuit is also used to self-adjust the output voltage so that the voltage at the first input terminal of the high-voltage amplifier is the same as the voltage at the second input terminal of the high-voltage amplifier.

2. The floating power rail generation circuit according to claim 1, characterized in that, The bias circuit includes: A common-source, common-gate current mirror, whose first terminal receives the external reference current and whose second terminal is grounded; A reference voltage generating resistor, the first end of which is connected to the power supply; A high-voltage bias transistor, the first end of which is connected to the second end of the reference voltage generating resistor, and its control end is connected to both its second end and the third end of the common-source cascode current mirror; The first copy current tube has its first end connected to the power supply, and its second end connected to its control terminal and the fourth end of the common source cascode current mirror.

3. The floating power rail generation circuit according to claim 2, characterized in that, The common-source, common-gate current mirror includes: The first high-voltage isolation tube, both its first end and its control end are used to receive the external reference current; The first current mirror transistor has its first end connected to its control terminal and the second end of the first high-voltage isolation transistor, and its second end is grounded. The second high-voltage isolation tube has its first end connected to the second end of the high-voltage bias tube, and its control end connected to the control end of the first high-voltage isolation tube. The second current mirror has its first end connected to the second end of the second high-voltage isolation tube, its control end connected to the control end of the first current mirror, and its second end grounded. The third high-voltage isolation tube has its first end connected to the second end of the first copy current tube, and its control end connected to the control end of the first high-voltage isolation tube. The third current mirror transistor has its first end connected to the second end of the third high-voltage isolation transistor, its control end connected to the control end of the first current mirror transistor, and its second end grounded.

4. The floating power rail generation circuit according to claim 3, characterized in that, The high-voltage amplifier includes: The second copy current transistor has its first end connected to the power supply and its control end connected to the control end of the first copy current transistor. The input transistor unit has its first terminal connected to the second terminal of the second copy current transistor, its second terminal connected to the second terminal of the reference voltage generating resistor, and its third terminal connected to the voltage divider feedback circuit. The high-voltage isolation unit is connected to the input pair transistors, the common-source cascode current mirror, the control terminal of the high-voltage bias transistor, and the high-speed regulation circuit. It is used to isolate the power supply and transmit the voltage amplification signal to the high-speed regulation circuit. The load-pair unit has its first and second ends connected to the high-voltage isolation unit, and its third end grounded.

5. The floating power rail generation circuit according to claim 4, characterized in that, The input transistor unit includes: The first input transistor has its first terminal connected to the second terminal of the second copy current transistor, and its control terminal connected to the second terminal of the reference voltage generating resistor. The second input transistor has its first terminal connected to the second terminal of the second copy current transistor, and its control terminal connected to the voltage divider feedback circuit.

6. The floating power rail generation circuit according to claim 5, characterized in that, The high-voltage isolation unit includes: The fourth high-voltage isolation tube has its first end connected to the second end of the first input tube, and its control end connected to the control end of the high-voltage bias tube. The fifth high-voltage isolation tube has its first end connected to the second end of the second input tube, and its control end connected to the control end of the high-voltage bias tube. The sixth high-voltage isolation tube has its first end connected to the second end of the fourth high-voltage isolation tube, and its control end connected to the control end of the first high-voltage isolation tube. The seventh high-voltage isolation tube has its first end connected to the second end of the fifth high-voltage isolation tube, and its control end connected to the control end of the first high-voltage isolation tube.

7. The floating power rail generation circuit according to claim 6, characterized in that, The load pair unit includes: The first load tube has its first end connected to its control end and the second end of the sixth high-voltage isolation tube, and its second end is grounded. The second load tube has its first end connected to the second end of the seventh high-voltage isolation tube, its control end connected to the control end of the first load tube, and its second end grounded.

8. The floating power rail generation circuit according to claim 3, characterized in that, The high-speed adjustment circuit includes: The third copy current transistor has its first end connected to the power supply and its control end connected to the control end of the first copy current transistor. A fast-response transistor, the first end of which is connected to the second end of the third copy current transistor, and its control end is connected to the high-voltage bias transistor; An adjustable resistor is provided, with its first end connected to the second end of the fast response transistor, and the second end grounded. An output regulating tube, the first end of which is connected to the first end of the fast response tube, and its control end is connected to the output end of the high voltage amplifier; The power transistor has its first terminal connected to the second terminal of the output regulating transistor, its control terminal connected to the first terminal of the regulating resistor, and its second terminal grounded. The zero-point resistor has its first end connected to the second end of the output regulating tube, and its second end outputs the output voltage of the floating power rail generation circuit.

9. The floating power rail generation circuit according to claim 4, characterized in that, The voltage divider feedback circuit includes: The first voltage divider resistor has its first end connected to the power supply. The second voltage divider resistor has its first end connected to the second end of the first voltage divider resistor and the second input terminal of the high-voltage amplifier, and its second end connected to the output terminal of the high-speed adjustment circuit.

10. A method for generating floating power rails, characterized in that, include: The control bias circuit generates a bias current based on the received external reference current and determines the reference voltage in conjunction with the power supply to provide it to the first input terminal of the high voltage amplifier. The high-voltage amplifier is controlled to generate a voltage amplification signal according to the bias circuit; The high-speed adjustment circuit obtains the output voltage based on the voltage amplification signal. The control voltage divider feedback circuit divides the acquired output voltage to generate a feedback voltage, and feeds the feedback voltage back to the second input terminal of the high voltage amplifier; The high-speed adjustment circuit is controlled to self-adjust the output voltage so that the voltage at the first input terminal of the high-voltage amplifier is the same as the voltage at the second input terminal of the high-voltage amplifier.

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