A fast response LDO circuit without off-chip capacitor

Abstract

The application relates to a fast-response LDO circuit without an external capacitor, and belongs to the technical field of integrated circuits. The circuit comprises a high-gain Class AB OTA module, a capacitor multiplication circuit module and a voltage output module; wherein the voltage output module is connected with the output end of the high-gain Class AB OTA module and the output end of the capacitor multiplication circuit module. The high-gain Class AB OTA module is used for charging and discharging the voltage output module, generating a larger current under lower power consumption, and improving the transient response capability of the circuit; the capacitor multiplication circuit module is used for reducing the capacitor area required for loop compensation, and realizing faster transient response. The application improves the transient response capability of the circuit, reduces the capacitor area, and is easy to integrate.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a fast-response LDO circuit without external capacitors. Background Technology

[0002] In many integrated circuit chips, LDOs (Low Dropout Linear Regulators) are required to regulate the power supply of various modules. If a large off-chip capacitor for frequency compensation is added to the output, dedicated pads for the external capacitor's pins must be reserved on the chip. If the frequency compensation capacitor is designed inside the chip, its large size typically occupies considerable chip area. Therefore, placing the output compensation capacitor off-chip or on-chip wastes chip area, increases cost, and makes on-chip system integration difficult. To address these issues, capacitor-free design has become a significant trend in LDO design. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a fast-response LDO circuit without external capacitors, so as to solve the problems of large chip area and difficulty in integration of traditional LDO circuits.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A capacitor-free, fast-response LDO circuit includes a high-gain Class AB OTA module, a capacitance multiplier circuit module, and a voltage output module. The voltage output module is connected to the output terminals of both the high-gain Class AB OTA module and the capacitance multiplier circuit module. The high-gain Class AB OTA module charges and discharges the gate of the power NMOS transistor MN0 in the voltage output module, improving the circuit's transient response capability. The capacitance multiplier circuit module reduces the capacitor area required for loop compensation and lowers the capacitance at the gate of the power NMOS transistor, achieving a faster transient response.

[0006] Optionally, the high-gain Class AB OTA module includes NMOS transistors MN1 to MN7, PMOS transistors MP1 to MP8, and resistors R1 and R2.

[0007] The gates of NMOS transistors MN1 and MN2 are both connected to a bias voltage VN, and the sources of NMOS transistors MN1 and MN2 are both grounded. The drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP3 and the gate of PMOS transistor MP5, respectively. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP4 and the gate of PMOS transistor MP6, respectively. The gate of NMOS transistor MN3 is connected to the gate of NMOS transistor MN4, and is connected to the gate of NMOS transistor MN5, the drain of MN3, and the drain of PMOS transistor MP1 through resistor R1. The source of NMOS transistor MN1 is grounded. The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN6, the drain of MN4, and PMOS transistor MP5 through resistor R2. The drain of MOSFET MP2 is connected to the ground, and the source of NMOS transistor MN4 is grounded. The drain of NMOS transistor MN5 is connected to the drain and gate of PMOS transistor MP7 and the gate of PMOS transistor MP8, respectively, and the source of MN5 is grounded. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP8, and the source of MN6 is grounded. The gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP4, and its source is connected to the source of PMOS transistor MP3 and the drain of MP5, respectively. The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP3, and its source is connected to the source of PMOS transistor MP4 and the drain of MP6, respectively. The sources of PMOS transistors MP5 to MP8 are all connected to the power supply voltage.

[0008] In this module, the drain of the PMOS transistor MP8 serves as the output Vo1 of the high-gain Class AB OTA module, and is connected to the capacitor multiplier circuit module and the voltage output module, respectively.

[0009] Optionally, the capacitor multiplier circuit module includes NMOS transistors MN7 and MN8, PMOS transistors MP9 and MP10, and capacitor Cc.

[0010] The gate of NMOS transistor MN7 is connected to the gate and drain of NMOS transistor MN8 and the drain of PMOS transistor MP10, respectively. The drain of MN7 is connected to the drain of PMOS transistor MP9 and one end of capacitor Cc, respectively. The drain of NMOS transistor MN8 is connected to the other end of capacitor Cc. The sources of NMOS transistors NM7 and NM8 are both grounded. The gate of PMOS transistor MP9 is connected to the gate of PMOS transistor MP10 and is also connected to the bias voltage VP. The sources of PMOS transistors MP9 and MP10 are both connected to the power supply voltage.

[0011] In this circuit, the drain of PMOS transistor MP9 serves as the output Vo2 of the capacitance multiplier circuit module, and is connected to the output of the high-gain ClassAB OTA module and the voltage output module, respectively.

[0012] Optionally, the voltage output module includes a power NMOS transistor MN0 and resistors R3 and R4. The gate of the power transistor MN0 is connected to the output of the high-gain Class AB OTA module and the output of the capacitor multiplier circuit module, respectively. Its drain is connected to the power supply voltage, and its source is grounded through resistors R3 and R4. The connection point of resistors R3 and R4 is connected to the gate of the PMOS transistor MP1 in the high-gain Class AB OTA module, forming a negative feedback loop. The source of the NMOS transistor MN0 serves as the output of the entire LDO circuit. The output voltage of the voltage output module can be adjusted by adjusting the ratio of resistors R3 and R4.

[0013] The beneficial effects of this invention are as follows: This invention utilizes a Class AB OTA structure to charge and discharge the gate of the power transistor, thereby generating a very large current for charging and discharging the gate of the power transistor at low power consumption, thus improving the transient response capability of the circuit; at the same time, it improves the traditional Class AB OTA structure by adding a first resistor and a second resistor in the loop, thereby increasing the loop gain; and it introduces a capacitor multiplier circuit to enhance the transient response speed, while reducing the capacitor area, making this invention easy to integrate.

[0014] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0015] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0016] Figure 1 This is a system block diagram of the LDO circuit of the present invention;

[0017] Figure 2 The circuit structure diagram is shown for the high-gain Class AB OTA module.

[0018] Figure 3 This is a circuit structure diagram of the capacitor multiplier circuit module;

[0019] Figure 4 The PSRR-frequency simulation diagram obtained by HSPace simulation of the LDO circuit;

[0020] Figure 5 The image shows the load step simulation diagram obtained by HSPace simulation of the LDO circuit. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0023] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0024] This invention addresses the problems of increased chip area and cost caused by the need for large external capacitors in traditional LDO structures, as well as difficulties in integration. It proposes a capacitor-free LDO circuit, the block diagram of which is shown below. Figure 1 As shown, the LDO circuit includes a high-gain Class AB OTA module, a capacitor multiplier circuit module, and a voltage output module. The high-gain Class AB OTA module achieves better transient response by using both FVF and Class AB structures, and further increases loop gain by adding resistors R3 and R4 to the traditional Class AB OTA structure. The capacitor multiplier circuit module amplifies the capacitance of the compensation capacitor through its circuit structure, reducing the capacitance of the gate of the power NMOS transistor MN0 while saving chip area, thus further improving the circuit's response speed. The voltage output module adjusts the output voltage by regulating the ratio of the third and fourth resistors. The LDO circuit proposed in this invention can be fabricated into an integrated circuit using standard CMOS technology. The circuit structure and connection relationships of the modules are described below.

[0025] The structure of the high-gain Class AB OTA module is as follows: Figure 2 As shown, it includes NMOS transistors MN1 to MN7, PMOS transistors MP1 to MP8, and resistors R1 and R2.

[0026] In this configuration, the gates of NMOS transistors MN1 and MN2 are both connected to a bias voltage VN, and the sources of NMOS transistors MN1 and MN2 are both grounded. The drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP3 and the gate of PMOS transistor MP5, respectively. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP4 and the gate of PMOS transistor MP6, respectively. The gate of NMOS transistor MN3 is connected to the gate of NMOS transistor MN4, and is also connected to the gate of NMOS transistor MN5, the drain of MN3, and the drain of PMOS transistor MP1 through resistor R1. The source of NMOS transistor MN1 is grounded. The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN6 and the drain of MN4 through resistor R2. The drain of PMOS transistor MP2 is connected, and the source of NMOS transistor MN4 is grounded. The drain of NMOS transistor MN5 is connected to the drain and gate of PMOS transistor MP7 and the gate of PMOS transistor MP8, and the source of MN5 is grounded. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP8, and the source of MN6 is grounded. The gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP4, and its source is connected to the source of PMOS transistor MP3 and the drain of MP5, respectively. The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP3, and its source is connected to the source of PMOS transistor MP4 and the drain of MP6, respectively. The sources of PMOS transistors MP5 to MP8 are all connected to the power supply voltage. The drain of PMOS transistor MP8 serves as the output terminal of the high-gain Class AB OTA module, and is connected to the capacitor multiplier circuit module and the voltage output module, respectively. During dynamic operation, it outputs a large current to charge and discharge the gate capacitor of NMOS transistor MN0.

[0027] The structure of the capacitor multiplier circuit module is as follows: Figure 3As shown, it includes NMOS transistors MN7 and MN8, PMOS transistors MP9 and MP10, and capacitor Cc. The gate of NMOS transistor MN7 is connected to the gate and drain of NMOS transistor MN8 and the drain of PMOS transistor MP10, respectively. The drain of MN7 is connected to the drain of PMOS transistor MP9 and one end of capacitor Cc, respectively. The drain of NMOS transistor MN8 is connected to the other end of capacitor Cc. The sources of NMOS transistors NM7 and NM8 are both grounded. The gate of PMOS transistor MP9 is connected to the gate of PMOS transistor MP10 and also to the bias voltage VP. The sources of PMOS transistors MP9 and MP10 are both connected to the power supply voltage. The drain of PMOS transistor MP9 serves as the output terminal of the capacitance multiplier circuit module, connected to the gate of power transistor MN0 in the voltage output module. This allows the capacitance multiplier circuit module to function as a loop compensation module and reduce the required capacitance value, thereby reducing the gate capacitance of the power NMOS transistor MN and improving the circuit response speed.

[0028] The structure of the voltage output module is as follows: Figure 1 As shown, it includes a power NMOS transistor MN0 and resistors R3 and R4. The gate of power transistor MN0 is connected to the output of the high-gain Class AB OTA module and the output of the capacitor multiplier circuit module, respectively. Its drain is connected to the power supply voltage, and its source is grounded through resistors R3 and R4. The connection point of resistors R3 and R4 is connected to the gate of PMOS transistor MP1 in the high-gain Class AB OTA module, forming a negative feedback loop. The voltage output module can adjust the output voltage by adjusting the ratio of resistors R3 and R4. The source of NMOS transistor MN0 serves as the output terminal of the entire circuit, outputting the final stable voltage. This invention allows adjustment of the output voltage by adjusting the ratio of resistors R3 and R4.

[0029] The technical effects of the LDO circuit proposed in this invention are illustrated by the simulation results. The results obtained through Hspice simulation are as follows: Figure 4 and Figure 5 The simulation diagram is shown below. Figure 4 The figure shows the PSRR frequency simulation results. As can be seen from the figure, at 1MHz, the PSRR for loads of 200uA, 10mA, and 20mA are -42dB, -36dB, and -23dB, respectively. The above three working loads are only examples. The simulation results show that the PSRR characteristics of the present invention are applicable to various working states within a small load range. Figure 5 The figure shows the simulation results of load step change. As can be seen from the figure, the load current jumps between 200μA and 20mA, and the jump time is 1μs. The maximum values ​​of the LDO overshoot voltage and undershoot voltage are 90mV and 70mV, respectively, and the recovery times are 1.2μs and 1.1μs, respectively.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A fast-response LDO circuit without external capacitors, characterized in that: The circuit includes a high-gain Class AB OTA module, a capacitance multiplier circuit module, and a voltage output module; the voltage output module is connected to the output terminal of the high-gain Class AB OTA module and the output terminal of the capacitance multiplier circuit module, respectively. The high-gain Class AB OTA module is used to charge and discharge the voltage output module, improving the transient response capability of the circuit; the capacitor multiplication circuit module is used to reduce the capacitor area required for loop compensation, achieving a faster transient response. The high-gain Class AB OTA module includes NMOS transistors MN1~MN7, PMOS transistors MP1~MP8, and resistors R1 and R2; The gates of NMOS transistors MN1 and MN2 are both connected to a bias voltage VN, and the sources of NMOS transistors MN1 and MN2 are both grounded. The drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP3 and the gate of PMOS transistor MP5, respectively. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP4 and the gate of PMOS transistor MP6, respectively. The gate of NMOS transistor MN3 is connected to the gate of NMOS transistor MN4, and is connected to the gate of NMOS transistor MN5, the drain of MN3, and the drain of PMOS transistor MP1 through resistor R1. The source of NMOS transistor MN1 is grounded. The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN6, the drain of MN4, and PMOS transistor MP5 through resistor R2. The drain of MOSFET MP2 is connected to the ground, and the source of NMOS transistor MN4 is grounded. The drain of NMOS transistor MN5 is connected to the drain and gate of PMOS transistor MP7 and the gate of PMOS transistor MP8, respectively, and the source of MN5 is grounded. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP8, and the source of MN6 is grounded. The gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP4, and its source is connected to the source of PMOS transistor MP3 and the drain of MP5, respectively. The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP3, and its source is connected to the source of PMOS transistor MP4 and the drain of MP6, respectively. The sources of PMOS transistors MP5 to MP8 are all connected to the power supply voltage. The drain of the PMOS transistor MP8 serves as the output Vo1 of the high-gain Class AB OTA module, and is connected to the capacitor multiplier circuit module and the voltage output module, respectively.

2. The capacitor-free fast-response LDO circuit according to claim 1, characterized in that: The capacitor multiplier circuit module includes NMOS transistors MN7 and MN8, PMOS transistors MP9 and MP10, and capacitor Cc. The gate of NMOS transistor MN7 is connected to the gate and drain of NMOS transistor MN8 and the drain of PMOS transistor MP10. The drain of MN7 is connected to the drain of PMOS transistor MP9 and one end of capacitor Cc. The drain of NMOS transistor MN8 is connected to the other end of capacitor Cc. The sources of NMOS transistors NM7 and NM8 are both grounded. The gate of PMOS transistor MP9 is connected to the gate of PMOS transistor MP10 and is also connected to the bias voltage VP. The sources of PMOS transistors MP9 and MP10 are both connected to the power supply voltage. The drain of PMOS transistor MP9 serves as the output Vo2 of the capacitance multiplier circuit module, and is connected to the output of the high-gain Class ABOTA module and the voltage output module, respectively.

3. The capacitor-free, fast-response LDO circuit according to claim 1, characterized in that: The voltage output module includes a power NMOS transistor MN0 and resistors R3 and R4. The gate of the power transistor MN0 is connected to the output of the high-gain Class AB OTA module and the output of the capacitor multiplier circuit module, respectively. Its drain is connected to the power supply voltage, and its source is grounded through resistors R3 and R4. The connection terminals of resistors R3 and R4 are connected to the high-gain Class AB OTA module to form a negative feedback loop.

4. The capacitorless fast-response LDO circuit according to claim 3, characterized in that: The output voltage is adjusted by adjusting the ratio of resistors R3 and R4.

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