Controller and method of operation thereof

Abstract

Embodiments of the present disclosure relate to a controller and an operating method thereof. According to embodiments of the present disclosure, the controller can include i) a plurality of sub-circuits, and ii) a processor configured to determine states of the plurality of sub-circuits, determine whether an activation condition corresponding to the plurality of sub-circuits is satisfied at a first point in time, and control the controller to operate in an activation mode or in a low-power mode at a second point in time according to whether the activation condition corresponding to the plurality of sub-circuits is satisfied.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0183831, filed on December 21, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a controller and its operation method that executes an active mode or a low-power mode based on the state of multiple sub-circuits. Background Technology

[0004] Memory systems include data storage devices that store data based on requests from a host such as a computer, server, smartphone, tablet PC, or other electronic device. Examples of memory systems range from traditional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory (UFS) devices, or embedded multimedia cards (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory devices. The memory controller can receive commands from the host and, based on the received commands, can execute commands or control read / write / erase operations on the memory devices in the memory system. The memory controller can be used to perform firmware operations to perform logical operations for controlling these operations.

[0006] Typically, when no commands are input from the host within a predetermined time, the memory system reduces the amount of current used to conserve power. However, the frequency with which commands are input from the host to the memory system may vary over time, potentially leading to unnecessary power consumption or performance degradation in the memory system. Summary of the Invention

[0007] The various embodiments of the disclosed technology relate to a controller and operating method that can prevent unnecessary power consumption or performance degradation of the controller.

[0008] On one hand, the disclosed technology can provide a controller comprising: i) a plurality of sub-circuits, and ii) a processor configured to: determine the state of the plurality of sub-circuits, determine whether an activation condition corresponding to the plurality of sub-circuits is met at a first time point, and, based on whether the activation condition of the plurality of sub-circuits is met, control the controller to operate at a second time point in either an activation mode using a current greater than or equal to an activation current value or in a low-power mode using a current lower than an activation current value. The second time point is a time point elapsed after a predetermined time since processing a command received from outside the controller using a current equal to or greater than the activation current value.

[0009] In this case, when it is determined that at least one of the activation conditions corresponding to multiple sub-circuits is satisfied, the processor can control the controller to operate in activation mode at a second time point.

[0010] On the other hand, the disclosed technology can provide a method for operating a controller, including: i) determining the state of a plurality of sub-circuits, ii) determining whether an activation condition corresponding to the plurality of sub-circuits is met at a first time point, and iii) depending on whether the activation conditions of the plurality of sub-circuits are met, operating at a second time point in either an activation mode using a current greater than or equal to an activation current value or in a low-power mode using a current lower than an activation current value. The second time point is a predetermined time elapsed after processing a command from outside the controller using a current equal to or greater than the activation current value.

[0011] In this case, when it is determined that at least one of the activation conditions corresponding to multiple sub-circuits is satisfied, the controller can operate in activation mode at a second time point.

[0012] According to embodiments of the disclosed technology, unnecessary power consumption or performance degradation of the controller can be prevented. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating the configuration of a memory system based on an embodiment of the disclosed technology.

[0014] Figure 2 This is a block diagram schematically illustrating a memory device based on an embodiment of the disclosed technology.

[0015] Figure 3 This is a diagram illustrating the structure of word lines and bit lines of a memory device based on an embodiment of the disclosed technology.

[0016] Figure 4 This is a diagram illustrating a schematic structure of a controller based on an embodiment of the disclosed technology.

[0017] Figure 5 This is a flowchart illustrating the schematic operation of a controller based on an embodiment of the disclosed technology.

[0018] Figure 6 This is a diagram illustrating an example of changes in the amount of current used by the controller.

[0019] Figure 7 This is a diagram illustrating another example of the variation in the amount of current used by a controller based on an embodiment of the disclosed technology.

[0020] Figure 8 This is a diagram illustrating a processing unit as an example of a sub-circuit based on an embodiment of the disclosed technology.

[0021] Figure 9 This indicates whether the controller determines whether the condition is met. Figure 8 A flowchart illustrating an example of the operation of the activation conditions of the processing unit shown.

[0022] Figure 10 It is shown Figure 8 A diagram illustrating an example of the operation of the processing unit shown.

[0023] Figure 11 This is a diagram illustrating a sequential information reading circuit as an example of a sub-circuit based on an embodiment of the disclosed technology.

[0024] Figure 12 This indicates whether the controller determines whether the condition is met. Figure 11 The flowchart shows an example of the operation of the activation condition of the sequential information reading circuit.

[0025] Figure 13 This is a diagram illustrating a vector search circuit as an example of a sub-circuit based on an embodiment of the disclosed technology.

[0026] Figure 14 This indicates whether the controller determines whether the condition is met. Figure 13 The flowchart shows an example of the operation of the activation condition of the vector search circuit.

[0027] Figure 15 This is a diagram illustrating a mapping table search circuit as an example of a sub-circuit based on an embodiment of the disclosed technology.

[0028] Figure 16 This indicates whether the controller determines whether the condition is met. Figure 15 The flowchart shows an example of the operation of the activation condition of the mapping table search circuit.

[0029] Figure 17 This is a diagram illustrating a command queue storage circuit as an example of a sub-circuit based on an embodiment of the disclosed technology.

[0030] Figure 18 This indicates whether the controller determines whether the condition is met. Figure 17 The flowchart shows an example of the operation of the activation condition of the command queue storage circuit.

[0031] Figure 19 This is a diagram illustrating a buffer storage circuit as an example of a sub-circuit based on an embodiment of the disclosed technology.

[0032] Figure 20 This indicates whether the controller determines whether the condition is met. Figure 19The flowchart illustrates an example of the operation of the activation condition of the buffer storage circuit shown.

[0033] Figure 21 This is a diagram illustrating a method of operating a controller based on an embodiment of the disclosed technology.

[0034] Figure 22 This is a diagram illustrating the configuration of a computing system based on some embodiments of the disclosed technology. Detailed Implementation

[0035] Hereinafter, various embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. When the term "embodiment" is used herein, it does not necessarily refer to all embodiments.

[0036] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, it should be noted that the invention can be implemented in different forms and variations and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts throughout the various drawings and embodiments of the invention.

[0037] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the apparatus described herein or elements other than those described herein. Because the algorithms underlying the method (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0038] When implemented at least in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0039] Figure 1 This is a diagram illustrating a schematic configuration of a memory system 100 based on an embodiment of the disclosed technology.

[0040] In some embodiments, memory system 100 may include memory device 110 configured to store data and memory controller 120 configured to control memory device 110.

[0041] Memory device 110 may include multiple memory blocks, each memory block including multiple memory cells for storing data. Memory device 110 may be configured to operate in response to control signals received from memory controller 120. Operation of memory device 110 may include, for example, read operations, programming operations (also referred to as "write operations"), erase operations, etc.

[0042] The memory cells in memory device 110 are used to store data and can be arranged in an array of memory cells. The array of memory cells can be divided into blocks of memory cells, and each block includes different pages of memory cells. In a typical implementation of a NAND flash memory device, a page of a memory cell is the smallest unit of memory that can be programmed or written, and the data stored in the memory cell can be erased on a block-by-block basis.

[0043] In some implementations, the memory device 110 may be implemented as various types such as: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM).

[0044] The memory device 110 can be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology can be applied to any type of flash memory device having a charge storage layer. In one embodiment, the charge storage layer can be formed of a conductive material, and such a charge storage layer can be referred to as a floating gate. In another embodiment, the charge storage layer can be formed of an insulating material, and such a flash memory device can be referred to as charge-fetch flash (CTF).

[0045] The memory device 110 can be configured to receive commands and addresses from the memory controller 120 to access a region of the memory cell array selected using that address. In other words, the memory device 110 can perform operations corresponding to the received commands on a memory region of the memory device having a physical address corresponding to the address received from the memory controller 120.

[0046] In some implementations, the memory device 110 can perform programming operations, reading operations, erasing operations, etc. During a programming operation, the memory device 110 can write data to an address-selected region. During a reading operation, the memory device 110 can read data from an address-selected memory region. During an erasing operation, the memory device 110 can erase data stored in an address-selected memory region.

[0047] The memory controller 120 can control write (programming) operations, read operations, erase operations, and background operations performed on the memory device 110. Background operations may include, for example, operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0048] The memory controller 120 can control the operation of the memory device 110 upon request from the host. Optionally, when the memory controller 120 performs such background operation of the memory device, the memory controller 120 can control the operation of the memory device 110 even without a request from the host.

[0049] The memory controller 120 and the host can be separate devices. In some embodiments, the memory controller 120 and the host can be integrated and implemented as a single device. In the following description, the memory controller 120 and the host will be discussed as separate devices by way of example.

[0050] Reference Figure 1 The memory controller 120 may include a memory interface (memory I / F) 122, a control circuit 123, and a host interface (host I / F) 121.

[0051] Host interface 121 can be configured to provide an interface for communicating with a host.

[0052] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and perform operations to process the received command.

[0053] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface to the memory device 110 and the memory controller 120 for the memory controller 120 to perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0054] The control circuit 123 can be configured to control the operation of the memory device 110 via the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126, etc.

[0055] Processor 124 can control all operations of memory controller 120. Processor 124 can perform logical operations. Processor 124 can communicate with host via host interface 121. Processor 124 can communicate with memory device 110 via memory interface 122.

[0056] Processor 124 can be used to perform operations associated with the Flash Translation Layer (FTL) to efficiently manage memory operations on memory system 100. Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive LBAs and translate them into PBAs using a mapping table.

[0057] Based on the mapping unit, FTL can employ various address mapping methods. Typical address mapping methods can include page mapping, block mapping, and hybrid mapping.

[0058] Processor 124 can be configured to randomize data received from the host to write the randomized data to the memory cell array. For example, processor 124 can randomize data received from the host by using a randomization seed. The randomized data is provided to memory device 110 and written to the memory cell array.

[0059] Processor 124 can be configured to derandomize data received from memory device 110 during a read operation. For example, processor 124 can derandomize data received from memory device 110 by using a derandomization seed. The derandomized data can then be output to the host.

[0060] The processor 124 can run firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 can control all operations of the memory controller 120, and in order to perform logical operations, it can run (drive) the firmware loaded into the working memory 125 during startup.

[0061] Firmware refers to a program or software stored on a non-volatile memory and running inside the memory system 100.

[0062] In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer (FTL) is configured to translate a logical address in a host request into a physical address of the memory device 110, the host interface layer (HIL) is configured to interpret commands issued by the host to a data storage device such as the memory system 100 and pass the commands to the FTL, and the flash interface layer (FIL) is configured to pass commands issued by the FTL to the memory device 110.

[0063] For example, firmware can be stored in memory device 110 and then loaded into working memory 125.

[0064] The working memory 125 may store firmware, program code, commands, or data strips necessary for operating the memory controller 120. The working memory 125 may include at least one of, for example, static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM) as volatile memory.

[0065] Error detection / correction circuitry 126 can be configured to detect and correct one or more error bits in data using error detection and correction codes. In some embodiments, the data for error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110.

[0066] The error detection / correction circuit 126 can be implemented to decode data using an error correction code. The error detection / correction circuit 126 can be implemented using various decoding schemes. For example, a decoder performing non-system code decoding or a decoder performing system code decoding can be used.

[0067] In some implementations, the error detection / correction circuit 126 can detect one or more error bits based on sectors. That is, each read data entry can include multiple sectors. A sector can refer to a data unit smaller than a read unit of flash memory (e.g., a page). The sectors constituting each read data entry can be mapped based on addresses.

[0068] In some implementations, the error detection / correction circuit 126 can calculate the bit error rate (BER) sector by sector and determine whether the number of erroneous bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the erroneous bits in the corresponding sector are uncorrectable, and the corresponding sector is marked as "failed". If the BER is lower than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable, or the corresponding sector can be marked as "passed".

[0069] Error detection / correction circuit 126 can sequentially perform error detection and correction operations on all read data. When a sector in the read data is correctable, error detection / correction circuit 126 can proceed to the next sector to check if error correction is required for that sector. After completing error detection and correction operations on all read data in this manner, error detection / correction circuit 126 can obtain information about which sector in the read data is considered uncorrectable. Error detection / correction circuit 126 can provide this information (e.g., the address of the uncorrectable bit) to processor 124.

[0070] The memory system 100 may also include a bus 127 to provide a channel between the constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. The bus 127 may include, for example, a control bus for transmitting various types of control signals and commands, and a data bus for transmitting various types of data.

[0071] By way of examples Figure 1 The aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are shown. Note that some constituent elements shown in the figures may be omitted, or some of the aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. Additionally, in some embodiments, one or more other constituent elements may be added to the aforementioned constituent elements of the memory controller 120.

[0072] Figure 2 This is a block diagram schematically illustrating a memory device 110 based on an embodiment of the disclosed technology.

[0073] In some implementations, the memory device 110 based on the disclosed technology may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0074] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0075] In multiple memory blocks BLK1 to BLKz, multiple word lines WL and multiple bit lines BL can be set up in rows and columns, and multiple memory cells MC can be arranged.

[0076] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read / write circuitry 230 via multiple bit lines BL.

[0077] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells are non-volatile memory cells. In some embodiments, such non-volatile memory cells may be arranged in a vertical channel configuration.

[0078] The memory cell array 210 can be configured as a memory cell array with a two-dimensional structure. In some embodiments, the memory cell array 210 can be arranged in a three-dimensional structure.

[0079] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data. Another example is that each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) configured to store two bits of data per memory cell. Yet another example is that each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) configured to store three bits of data per memory cell. Yet another example is that each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) configured to store four bits of data per memory cell. Furthermore, the memory cell array 210 can include a plurality of memory cells, each of which can be configured to store at least five bits of data per memory cell.

[0080] Reference Figure 2 The address decoder 220, read / write circuit 230, control logic 240, and voltage generation circuit 250 can operate as peripheral circuits configured to drive the memory cell array 210.

[0081] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0082] Address decoder 220 can be configured to operate in response to commands and control signals from control logic 240.

[0083] Address decoder 220 can receive addresses through an input / output buffer within memory device 110. Address decoder 220 can be configured to decode block addresses among the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0084] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0085] During a read operation, the address decoder 220 can apply a read voltage Vread to the selected word line WL within the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0086] During the programming verification operation, the address decoder 220 can apply a verification voltage generated by the voltage generation circuit 250 to the selected word line WL within the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0087] Address decoder 220 can be configured to decode column addresses from received addresses. Address decoder 220 can then transmit the decoded column addresses to read / write circuitry 230.

[0088] The memory device 110 can perform read and program operations page by page. The address received when requesting a read or program operation may include at least one of a block address, a row address, and a column address.

[0089] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read / write circuitry 230.

[0090] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0091] The read / write circuit 230 may include multiple page buffers PB. When the memory cell array 210 performs a read operation, the read / write circuit 230 can operate as a "read circuit", and when the memory cell array 210 performs a write operation, the read / write circuit 230 can operate as a "write circuit".

[0092] The read / write circuit 230 described above is also referred to as a data register circuit or a page buffer circuit including multiple page buffers PB. The read / write circuit 230 may include data buffers involved in data processing functions, and in some embodiments, may further include cache buffers for data caching.

[0093] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cell during read operations and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cell to detect changes in current proportional to the current at the sensing node and to hold or latch the corresponding voltage as sensing data, wherein the current varies according to the programming state of the corresponding memory cell.

[0094] The read / write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0095] During a read operation, the read / write circuit 230 senses the voltage value of the memory cell and reads that voltage value as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or page register, the read / write circuit 230 may also include column select circuitry.

[0096] Control logic 240 can be connected to address decoder 220, read / write circuit 230, and voltage generation circuit 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory device 110.

[0097] Control logic 240 can be configured to control all operations of memory device 110 in response to control signal CTRL. Control logic 240 can output control signals to adjust the voltage levels of the sensing nodes of multiple page buffers PB to precharge voltage levels.

[0098] Control logic 240 can control read / write circuit 230 to perform read operations in memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass used during read operations in response to voltage generation circuit control signals output from control logic 240.

[0099] The memory block BLK included in the memory device 110 may include multiple pages PG. In some embodiments, multiple memory cells arranged in columns form a memory cell string, and multiple memory cells arranged in rows form a memory block. Each of the multiple pages PG is connected to a word line WL, and each of the memory cell strings STR is connected to a bit line BL.

[0100] Within a storage block BLK, multiple word lines (WLs) and multiple bit lines (BLs) can be arranged in rows and columns. For example, each of the multiple word lines (WLs) can be arranged along the row direction, and each of the multiple bit lines (BLs) can be arranged along the column direction. Alternatively, each of the multiple word lines (WLs) can be arranged along the column direction, and each of the multiple bit lines (BLs) can be arranged along the row direction.

[0101] In some implementations, multiple word lines (WL) and multiple bit lines (BL) may intersect each other, thereby addressing a single memory cell in an array of multiple memory cells (MC). In some implementations, each memory cell (MC) may include a transistor (TR) comprising a layer of material having a charge-retaining structure.

[0102] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected directly or via another transistor to the corresponding bit line BL. The source (or drain) of the transistor TR may be connected directly or via another transistor to the source line (which may be ground). The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from the word line WL.

[0103] In each of the multiple memory blocks BLK1 to BLKz, a first select line (also called a source select line or drain select line) may be additionally arranged outside the first outermost word line closer to the read / write circuit 230 among the two outermost word lines, and a second select line (also called a drain select line or source select line) may be additionally arranged outside the other second outermost word line.

[0104] In some implementations, at least one dummy word line may be additionally arranged between the first outermost word line and the first select line. Additionally, at least one dummy word line may be additionally arranged between the second outermost word line and the second select line.

[0105] It can perform read and write operations on storage blocks one page at a time, and it can also perform erase operations on storage blocks one by one.

[0106] Figure 3This is a diagram illustrating the structure of the word line WL and bit line BL of a memory device (e.g., memory device 110) based on an embodiment of the disclosed technology.

[0107] Reference Figure 3 The memory device has a core region where memory cells MC are arranged and an auxiliary region (the remaining region other than the core region) including circuitry for performing operations of the memory cell array (e.g., memory cell array 210).

[0108] In the kernel region, a certain number of memory cells arranged in one direction can be called a "page" (PG), and a certain number of memory cells connected in series can be called a "memory cell string" (STR).

[0109] Word lines WL1 to WL9 can be connected to row decoder 310. Bit line BL can be connected to column decoder 320. Figure 2 The data register 330 corresponding to the read / write circuit 230 can exist between multiple bit lines BL and column decoder 320.

[0110] Multiple word lines WL1 to WL9 can correspond to multiple pages PG.

[0111] For example, such as Figure 3 As shown, each of the multiple word lines WL1 to WL9 can correspond to a page PG. When the size of each of the multiple word lines WL1 to WL9 is large, each of the multiple word lines WL1 to WL9 can correspond to at least two (e.g., two or four) page PGs. Each page PG is the smallest unit in programming and reading operations, and when programming and reading operations are performed, all memory cells MC within the same page PG can be operated on simultaneously.

[0112] Multiple bit lines BL can be connected to column decoder 320. In some implementations, the multiple bit lines BL can be divided into odd bit lines BL and even bit lines BL, such that a pair of odd bit lines and even bit lines are connected together to column decoder 320.

[0113] When accessing a memory cell MC, row decoder 310 and column decoder 320 are used to locate the desired memory cell based on its address.

[0114] In some implementations, all data processing performed by memory device 110, including programming and reading operations, can occur via data register 330. If data processing via data register 330 is delayed, some or all of the data processing in other areas may have to wait until data register 330 has finished processing, which degrades the overall performance of memory device 110.

[0115] Reference Figure 3 In the example shown, in a memory cell string STR, multiple transistors TR1 to TR9 can be connected to multiple word lines WL1 to WL9, respectively. In some embodiments, the multiple transistors TR1 to TR9 correspond to memory cells MC. In this example, the multiple transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0116] The multiple word lines WL1 to WL9 include two outermost word lines, WL1 and WL9. A first select line DSL can be additionally arranged outside the first outermost word line WL1, which is closer to the data register 330 and has a shorter signal path compared to the other outermost word line WL9. A second select line SSL can be additionally arranged outside another second outermost word line WL9.

[0117] The first selection transistor D-TR, controlled by the first selection line DSL to be turned on / off, has a gate electrode connected to the first selection line DSL, but does not include a floating gate FG. The second selection transistor S-TR, controlled by the second selection line SSL to be turned on / off, has a gate electrode connected to the second selection line SSL, but also does not include a floating gate FG.

[0118] The first selection transistor D-TR serves as a switching circuit to connect the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR serves as a switching circuit to connect the corresponding memory cell string STR to the source line SL. In other words, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0119] In some embodiments, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR to turn on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR to turn off the second selection transistor S-TR.

[0120] During a read or verify operation, the memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during a read or verify operation, current can flow through the corresponding memory cell string STR and to the source line SL corresponding to ground, allowing measurement of the voltage level on the bit line BL. However, during a read operation, there may be a time difference in the turn-on / turn-off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0121] During the erase operation, the memory system 100 can apply a predetermined voltage (e.g., +20V) to the substrate via the source line SL. During the erase operation, the memory system 100 applies a specific voltage to float both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, the applied erase voltage can remove charge from the floating gate FG of the selected memory cell.

[0122] Figure 4 This is a diagram illustrating a schematic structure of a controller 10 based on an embodiment of the disclosed technology.

[0123] Reference Figure 4 The controller 10 may include multiple sub-circuits SUB_C and processor PROC.

[0124] Each of the multiple sub-circuits SUB_C is a hardware module configured to perform a specific operation within the controller 10.

[0125] The processor PROC can be electrically connected to multiple sub-circuits SUB_C. The processor PROC can be directly connected to each of the multiple sub-circuits SUB_C via wires or indirectly connected to each of the multiple sub-circuits SUB_C via another module.

[0126] The processor PROC can determine the status of multiple sub-circuits SUB_C connected to it. If needed, the processor PROC can request these sub-circuits SUB_C to perform specific operations.

[0127] On the other hand, controller 10 can receive commands CMD from outside controller 10. Processor PROC can execute logical operations for processing operations requested by the received commands CMD (e.g., read / write operations). For example, the operation of receiving commands CMD from outside controller 10 can be performed by at least one of a plurality of sub-circuits SUB_C.

[0128] On the other hand, the controller 10 and the multiple sub-circuits SUB_C and processor PROC included in the controller 10 can be implemented in various ways.

[0129] For example, controller 10 can be Figure 1 The memory controller 120 is described in the document. Additionally, the processor PROC can be... Figure 1 The processor 124 described herein. Additionally, each of the plurality of sub-circuits SUB_C can be Figure 1 The host interface 121, memory interface 122, working memory 125, error detection / correction circuit 126, or other hardware modules described herein.

[0130] For example, controller 10 can be a SoC (System-on-a-Chip). Additionally, processor PROC can be a microprocessor included within the SoC. Furthermore, multiple sub-circuit SUB_C can include one or more IP (Intellectual Property) blocks within the SoC.

[0131] In the following text, reference will be made to Figure 5 The flowchart describes in detail the operations performed by the controller 10 in the embodiments of this disclosure.

[0132] Figure 5 This is a flowchart illustrating the schematic operation of the controller 10 based on an embodiment of the disclosed technology.

[0133] Reference Figure 5 The processor PROC of controller 10 can determine the state of multiple sub-circuits SUB_C at the first point in time (S510).

[0134] In this scenario, the processor PROC can determine the first time point in various ways. For example, the processor PROC can determine the first time point randomly.

[0135] For example, the processor PROC can determine the first time point as the time point after a predetermined time has elapsed since the controller 10 receives the command CMD from the outside of the controller 10. In this case, the first time point can be the time point before the time point when the controller 10 automatically starts operating in low-power mode after receiving the command CMD from the outside of the controller 10.

[0136] The processor PROC can determine whether the activation conditions of the multiple sub-circuits SUB_C are met at the first time point based on the state of the multiple sub-circuits SUB_C determined in step S510 (S520).

[0137] The processor PROC can determine whether the controller 10 operates in active mode or low-power mode at a second time point based on whether the activation conditions of multiple sub-circuits SUB_C are met.

[0138] In this case, the second time point can be a time point after a predetermined time elapsed from the time point when the controller 10 receives the command CMD from outside the controller 10 and uses a current greater than or equal to the set activation current value.

[0139] In this case, the length of the predetermined time can be preset or determined based on information from the command CMD received from outside the controller 10 (e.g., the type of command CMD, or the size of data requested to be read or written by the command CMD). The second time point can occur at the same time as the first time point, or it can occur later than the first time point.

[0140] When controller 10 operates in active mode, this means that the current consumed by controller 10 is greater than or equal to the set active current value. In this case, the performance of controller 10 can be improved, but the power consumption of controller 10 may increase.

[0141] When controller 10 operates in low-power mode, this means that controller 10 consumes less current than the set activation current value. In this case, the power consumption of controller 10 may be reduced, but the performance of the controller may be degraded.

[0142] Specifically, the processor PROC determines whether the activation condition of at least one of the multiple sub-circuits SUB_C is met (S530).

[0143] When it is determined that the activation condition of at least one of the multiple sub-circuits SUB_C is met (S530-Yes), the processor PROC can control the controller 10 to operate in activation mode after the second time point (S540).

[0144] If controller 10 operates in low-power mode when at least one of the multiple sub-circuits SUB_C needs to be activated, the sub-circuit may lack sufficient current to activate. Therefore, the sub-circuit to be activated may malfunction or operate at low power. In this case, the performance of controller 10 may degrade. Specifically, if a new command is received immediately after controller 10 begins operating in low-power mode, controller 10 may need time to switch back to active mode to process the new command, thus potentially degrading its performance.

[0145] Therefore, when at least one of the multiple sub-circuits SUB_C needs to be activated, the controller 10 does not operate in low-power mode, but continues to operate in active mode to prevent performance degradation.

[0146] On the other hand, when it is determined that the activation conditions of all multiple sub-circuits SUB_C are not met, the processor PROC can control the controller 10 to operate in low-power mode after the second time point (S550).

[0147] This is because if controller 10 operates in active mode, even when none of the multiple sub-circuits SUB_C need to be activated, controller 10 may consume more power than is required for operation.

[0148] Therefore, when none of the multiple sub-circuits SUB_C need to be activated, the controller 10 can prevent unnecessary power consumption by operating in a low-power mode.

[0149] In this way, the processor PROC can prevent unnecessary power consumption of the controller 10 or avoid performance degradation of the controller 10 based on the state of multiple sub-circuits SUB_C.

[0150] In the following text, Figure 6 and Figure 7 The description is of the changes in the amount of current used by controller 10.

[0151] Figure 6 This is a diagram illustrating an example of the variation in the amount of current used by controller 10.

[0152] Reference Figure 6 The controller 10 can operate in a state using a current greater than or equal to the activation current value ACTIVE_C and in a state using a low power current value LOW_C.

[0153] In the following description, when controller 10 receives command CMD_1 from an external source, controller 10 can operate in an active mode using a current greater than or equal to the activation current value ACTIVE_C to process command CMD_1. Controller 10 can maintain this active mode operation for a predetermined time T, starting from the point when the consumed current reaches a value greater than or equal to the activation current value ACTIVE_C. The predetermined time T can correspond to the amount of time required to process command CMD_1 using a current greater than or equal to the activation current value ACTIVE_C.

[0154] In the following text, controller 10 reduces the current consumed by controller 10 from the active current value ACTIVE_C to the low power current value LOW_C in order to reduce power consumption.

[0155] In this scenario, controller 10 can receive a new command CMD_2 from outside the controller while reducing the current consumption from the active current value ACTIVE_C to the low power current value LOW_C. Controller 10 then needs to increase the current consumption again to be greater than or equal to the active current value ACTIVE_C to process the new command CMD_2.

[0156] As mentioned above, because the controller 10 needs time to increase the current consumption for processing the new command CMD_2 back to be greater than or equal to the activation current value ACTIVE_C, there may be a time delay in the controller 10 processing the new command CMD_2.

[0157] Figure 7 This is a diagram illustrating another example of the variation in the amount of current used by the controller 10 based on an embodiment of the disclosed technology.

[0158] Reference Figure 7 Similar to Figure 6The controller 10 can operate in a state where it consumes a current greater than or equal to the activation current value ACTIVE_C and then consumes a low power current value LOW_C lower than the activation current value ACTIVE_C.

[0159] In the following description, when controller 10 receives command CMD_1 from an external source, controller 10 can operate in an active mode that consumes a current greater than or equal to the activation current value ACTIVE_C to process command CMD_1. Controller 10 can maintain this active mode operation for a predetermined time T, starting from the point when the consumed current reaches a value equal to or greater than the activation current value ACTIVE_C. The predetermined time T can correspond to the amount of time required to process command CMD_1 using a current greater than or equal to the activation current value ACTIVE_C.

[0160] Then, controller 10 can continue to operate in activation mode using a current greater than or equal to the activation current value ACITVE_C, instead of as Figure 6 In this way, the amount of current to be used is reduced from the active current value ACTIVE_C to the low power current value LOW_C. For example... Figure 5 As described above, when it is determined that the activation condition of at least one of the plurality of sub-circuits SUB_C included in the controller 10 is satisfied, the controller 10 can operate as described above.

[0161] In this scenario, when controller 10 receives a new command CMD_2 from an external source, controller 10 can process the new command CMD_2 without increasing the consumed current to be higher than or equal to the activation current value ACTIVE_C. This resolves the time delay issue in controller 10's processing of the new command CMD_2.

[0162] The controller 10 has been described above as operating in active mode or low-power mode based on the states of multiple sub-circuits SUB_C.

[0163] The following text will describe specific examples of the multiple sub-circuits SUB_C mentioned above, and will describe the operations for determining whether the activation conditions of each of the examples are met.

[0164] Figure 8 This is a diagram illustrating a processing unit PU as an example of a sub-circuit SUB_C based on an embodiment of the disclosed technology.

[0165] Reference Figure 8One of the multiple sub-circuits SUB_C is a processing unit PU capable of performing logical operations. The processing unit PU can execute logical operations for processing specific operations, either upon request from the processor PROC or independently. The processing unit PU can be a microprocessor, a processing core, or a hardware module including a microprocessor or a processing core capable of performing logical operations.

[0166] Figure 9 This shows that controller 10 determines whether the condition is met. Figure 8 The flowchart shows an example of the operation of the activation conditions of the processing unit PU.

[0167] Reference Figure 9 The processor PROC of the controller 10 determines whether the processing unit PU performs a logical operation at the first time point (S910).

[0168] When it is determined that the processing unit PU is performing a logic operation (S910 - Yes), the processor PROC determines that the activation condition of the processing unit PU is met (S920). This is because sufficient current needs to be supplied to the processing unit PU so that the processing unit PU can quickly complete the logic operation being executed.

[0169] On the other hand, when it is determined that the processing unit PU is not performing a logical operation (e.g., in a sleep state) (S910 - No), the processor PROC determines that the activation condition of the processing unit PU is not met (S930).

[0170] Figure 10 It is shown Figure 8 A diagram illustrating an example of the operation of the processing unit PU.

[0171] Reference Figure 10 The processing unit PU can perform logical operations to transfer commands CMD or data DATA received from the outside of the controller 10 to the processor PROC.

[0172] For example, when controller 10 is Figure 1 When the memory controller 120 is shown, the processing unit PU can be either the host interface 121 or the memory interface 122.

[0173] Figure 11 This is a diagram illustrating a sequential information reading circuit CLSE, which is an example of a sub-circuit SUB_C, based on an embodiment of the disclosed technology.

[0174] Reference Figure 11 One of the multiple sub-circuits SUB_C is a sequential read information circuit CLSE that stores information about a logical address region that has been requested to be read sequentially from the logical address region by a command CMD received from outside the controller 10.

[0175] exist Figure 11 In this process, the controller 10 can receive a command CMD requesting a sequential read of a logical address region (e.g., 0x00000 to 0x40000). The processor PROC of the controller 10 can sequentially read the data corresponding to the logical address region requested by the command CMD.

[0176] In this case, the sequential read information circuit CLSE can store information about the logical address region LA_INFO. For example, the sequential read information circuit CLSE can store the starting address START (e.g., 0x00000) and the length LEN of the logical address region (e.g., 0x40000 - 0x00000 = 0x40000).

[0177] For example, the processor PROC can determine whether a sequential read operation is being performed on a logical address region that has been requested for sequential read by the command CMD, based on the information LA_INFO stored in the sequential read information circuit CLSE.

[0178] For example, if the processor PROC is currently performing a read operation on logical address 0x12345, then because logical address 0x12345 is included in the logical address range 0x00000 to 0x40000 that the command CMD has requested to read, the processor PROC can determine that it is performing a sequential read operation on the logical address range that the command CMD has requested to read sequentially.

[0179] Figure 12 This shows that controller 10 determines whether the condition is met. Figure 11 The flowchart shows an example of the operation of the activation condition of the sequential information reading circuit CLSE.

[0180] Reference Figure 12 The processor PROC of controller 10 determines whether a sequential read operation is being performed on a logical address region that was requested to be read sequentially by command CMD at the first time point (S1210).

[0181] When a sequential read operation targeting a logical address region is being performed (S1210 - Yes), the processor PROC determines that the activation condition of the sequential read information circuit CLSE is met (S1220). This is because the controller 10 needs to operate in active mode to complete the sequential read operation targeting the logical address region.

[0182] On the other hand, when a sequential read operation for a logical address region is not performed (S1210 - No), the processor PROC determines that the activation condition of the sequential read information circuit CLSE is not met (S1230).

[0183] Figure 13 This is a diagram illustrating a vector search circuit VSE, as an example of a sub-circuit SUB_C, based on an embodiment of the disclosed technology.

[0184] Reference Figure 13 One of the multiple sub-circuits SUB_C can be a vector search circuit VSE that searches for the physical address PA of the logical address LA corresponding to the command CMD.

[0185] In this case, the command CMD received by the controller 10 from outside the controller 10 can be a read command or a write command.

[0186] For example, the vector search circuit VSE can search for the physical address PA corresponding to the logical address LA that corresponds to the command CMD, which requests to read or write.

[0187] Although already Figure 13 The example described above illustrates the case where the vector table VEC_TBL is stored within the vector search circuit VSE. However, the vector table VEC_TBL can also be stored outside the vector search circuit VSE. In this case, the vector search circuit VSE can access the externally stored vector table VEC_TBL or load the vector table VEC_TBL into the vector search circuit VSE.

[0188] For example, the vector table VEC_TBL may include one or more vector table entries VEC_ENT. Each vector table entry VEC_ENT may indicate a physical address mapped to a logical address or may indicate a contiguous range of physical addresses corresponding to a range of logical addresses.

[0189] For example, when the processor PROC requests the physical address (or physical address range) corresponding to a specific logical address from the vector search circuit VSE, the vector search circuit VSE transmits the information of the physical address (or physical address range) corresponding to the logical address to the processor PROC.

[0190] If a logical address for a read operation is received, the Vector Search circuit (VSE) can transmit information about the physical address corresponding to the logical address, as well as information indicating the size of the contiguous physical address region including the corresponding physical address, to the processor (PROC).

[0191] Upon receiving a logical address for which a write operation is to be performed, the Vector Search circuit (VSE) can transmit the position (offset) of the vector table entry VEC_ENT corresponding to the logical address in the vector table VEC_TBL to the processor PROC to indicate the physical address corresponding to the logical address.

[0192] Figure 14 This shows that controller 10 determines whether the condition is met. Figure 13 The flowchart shows an example of the operation of the activation condition of the vector search circuit VSE.

[0193] Reference Figure 14 The processor PROC of controller 10 determines whether the vector search circuit VSE performs an operation to search for a physical address for a specific logical address at the first time point (S1410).

[0194] When the vector search circuit VSE is searching for a physical address for a specific logical address (S1410 - Yes), the processor PROC determines that the activation condition of the vector search circuit is met (S1420).

[0195] On the other hand, when the vector search circuit VSE does not search for a physical address for a specific logical address (S1410 - No), the processor PROC determines that the activation condition of the vector search circuit is not met (S1430).

[0196] Figure 15 This is a diagram illustrating a mapping table search circuit MTSE, which is an example of a sub-circuit SUB_C, based on an embodiment of the disclosed technology.

[0197] Reference Figure 15 One of the multiple sub-circuits is the Map Table Search Circuit (MTSE), which is used to search the Map Cache entry MC_ENT in the Map Cache that corresponds to a specific logical address LA.

[0198] The MAP_CACHE cache can cache one or more MAP_ENT entries, and each MAP_ENT entry can store information about a specific logical address and the physical address mapped to that specific logical address.

[0199] exist Figure 15 In this context, the mapping cache MAP_CACHE is located outside the processor PROC and multiple sub-circuits SUB_C, but it can also be included in the processor PROC and / or one of the multiple sub-circuits SUB_C.

[0200] When the Map Table Searching (MTSE) circuit receives a search request for logical address LA from the processor PROC, the MTSE searches the MAP_CACHE for the corresponding cache entry MC_ENT. Then, the MTSE indicates to the processor PROC whether the cache entry MC_ENT corresponding to logical address LA has been successfully found in the MAP_CACHE (a cache hit has occurred).

[0201] If the search is successful (i.e., a cache hit occurs at logical address LA), the Map Table Search Circuit (MTSE) can transmit information about the mapped cache entry MC_ENT or information about the physical address corresponding to the mapped cache entry MC_ENT to the processor PROC. Conversely, if the search fails (i.e., a cache miss occurs at logical address LA), the MTSE can transmit information indicating the search failure to the processor PROC.

[0202] Figure 16 This shows that controller 10 determines whether the condition is met. Figure 15 The flowchart shows an example of the operation of the activation condition of the mapping table search circuit.

[0203] Reference Figure 16 The processor PROC of controller 10 determines whether the mapping table search circuit MTSE performs the operation of searching the mapping cache entry MC_ENT in the mapping cache MAP_CACHE corresponding to a specific logical address at the first time point (S1610).

[0204] When the Map Table Search circuit MTSE is searching the Map Cache entry MC_ENT in the Map Cache MAP_CACHE for a specific logical address (S1610 - Yes), the processor PROC determines that the activation condition of the Map Table Search circuit MTSE is met (S1620).

[0205] When the Map Table Search Circuit (MTSE) fails to search for the Map Cache entry MC_ENT corresponding to a specific logical address in the Map Cache (MAP_CACHE) (S1610 - No), the processor PROC determines that the activation condition of the Map Table Search Circuit (MTSE) is not met (S1630).

[0206] Figure 17 This is a diagram illustrating a command queue storage circuit CQE, as an example of a sub-circuit SUB_C, based on an embodiment of the disclosed technology.

[0207] Reference Figure 17One of the multiple sub-circuits SUB_C can be a command queue storage circuit CQE that stores a command queue CMD_QUEUE for queuing commands received from outside the controller 10.

[0208] For example, the command queue storage circuit (CQE) can be a volatile memory (e.g., SRAM, DRAM) capable of storing data. When controller 10 is Figure 1 When the memory controller 120 is described, the command queue storage circuit CQE can be the working memory 125.

[0209] The processor PROC can dequeue the command CMD from the command queue CMD_QUEUE and execute the dequeued command CMD.

[0210] In this scenario, some of the commands queued in the command queue CMD_QUEUE may be commands indicating operations to be performed in the idle state. For example, commands indicating operations to be performed in the idle state may be commands indicating the execution of background operations (e.g., garbage collection, wear leveling, read recycling) in the idle state. Controller 10 may perform operations in a low-power mode during the idle state.

[0211] On the other hand, some of the commands CMD queued in the command queue CMD_QUEUE may be commands indicating urgent operations (e.g., urgent garbage collection). Controller 10 should process commands indicating urgent operations with a higher priority than other commands. For example, whether a received command is a command indicating an urgent operation can be determined by ID information indicating the level of the corresponding command to be processed (e.g., 0: normal priority, 1: higher priority, 2: lower priority, 3: urgent).

[0212] On the other hand, some of the commands queued in the command queue CMD_QUEUE may be commands that instruct operations to be performed on modules located outside the controller 10 (e.g., the host's memory buffer) (e.g., loading the mapping information between logical addresses and physical addresses stored in the controller 10 into the host's memory buffer).

[0213] After the controller 10 has completed processing the corresponding command, it is expected that the probability of receiving a new command from outside the controller 10 is temporarily low.

[0214] In embodiments of this disclosure, the controller 10 determines whether the activation conditions of the command queue storage circuit CQE are met based on the commands queued in the command queue storage circuit CQE.

[0215] Figure 18 This shows that controller 10 determines whether the condition is met. Figure 17The flowchart shows an example of the operation of the activation condition of the command queue storage circuit (CQE).

[0216] Reference Figure 18 The processor PROC of controller 10 determines whether at least one command, other than the command used to indicate the operation to be performed in the idle state, is queued in the command queue CMD_QUEUE at the first time point (S1810).

[0217] When at least one command other than the command used to indicate the operation to be performed in the idle state is queued in the command queue CMD_QUEUE (S1810 - Yes), the processor PROC determines that the activation condition of the command queue storage circuit CQE is met (S1820).

[0218] When no commands are queued in the command queue CMD_QUEUE except for commands indicating operations to be performed in the idle state (S1810 - No), the processor PROC determines that the activation condition of the command queue storage circuit CQE is not met (S1830). This is because if the command queue CMD_QUEUE is empty, there is no need to activate the command queue storage circuit CQE, and commands indicating operations to be performed in the idle state can be executed in low-power mode.

[0219] Figure 19 This is a diagram illustrating a buffer storage circuit BUFC, which is an example of a sub-circuit SUB_C based on an embodiment of the disclosed technology.

[0220] Reference Figure 19 One of the multiple sub-circuits SUB_C can be the buffer storage circuit BUFC of the storage buffer BUF.

[0221] For example, the buffer storage circuit BUFC can be a volatile memory (e.g., SRAM, DRAM) capable of storing data. When controller 10 is Figure 1 When the memory controller 120 is described, the buffer storage circuit BUFC can be the working memory 125.

[0222] In this case, the buffer BUF can store data, and the data can be read or written.

[0223] Figure 20 This shows that controller 10 determines whether the condition is met. Figure 19 The flowchart shows an example of the operation of the activation condition of the buffer storage circuit BUFC.

[0224] Reference Figure 20 The processor PROC of controller 10 determines whether read or written data is stored in buffer BUF at the first time point (S2010).

[0225] When data is read or written and stored in the buffer BUF (S2010 - Yes), the processor PROC determines that the activation condition of the buffer storage circuit BUFC is met (S2020). This is because there is a high probability that a clearing operation will be performed on the data stored in the buffer BUF.

[0226] When neither read nor write data is stored in the buffer BUF (S2010 - No), the processor PROC determines that the activation condition of the buffer storage circuit BUFC is not met (S2030).

[0227] Figure 21 This is a diagram illustrating a method of operating the controller 10 based on an embodiment of the disclosed technology.

[0228] Reference Figure 21 The method for operating the controller 10 may include: determining the state of a plurality of sub-circuits SUB_C (S2110).

[0229] Furthermore, the method for operating the controller 10 may include: determining whether the activation conditions of the multiple sub-circuits SUB_C are met at a first time point (S2120).

[0230] For example, one of the multiple sub-circuits SUB_C is a processing unit PU capable of performing logic operations.

[0231] In this case, when the processing unit PU performs a logic operation at the first time point, operation S2120 can determine that the activation condition of the processing unit PU is met.

[0232] For example, one of the multiple sub-circuits SUB_C is the sequential read information circuit CLSE, which stores information about the logical address regions that the command has requested to be read sequentially.

[0233] In this case, when a sequential read operation is performed on the logical address region at the first time point, operation S2120 can determine that the activation condition of the sequential read information circuit CLSE is met.

[0234] For example, one of the multiple sub-circuits SUB_C is a vector search circuit VSE that searches for physical addresses that correspond to logical addresses received from outside the controller 10.

[0235] In this case, when the vector search circuit VSE searches for the physical address of a specific logical address at the first time point, operation S2120 can determine that the activation condition of the vector search circuit VSE is met.

[0236] For example, one of the multiple sub-circuits SUB_C is the Map Table Search Circuit (MTSE) that searches the Map Cache Entry MC_ENT in the Map Cache corresponding to a specific logical address. The Map Cache MAP_CACHE contains the Map Cache Entry MC_ENT, which contains mapping information between logical addresses and physical addresses.

[0237] In this case, when the mapping table search circuit MTSE searches for the mapping cache entry MC_ENT in the mapping cache MAP_CACHE corresponding to a specific logical address at the first time point, operation S2120 can determine that the activation condition of the mapping table search circuit MTSE is met.

[0238] For example, one of the multiple sub-circuits SUB_C is a command queue storage circuit CQE that stores a command queue CMD_QUEUE for queuing commands received from outside the controller 10.

[0239] In this case, when at least one command other than the command used to indicate the operation to be performed in the idle state is queued in the command queue CMD_QUEUE at the first time point, S2120 can determine that the activation condition of the command queue storage circuit CQE is met.

[0240] For example, one of the multiple sub-circuits SUB_C is the buffer storage circuit BUFC of the storage buffer BUF, which stores data for reading or writing.

[0241] In this case, when data is read or written and stored in the buffer BUF at the first time point, S2120 can determine that the activation condition of the buffer storage circuit BUFC is met.

[0242] The method for operating the controller 10 may include: operating in an active mode or a low-power mode at a second time point, depending on whether the activation conditions of multiple sub-circuits are met (S2130).

[0243] The second time point can be a predetermined time point after receiving a command from outside the controller 10, starting from the time point when a current greater than the activation current value is used.

[0244] The activation mode is a mode that uses a current greater than or equal to the activation current value, while the low-power mode is a mode that uses a current lower than the activation current value.

[0245] In embodiments of this disclosure, when it is determined that the activation conditions of at least one of the plurality of sub-circuits SUB_C are satisfied, operation S2130 may operate in an activation mode after a second time point. When it is determined that the activation conditions of all the plurality of sub-circuits are not satisfied, operation S2130 may operate in a low-power mode after the second time point. The plurality of sub-circuits may refer to some or all of the sub-circuits implemented in the controller.

[0246] Figure 22 This is a diagram illustrating the configuration of a computing system 2200 based on an embodiment of the disclosed technology.

[0247] Reference Figure 22 The computing system 2200 based on the disclosed technology may include: a memory system 100 electrically connected to a system bus 2260; a CPU 2210 configured to control all operations of the computing system 2200; RAM 2220 configured to store data and information related to the operation of the computing system 2200; a user interface / user experience (UI / UX) module 2230 configured to provide a user environment to a user; a communication module 2240 configured to communicate with external devices in wired and / or wireless manner; and a power management module 2250 configured to manage the power used by the computing system 2200.

[0248] The computing system 2200 may be a personal computer (PC) or may include a mobile terminal such as a smartphone, tablet computer or various electronic devices.

[0249] The computing system 2200 may further include a battery for supplying operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and DRAM. Other components will be apparent to those skilled in the art.

[0250] The memory system 100 may include not only devices such as hard disk drives (HDDs) configured to store data on disks, but also devices such as solid-state drives (SSDs), general-purpose flash memory devices, or embedded MMC (eMMC) devices configured to store data in non-volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Furthermore, the memory system 100 can be implemented as various types of storage devices and installed inside various electronic devices.

[0251] Based on the exemplary embodiments of the disclosed technology described above, the operation latency of the memory system can be advantageously reduced or minimized. Furthermore, based on the embodiments of the disclosed technology, the overhead incurred in processes that invoke specific functions can be advantageously reduced or minimized. While various embodiments of the disclosed technology have been described in particular detail and with varying degrees of detail for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made based on what is disclosed or shown in this disclosure and the appended claims without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A controller, comprising: Multiple sub-circuits; as well as Processor, the processor: In response to receiving a command from an external source, the controller is controlled to operate in an activation mode, which causes the controller to use a current value greater than or equal to the activation current value. During the activation mode, it is determined whether the activation conditions of the plurality of sub-circuits are met, each of the activation conditions indicating whether the corresponding sub-circuit requires a current value greater than or equal to the activation current value; and When the activation conditions of all the plurality of sub-circuits are not met and a predetermined time has elapsed since the start of the activation mode, the controller is controlled to operate in a low-power mode, which causes the controller to use a current value lower than the activation current value.

2. The controller according to claim 1, The processor determines whether the activation conditions of the plurality of sub-circuits are met at a first time point, and The processor controls the controller to operate in an active mode or a low-power mode at a second time point. The second time point is the time point after a predetermined time has elapsed since the command received from outside the controller was processed using a current greater than or equal to the activation current value. The first time point is the point in time after a predetermined time has elapsed since the controller received the command from an external source. The second time point is determined based on the information in the command.

3. The controller according to claim 2, One of the plurality of sub-circuits is a processing unit capable of performing logic operations, and When the processing unit performs the logical operation at the first time point, the processor determines that the activation condition of the processing unit is met.

4. The controller according to claim 3, The logical operation described therein involves transmitting external commands or data received from outside the controller to the processor.

5. The controller according to claim 2, One of the plurality of sub-circuits is a sequential read information circuit that stores information about a logical address region, on which the command has requested a sequential read operation. When the sequential read operation targeting the logical address region is performed at the first time point, the processor determines that the activation condition of the sequential read information circuit is met.

6. The controller according to claim 2, One of the plurality of sub-circuits is a vector search circuit, which searches for a physical address mapped to the logical address corresponding to the command. When the vector search circuit searches for a physical address for a specific logical address at the first time point, the processor determines that the activation condition of the vector search circuit is met.

7. The controller according to claim 2, One of the plurality of sub-circuits is a mapping table search circuit, which searches the mapping cache entry in the mapping cache corresponding to a specific logical address. The mapping cache entry contains mapping information between logical addresses and physical addresses. When the mapping table search circuit searches for the mapping cache entry corresponding to the specific logical address in the mapping cache at the first time point, the processor determines that the activation condition of the mapping table search circuit is met.

8. The controller according to claim 2, One of the plurality of sub-circuits is a command queue storage circuit, which stores a command queue that queues commands received from outside the controller. When at least one command, other than the command indicating an operation to be performed in the idle state, is queued in the command queue at the first time point, the processor determines that the activation condition of the command queue storage circuit is met.

9. The controller according to claim 2, One of the plurality of sub-circuits is a buffer storage circuit, which stores a buffer that stores read or write data. When data is read or written and stored in the buffer at a first time point, the processor determines that the activation condition of the buffer storage circuit is met.

10. A method of operating a controller, comprising: In response to receiving a command from an external source, the controller is controlled to operate in an activation mode, which causes the controller to use a current value greater than or equal to the activation current value. During the activation mode, it is determined whether the activation conditions of a plurality of sub-circuits included in the controller are met, each of the activation conditions indicating whether the corresponding sub-circuit requires a current value greater than or equal to the activation current value; and When the activation conditions of all the plurality of sub-circuits are not met and a predetermined time has elapsed since the start of the activation mode, the controller is controlled to operate in a low-power mode, which causes the controller to use a current value lower than the activation current value.

11. The method according to claim 10, This involves determining whether the activation conditions of the multiple sub-circuits are met at the first time point, and The controller is controlled to operate in the active mode or the low-power mode at a second time point. The second time point is the time point after a predetermined time has elapsed since the command received from outside the controller was processed using a current greater than or equal to the activation current value. The first time point is the point in time after a predetermined time has elapsed since the controller received the command from an external source. The second time point is determined based on the information in the command.

12. The method according to claim 11, One of the plurality of sub-circuits is a processing unit capable of performing logic operations, and When the processing unit performs the logical operation at the first time point, the activation condition of the processing unit is satisfied.

13. The method according to claim 12, The logic operation described therein is used to transmit external commands or data received from outside the controller.

14. The method according to claim 11, One of the plurality of sub-circuits is a sequential read information circuit that stores information about a logical address region, and the command has requested a sequential read operation on the logical address region. When the sequential read operation targeting the logical address region is performed at the first time point, the activation condition of the sequential read information circuit is satisfied.

15. The method according to claim 11, One of the plurality of sub-circuits is a vector search circuit, which searches for a physical address mapped to the logical address corresponding to the command. When the vector search circuit searches for a physical address for a specific logical address at the first time point, the activation condition of the vector search circuit is met.

16. The method according to claim 11, One of the plurality of sub-circuits is a mapping table search circuit, which searches the mapping cache entry in the mapping cache corresponding to a specific logical address. The mapping cache entry contains mapping information between logical addresses and physical addresses. When the mapping table search circuit searches for the mapping cache entry corresponding to the specific logical address in the mapping cache at the first time point, the activation condition of the mapping table search circuit is satisfied.

17. The method according to claim 11, One of the plurality of sub-circuits is a command queue storage circuit, which stores a command queue that queues commands received from outside the controller. The activation condition of the command queue storage circuit is satisfied when at least one command, other than the command indicating an operation to be performed in the idle state, is queued in the command queue at the first time point.

18. The method according to claim 11, One of the plurality of sub-circuits is a buffer storage circuit, which stores a buffer that stores read or write data. The activation condition of the buffer storage circuit is met when data is read or written and stored in the buffer at the first time point.

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