A first-in-first-out memory, a method for reading and writing data, a device and a medium

Abstract

The application discloses a first-in first-out memory, a data reading and writing method and device and medium, and relates to the field of memories. In the first-in first-out memory, a first cache module is added, so that the first-in first-out memory has high performance; when input data is written, the first cache module is written preferentially. Only when the module is full, data is written into RAM. When data is read, the data is directly read from the first cache module. If the first cache module is not full during reading, data is read from RAM to fill the idle position of the first cache module, so that the pre-reading function is realized, and the read-write delay is reduced, that is, the read-write delay is reduced while the performance of the first-in first-out memory is improved. In addition, the application also provides a data reading and writing method and device and computer readable storage medium, and the effects are the same.

Description

Technical Field

[0001] This application relates to the field of memory, and in particular to a first-in-first-out memory, a method, apparatus and medium for reading and writing data. Background Technology

[0002] First-In-First-Out (FIFO) memory is a type of system cache. The data that is first stored in the FIFO is the first to be read out. It has wide applications in modern integrated circuit systems, System-on-Chips (SoCs), and Field-Programmable Gate Arrays (FPGAs).

[0003] Currently, the input port of a FIFO is directly connected to Random Access Memory (RAM), while the output port is directly connected to the output buffer. This means that when data is input, it must first be stored in RAM. Only after the data is in RAM is a read request initiated, and the data is read and sent to the output buffer on the second clock cycle after the read enable is active. This artificially increases read / write latency when the data volume is small.

[0004] Therefore, improving FIFO performance while reducing read / write latency to adapt to sensitive application scenarios is a technical problem that urgently needs to be solved by those in this field. Summary of the Invention

[0005] The purpose of this application is to provide a first-in-first-out (FIFO) memory, a method, apparatus, and medium for reading and writing data, which can reduce read and write latency while improving FIFO performance to adapt to sensitive application scenarios.

[0006] To address the aforementioned technical problems, this application provides a first-in-first-out (FIFO) memory, comprising: RAM, and further comprising: a data write selection module, a data read control module, a level 1 cache module, and a cache counter module;

[0007] The data write selection module is connected to the cache counting module, the RAM, and the first-level cache module, respectively. It is used to determine the first state of the first-level cache module based on the cache counting module. If the first state is not full, it determines to write data to the first-level cache module; if the first state is full, it determines to write the data to the RAM.

[0008] The data read control module is connected to the cache counter module, the RAM, and the first-level cache module, respectively. It is used to determine the second state of the first-level cache module according to the cache counter module. When the second state is full, it reads the data from the first-level cache module; when the second state is not full, it reads the data from the RAM, stores the data read from the RAM into the first-level cache module, and reads the data from the first-level cache module.

[0009] Preferably, it further includes: a secondary cache module;

[0010] The secondary cache module is connected to the cache counting module, the data write selection module, the data read control module, and the primary cache module, respectively.

[0011] The cache counting module is used to determine the third state of the secondary cache module when the last piece of data has been read from the RAM, and the data is flight data, and there is data being written to the first-in-first-out memory;

[0012] The data write selection module is used to write the data to the secondary cache module when the third state is not full; and to write the data to the RAM when the third state is full.

[0013] The data read control module is configured to, when the data exists in the secondary cache module, read the data from the secondary cache module, store the data read from the secondary cache module in the primary cache module, and read the data from the primary cache module; when the data does not exist in the secondary cache module but exists in the RAM, read the data from the RAM, store the data read from the RAM in the primary cache module, and read the data from the primary cache module.

[0014] Preferably, the cache counting module is used to count the data in the first-level cache module according to the read enable signal and write enable signal of the first-level cache module, the flight data, the read enable signal of the second-level cache module, or the read enable signal of the RAM; to count the data in the second-level cache module according to the read enable signal and write enable signal of the second-level cache module; and to count the data in the RAM according to the read enable signal and write enable signal of the RAM.

[0015] Preferably, the cache counting module is used to count the data in the first-level cache module according to the read enable signal and write enable signal of the first-level cache module, the read enable signal of the second-level cache module, or the read enable signal of the RAM, including:

[0016] The cache counting module is used to obtain a first initial data amount in the first-level cache module; when a write enable signal exists in the first-level cache module, the first initial data amount is incremented by 1 to obtain the first data amount of the first-level cache module; when a read enable signal exists in the second-level cache module or in the RAM, the first data amount is incremented by 1 to obtain the second data amount; when a read enable signal exists in the first-level cache module, the second data amount is decremented by 1 to obtain the third data amount; when the flight data exists, the sum of the third data amount and the flight data amount is obtained as the total data amount in the first-level cache module.

[0017] Preferably, the cache counting module is used to count the data in the secondary cache module according to the read enable signal and write enable signal in the secondary cache module, including:

[0018] The secondary cache module is used to obtain the second initial data amount of the secondary cache module; when a write enable signal exists in the secondary cache module, the second initial data amount is incremented by 1 to obtain the fourth data amount; when a read enable signal exists in the secondary cache module, the fourth data amount is decremented by 1 to obtain the total data amount in the secondary cache module.

[0019] Preferably, the cache counting module is used to count the data in the RAM according to the read enable signal and write enable signal in the RAM, including:

[0020] The cache counting module is used to obtain the third initial data amount of the RAM; when a write enable signal exists in the RAM, the third initial data amount is incremented by 1 to obtain the fifth data amount; when a read enable signal exists in the RAM, the fifth data amount is decremented by 1 to obtain the total data amount in the RAM.

[0021] To address the aforementioned technical problems, this application also provides a method for reading and writing data, applied to a first-in-first-out (FIFO) memory comprising RAM, a data write selection module, a data read control module, a level 1 cache module, and a cache counter module. The data write selection module is connected to the cache counter module, the RAM, and the level 1 cache module, respectively. The data read control module is connected to the cache counter module, the RAM, and the level 1 cache module, respectively. The method includes:

[0022] The first state of the first-level cache module is determined based on the cache counting module;

[0023] When the first state is not full, the data is written to the first-level cache module through the data write selection module; when the first state is full, the data is written to the RAM through the data write selection module.

[0024] The second state of the first-level cache module is determined based on the cache counting module;

[0025] When the second state is full, the data is read from the first-level cache module through the data read control module; when the second state is not full, the data is read from the RAM through the data read control module, the data read from the RAM is stored in the first-level cache module, and the data is read from the first-level cache module.

[0026] Preferably, writing data to the first-level cache module through the data write selection module includes:

[0027] From the moment the first state is determined to be a non-full state, data is written to the first-level cache module through the data write selection module within a first preset time period;

[0028] The step of writing the data into the RAM through the data writing selection module includes:

[0029] Once the first state is determined to be a full state, the data is written to the RAM through the data writing selection module within a second preset time period.

[0030] Preferably, reading the data from the first-level cache module through the data read control module includes:

[0031] If the second state is determined to be full, the data is read from the first-level cache module through the data reading control module within a third preset time period;

[0032] The step of reading the data from the RAM via the data read control module includes:

[0033] If the second state is determined to be a non-full state, the data is read from the RAM by the data reading control module within a fourth preset time period.

[0034] Preferably, after obtaining the first state of the first-level cache module generated by the cache counting module and / or obtaining the second state of the first-level cache module generated by the cache counting module, the method further includes:

[0035] Different prompts are used to indicate the non-full state and the full state.

[0036] Preferably, the method further includes:

[0037] Display the amount of data in the first-level cache module within the cache counting module.

[0038] To address the aforementioned technical problems, this application also provides a data reading and writing device applied to a first-in-first-out (FIFO) memory comprising RAM, a data write selection module, a data read control module, a level 1 cache module, and a cache counter module. The data write selection module is connected to the cache counter module, the RAM, and the level 1 cache module, respectively. The data read control module is connected to the cache counter module, the RAM, and the level 1 cache module, respectively. The device includes:

[0039] The first determining module is used to determine the first state of the first-level cache module based on the cache counting module;

[0040] The write module is used to write data to the first-level cache module through the data write selection module when the first state is not full; and to write the data to the RAM through the data write selection module when the first state is full.

[0041] The second determining module is used to determine the second state of the first-level cache module based on the cache counting module;

[0042] The read module is used to read the data from the first-level cache module through the data read control module when the second state is full; and to read the data from the RAM through the data read control module when the second state is not full, store the data read from the RAM into the first-level cache module, and read the data from the first-level cache module.

[0043] Preferably, the device further includes: a prompting module and a display module;

[0044] The prompting module is used to provide different prompting messages for the non-full state and the full state after obtaining the first state of the first-level cache module generated by the cache counting module and / or obtaining the second state of the first-level cache module generated by the cache counting module;

[0045] The display module is used to display the amount of data in the first-level cache module of the cache counting module.

[0046] To address the aforementioned technical problems, this application also provides a data reading and writing device, comprising:

[0047] Memory, used to store computer programs;

[0048] A processor is configured to implement the steps of the above-described method for reading and writing data when executing the computer program.

[0049] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned method for reading and writing data.

[0050] This application provides a First-In-First-Out (FIFO) memory, comprising: RAM, and further comprising: a data write selection module, a data read control module, a level 1 cache module, and a cache counter module. The data write selection module is connected to the cache counter module, RAM, and level 1 cache module, and is used to determine a first state of the level 1 cache module based on the cache counter module. If the first state is not full, it determines to write data to the level 1 cache module; if the first state is full, it determines to write data to RAM. The data read control module is also connected to the cache counter module, RAM, and level 1 cache module, and is used to determine a second state of the level 1 cache module based on the cache counter module. If the second state is full, it reads data from the level 1 cache module; if the second state is not full, it reads data from RAM, stores the data read from RAM in the level 1 cache module, and reads data from the level 1 cache module. Therefore, by adding a level 1 cache module, this FIFO memory achieves higher performance. When input data is written, it is preferentially written to the level 1 cache module. Data is only written to RAM when this module is full. Data is always read directly from the level 1 cache module. If the L1 cache module is not full during the read process, data is read from RAM to fill the free space in the L1 cache module. This implements the prefetch function and reduces read / write latency. In other words, it reduces read / write latency while improving the performance of the first-in-first-out memory.

[0051] In addition, this application also provides a method, apparatus and medium for reading and writing data, which have the same or corresponding technical features as the aforementioned first-in-first-out memory and have the same effect. Attached Figure Description

[0052] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of a synchronous FIFO implemented based on RAM;

[0054] Figure 2a A schematic diagram of a FIFO under ideal layout and routing conditions;

[0055] Figure 2b A schematic diagram of a FIFO layout under non-ideal conditions;

[0056] Figure 3 This is a diagram of the FIFO structure after adding registers;

[0057] Figure 4 A block diagram illustrating the principle of a FIFO provided in this application embodiment;

[0058] Figure 5 This application provides a timing diagram for normal RAM read / write operations using RAM and a level 1 cache module, as shown in an embodiment.

[0059] Figure 6 This application provides a timing diagram for a specific RAM read / write operation when using RAM, a level 1 cache module, and a level 2 cache module, as an embodiment of the present application.

[0060] Figure 7 A control flowchart for a cache counting module is provided in an embodiment of this application;

[0061] Figure 8 A structural diagram of a data reading and writing device provided in an embodiment of this application;

[0062] Figure 9 A structural diagram of a data reading and writing device provided in another embodiment of this application;

[0063] Figure 10 This application provides a control flowchart for a data writing selection module and a data reading control module. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0065] The core of this application is to provide a first-in-first-out (FIFO) memory, a method, apparatus, and medium for reading and writing data, which can reduce read and write latency while improving FIFO performance to adapt to sensitive application scenarios.

[0066] FIFO (First-In, First-Out) memory is the first to be read from a FIFO. It has significant applications in modern integrated circuit systems, SOCs (System-on-a-Chip), and FPGAs. In previous technologies, FIFOs were based on RAM, with added control logic forming an interconnected network protocol (Internet Protocol, IP). Figure 1 This is a schematic diagram of a synchronous FIFO implemented using RAM. FIFOs are implemented using RAM because, to achieve the same storage capacity, RAM occupies less area than registers, thus saving resources. However, this design introduces another problem: when the chip operates at a high frequency, because the FIFO's control section (read / write enable / control module) and storage section (RAM) are separate, they may be far apart during placement and routing, thus posing a timing risk. Figure 2a A schematic diagram of a FIFO under ideal layout and routing conditions; Figure 2b This diagram illustrates a FIFO with a non-ideal layout. Ideally, the control and storage sections are adjacent, resulting in short signal paths and easy timing convergence. However, in engineering practice, due to various constraints, the control and storage sections of a FIFO are often far apart. This longer signal path makes timing convergence difficult within the FIFO. To address this... Figure 2a To address the timing convergence problem, a register was added to the output port of the control section to disrupt the timing path, such as... Figure 3 As shown, Figure 3 The diagram shows the FIFO structure after adding registers. However, adding registers significantly increases the FIFO's read / write latency, expanding to 5 cycles, which is unacceptable for most applications. It's clear that while registering the RAM input and output signals in the FIFO optimizes timing and improves performance (allowing it to operate at higher frequencies), it also significantly increases read / write latency. Therefore, this application uses a buffer (BUF) as both input and output buffers, referred to as the "Level 1 Buffer Module." When input data is written, it is preferentially written to the "Level 1 Buffer Module." Data is only written to RAM when this module is full. Data is always read directly from the "Level 1 Buffer Module." If the "Level 1 Buffer Module" is not full during the read process, data is actively read from RAM to fill the free space in the "Level 1 Buffer Module," implementing a pre-read function and reducing read / write latency.

[0067] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment provides a first-in, first-out (FIFO) memory, which includes: RAM, and further includes: a data write selection module, a data read control module, a level 1 cache module, and a cache counting module;

[0068] The data write selection module is connected to the cache counter module, RAM, and L1 cache module respectively. It is used to determine the first state of the L1 cache module based on the cache counter module. If the first state is not full, it determines to write data to the L1 cache module; if the first state is full, it determines to write data to RAM.

[0069] The data read control module is connected to the cache counter module, RAM, and L1 cache module respectively. It is used to determine the second state of the L1 cache module based on the cache counter module. When the second state is full, it reads data from the L1 cache module; when the second state is not full, it reads data from RAM, stores the data read from RAM into the L1 cache module, and reads data from the L1 cache module.

[0070] Figure 4 This is a block diagram illustrating the principle of a FIFO (FIFO) system, provided as an embodiment of this application. Figure 4 As shown, the FIFO memory consists of the following parts:

[0071] (1) Cache counting module 101: Collects the read / write enable and flight data counts of RAM, Level 1 cache module, and Level 2 cache module, and converts these signals into counter values ​​such as RAM_COUNT, BUF_COUNT, PRE_BUF_COUNT, and TEMP_BUF_COUNT for use by the data write selection module; where RAM_COUNT indicates how much data is currently in RAM; BUF_COUNT indicates how much data is currently in Level 1 cache module; PRE_BUF_COUNT indicates how much data will be in Level 1 cache module at some point in the future, which is a comprehensive result including the data in BUF_COUNT and flight data; TEMP_BUF_COUNT indicates how much data is currently in Level 2 cache module.

[0072] (2) Data write selection module 102: Based on the empty / full status of the counter generated by the cache counting module, determine which position the currently written data should be placed in;

[0073] (3) Data read control module 103: used to control the read enable of RAM and L2 cache module;

[0074] (4) Register 104: Registers the read enable, write enable and write data of RAM to improve timing and improve FIFO performance (operating frequency);

[0075] (5) RAM 200: Used for storing data, depth is configured by the user;

[0076] (6) Level 1 cache module 201: used to cache written data under normal circumstances. FIFO also only reads data from the level 1 cache module, with a depth of 4.

[0077] (7) Second-level cache module 202: Used to cache data written under special circumstances, with a depth of 4. It should be noted that, for the convenience of timing processing, the FIFO implemented in this embodiment has both cache depths set to 4. In actual use, the cache depth should be able to be further reduced.

[0078] Data written to the FIFO is first cached in the "Level 1 cache module". When the "Level 1 cache module" is full, writing to RAM begins. During reading, data is only read from the "Level 1 cache module". If the "Level 1 cache module" is not full and there is data in RAM, data needs to be read from RAM and stored in the "Level 1 cache module", implementing a read-ahead function.

[0079] It's important to note that the PRE_BUF_COUNT counter is used to determine if the L1 cache is full. This is because the PRE_BUF_COUNT counter contains not only the remaining data in the L1 cache but also the flight data already read from RAM and awaiting writing to the L1 cache. In the worst-case scenario, if the FIFO is not enabled for reading from the current moment, flight data will gradually be written to the L1 cache, causing BUF_COUNT at some future moment to equal the current PRE_BUF_COUNT. Therefore, PRE_BUF_COUNT essentially represents how much data the L1 cache can retain under the slowest reading conditions. Thus, PRE_BUF_COUNT is used to determine whether data is being read from RAM and written to the L1 cache.

[0080] When a read operation begins, data is first read from the L1 cache. Once the L1 cache is read, it becomes partially full, and data is then read from RAM. The first read from RAM requires a two-clock-cycle gap (GAP), specifically the time between data writing and data reading. However, because the L1 cache still contains three clock cycles of data during this gap, this delay is absorbed. The second read from RAM is also continuous because it's enabled consecutively with the first read, eliminating the need for extra data in the cache to absorb the gap, thus allowing for continuous read and write operations to the FIFO. Once the RAM data is completely read, only the data in the L1 cache remains. The L1 cache is then read completely, at which point the FIFO read operation is complete. Figure 5 This is a timing diagram illustrating normal RAM read / write operations using RAM and a level 1 cache module, as provided in an embodiment of this application. For ease of subsequent description, this embodiment can be considered as working scenario one.

[0081] This embodiment provides a First-In-First-Out (FIFO) memory, including RAM, a data write selection module, a data read control module, a level 1 cache module, and a cache counter module. The data write selection module is connected to the cache counter module, RAM, and level 1 cache module, and is used to determine a first state of the level 1 cache module based on the cache counter module. If the first state is not full, it determines to write data to the level 1 cache module; if the first state is full, it determines to write data to RAM. The data read control module is also connected to the cache counter module, RAM, and level 1 cache module, and is used to determine a second state of the level 1 cache module based on the cache counter module. If the second state is full, it reads data from the level 1 cache module; if the second state is not full, it reads data from RAM, stores the data read from RAM in the level 1 cache module, and reads data from the level 1 cache module. Therefore, by adding a level 1 cache module, this FIFO memory achieves higher performance. When input data is written, it is preferentially written to the level 1 cache module. Data is only written to RAM when this module is full. Data is always read directly from the level 1 cache module. If the L1 cache module is not full during the read process, data is read from RAM to fill the free space in the L1 cache module. This implements the prefetch function and reduces read / write latency. In other words, it reduces read / write latency while improving the performance of the first-in-first-out memory.

[0082] Based on the above embodiments, in practice, a FIFO write operation may occur when the last data is read from RAM, and this data is flight data. At this time, the FIFO's wr_data obviously cannot be written to the first-level cache module because earlier data is still en route; wr_data also cannot be written to RAM because it would take 3 cycles to read it after being written to RAM; moreover, subsequent wr_data can only be written to RAM sequentially to maintain order. Writing only requires 1 cycle, but reading requires at least 3 cycles, making reading slow and writing fast. If the port's wr_en and rd_en are consecutive at this time, the RAM data will quickly become unreadable, causing the FIFO to malfunction (Scenario 2). To enable continuous read and write operations, a preferred implementation includes a second-level cache module 202; as described above... Figure 4 As shown,

[0083] The secondary cache module 202 is connected to the cache counting module 101, the data write selection module 102, the data read control module 103, and the primary cache module 201, respectively.

[0084] The cache counting module 101 is used to determine the third state of the secondary cache module 202 when the last data is read from the RAM 200, and the data is flight data, and there is data being written to the first-in-first-out memory.

[0085] The data write selection module 102 is used to write data to the secondary cache module 202 when the third state is not full; and to write data to RAM 200 when the third state is full.

[0086] The data read control module 103 is used to read data from the secondary cache module 202 when data exists in the secondary cache module 202, store the data read from the secondary cache module 202 into the primary cache module 201, and read data from the primary cache module 201; when no data exists in the secondary cache module 202, but data exists in the RAM 200, it reads data from the RAM 200, stores the data read from the RAM 200 into the primary cache module 201, and reads data from the primary cache module 201.

[0087] When the last data is read from RAM and it is flight data, a FIFO write operation occurs. In this case, there is not enough data in the cache, making it difficult to absorb the read / write gap (when the last data in RAM is written to the L1 cache, if the FIFO read is enabled continuously, then the L1 cache often only has one data left). To address this special case, a L2 cache module is added to eliminate the gap by reducing read / write latency.

[0088] When a FIFO write operation occurs after reading the last data from RAM (and this data is flight data), wdata is written to the L2 cache module. If the L2 cache module is full, data continues to be written to RAM. Since RAM was previously empty, the data at this point, if ordered from oldest to newest, is in the following sequence: L1 cache module data > L2 cache module data > RAM data.

[0089] When the Level 1 cache module is not empty and there is no more flight data to be written, the data in the Level 2 cache module is cleared first, and then filled into the Level 1 cache module. Once the Level 2 cache module is empty, data is then read from RAM. During this process, any data to be written is written to RAM. Since the Level 1 and Level 2 cache modules together have a total of 5 cycles of valid data that can be used to absorb RAM read gaps, continuous read and write operations using a FIFO are achieved.

[0090] Once the secondary cache module is cleared, it's equivalent to returning to the first working scenario and resuming normal read and write operations.

[0091] Figure 6 This application provides a timing diagram for reading and writing RAM in a specific manner when using RAM, a level 1 cache module, and a level 2 cache module, as an embodiment of the present application.

[0092] The embodiment provided uses RAM, a level 1 cache module, and a level 2 cache module to ensure continuous read and write operations as much as possible.

[0093] The cache counting module is used to count the data in the first-level cache module, the second-level cache module, and RAM. In a preferred embodiment, the cache counting module is used to count the data in the first-level cache module based on the read enable signal, write enable signal, flight data, read enable signal of the second-level cache module, or read enable signal of RAM; to count the data in the second-level cache module based on the read enable signal and write enable signal of the second-level cache module; and to count the data in RAM based on the read enable signal and write enable signal of RAM.

[0094] Specifically, the cache counting module is used to count the data in the first-level cache module based on the read enable signal, write enable signal of the first-level cache module, read enable signal of the second-level cache module, or read enable signal of RAM, including:

[0095] The cache counting module is used to obtain the first initial data amount in the first-level cache module; when a write enable signal exists in the first-level cache module, the first initial data amount is incremented by 1 to obtain the first data amount of the first-level cache module; when a read enable signal exists in the second-level cache module or in RAM, the first data amount is incremented by 1 to obtain the second data amount; when a read enable signal exists in the first-level cache module, the second data amount is decremented by 1 to obtain the third data amount; when flight data exists, the sum of the third data amount and the flight data amount is taken as the total data amount in the first-level cache module.

[0096] The cache counting module is used to count the data in the L2 cache module based on the read enable signal and write enable signal in the L2 cache module, including:

[0097] The second-level cache module is used to obtain the second initial data amount of the second-level cache module; when a write enable signal exists in the second-level cache module, the second initial data amount is incremented by 1 to obtain the fourth data amount; when a read enable signal exists in the second-level cache module, the fourth data amount is decremented by 1 to obtain the total data amount in the second-level cache module.

[0098] The cache counting module is used to count the data in RAM based on the read enable signal and write enable signal in RAM, including:

[0099] The cache counting module is used to obtain the third initial data amount of RAM; when a write enable signal exists in RAM, the third initial data amount is incremented by 1 to obtain the fifth data amount; when a read enable signal exists in RAM, the fifth data amount is decremented by 1 to obtain the total data amount in RAM.

[0100] Figure 7 This is a control flowchart for a cache counting module provided in an embodiment of this application. Figure 7 As shown, the control flow diagram includes:

[0101] S10: Counting the data in the L1 cache module;

[0102] S11: Counting the data in the L2 cache module;

[0103] S12: Count the data in RAM.

[0104] The cache counting module provided in this embodiment enables relatively accurate counting of data in the first-level cache module, the second-level cache module, and RAM.

[0105] The foregoing describes a first-in-first-out (FIFO) memory. This embodiment also provides a method for reading and writing data, applied to a FIFO memory including RAM, a data write selection module, a data read control module, a level 1 cache module, and a cache counter module. The data write selection module is connected to the cache counter module, RAM, and level 1 cache module, respectively. The data read control module is connected to the cache counter module, RAM, and level 1 cache module, respectively. The method for reading and writing data includes:

[0106] The first state of the first-level cache module is determined based on the cache counting module;

[0107] When the first state is not full, the data is written to the first-level cache module through the data write selection module; when the first state is full, the data is written to RAM through the data write selection module.

[0108] The second state of the first-level cache module is determined based on the cache counting module;

[0109] When the second state is full, data is read from the first-level cache module through the data read control module; when the second state is not full, data is read from RAM through the data read control module, the data read from RAM is stored in the first-level cache module, and data is read from the first-level cache module.

[0110] The data reading and writing method provided in this embodiment has corresponding technical features to the FIFO memory mentioned above. The embodiments of the FIFO memory have been described in detail above, and the embodiments of the data reading and writing method will not be repeated here. It has the same beneficial effects as the FIFO memory mentioned above.

[0111] Based on the above embodiments, in order to reduce read / write latency, a preferred implementation method is to write data to the first-level cache module through the data write selection module, including:

[0112] Once the first state is determined to be a non-full state, the data is written to the first-level cache module through the data writing selection module within the first preset time period.

[0113] Writing data to RAM via the data write selection module includes:

[0114] If the first state is determined to be full, the data is written to RAM through the data write selection module within the second preset time period.

[0115] Reading data from the first-level cache module through the data read control module includes:

[0116] If the second state is determined to be full, data is read from the first-level cache module through the data read control module within the third preset time period;

[0117] Reading data from RAM via the data read control module includes:

[0118] If the second state is determined to be a non-full state, data is read from RAM through the data read control module within the fourth preset time period.

[0119] The first, second, third, and fourth preset durations are not limited and can be determined according to the actual situation. However, in order to reduce read and write latency, it is preferable to set the first, second, third, and fourth preset durations to a smaller value.

[0120] In the method provided in this embodiment, by setting a preset time for reading or writing data, the read / write latency can be reduced as much as possible.

[0121] In practice, to facilitate users' understanding of the cache module's status, a preferred implementation method is that, after obtaining the first state of the first-level cache module generated by the cache counter module and / or obtaining the second state of the first-level cache module generated by the cache counter module, the data reading and writing method further includes:

[0122] Different prompts are used to indicate the non-full state and the full state.

[0123] Methods for reading and writing data also include:

[0124] Display the amount of data in the first-level cache module within the cache counting module.

[0125] There are no restrictions on the method, content, or data volume displayed for the prompts; they can be determined based on the actual situation. By displaying the prompts and data volume, users can intuitively understand the amount of data in the cache module.

[0126] In the above embodiments, the method for reading and writing data has been described in detail. This application also provides embodiments corresponding to the device for reading and writing data. It should be noted that this application describes the embodiments of the device part from two perspectives: one is based on the functional module, and the other is based on the hardware.

[0127] This embodiment provides a device for reading and writing data, applied to a first-in-first-out memory including RAM, a data write selection module, a data read control module, a level 1 cache module, and a cache counter module. The data write selection module is connected to the cache counter module, RAM, and level 1 cache module respectively, and the data read control module is connected to the cache counter module, RAM, and level 1 cache module respectively. Figure 8A structural diagram of a data reading and writing device provided in one embodiment of this application. This embodiment, based on functional modules, includes:

[0128] The first determining module 10 is used to determine the first state of the first-level cache module based on the cache counting module;

[0129] The write module 11 is used to write data to the first-level cache module through the data write selection module when the first state is not full; and to write data to RAM through the data write selection module when the first state is full.

[0130] The second determining module 12 is used to determine the second state of the first-level cache module based on the cache counting module;

[0131] The read module 13 is used to read data from the first-level cache module through the data read control module when the second state is full; and to read data from RAM through the data read control module when the second state is not full, store the data read from RAM into the first-level cache module, and read data from the first-level cache module.

[0132] In addition, the device also includes: a prompting module and a display module;

[0133] The prompting module is used to provide different prompting messages for the non-full state and the full state after obtaining the first state of the first-level cache module generated by the cache counting module and / or obtaining the second state of the first-level cache module generated by the cache counting module;

[0134] The display module is used to display the amount of data in the first-level cache module of the cache counting module.

[0135] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus. They will not be repeated here, but the effect is the same.

[0136] Figure 9 This is a structural diagram of a data reading and writing device provided in another embodiment of this application. This embodiment is based on a hardware perspective, such as... Figure 9 As shown, the device for reading and writing data includes:

[0137] Memory 20 is used to store computer programs;

[0138] The processor 21 is configured to implement the steps of the method for reading and writing data as described in the above embodiments when executing a computer program.

[0139] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from Digital Signal Processors (DSPs), FPGAs, and Programmable Logic Arrays (PLAs). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0140] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the data reading and writing methods disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the aforementioned data reading and writing methods.

[0141] In some embodiments, the device for reading and writing data may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0142] Those skilled in the art will understand that Figure 9 The structure shown does not constitute a limitation on the device for reading and writing data, and may include more or fewer components than shown.

[0143] The device for reading and writing data provided in this application includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: the method for reading and writing data has the same effect as above.

[0144] This application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0145] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0146] The computer-readable storage medium provided in this application includes the aforementioned methods for reading and writing data, with the same effect.

[0147] To enable those skilled in the art to better understand the present application, the following description is provided in conjunction with the appendix. Figure 10 The present application will be further described in detail with reference to specific embodiments. Figure 10 This document provides a control flowchart for a data writing selection module and a data reading control module, as illustrated in an embodiment of this application. Figure 10 As shown, the method includes:

[0148] S13: Determine if write enable is enabled; if yes, proceed to step S14; if no, proceed to step S21.

[0149] S14: Determine if the L1 cache prefetch counter is full; if not, proceed to step S15; if yes, proceed to step S20.

[0150] S15: Determine if there is no flight data; if yes, proceed to step S16; if no, proceed to step S17.

[0151] S16: Write to the first-level cache module;

[0152] S17: Determine if the L2 cache is not empty; if yes, proceed to step S18; otherwise, proceed to step S20.

[0153] S18: Determine if there is flight data and RAM is empty; if yes, proceed to step S19; otherwise, proceed to step S20.

[0154] S19: Write to the second-level cache module;

[0155] S20: Write to RAM cache;

[0156] S21: Determine if there is data in the secondary cache module; if yes, proceed to step S22; if no, proceed to step S23.

[0157] S22: Read data from the second-level cache and write the data to the first-level cache;

[0158] S23: Determine if RAM is not empty; if yes, proceed to step S24; otherwise, end.

[0159] S24: Determine if the L1 cache prefetch counter is not full; if yes, proceed to step S25; otherwise, end.

[0160] S25: Read RAM data and write the data to the first-level cache.

[0161] This application enables continuous read and write operations on the FIFO in both scenario one and scenario two. Furthermore, read operations are performed only through the L1 cache module, resulting in a read latency of only one cycle, the theoretical minimum. When reading from RAM is required, the data in the L1 and L2 cache modules can eliminate the read gap, and the read data is ultimately output to the L1 cache module, awaiting user access. From the user's perspective, the timing behavior of this solution is completely consistent with that of a FIFO built with registers. Moreover, this solution registers all RAM read and write control signals, optimizing timing and thus improving performance (allowing operation at higher frequencies).

[0162] Compared to traditional prefetch FIFOs, this application proposes a dual-buffered FIFO that effectively replaces the functionality of traditional prefetch FIFOs. Its timing and performance are essentially the same as traditional register FIFOs, allowing for seamless user switching. Since both input and output data are stored in the first-level cache module, the latency is only one cycle, offering a significant advantage in latency. Compared to traditional RAM-based FIFO schemes, this scheme registers both RAM read and write control signals, optimizing timing and thus improving performance (allowing operation at higher frequencies).

[0163] Specifically, by registering all RAM chip select, read enable, and write enable signals before use, the timing analysis path is shortened, improving module performance / operating frequency. This application uses two small caches for reading and writing data. Under normal circumstances, only the L1 cache is used to write and read FIFO data, utilizing residual data in the L1 cache to eliminate RAM read gaps. When special timing events occur (RAM is empty, there is flying data, and data is waiting to be written), the L2 cache is used to temporarily replace the L1 cache, and then the L2 cache is cleared to restore normal read / write operation. Under all circumstances, the read / write latency is only one clock cycle. Only a few counters are used to determine the current operating mode of the FIFO, and the empty / full flags of the counters determine the current read / write state of each memory (cache / RAM), eliminating the need for a complex state machine and saving module area.

[0164] In summary, the FIFO proposed in this application can not only effectively replace the traditional prefetch FIFO function, but also has lower output latency, higher operating frequency, and greater versatility compared to existing FIFO solutions.

[0165] The foregoing has provided a detailed description of a first-in-first-out (FIFO) memory, a method for reading and writing data, an apparatus, and a medium provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0166] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A first-in, first-out (FIFO) memory, comprising: The RAM is characterized by further comprising: a data write selection module, a data read control module, a first-level cache module, and a cache counting module; The data write selection module is connected to the cache counting module, the RAM, and the first-level cache module, respectively. It is used to determine the first state of the first-level cache module based on the cache counting module. If the first state is not full, it determines to write data to the first-level cache module; if the first state is full, it determines to write the data to the RAM. The data read control module is connected to the cache counter module, the RAM, and the first-level cache module, respectively. It is used to determine the second state of the first-level cache module according to the cache counter module. When the second state is full, it reads the data from the first-level cache module; when the second state is not full, it reads the data from the RAM, stores the data read from the RAM into the first-level cache module, and reads the data from the first-level cache module. It also includes: a second-level cache module; The secondary cache module is connected to the cache counting module, the data write selection module, the data read control module, and the primary cache module, respectively. The cache counting module is used to count the data in the first-level cache module according to the read enable signal, write enable signal, flight data, read enable signal of the second-level cache module, or read enable signal of the RAM; wherein, the flight data is the data that has been read from the RAM and is to be written to the first-level cache module; Specifically, the cache counting module is used to obtain a first initial data amount in the first-level cache module; when a write enable signal exists in the first-level cache module, the first initial data amount is incremented by 1 to obtain the first data amount of the first-level cache module; when a read enable signal exists in the second-level cache module or in the RAM, the first data amount is incremented by 1 to obtain the second data amount; when a read enable signal exists in the first-level cache module, the second data amount is decremented by 1 to obtain the third data amount; and when the flight data exists, the sum of the third data amount and the flight data amount is obtained as the total data amount in the first-level cache module.

2. The first-in-first-out memory according to claim 1, characterized in that, The cache counting module is used to determine the third state of the secondary cache module when the last piece of data has been read from the RAM, and the data is flight data, and there is data being written to the first-in-first-out memory; The data write selection module is used to write the data to the secondary cache module when the third state is not full. When the third state is a full state, the data is written into the RAM; The data read control module is used to read the data from the secondary cache module when the data exists in the secondary cache module, store the data read from the secondary cache module into the primary cache module, and read the data from the primary cache module. If the data is not present in the secondary cache module but exists in the RAM, the data is read from the RAM, the data read from the RAM is stored in the primary cache module, and the data is read from the primary cache module.

3. The first-in-first-out memory according to claim 2, characterized in that, The cache counting module is used to count the data in the secondary cache module according to the read enable signal and write enable signal in the secondary cache module; and to count the data in the RAM according to the read enable signal and write enable signal in the RAM.

4. The first-in-first-out memory according to claim 3, characterized in that, The cache counting module is used to count the data in the secondary cache module according to the read enable signal and write enable signal in the secondary cache module, including: The secondary cache module is used to obtain the second initial data amount of the secondary cache module; when a write enable signal exists in the secondary cache module, the second initial data amount is incremented by 1 to obtain the fourth data amount; when a read enable signal exists in the secondary cache module, the fourth data amount is decremented by 1 to obtain the total data amount in the secondary cache module.

5. The first-in-first-out memory according to claim 4, characterized in that, The cache counting module is used to count the data in the RAM based on the read enable signal and write enable signal in the RAM, including: The cache counting module is used to obtain the third initial data amount of the RAM; when a write enable signal exists in the RAM, the third initial data amount is incremented by 1 to obtain the fifth data amount; when a read enable signal exists in the RAM, the fifth data amount is decremented by 1 to obtain the total data amount in the RAM.

6. A method for reading and writing data, characterized in that, The method, applied to the first-in-first-out memory according to any one of claims 1 to 5, comprises: The first state of the first-level cache module is determined based on the cache counting module; When the first state is not full, the data is written to the first-level cache module through the data write selection module; when the first state is full, the data is written to the RAM through the data write selection module. The second state of the first-level cache module is determined based on the cache counting module; When the second state is full, the data is read from the first-level cache module through the data read control module; when the second state is not full, the data is read from the RAM through the data read control module, the data read from the RAM is stored in the first-level cache module, and the data is read from the first-level cache module.

7. The method for reading and writing data according to claim 6, characterized in that, The step of writing data to the first-level cache module through the data write selection module includes: From the moment the first state is determined to be a non-full state, data is written to the first-level cache module through the data write selection module within a first preset time period; The step of writing the data into the RAM through the data writing selection module includes: Once the first state is determined to be a full state, the data is written to the RAM through the data writing selection module within a second preset time period.

8. The method for reading and writing data according to claim 7, characterized in that, The step of reading the data from the first-level cache module through the data read control module includes: If the second state is determined to be full, the data is read from the first-level cache module through the data reading control module within a third preset time period; The step of reading the data from the RAM via the data read control module includes: If the second state is determined to be a non-full state, the data is read from the RAM by the data reading control module within a fourth preset time period.

9. The method for reading and writing data according to claim 8, characterized in that, After obtaining the first state of the first-level cache module generated by the cache counting module and / or obtaining the second state of the first-level cache module generated by the cache counting module, the method further includes: Different prompts are used to indicate the non-full state and the full state.

10. The method for reading and writing data according to any one of claims 6 to 9, characterized in that, The method further includes: Display the amount of data in the first-level cache module within the cache counting module.

11. A device for reading and writing data, characterized in that, The device, applied to the first-in-first-out memory according to any one of claims 1 to 5, comprises: The first determining module is used to determine the first state of the first-level cache module based on the cache counting module; The write module is used to write data to the first-level cache module through the data write selection module when the first state is not full; and to write the data to the RAM through the data write selection module when the first state is full. The second determining module is used to determine the second state of the first-level cache module based on the cache counting module; The read module is used to read the data from the first-level cache module through the data read control module when the second state is full; and to read the data from the RAM through the data read control module when the second state is not full, store the data read from the RAM into the first-level cache module, and read the data from the first-level cache module.

12. The data reading and writing apparatus according to claim 11, characterized in that, The device further includes: a prompting module and a display module; The prompting module is used to provide different prompting messages for the non-full state and the full state after obtaining the first state of the first-level cache module generated by the cache counting module and / or obtaining the second state of the first-level cache module generated by the cache counting module; The display module is used to display the amount of data in the first-level cache module of the cache counting module.

13. A device for reading and writing data, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the method for reading and writing data as described in any one of claims 6 to 10 when executing the computer program.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for reading and writing data as described in any one of claims 6 to 10.

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