Coarse-grained reconfigurable array operator design method and system for deep learning

Abstract

This invention provides a method and system for designing coarse-grained reconfigurable array operators for deep learning, relating to the field of deep learning accelerator compiler technology. The method includes: providing at least one operator OP with a preset convolutional kernel size k and a preset sliding stride s. k,s k and s ≥ 1 and are integers; based on operator OP k,s Determine the OP of each operator k，s The number of processing units (PEs) required is determined based on the required PEs to perform row convolution computation, where PE ≥ 1 and is an integer; based on each operator (OP). k，s The required number of processing units (PEs) determines the hardware interconnection structure between the PEs required by the operator, thus forming the operator (OP). k，s Library.

Description

Technical Field

[0001] This invention relates to the field of deep learning accelerator compiler technology, and in particular to the design and implementation of a coarse-grained reconfigurable array operator for deep learning. Background Technology

[0002] In recent years, deep learning has achieved tremendous success in tasks such as computer vision and speech recognition, surpassing human capabilities in both accuracy and speed across a variety of complex tasks. However, the high computational demands and large data volumes inherent in deep learning applications, along with the varying network architectures, place higher demands on the computing power and programmability of chips. Furthermore, with the deployment of deep learning in embedded devices such as the Internet of Things and autonomous driving, chip energy efficiency is also a crucial consideration.

[0003] Energy efficiency and throughput are two crucial metrics for deep learning accelerators. Deep learning involves numerous perfectly nested loops, and previous compiler work focused primarily on loop order and tiling strategies. These factors collectively influence the communication volume between DRAM and on-chip memory, thus determining the overall chip energy efficiency. However, real-time applications such as autonomous driving and object tracking require accelerators to rapidly process massive amounts of image and audio information, placing higher demands on their throughput. Coarse-grained reconfigurable arrays (CGRAs) are gaining increasing attention in deep learning applications. CGRA throughput largely depends on how efficiently the compiler maps applications to the corresponding hardware resources of the CGRA, improving resource utilization, especially computational resources, namely the Process Elements Array (PEA). However, previous CGRA compiler work has rarely addressed the mapping of deep learning applications onto CGRAs. Summary of the Invention

[0004] This invention provides a design method and system for coarse-grained reconfigurable array operators for deep learning, which meets the two important indicators of energy efficiency and throughput for deep learning, and efficiently maps the application to the corresponding hardware resources of CGRA.

[0005] This invention provides a method for designing coarse-grained reconfigurable array operators for deep learning, comprising: providing at least one operator OP having a preset convolutional kernel size k and a preset sliding stride s. k，s k and s ≥ 1 and are integers; based on operator OP k,s Determine the OP of each operator k，sThe number of processing units (PEs) required is determined based on the required PEs for performing row convolution computation, where PE ≥ 1 and is an integer; based on each operator (OP). k，s The required number of processing units (PEs) determines the operator (OP). k，s The hardware interconnection structure between the required processing units (PEs) constitutes the operator (OP). k，s Library.

[0006] According to an embodiment of the present invention, performing row convolution calculation includes: splitting the convolution kernel into i rows, where i ≥ 1 and is an integer; and performing an inner product operation on the weight vector and input vector of each row convolution kernel using a sliding window method based on the required processing unit PE, to obtain the partial sum of each row convolution kernel; wherein, the window sliding includes: sliding on each row convolution kernel with a preset stride s. According to an embodiment of the present invention, performing row convolution calculation further includes: obtaining and accumulating the partial sum of each row convolution kernel to obtain the final output feature image.

[0007] According to an embodiment of the present invention, each operator OP k，s The required number of processing units (PEs) is determined by the following formula:

[0008]

[0009] Among them, PE n Represents each operator OP k，s Number of processing units (PEs) required

[0010] According to an embodiment of the present invention, performing row convolution calculation further includes: obtaining the start interval of adjacent windows when the window slides; when each row convolution kernel is performed in a window sliding manner, the inner product operation is started sequentially according to the start interval, the start interval being determined according to the following formula:

[0011]

[0012] Where II is the startup interval, and PEn is each operator OP. k，s The number of processing units (PEs) required, where Q is the number of multiplications and accumulations in the inner product operation within a single sliding window.

[0013] According to embodiments of the present invention, the hardware interconnection structure between the required processing units (PEs) includes various arrangements such as row arrangement, column arrangement, or L-shaped arrangement.

[0014] According to an embodiment of the present invention, a weight vector for each row of convolutional kernels and a vector of the input feature map are provided; the starting position and data length in the input feature map are obtained, and window sliding and inner product operation are performed based on the starting position and data length.

[0015] According to another embodiment of the present invention, a coarse-grained reconfigurable array operator design system for deep learning, for implementing any of the above embodiments, is provided, comprising: a controller for inputting information to at least one processing unit PE, wherein the input information includes a weight vector, an input vector, a state instruction, and an operation instruction, the state instruction being used to determine the execution state of the operation instruction, and the operation instruction being used by at least one processing unit PE to calculate the inner product of the weight vector and the input vector; an input bus for inputting the weight vector and the input vector to at least one processing unit PE; a configuration bus for inputting the state instruction and the operation instruction to at least one processing unit PE; a processing unit array PEA including a plurality of processing units PE, each processing unit PE being used to perform an inner product operation on the weight vector and the input vector according to the operation instruction to obtain an inner product result; and an output bus for outputting the inner product result to at least one processing unit PE.

[0016] According to another embodiment of the present invention, the processing unit array PEA has M columns and N rows, where M ≥ 1 and is an integer, and N ≥ 1 and is an integer, wherein: each column of processing units PE shares an input bus; each row of processing units PE shares an output bus; and each column of processing units PE shares a configuration bus.

[0017] According to another embodiment of the present invention, the processing unit PE includes: an instruction register subunit for storing operation instructions and status instructions; an instruction decoding subunit for decoding operation instructions and status instructions; a weight register subunit for storing weight vectors or input vectors; a local register subunit for storing intermediate data; and a logic operation subunit for performing an inner product operation on the weight vectors and input vectors according to the operation instructions to obtain the inner product result.

[0018] Compared with existing technologies, the coarse-grained reconfigurable array operator design method for deep learning provided by this invention has at least the following beneficial effects:

[0019] With the goal of maximizing resource utilization, and under the constraints of storage and input / output bandwidth resources, as many identical or different operator implementations as possible are mapped onto a coarse-grained reconfigurable array. Based on row convolution computation, each operator is piped in software under different numbers of processing units (PEs), while the input data requirements of the operators are analyzed under different startup intervals. Furthermore, different operators correspond to different hardware implementations, realizing multiple interconnection structures for PEs. All hardware implementations constitute an operator library, providing a new solution for mapping methods in deep learning applications. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 This is a flowchart illustrating the design of a coarse-grained reconfigurable array operator for deep learning according to an embodiment of the present invention.

[0022] Figure 2a For traditional 3×3 convolution calculation and Figure 2b This is a schematic diagram of row convolution calculation according to an embodiment of the present invention;

[0023] Figure 3a , 3b Operator OP in this embodiment of the invention 3，1 Diagram of inner product operation;

[0024] Figure 4 For the embodiments of the present invention, the operator OP is used when the number of PEs is 2 and 3 respectively. 3，1 A structural diagram of software pipeline implementation;

[0025] Figure 5a , 5b Operator OP in this embodiment of the invention 3，1 Schematic diagram of the interconnection structure between the required processing units (PE);

[0026] Figure 6 Operator OP in this embodiment of the invention 5，1 A partial schematic diagram of the interconnection structure between the required processing units (PE);

[0027] Figure 7 Operator OP in this embodiment of the invention 3，1 exist Figure 5a A schematic diagram of the mapping on (a).

[0028] Figure 8 This is a schematic diagram of a PEA array system according to an embodiment of the present invention;

[0029] Figure 9 This is a schematic diagram of the processing unit PE in an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] This invention proposes a row convolution operator design method with streaming data access characteristics. Different network models correspond to different operators, which can, for example, form an operator set. Simultaneously, based on a coarse-grained reconfigurable array (CGRA), hardware implementation schemes for each operator are provided, forming an operator library. The mapping problem for deep learning applications on CGRA is transformed into: maximizing the utilization of processing elements (PEs), while satisfying storage and input / output bandwidth resource constraints, mapping as many identical or different operator implementations as possible onto the CGRA's processing element array (PEA). This provides a new solution for mapping methods in deep learning applications.

[0034] Figure 1 This is a flowchart illustrating the design process of a coarse-grained reconfigurable array operator for deep learning, as described in an embodiment of the present invention. Figure 7 Operator OP in this embodiment of the invention 3，1 exist Figure 5a A schematic diagram of the mapping on (a).

[0035] Please see Figure 1 and Figure 7 This invention provides a method for designing coarse-grained reconfigurable array operators for deep learning, comprising the following steps S1-S3:

[0036] S1, providing at least one operator OP with a preset convolution kernel size k and a preset sliding stride s. k，s k and s ≥ 1 and are integers.

[0037] S2, based on operator OP k，s Determine the OP of each operator k，s The number of processing units (PEs) required, based on the required PEs to perform row convolution calculations, where PE ≥ 1 and is an integer.

[0038] S3, based on each operator OP k，s The number of processing units (PEs) required and the data transmission characteristics of the PEs determine the operator (OP). k，s The hardware interconnection structure between the required processing units (PEs) constitutes the operator (OP). k，s Library.

[0039] Through the embodiments of the present invention, data streams can be provided row by row based on row convolution computation with streaming data access characteristics to form streaming data.

[0040] Figure 2a For traditional 3×3 convolution calculation and Figure 2b This is a schematic diagram of row convolution calculation according to an embodiment of the present invention.

[0041] For example, please refer to Figure 2a and Figure 2b The embodiments of the present invention provide the operators OP corresponding to the following network models. k，s :

[0042] Operator OP with a convolution kernel size of 3×3 and a stride of 1 3，1 Operator OP with a convolution kernel size of 5×5 and a stride of 1 5，1 Operator OP with a convolution kernel size of 3×3 and a stride of 2 3，2 Operator OP with a convolution kernel size of 5×5 and a stride of 2 5，2 Operator OP with a convolution kernel size of 7×7 and a stride of 2 7，2 These operators OP k，s Constitutes a set of operators, and the above operators OP k，s All require different numbers of processing units (PEs) to participate in the inner product operation.

[0043] In this embodiment of the invention, performing row convolution calculation includes: splitting the convolution kernel into i rows, i≥1 and being an integer; performing an inner product operation on the weight vector and input vector of each row convolution kernel using a window sliding method based on the required processing unit PE, to obtain the partial sum (psum) of each row convolution kernel, wherein the window sliding includes: sliding on each row convolution kernel with a preset stride s.

[0044] Specifically, each row participates in the inner product operation independently, and the convolution kernel of the next row only slides after the convolution kernel of one row has finished sliding.

[0045] Furthermore, performing row convolution calculations also includes: obtaining a partial sum of each row's convolution kernel and accumulating it to obtain the final output feature map (ofmap).

[0046] It should be noted that, except for the first row of convolution kernels, the partial sum psum generated by the subsequent rows of convolution kernels is accumulated with the partial sum psum corresponding to the previous row of convolution kernels. The final output feature image ofmap is obtained after the last row of convolution kernels is calculated.

[0047] Figure 3a , 3bOperator OP in this embodiment of the invention 3，1 A diagram illustrating inner product operations. Figure 4 For the embodiments of the present invention, the operator OP is used when the number of PEs is 2 and 3 respectively. 3，1 A structural diagram of software pipeline.

[0048] Please see Figures 3a-b The ifmap required for the multiply-accumulate operation corresponding to weight a (or a') in the i-th window is the same as the ifmap required for the multiply-accumulate operation corresponding to weight b (or b') in the (i-1)-th window and weight c (or c') in the (i-2)-th window.

[0049] Please see Figure 4 Get the startup interval of adjacent windows when the window is slid.

[0050] When each row of convolution kernels is processed by sliding the window, the inner product operation is initiated sequentially according to the initiation interval, which is determined by the following formula:

[0051]

[0052] Where II is the startup interval, and PEn is each operator OP. k，s The number of processing units (PEs) required, where Q is the number of multiplications and accumulations in the inner product operation within a single sliding window.

[0053] Please see Figure 4 , Figure 4 (A) in the diagram represents the process of adjacent window iteration when there are two processing units (PE). Figure 4 (B) in the diagram represents the process of adjacent window iteration when there are 3 processing units PE.

[0054] The startup interval between adjacent windows varies depending on the number of processing units (PEs). When the number of processing units (PEs) is 2:

[0055] II = 6 / 2 = 3

[0056] It can be seen that II has 3 time steps, where 6 represents the number of operations of the inner product of the convolution kernel within a single row sliding window. When the time step is 3, the calculation of a new window is started every three cycles, and at most two windows are calculated at the same time.

[0057] When the processing unit PE is 3:

[0058] II = 6 / 3 = 2

[0059] It can be seen that II represents 2 time steps, where 6 represents the number of operations of the inner product of the convolution kernel within a single row sliding window. When the time step is 2, the calculation of a new window is started every two cycles, and within this cycle, a maximum of three windows can be calculated simultaneously.

[0060] When the number of PEs is 2, the buffer unit needs to provide two different input data to the PEA in each cycle. Since the interconnect structure between PEs is only used to transmit the calculation results of the PEs, the same data needs to be provided three times in three adjacent cycles. When the number of PEs is 3, the buffer unit only needs to provide one input data to the PEA in each cycle, and this input data is used by all three windows simultaneously, so it does not need to be provided repeatedly. Furthermore, when the operator is in stable pipelined mode, it performs three operations per cycle, and its processing unit PE utilization is 100%. Therefore, from the perspective of input data and PE utilization, the operator operation with 2 input channels is more efficient. 3，1 The optimal implementation has 3 processing units (PEs). Each operator (OP) k，s The required number of processing units (PEs) is determined by the following formula:

[0061]

[0062] Among them, PE n Represents each operator OP k，s The number of processing units (PEs) required.

[0063] For example, operator OP 5，1 OP 3，2 OP 5，2 OP 7，2 The optimal implementation requires, for example, 5, 2, 3, and 4 processing units (PEs).

[0064] Because PE only supports single-cycle, single-hop data transmission. Figure 5a , 5b Operator OP in this embodiment of the invention 3，1 A schematic diagram of the interconnection structure between the required processing units (PE). Figure 6 Operator OP in this embodiment of the invention 5，1 A partial schematic diagram of the interconnection structure between the required processing units (PE).

[0065] Please see Figures 5a-6 , respectively, operators OP 3，1 and operator OP 5，1 The interconnection structure requires various hardware interconnection methods for the processing units (PE), including row, column, and L-shaped arrangements, as long as the interconnection of the processing units (PE) is guaranteed (see details). Figure 5a (a), (b), and (c) in the text. Figure 5b (d), (e), (f) and Figure 6 (a), (b), (c), (d) in the example, and the operator OP k，s For example, different interconnect structures can be used to implement different operators corresponding to different hardware implementations.

[0066] For example, before each row of convolution kernels slides through the window, the method further includes: providing the weight vector of the row convolution and the vector of the input feature map; obtaining the starting position and data length in the input feature map; and performing window sliding and inner product calculation based on the starting position and data length.

[0067] Figure 8 This is a schematic diagram of the PEA array system according to an embodiment of the present invention.

[0068] Please see Figure 8 Another embodiment of the present invention provides a coarse-grained reconfigurable array operator design system for deep learning, used to implement the aforementioned disclosed coarse-grained reconfigurable array operator design method for deep learning, comprising:

[0069] A controller is used to input information to at least one processing unit PE, wherein the input information includes a weight vector, an input vector, a status instruction, and an operation instruction, the status instruction is used to determine the execution status of the operation instruction, and the operation instruction is used by at least one processing unit PE to calculate the inner product of the weight vector and the input vector;

[0070] An input bus is used to input a weight vector and an input vector to at least one processing unit PE.

[0071] A configuration bus is used to input status instructions and operation instructions to at least one processing unit (PE).

[0072] The processing unit array PEA includes multiple processing units PE. Each processing unit PE is used to calculate the inner product of the weight vector and the input vector according to the operation instructions to obtain the inner product result.

[0073] The output bus is used to output the inner product result for at least one processing unit (PE).

[0074] The controller (Top Ctrl) is responsible for coordinating the overall execution process of the reconfigurable array, such as preloading, execution, idle, or interrupted execution.

[0075] For example, the input bus can support a data width of 32 bits, allowing 32-bit weights and input data to be input, and the output bus can support a data width of 32 bits, so that the processing unit PE can output 32-bit result data.

[0076] For example, the data bit width supported by the configuration bus can be 20 bits.

[0077] In this embodiment, the processing unit array PEA has M columns and N rows, where M ≥ 1 and is an integer, and N ≥ 1 and is an integer, wherein:

[0078] Each processing unit (PE) shares a single input bus;

[0079] Each processing unit (PE) shares one output bus;

[0080] Each processing unit (PE) shares a configuration bus.

[0081] In this embodiment, the processing unit PE includes:

[0082] The instruction register subunit is used to store operation instructions and status instructions;

[0083] The instruction decoding subunit is used to decode operation instructions and status instructions;

[0084] The weight register subunit is used to store the weight vector or the input vector;

[0085] Local register subunits are used to store intermediate data;

[0086] The logic operation subunit is used to perform inner product calculation on the weight vector and the input vector according to the operation instructions, and obtain the inner product result.

[0087] Figure 9 This is a schematic diagram of the processing unit PE in an embodiment of the present invention.

[0088] Please see Figure 9 The PE internal instruction register subunit includes an Operation Config Register File (OCRF) of 32×20 bits and a Status Config Register File (SCRF) of 32×20 bits. Figure 9 This is represented as CRF*2. PE includes a 32×32-bit Weight Register File (WRF) and a 2×32-bit Local Register File (LRF). The operation instruction register is located in... Figure 9 In this context, it is represented as PE STAT Ctrl, and the status instruction register subunit is located in... Figure 9 This is represented as PE_Ctrl.

[0089] Furthermore, Figure 9 The processing unit PE also includes two selectors and one output port, denoted as Op1_MUX, Op2_MUX, and Output_Reg, respectively. N, S, E, and W represent the inputs from other processing units PEs (north, south, east, west, and north) from the processing unit PE, respectively, and D represents the weights and input data input from the input bus. The selectors in the processing unit PE can be used to select and receive the weight vector, the input vector, the calculation results from other PEs (north, south, east, west, and north), and Output_Reg.

[0090] According to an embodiment of the present invention, CGRA adopts a distributed storage method, with each PE containing local data storage. The WRF (Write-Offset Rendering) is writable only during the preloading phase and can only be read locally by the PE during array operation. Its read address can be flexibly controlled according to operation instructions and status instructions, while its write address is generated by the PE's own increment and its upper limit is controlled by the number of weight vectors in the PE. The LRF (Read-Offset Rendering) is used for accessing intermediate data during array operation, with dual read ports and a single write port; its read and write addresses are controlled according to operation instructions. By reading the weights and input data locally on the PE for calculation, near-memory computation is achieved, effectively reducing energy consumption during data movement.

[0091] It should be understood that the specific order or hierarchy of steps in the inventive process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of the invention. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to a specific order or hierarchy.

[0092] Similarly, to simplify the invention and aid in understanding one or more aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0093] Features specified as "first" or "second" may explicitly or implicitly include one or more of those features. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Unless otherwise stated, the expressions "about," "approximately," "substantially," and "around" indicate a percentage of less than 10%, preferably less than 5%.

[0094] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for designing coarse-grained reconfigurable array operators for deep learning, characterized in that, include: Provide at least one operator OP with a preset kernel size k and a preset stride s. k，s k and s ≥ 1 and are integers; Based on the operator OP k，s Determine each of the operators OP k，s The required number of processing units (PEs) is used to perform row convolution calculations, where PE ≥ 1 and is an integer; the row convolution calculation includes: splitting the convolution kernel into i rows, where i ≥ 1 and is an integer, and performing an inner product operation on the weight vector and input vector of each row convolution kernel using a window sliding method based on the required processing units (PEs) to obtain the partial sum of each row convolution kernel; wherein, the window sliding includes: sliding on each row convolution kernel with the preset sliding stride s; According to each of the operators OP k，s The required number of processing units (PEs) determines the operator (OP). k，s The hardware interconnection structure between the required processing units (PEs) constitutes the operator (OP). k，s library; Wherein, each of the operators OP k，s The required number of processing units (PEs) is determined by the following formula: ON n = Among them, PE n Each of the operators OP represents k，s The required number of processing units (PEs); The hardware interconnection structure between the required processing units (PEs) includes various arrangement methods such as row arrangement, column arrangement, or L-shaped arrangement.

2. The coarse-grained reconfigurable array operator design method for deep learning according to claim 1, characterized in that, The execution of row convolution calculation also includes: obtaining a partial sum of the convolution kernels in each row and accumulating them to obtain the final output feature image.

3. The coarse-grained reconfigurable array operator design method for deep learning according to claim 1, characterized in that, The process of performing row convolution calculations also includes: Get the startup interval of adjacent windows when the window is slid; When each row of convolution kernels is processed using a sliding window method, the inner product operation is initiated sequentially according to the initiation interval, which is determined according to the following formula: II= Wherein, II represents the start interval. For each of the operators OP k，s The number of processing units (PEs) required, where Q is the number of multiplications and accumulations in the inner product operation within a single sliding window.

4. The coarse-grained reconfigurable array operator design method for deep learning according to claim 2, characterized in that, Before each row of convolutional kernels slides through the window, the following is also included: Provide the weight vector of each row of convolutional kernels and the vector of the input feature map; Obtain the starting position and data length in the input feature map, and perform window sliding and inner product operation based on the starting position and data length.

5. A coarse-grained reconfigurable array operator design system for deep learning, used to implement the coarse-grained reconfigurable array operator design method for deep learning as described in any one of claims 1-4, characterized in that, The system includes: A controller is configured to input information to at least one processing unit PE, wherein the input information includes a weight vector, an input vector, a status instruction, and an operation instruction, the status instruction being configured to determine the execution status of the operation instruction, and the operation instruction being configured to at least one processing unit PE to calculate the inner product of the weight vector and the input vector; An input bus is used to input the weight vector and the input vector to at least one of the processing units PE; A configuration bus is used to input the status instructions and the operation instructions to at least one of the processing units PE; The processing unit array PEA includes multiple processing units PE, each of which is used to perform an inner product operation on the weight vector and the input vector according to the operation instruction to obtain the inner product result. An output bus is provided for at least one of the processing units PE to output the inner product result.

6. The coarse-grained reconfigurable array operator design system for deep learning according to claim 5, characterized in that, The processing unit array PEA has M columns and N rows, where M ≥ 1 and is an integer, and N ≥ 1 and is an integer, where: Each of the processing units (PEs) in the column shares one input bus; Each of the processing units (PE) in each row shares one output bus; Each of the processing units (PEs) in the column shares a single configuration bus.

7. The coarse-grained reconfigurable array operator design system for deep learning according to claim 6, characterized in that, The processing unit PE includes: An instruction register subunit is used to store the operation instructions and the status instructions; An instruction decoding subunit is used to decode the operation instruction and the status instruction; A weight register subunit is used to store the weight vector or the input vector; Local register subunits are used to store intermediate data; The logic operation subunit is used to perform an inner product operation on the weight vector and the input vector according to the operation instruction to obtain the inner product result.

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