Homomorphic operation apparatus and method

Abstract

A homomorphic operation device and method, the homomorphic operation device comprises a format conversion unit, a homomorphic operation instruction compiling unit and a hardware operation unit. The format conversion unit is used for converting homomorphic operation task information into text information; the homomorphic operation instruction compiling unit is used for obtaining homomorphic computing task information by identifying the text information, and converting the homomorphic computing task information into a homomorphic computing static graph, and then generating a homomorphic computing instruction set according to the homomorphic computing static graph; and the hardware operation unit executes homomorphic computing instructions in the homomorphic computing instruction set to complete the homomorphic operation task. Since the homomorphic computing static graph is first generated according to the homomorphic operation task information, and then the hardware circuit executes the homomorphic computing instruction set according to the homomorphic computing static graph to complete the homomorphic operation, the hardware circuit schedules the internal functional units in a pre-optimized order to process the computing task in parallel, so that the utilization rate of the hardware is higher, and the operation efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of data security protection technology, specifically to a homomorphic operation device and method. Background Technology

[0002] With the rapid development of internet technology, an ever-increasing amount of data is being transmitted, stored, and computed. Much of this data is critical, encrypted, secure, or private. Private data, in particular, may be protected by confidentiality laws and regulations. Users typically protect their data by encrypting it to prevent malicious insiders, external attackers, or accidental exposure. Under traditional encryption mechanisms, data can be encrypted during transmission and storage. However, in the data usage stage, ciphertext data often needs to be decrypted before processing, making plaintext data highly vulnerable to attacks. Academia and industry have been proposing various solutions to address this problem, such as homomorphic encryption. Homomorphic encryption (HE) is a widely used cryptographic tool that satisfies the homomorphic operation property of ciphertext. That is, after data is homomorphically encrypted, performing specific calculations on the ciphertext yields a ciphertext that, when homomorphically decrypted, results in plaintext that is equivalent to performing the same calculation directly on the plaintext data, achieving "computable but invisible" data. Therefore, it is widely used in privacy-preserving scenarios such as cloud computing services, outsourced computing, and federated learning, and represents a direction for emerging privacy technologies.

[0003] Homomorphic encryption computation requires the entire computation to be performed in ciphertext. Compared to plaintext computation, ciphertext computation is 3-6 orders of magnitude slower, thus requiring significantly more computing resources. By programming computing chips or FPGA (Field-Programmable Gate Array) hardware, hardware architectures suitable for handling homomorphic encryption algorithms can be constructed to accelerate ciphertext computation. Currently, mainstream FPGA-based homomorphic computing solutions achieve significant speedups by fixing computational tasks, enabling the FPGA hardware to handle single or a few fixed tasks. However, they do not fully utilize all the hardware resources of the FPGA, and the computational instructions supported by the FPGA are also relatively limited. Summary of the Invention

[0004] The main technical problem addressed in this application is how to improve the utilization rate of hardware circuits used for homomorphic operations in order to accelerate homomorphic computation.

[0005] In one embodiment, a homomorphic computing device is provided, including a homomorphic computing instruction compilation unit and a hardware computing unit; The homomorphic operation instruction compilation unit is used to recognize text information in a preset format and convert the homomorphic computation task information obtained through recognition into a homomorphic computation static graph; the homomorphic operation instruction compilation unit is also used to obtain a homomorphic computation instruction set based on the homomorphic computation static graph and send the obtained homomorphic computation instruction set to the hardware operation unit; the homomorphic computation instruction set includes at least one homomorphic computation instruction, and each homomorphic computation instruction can be executed by the hardware operation unit; The hardware computing unit includes an instruction execution control unit, at least two storage units, and at least two homomorphic computing units; The storage unit is used to store homomorphic operation data, which includes homomorphic operation source data, homomorphic operation process data, and homomorphic operation result data; the homomorphic operation source data includes plaintext data and / or ciphertext data, and the homomorphic operation process data is intermediate data generated during the homomorphic computation process. The homomorphic computation unit is used to perform homomorphic computation; The instruction execution control unit is used to schedule the storage unit and homomorphic computing unit of the hardware computing unit to complete homomorphic computing tasks according to the homomorphic computing instruction set.

[0006] Secondly, in one embodiment, a homomorphic operation method is provided, applied in the homomorphic operation apparatus as described in the first aspect, the homomorphic operation method comprising: Convert the received homomorphic operation task information into text information in a preset format; Identify the text information to obtain homomorphic computation task information; The homomorphic computation task information is converted into a homomorphic computation static graph; Obtain the homomorphic computation instruction set based on the aforementioned homomorphic computation static diagram; The hardware arithmetic unit executes the homomorphic computation instruction set to complete the homomorphic computation.

[0007] Thirdly, in one embodiment, a computer-readable storage medium is provided, including a program that can be executed by a processor to implement the homomorphic operation method as described in the second aspect.

[0008] The homomorphic operation method disclosed in the above embodiments first converts the received homomorphic operation task information into text information in a preset format. Then, it generates a homomorphic operation static graph based on the identified text information to obtain the homomorphic operation task information. Next, it generates a homomorphic operation instruction set according to the static graph, which is then executed sequentially by the hardware operation unit to complete the homomorphic operation task. Because the homomorphic operation static graph is generated first based on the homomorphic operation task information, and then the hardware circuit executes the homomorphic operation instruction set according to the static graph to complete the homomorphic operation, the hardware schedules its internal functional units to process the computation tasks in parallel according to a pre-optimized order, greatly improving hardware utilization and computational efficiency. Attached Figure Description

[0009] Figure 1 This is a structural block diagram of a homomorphic computing device in one embodiment; Figure 2 This is a schematic diagram of the homomorphic operation method in one embodiment. Detailed Implementation

[0010] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0011] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0012] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0013] This application sets up a homomorphic operation instruction compilation unit on the basis of the original homomorphic operation hardware architecture. The homomorphic operation instruction compilation unit first converts the homomorphic operation task information into a homomorphic computation static graph, and then generates a homomorphic computation instruction set based on the homomorphic computation static graph. This allows the hardware circuit to schedule its internal functional units to process computation tasks in parallel in a pre-optimized order, which greatly improves the utilization rate of the hardware and the computation efficiency, thereby accelerating homomorphic operations.

[0014] Example 1: Please refer to Figure 1 The diagram below shows a structural block diagram of a homomorphic computing device in one embodiment. The homomorphic computing device includes a format conversion unit 1, a homomorphic computing instruction compilation unit 2, and a hardware computing unit 3. The format conversion unit 1 receives homomorphic computing task information, converts the received homomorphic computing task information into text information of a preset format, and sends it to the homomorphic computing instruction compilation unit 2. The homomorphic computing instruction compilation unit 2 identifies the text information of the preset format and converts the homomorphic computing task information obtained through identification into a homomorphic computing static diagram. The homomorphic computing instruction compilation unit 2 is also used to obtain a homomorphic computing instruction set based on the homomorphic computing static diagram and send the obtained homomorphic computing instruction set to the hardware computing unit 3. The homomorphic computing instruction set includes at least one homomorphic computing instruction, and each homomorphic computing instruction can be executed by the hardware computing unit 3. The hardware computing unit 3 includes an instruction execution control unit 31, at least two storage units 32, and at least two homomorphic computing units 33. The storage units 31 store homomorphic computing data, which includes homomorphic computing source data, homomorphic computing process data, and homomorphic computing result data. The source data for homomorphic operations includes plaintext data and / or ciphertext data, while the process data for homomorphic operations consists of intermediate data generated during the homomorphic computation. The homomorphic computation unit 33 performs homomorphic computations, including NTT / INTT polynomial multiplication, modular multiplication, modular addition, modular subtraction, mod switch operations, and / or rotation operations. The instruction execution control unit 31 schedules the storage unit 32 of the hardware computation unit 3 and the homomorphic computation unit 33 to complete the homomorphic computation task according to the homomorphic computation instruction set. Specifically, the instruction execution control unit 31 sets the homomorphic computation data stored in each storage unit 32 according to the homomorphic computation instruction set. The instruction execution control unit 31 also sets the computation type of each homomorphic computation unit 33 and the associated storage unit 32 for the source and result data of the homomorphic computation unit during homomorphic computation according to the homomorphic computation instruction set.

[0015] In one embodiment, the homomorphic operation instruction compilation unit 2 includes a static graph generator 21 and an instruction set generator 22. The static graph generator 21 is used to identify text information to obtain homomorphic source data information and homomorphic computation information, and to generate a homomorphic computation static graph based on the homomorphic source data information and homomorphic computation information. The homomorphic source data information includes data storage information. The homomorphic computation information includes the type information of the homomorphic computation. The homomorphic computation static graph is composed of the most basic homomorphic computation nodes. The instruction set generator 22 is used to generate a homomorphic computation instruction set based on the homomorphic computation static graph.

[0016] In one embodiment, the homomorphic operation device further includes an operation result output unit 34, which is used to output homomorphic operation completion information and / or homomorphic operation result data after the hardware operation unit 3 completes the homomorphic operation according to the homomorphic operation instruction set.

[0017] In one embodiment, the instruction execution control unit 31 is used to schedule the storage unit 32 and the homomorphic computing unit 33 of the hardware arithmetic unit to complete the homomorphic computing task according to the homomorphic computing instruction set, including: The instruction execution control unit 31 is used to set the homomorphic operation data stored in each storage unit 32 according to the homomorphic computation instruction set; the instruction execution control unit 31 is also used to set the computation type of each homomorphic computation unit 33 and the storage unit of the homomorphic computation source data and homomorphic computation result data associated with the homomorphic computation when the homomorphic computation unit 33 performs homomorphic computation according to the homomorphic computation instruction set.

[0018] Please refer to Figure 2 The diagram illustrates a homomorphic operation method in one embodiment. In another embodiment, this application also discloses a homomorphic operation method applied to the homomorphic operation device described above, comprising: Step 101: Obtain text information.

[0019] The received homomorphic operation task information is converted into text information in a preset format. In one embodiment, the text information is in the form of a CSV file, a TXT file, or a JSON file.

[0020] Step 102: Obtain homomorphic computation task information.

[0021] Identify textual information to obtain information about homomorphic computation tasks.

[0022] Step 103: Obtain the static graph of homomorphic computation.

[0023] The homomorphic computation task information is converted into a homomorphic computation static graph. In one embodiment, after obtaining the homomorphic computation static graph, the homomorphic computation static graph is compared with the homomorphic computation task information, and the data storage information of the homomorphic computation source data is matched.

[0024] Step 104: Generate the homomorphic computation instruction set.

[0025] The homomorphic computation instruction set is obtained based on the homomorphic computation static graph. All homomorphic computation nodes on the homomorphic computation static graph are searched and traversed, and each homomorphic computation node is planned using a preset optimization algorithm to compile the homomorphic computation instruction set.

[0026] Step 105: Complete the homomorphic operation.

[0027] The hardware arithmetic unit executes the homomorphic computation instruction set to complete homomorphic operations.

[0028] In one embodiment, the homomorphic operation method further includes: Step 106: Complete information output.

[0029] Output information about the completion of the homomorphic operation and / or the result data of the homomorphic operation.

[0030] The homomorphic computation method disclosed in this application is a compiler that schedules computing chips or FPGA hardware to perform homomorphic computation tasks. The hardware computing unit includes storage units, homomorphic computation units, and communication modules between them. By dynamically decomposing the computation task into a static graph composed of basic operators, and inputting this graph into an instruction set generator (compiler), the compiler coordinates the cooperation between the units within the hardware computing unit according to an optimization algorithm, planning data transmission and computation in parallel to achieve high-efficiency computing capabilities and execute corresponding hardware instructions in parallel. This homomorphic computation method mainly has two steps: first, the computation task is transformed into a static graph; then, these sub-static graphs are compiled, ultimately outputting instructions that the hardware computing unit can run. This homomorphic computation method can be used for any type of homomorphic computation task, transforming the task into a specific data format (text information). When recognizing text information, computation nodes composed of basic operators form a static graph. Furthermore, the optimization algorithm considers the characteristics of the FPGA hardware architecture, including but not limited to homomorphic computation units, storage units, and communication transmission methods, and rationally plans each computation node according to the physical limitations of the FPGA architecture. It should be noted that the compilation result of the static graph is hardware instructions, which will direct and schedule the hardware computing units to execute dynamic computing tasks. Compared with existing homomorphic computing FPGA hardware architectures, firstly, it supports arbitrary homomorphic computing tasks and realizes dynamic compilation of computing tasks; secondly, it increases the flexibility of FPGA hardware for homomorphic encryption algorithm schemes, while improving homomorphic computing performance; in addition, this homomorphic computing method is suitable for a certain type of FPGA hardware architecture and has wide applicability.

[0031] The application process of the homomorphic computing device disclosed in this application is described below through a specific embodiment.

[0032] Suppose a homomorphic convolution computation task has three convolutional layers, each layer including several ciphertext-to-plaintext, ciphertext-to-multiplication-of-plaintext, and ciphertext-to-ciphertext multiplications. The homomorphic computation device only needs to generate a hardware instruction set (homomorphic computation instruction set) to perform this computation task on the hardware computing unit.

[0033] First, the homomorphic convolution computation task is converted into a specific data format, such as a .csv file, and input into the homomorphic operation instruction compilation unit.

[0034] Then, after identifying the computation task, the static graph generator breaks it down, constructing a static graph from the operations in each convolutional layer. After obtaining the static graph, it is compiled according to the specific implementation process of the homomorphic encryption algorithm and the FPGA design architecture. For example, two homomorphic computation units in the hardware computing unit are used: one as the computation node for ciphertext multiplication and the other as the computation node for ciphertext multiplication. The generator also coordinates the start time of computation between the data storage unit and the homomorphic computation unit, as well as communication between the computation units. The output hardware homomorphic computation instructions include "Storage unit 1 to homomorphic computation unit 1", "Homomorphic computation unit 2 to storage unit 3", and "Homomorphic computation unit 1 starts". Furthermore, all computation nodes on the static graph are searched and traversed, and an optimization algorithm is used to plan each computation node.

[0035] The static graph is then mapped to the original computation task, data addresses are matched, and hardware instructions are integrated. The final output is the complete homomorphic computation instruction set that completes the computation task.

[0036] Finally, the hardware arithmetic unit executes the homomorphic computation instruction set to complete the homomorphic computation task.

[0037] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0038] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A homomorphic computing device, characterized in that, This includes a homomorphic operation instruction compilation unit and a hardware arithmetic unit; The homomorphic operation instruction compilation unit is used to recognize text information in a preset format and convert the homomorphic computation task information obtained through recognition into a homomorphic computation static graph; the homomorphic operation instruction compilation unit is also used to obtain a homomorphic computation instruction set based on the homomorphic computation static graph and send the obtained homomorphic computation instruction set to the hardware operation unit; the homomorphic computation instruction set includes at least one homomorphic computation instruction, and each homomorphic computation instruction can be executed by the hardware operation unit; The hardware computing unit includes an instruction execution control unit, at least two storage units, and at least two homomorphic computing units; The storage unit is used to store homomorphic operation data, which includes homomorphic operation source data, homomorphic operation process data, and homomorphic operation result data. The homomorphic operation source data includes plaintext data and / or ciphertext data, and the homomorphic operation process data is intermediate data generated during the homomorphic computation process. The homomorphic computation unit is used to perform homomorphic computation; The instruction execution control unit is used to schedule the storage unit and homomorphic computing unit of the hardware computing unit to complete the homomorphic computing task according to the homomorphic computing instruction set; The homomorphic operation instruction compilation unit includes a static graph generator and an instruction set generator; The static graph generator is used to identify the text information to obtain homomorphic source data information and homomorphic computation information, and to generate a homomorphic computation static graph based on the homomorphic source data information and the homomorphic computation information; The homomorphic source data information includes data storage information; The homomorphic computation information includes the type information of the homomorphic computation; The homomorphic computation static graph is composed of the most basic homomorphic computation nodes; The instruction set generator is used to generate the homomorphic computation instruction set based on the homomorphic computation static graph, including: The system searches and traverses all homomorphic computation nodes on the homomorphic computation static graph, and uses a preset optimization algorithm to plan each homomorphic computation node in order to compile the homomorphic computation instruction set.

2. The homomorphic computing device as described in claim 1, characterized in that, It also includes a format conversion unit for receiving the homomorphic operation task information, converting the received homomorphic operation task information into text information in the preset format, and then sending it to the homomorphic operation instruction compilation unit; The homomorphic operation device further includes an operation result output unit, which is used to output homomorphic operation completion information and / or homomorphic operation result data after the hardware operation unit completes the homomorphic operation according to the homomorphic operation instruction set.

3. The homomorphic computing device as described in claim 1, characterized in that, The types of homomorphic computations performed by the homomorphic computation unit include NTT / INTT polynomial multiplication, modular multiplication, modular addition, modular subtraction, mod switch operations, and / or rotation operations; The instruction execution control unit is used to schedule the storage unit and homomorphic computing unit of the hardware arithmetic unit to complete homomorphic computing tasks according to the homomorphic computing instruction set, including: The instruction execution control unit is used to set the homomorphic operation data stored in each of the storage units according to the homomorphic computation instruction set; The instruction execution control unit is also used to set the calculation type of each homomorphic calculation unit and the storage unit of the homomorphic operation source data and homomorphic operation result data associated with the homomorphic calculation when the homomorphic calculation unit performs homomorphic calculation according to the homomorphic calculation instruction set.

4. A homomorphic operation method, characterized in that, Applied in the homomorphic operation apparatus as described in any one of claims 1 to 3, the homomorphic operation method includes: Convert the received homomorphic operation task information into text information in a preset format; Identify the text information to obtain homomorphic computation task information; The homomorphic computation task information is converted into a homomorphic computation static graph; Obtain the homomorphic computation instruction set based on the aforementioned homomorphic computation static diagram; The hardware arithmetic unit executes the homomorphic computation instruction set to complete the homomorphic computation.

5. The homomorphic operation method as described in claim 4, characterized in that, Also includes: Output homomorphic operation completion information and / or the homomorphic operation result data.

6. The homomorphic operation method as described in claim 4, characterized in that, The text information can be in the form of a CSV file, a TXT file, or a JSON file.

7. The homomorphic operation method as described in claim 4, characterized in that, The step of converting the homomorphic computation task information into a homomorphic computation static graph includes: The homomorphic computation static graph is compared with the homomorphic operation task information, and the data storage information of the homomorphic operation source data is matched.

8. A computer-readable storage medium, characterized in that, The medium stores a program that can be executed by a processor to implement the homomorphic operation method as described in any one of claims 4-7.

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