A synchronization control method and circuit of a parallel memory access instruction pipeline
By dividing the memory access instruction pipeline into two parts, A and B, and adopting an inter-station hold protocol and an explicit tick counter, the synchronization control problem of parallel memory access units in VLIW microprocessors is solved, achieving efficient pipeline synchronization and sequential execution.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Filing Date
- 2022-12-30
- Publication Date
- 2026-08-04
AI Technical Summary
Existing VLIW microprocessors suffer from pipeline stalls in their parallel memory access units, making it difficult to achieve fast synchronous control and resulting in low overall execution efficiency.
The memory access instruction pipeline is divided into two parts, A and B. Part A uses the pipeline station hold protocol and synchronization control circuit, while part B only handles its own pauses and uses an explicit tick counter and write-back data buffer to achieve synchronization control.
It achieves efficient parallel memory access instruction pipeline synchronization control at a low hardware cost, and is suitable for multiple deeply parallel memory access instruction pipelines, especially for very long instruction word architecture microprocessors.
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Figure CN116302110B_ABST
Abstract
Description
Technical Field
[0001] This invention mainly relates to the field of microprocessor instruction pipeline design technology, specifically a synchronous control method and circuit for a parallel memory access instruction pipeline. Background Technology
[0002] VLIW technology uses a compiler to encapsulate multiple unrelated instructions into a single Very Long Instruction Set Producer (VLIW), which is then issued to different functional units for parallel execution. It primarily relies on statically exploiting instruction-level parallelism during the compilation phase to improve processor performance and is currently a mainstream microprocessor architecture for enhancing instruction-level parallelism. Compared to superscalar architecture microprocessors, which mainly rely on dynamic hardware implementation of instruction dependencies and out-of-order execution to exploit instruction-level parallelism, VLIW microprocessors have relatively simpler hardware implementations and lower power consumption. They are widely used in digital signal processors and various embedded microprocessors, such as Texas Instruments' TMS320C6000 series and Tensilica's BBE series processors. However, VLIW microprocessors require sequential issue, synchronization, and sequential commit of their instruction pipeline, meaning that the correctness of program execution must be guaranteed. Instruction scheduling and parallel implementation are based on the premise that the corresponding instructions complete at a predetermined timeframe, which necessitates the implementation of sequential execution and synchronization control of the instruction pipeline.
[0003] VLIW processors typically contain multiple parallel-executable functional units, such as instruction control, arithmetic, and memory access. A VLIW instruction packet is simultaneously issued to different functional units for parallel execution based on the initial decoding result. The pipeline lengths of each functional unit are different, but they are all affected by global pipeline anomalies. That is, when any functional unit encounters an anomaly, the instruction pipelines of other functional units must be paused, and the component that encountered the anomaly needs to resolve the anomaly to achieve synchronization of the parallel pipelines.
[0004] When hardware resource conflicts, interrupts, exceptions, debug requests, or cache misses occur in the VLIW processor instruction pipeline, the entire instruction pipeline will pause. The signals that generate these exceptions are referred to as the pipeline's global pause signal (Global_Stall). This global pause signal originates from different functional units, with varying latency and uncertainty. However, each functional unit needs to implement pipeline synchronization control based on the global pause signal. The functional unit generating the signal must also resolve related issues during the pipeline pause, eliminate the pause signal, and resume normal pipeline execution, thus achieving pipeline synchronization.
[0005] With the increasing performance demands of embedded applications and the rapid development of semiconductor technology, VLIW microprocessors typically incorporate multiple memory access units on-chip, resulting in increasingly longer memory access pipelines. Data memory access bandwidth performance is significantly increased by implementing parallel execution of multiple memory access instructions and raising the clock frequency. However, parallel memory access units often experience pipeline stalls due to memory access conflicts, memory misses, or global stall signals from other functional units. Therefore, quickly achieving sequential execution and synchronous control of the memory access pipeline has become a challenge in efficiently designing parallel memory access units for VLIW microprocessors. Summary of the Invention
[0006] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides a synchronization control method and circuit for a parallel memory access instruction pipeline that is simple in principle, low in implementation cost, and has good synchronization control effect.
[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0008] A synchronization control method for a parallel memory access instruction pipeline, comprising:
[0009] Step S1: Divide the memory access instruction pipeline clock into explicit memory access clock and actual memory access clock;
[0010] Step S2: Based on the explicit memory access cycle of the read memory access instruction, divide the read memory access instruction pipeline into two parts, A and B. The explicit cycle numbers of the pipelines in parts A and B are M1 and M2, respectively; M1 and M2 are both integers greater than or equal to 2.
[0011] Step S3: Implement different control strategies for parts A and B: Use pipeline inter-station hold protocol and synchronization control circuit to achieve synchronization control of the entire pipeline for parts A and B for part A of the memory access instruction pipeline; do not perform synchronization control on memory access requests within the pipeline for part B of the memory access instruction pipeline.
[0012] As a further improvement to the method of the present invention: each station in section A is controlled only by the global pause signal from the VLIW microprocessor; the output between stations in section A adopts the method of maintaining the output signal of the previous step when a global pause signal is encountered, so as to realize the lock-step execution of the pipeline in section A and complete the synchronous control of the pipeline in section A.
[0013] As a further improvement to the method of the present invention: Part A also includes a write-back data cache and a synchronization control pipeline, which is placed after the pipeline of Part B to implement the caching and synchronization of memory access requests in the pipeline of Part B.
[0014] As a further improvement to the method of the present invention: the write-back data buffer and synchronization control pipeline station sets up a write-back data synchronization buffer T with an explicit tick label according to the explicit tick number M2 of the B part pipeline. T is composed of (M2+1) sets of registers to realize the write-back data buffer when the B part pipeline occurs in the Global_Stall event.
[0015] As a further improvement to the method of the present invention: the pipeline in part B is only used to generate and process pipeline functions that are not affected by the global pause signal, and is only responsible for processing and eliminating the memory access pauses generated by the parallel memory access unit itself, completing data memory access, and reading data selection functions.
[0016] As a further improvement to the method of the present invention: the first station of the B section pipeline is equipped with a display tick counter CNT related to the display tick count M2 of the B section pipeline, which records the number of pipeline ticks without a global pause signal throughout the entire stage of the B section pipeline; the display tick counter CNT is used to give an explicit tick count tag to each read access request entering the first station of the B section pipeline, and together with the write-back data, it is sent to the write-back data buffer and synchronization control pipeline station in the subsequent pipeline register of the B section to realize the synchronous control of the read data access.
[0017] As a further improvement to the method of the present invention: In step S1, the explicit memory access clock is equal to the memory access instruction execution pipeline clock visible to the programmer provided by the VLIW microprocessor instruction set architecture plus the memory access instruction decoding pipeline clock. It is assumed that the number of explicit memory access clocks for read memory access instructions is M, where M is an integer greater than or equal to 4; the number of explicit memory access clocks for write memory access instructions is a positive integer less than M; the actual memory access clock is the actual memory access instruction execution clock after adding the clock delay caused by the global pause signal to the explicit memory access clock.
[0018] This invention further provides a synchronization control circuit for a parallel memory access instruction pipeline. Based on the explicit memory access cycle time of the read memory access instruction, the read memory access instruction pipeline is divided into two parts, A and B, with explicit cycle times of parts A and B being M1 and M2, respectively; M1 and M2 are both integers greater than or equal to 2; including:
[0019] The write-back data buffer and synchronization pipeline, following the pipeline section B, includes a write-back data synchronization buffer T, a read-write state machine WR_FSM, and a two-way switch S. The write-back data synchronization buffer T is used to buffer the read data of memory access requests that have not reached the specified explicit tick count due to pipeline pauses caused by the Global_Stall signal. The read-write state machine WR_FSM realizes the reading and writing of T and controls the output of the two-way switch S based on the explicit tick count tag of the memory access request flowing into the station, the current explicit tick counter CNT value, and the Global_Stall status sampled by the pipeline.
[0020] The explicit tick counter (CNT) is set at the first station of the B-section pipeline. It is related to the pipeline depth M2 of the B-section and records the pipeline tick count for each parallel memory access instruction during the B-section pipeline stage when there is no global pause signal (Global_Stall). It is used to give each read memory access request entering the first station of the B-section pipeline its explicit tick count label, and it is sent out along with the write-back data to the subsequent pipeline registers in the B-section pipeline until it is sent to the write-back data buffer and synchronization station in the A-section pipeline.
[0021] As a further improvement to the circuit of the present invention: the write-back data synchronization buffer T is composed of (M2+1) homogeneous registers T0-TM2. In addition to containing the data bit width required for the read instruction write-back, each register in the write-back data synchronization buffer T also adds an explicit tick count tag Count_Tag for each read memory access data. The write-back data synchronization buffer T is controlled by the read-write state machine WR_FSM of the pipeline station. WR_FSM performs read and write operations on the corresponding T according to the Global_Stall status sampled by the station, the Count_Tag value of the memory access request data band, and the current explicit tick counter CNT value.
[0022] As a further improvement to the circuit of the present invention: the counting register of the explicit beat counter CNT has a bit width of the positive integer L, where L is equal to log2(M2+1) rounded up. CNT starts counting from 0 and increments by 1. The maximum value of the count output is M2. When reset or when the count reaches M2, the CNT count value is cleared to 0. If the CNT output is not equal to M2 and the Global_Stall sample is invalid, the count is incremented by 1 until the count value reaches M2, at which point CNT is cleared to 0, and the same counting process begins again.
[0023] Compared with the prior art, the advantages of the present invention are as follows:
[0024] 1. The synchronization control method and circuit for the parallel memory access instruction pipeline of the present invention are simple in principle, low in implementation cost, and have good synchronization control effect. It is a method and circuit structure for implementing synchronization control of multiple deeply parallel memory access instruction pipelines based on the synchronization control requirements of VLIW architecture microprocessor instruction pipelines. The present invention controls the pause, memory access, result caching, and write-back of the parallel memory access pipeline based on the memory access pause generated by the parallel memory access unit itself and the global pause signal from other functional units. It can efficiently realize the synchronization and sequential execution of the parallel memory access instruction pipeline with low hardware cost.
[0025] 2. The parallel memory access instruction pipeline synchronization control method and circuit of the present invention are proposed to address the synchronization control requirements of a VLIW microprocessor instruction pipeline with P parallel memory access units (P being an integer greater than or equal to 2). This invention provides a deep parallel memory access pipeline synchronization control and circuit implementation method. Based on the generation and processing of memory access pause signals of parallel memory access units, the present invention divides the memory access instruction pipeline into two parts, employing different pipeline station protocols and dedicated circuits for pipeline control in each part. An explicit tick counter and a write-back data synchronization buffer are designed to achieve memory access data write-back synchronization, thereby efficiently achieving synchronous control and sequential execution of the parallel memory access instruction pipeline with low hardware cost.
[0026] 3. The synchronous control method and circuit of the parallel memory access instruction pipeline of the present invention are particularly applicable to microprocessors with very long instruction word (VLIW) architecture, and can quickly realize the synchronous control of parallel memory access instructions with low hardware cost according to the depth of the memory access pipeline. Attached Figure Description
[0027] Figure 1 This is a schematic diagram showing the division of a memory access pipeline into sections A and B in a specific application example of the present invention.
[0028] Figure 2 This is a functional logic block diagram of the write-back data cache and synchronization station in a specific application example of the present invention.
[0029] Figure 3 This is a schematic diagram of the data structure of the write-back data synchronization buffer T in a specific application example of the present invention.
[0030] Figure 4 This is a schematic diagram of the control flow of WR_FSM in a specific application example of the present invention.
[0031] Figure 5 This is a logical diagram of CNT in a specific application example of the present invention.
[0032] Figure 6 This is a flowchart illustrating the method of the present invention. Detailed Implementation
[0033] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0034] For a VLIW processor containing P parallel memory access units, a single VLIW instruction package can contain a maximum of P parallel memory access instructions. Each memory access unit can execute one memory access instruction; each memory access instruction can perform either a read or write operation. The write instruction pipeline implements pipelined functions such as address calculation, memory hit or arbitration, memory decoding, and data access. The read instruction pipeline, in addition to the stations of the write pipeline, must also perform additional pipelined functions such as read data selection processing and data write-back.
[0035] In this process, on the one hand, the memory access unit needs to synchronize its memory access instruction pipeline execution based on global pause signals with uncertain clock lengths from other functional components of the VLIW microprocessor; on the other hand, due to memory misses or conflicts in on-chip memory read / write port resources, the parallel memory access unit itself will also experience memory access pauses. The parallel memory access unit must, in the event of global pause signals from other functional components, quickly resolve its own memory access pauses while simultaneously synchronizing its memory access pipeline.
[0036] like Figure 6 As shown, the synchronization control method for the parallel memory access instruction pipeline of the present invention includes:
[0037] Step S1: Divide the memory access instruction pipeline clock into explicit memory access clock and actual memory access clock;
[0038] Step S2: Based on the explicit memory access cycle of the read memory access instruction, divide the read memory access instruction pipeline into two parts, A and B, with the explicit cycle numbers of the pipelines in parts A and B being M1 and M2, respectively.
[0039] Step S3: Implement different control strategies for parts A and B:
[0040] The pipeline A section of the memory access instruction pipeline uses a pipeline station hold protocol and a low-hardware-cost synchronization control circuit to achieve synchronous control of the entire pipeline, including both sections A and B.
[0041] The memory access request within the B part of the memory access instruction pipeline is not synchronously controlled in order to solve the memory access pipeline stall problem, eliminate the memory access stall signal, and quickly complete the data access.
[0042] As can be seen from the above, the present invention addresses the synchronization control requirements of the parallel memory access instruction pipeline in VLIW microprocessors by employing different methods for pipeline control to achieve execution synchronization of the entire parallel memory access pipeline.
[0043] In a specific application example, no parallel memory access conflicts or memory misses occur within the pipeline stations of Part A. Inter-station hold protocols are used between pipeline stations to achieve pipelined lockstep execution. Each pipeline station in Part A is controlled only by the global pause signal (Global_Stall) from the VLIW microprocessor. This stage typically implements pipelined functions such as instruction decoding, address calculation, write-back data caching and synchronization, and data write-back. Specifically, the output between pipeline stations in Part A maintains the output signal from the previous cycle upon encountering a global pause signal to achieve lockedstep execution of the Part A pipeline, thereby achieving synchronous control of the Part A pipeline. Simultaneously, a first-level pipeline station with "write-back data caching and synchronization control" is added to Part A and placed after the Part B pipeline, specifically for caching and synchronizing memory access requests within the Part B pipeline. This pipeline synchronization control hardware implementation is simple and inexpensive.
[0044] In a specific application example, the pipeline in Part B is only used to generate and handle necessary pipeline functions unaffected by global pause signals, such as memory access conflicts, missing data, data access, and read data selection. It is only responsible for handling and eliminating memory access pauses generated by the parallel memory access units themselves, completing data access, and read data selection. There is no longer pipeline synchronization control between pipeline stations in Part B, so as to ensure that memory access requests from each station within Part B flow quickly to the "write-back data buffer and synchronization control" pipeline station in Part A.
[0045] Furthermore, to facilitate the synchronization control of memory access requests in Part B at the subsequent "Write-back Data Cache and Synchronization Control" pipeline station, this invention specifically sets up a display tick counter (CNT) related to the display tick count M2 of Part B pipeline at the first station of the parallel memory access pipeline. This CNT records the number of pipeline ticks without a global pause signal throughout the entire stage of Part B pipeline. Simultaneously, the display tick counter CNT is used to provide an explicit tick count label for each read memory access request entering the first station of Part B pipeline. This label, along with the write-back data, is sent from the subsequent pipeline register station in Part B to the "Write-back Data Cache and Synchronization Control" pipeline station in Part A pipeline of the memory access instruction, thereby achieving synchronous control of memory access read data.
[0046] In a specific application example, in step S1, this invention divides the memory access instruction pipeline clock into explicit memory access clocks and actual memory access clocks. The explicit memory access clock equals the memory access instruction execution pipeline clock visible to the programmer provided by the VLIW microprocessor instruction set architecture, plus the memory access instruction decoding pipeline clock. Assume the number of explicit memory access clocks for read memory access instructions is M (M is an integer greater than or equal to 4); the number of explicit memory access clocks for write memory access instructions is a positive integer less than M. The actual memory access clock is the actual memory access instruction execution clock after adding the clock delay clock caused by the global pause signal to the explicit memory access clock.
[0047] In a specific application example, in step S2, a read memory access instruction pipeline is divided into two parts, A and B, with explicit pipeline tick numbers of M1 and M2 respectively (M1 and M2 are both integers greater than or equal to 2). Since the write pipeline is included in the read pipeline, only the read instruction pipeline needs to be considered here.
[0048] In a preferred embodiment, in this example, the present invention further divides the two production lines according to the following principles:
[0049] (a) Meets the basic requirements of pipeline main frequency timing and function;
[0050] (b) The function from the start of the memory access unit's own memory access pause signal to the read data entering the "write-back data buffer and synchronization control" pipeline station is divided into the minimum pipeline cycle, which is the B part pipeline, to solve the memory access pause, complete the memory access decoding and memory access, data read and other functions.
[0051] (c) All other pipeline stations belong to the pipeline section A, and are distributed in the pipelines before the pipeline station from instruction decoding to generating its own memory access pause signal, as well as the pipelines immediately following the pipeline section B.
[0052] (d) In addition to the normal pipeline implementation, the A part pipeline adds a "write-back data caching and synchronization" pipeline station immediately following the B part pipeline, which is specifically designed to implement the caching and synchronization control of all memory access requests in the B pipeline to write back data.
[0053] (e) The sum of all explicit cycle times of the pipeline belonging to part A is M1, and the number of explicit cycle times of the pipeline belonging to part B is M2, and M1 + M2 = M.
[0054] In Part A, no memory access conflicts or memory misses occur within the pipeline stations, and the synchronization of each pipeline station is controlled only by the VLIW microprocessor's global stop signal (Global_Stall). This stage typically implements pipeline functions such as instruction decoding, address calculation, write-back data buffering and synchronization, and data write-back.
[0055] Section B of the pipeline begins at the station where the memory access unit generates its own global pause signal. Including memory access decoding, memory access, and other functional processing stations, this section of the pipeline has an explicit cycle time of M2. Section B may generate memory access pause signals such as parallel memory access conflicts or memory misses. It needs to resolve these conflicts or misses as quickly as possible to eliminate its own pause signals. Therefore, the output between stations in this section of the pipeline is no longer directly affected by the global pause signal, avoiding pipeline pauses that could affect or delay the elimination of its own memory access pause signals.
[0056] For example Figure 1 The following example illustrates the division of the memory access pipeline into parts A and B. Here, the explicit cycle number M2 of part B is 4. Besides the normal division according to the instruction pipeline function, the first station of part B is defined as the pipeline station where the memory access unit itself generates a memory access pause signal, such as... Figure 1 The middle station is the "Hit or Arbitration" station. Following the B-section pipeline, a "Write-back Data Cache and Synchronization" station is added specifically to implement write-back data caching and synchronization control functions. This station belongs to the A-section pipeline and uses the A-section station synchronization control method to achieve synchronization.
[0057] In this invention, the outputs of each pipeline station in section A employ a Global Stall hold protocol to achieve lock-step execution and synchronization between pipeline stations at each level in section A. Here, Global Stall is a logical OR (Global Stall) of various pipeline pause signals generated by the functional components of the VLIW microprocessor (including memory access pause signals from parallel memory access units). When this signal is sampled, the outputs of each station in section A maintain their original outputs. This lock-step execution synchronization control circuit has simple logic and low hardware cost.
[0058] This invention further provides a synchronization control circuit for a parallel memory access instruction pipeline. Based on the explicit memory access cycle time of the read memory access instruction, the read memory access instruction pipeline is divided into two parts, A and B, with explicit cycle times of parts A and B being M1 and M2, respectively; M1 and M2 are both integers greater than or equal to 2; including:
[0059] The write-back data buffer and synchronization pipeline, following the pipeline section B, includes a write-back data synchronization buffer T, a read-write state machine WR_FSM, and a two-way switch S. The write-back data synchronization buffer T is used to buffer the read data of memory access requests that have not reached the specified explicit tick count due to pipeline pauses caused by the Global_Stall signal. The read-write state machine WR_FSM realizes the reading and writing of T and controls the output of the two-way switch S based on the explicit tick count tag of the memory access request flowing into the station, the current explicit tick counter CNT value, and the Global_Stall status sampled by the pipeline.
[0060] The explicit tick counter (CNT) is set at the first station of the B-section pipeline. It is related to the pipeline depth M2 of the B-section and records the pipeline tick count for each parallel memory access instruction during the B-section pipeline stage when there is no global pause signal (Global_Stall). It is used to give each read memory access request entering the first station of the B-section pipeline its explicit tick count label, and it is sent out along with the write-back data to the subsequent pipeline registers in the B-section pipeline until it is sent to the write-back data buffer and synchronization station in the A-section pipeline.
[0061] In a preferred embodiment, in addition to performing normal instruction functions, the A section of the pipeline further adds a write-back data buffer and a synchronization pipeline station. Following the B section of the pipeline, this pipeline station sets up a write-back data synchronization buffer T with an explicit tick label based on the explicit tick number M2 of the B section pipeline. T consists of (M2+1) sets of registers to enable the B section pipeline to write back to the data buffer when a Global_Stall occurs. Thus, the A section, based on the inter-station hold protocol and a dedicated "write-back data buffer and synchronization" pipeline station, achieves synchronous control of the entire memory access pipeline, including both A and B sections.
[0062] like Figure 2 The image shows an application example of the write-back data buffer and synchronization pipeline. The write-back data buffer and synchronization pipeline includes a write-back data synchronization buffer T, a read-write state machine WR_FSM, and a two-way switch S. The write-back data synchronization buffer T is used to buffer the read data of memory access requests that have not reached the specified explicit tick count due to pipeline pauses caused by the Global_Stall signal. The read-write state machine WR_FSM realizes the reading and writing of T and controls the output of the two-way switch S based on the explicit tick count tag of the memory access request flowing into the station, the current explicit tick counter CNT value, and the Global_Stall status sampled by the pipeline.
[0063] The main data structure of the write-back data synchronization buffer T is as follows: Figure 3As shown, the system consists of (M2+1) isomorphic registers T0-TM2. Since the explicit tick count of pipeline B is M2, and because pipeline A uses the Global_Stall hold protocol, the maximum number of memory access instruction requests flowing into pipeline B when Global_Stall is active is M2. Adding the write-back data buffer and the 1 memory access instruction request that the synchronization pipeline needs to buffer when Global_Stall is active, the write-back data synchronization buffer T uses (M2+1) registers to buffer the write-back data for synchronization control. Each register in the write-back data synchronization buffer T, in addition to containing the data bits required for read instruction write-back, also adds an explicit tick count tag Count_Tag (Count_Tag0-Count_TagM2) for each read memory access data. The tag bit width is a positive integer L, where L is equal to log2(M2+1) rounded up. For example, M2=3, L=2; M2=4, L=3.
[0064] The write-back data synchronization buffer T is controlled by the read / write state machine WR_FSM of the pipeline station. WR_FSM reads and writes the corresponding T based on the Global_Stall status sampled by the station, the Count_Tag value of the memory access request data band, and the current explicit tick counter CNT value; simultaneously, it outputs memory access request data that meets the explicit tick count. The flowchart for WR_FSM control is as follows: Figure 4 As shown.
[0065] In a specific application example, except for the first station in Part B, which may generate its own memory access pause signal and needs to use the memory access pause signal to control the output of that station, the output of the other stations in Part B is not affected by the Global_Stall signal and is normally piped to the "write-back data cache and synchronization" pipeline station, thereby reducing the actual execution clock delay caused by Global_Stall.
[0066] In a preferred embodiment, the present invention further sets up an explicit tick counter (CNT) related to the pipeline depth M2 of section B in the first station of the pipeline B, recording the pipeline tick count of each parallel memory access instruction during the section B pipeline stage when there is no global pause signal Global_Stall. Simultaneously, the present invention uses this explicit tick counter (CNT) to assign an explicit tick count label to each read memory access request entering the first station of the section B pipeline, and this label, along with the write-back data, exits through subsequent pipeline registers in section B until it is sent to the write-back data buffer and synchronization station in section A pipeline. This facilitates buffering and output synchronization at the write-back data buffer and synchronization pipeline station after the instruction exits the section B pipeline.
[0067] In a specific application example, the explicit tick counter CNT is an explicit tick counter for the B-section instruction pipeline. It only counts the ticks of memory access requests in the B-section pipeline that do not have a global pause signal, i.e., the explicit ticks of memory access instruction requests in the B-section. This filters out the global pause ticks of memory access requests in the B-section pipeline. The count value is assigned to each memory access request entering the B-section pipeline at that tick and enters the subsequent pipeline along with the memory access data. Finally, it flows into the "write-back data buffer and synchronization" pipeline station and is provided to the state machine WR_FSM for use. WR_FSM determines whether the incoming memory access request meets the explicit tick count and selects the appropriate request data to be output or enter the buffer T.
[0068] See Figure 5 The above is a logic diagram of the explicit beat counter CNT in a specific application example. The counting register of the explicit beat counter CNT has a bit width of the positive integer L, where L is equal to log2(M2+1) rounded up. CNT starts counting from 0 and increments by 1. The maximum count output is M2. The CNT count is cleared to 0 when the count reaches M2. If the CNT output is not equal to M2 and the sampled Global_Stall is invalid, the count is incremented by 1 until the count reaches M2, at which point CNT is cleared to 0, and the same counting process begins again.
[0069] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.
Claims
1. A method for synchronously controlling a parallel memory access instruction pipeline, characterized in that, include: Step S1: Divide the memory access instruction pipeline clock into explicit memory access clock and actual memory access clock; The explicit memory access clock cycle equals the memory access instruction execution pipeline clock cycle visible to the programmer provided by the VLIW microprocessor instruction set architecture, plus the memory access instruction decoding pipeline clock cycle. Assume the explicit memory access clock cycle cycle for read memory access instructions is M, where M is an integer greater than or equal to 4; the explicit memory access clock cycle cycle for write memory access instructions is a positive integer less than M. The actual memory access clock cycle is the actual memory access instruction execution clock cycle after adding the clock cycle cycle for instruction execution delays caused by global pause signals to the explicit memory access clock cycle cycle. Step S2: Based on the explicit memory access cycle of the read memory access instruction, divide the memory access instruction pipeline into part A pipeline and part B pipeline, with the explicit memory access cycle numbers of part A pipeline and part B pipeline being M1 and M2, respectively. M1 and M2 are both integers greater than or equal to 2; and M1 + M2 = M; Step S3: Implement different control strategies for pipeline A and pipeline B: Within each station of pipeline A, control is only provided by the global pause signal from the VLIW microprocessor; the inter-station output of pipeline A maintains the output signal of the previous step upon encountering a global pause signal to achieve lock-step execution of pipeline A and complete the synchronous control of pipeline A; pipeline A also includes a write-back data buffer and synchronization control pipeline station, which is placed after pipeline B to implement the buffering and synchronization of memory access requests within pipeline B; pipeline B is only used to generate and process pipeline functions unaffected by the global pause signal, and is only responsible for handling and eliminating memory access pauses generated by the parallel memory access unit itself, completing data memory access, and reading data selection functions.
2. The synchronization control method for a parallel memory access instruction pipeline according to claim 1, characterized in that, The write-back data cache and synchronization control pipeline station sets up a write-back data synchronization cache T with an explicit memory access tick label according to the explicit memory access tick number M2 of the B part pipeline. The write-back data synchronization cache T is composed of (M2+1) sets of registers to realize the write-back of the data cache when the B part pipeline occurs in Global_Stall. The Global_Stall signal is a global pause signal that originates from various functional units of the VLIW microprocessor and causes the entire pipeline to pause.
3. The synchronization control method for a parallel memory access instruction pipeline according to claim 1, characterized in that, The first station of the B-section pipeline is equipped with an explicit memory access clock counter (CNT) related to the explicit memory access clock count M2 of the B-section pipeline. This CNT records the number of pipeline clock cycles without a global pause signal throughout the entire B-section pipeline. The explicit memory access clock counter CNT is used to assign an explicit memory access clock count tag to each read memory access request entering the first station of the B-section pipeline. This tag, along with the write-back data, is sent to the write-back data buffer and synchronization control pipeline station at subsequent pipeline registers in the B-section pipeline to achieve synchronous control of memory access read data.
4. A synchronization control circuit for a parallel memory access instruction pipeline, characterized in that, Based on the explicit memory access cycle of the read memory access instruction, the memory access instruction pipeline is divided into part A pipeline and part B pipeline, with the explicit memory access cycle numbers of part A pipeline and part B pipeline being M1 and M2, respectively. M1 and M2 are both integers greater than or equal to 2; including: The write-back data buffer and synchronization pipeline in section A, which follows section B, includes a write-back data synchronization buffer T, a read-write state machine WR_FSM, and a two-way switch S. The write-back data synchronization buffer T is used to buffer the read data of memory access requests that have not reached the specified explicit memory access tick count due to pipeline pauses caused by the global pause signal Global_Stall. The read-write state machine WR_FSM realizes the read and write of the write-back data synchronization buffer T and controls the output of the two-way switch S based on the explicit memory access tick count tag of the memory access request flowing into the write-back data buffer and synchronization pipeline, the current explicit memory access tick counter CNT value, and the global pause signal Global_Stall status sampled by the write-back data buffer and synchronization pipeline. The explicit memory access clock counter (CNT) is set at the first station of the B-section pipeline. It is related to the depth of the B-section pipeline and records the number of pipeline clock cycles for each parallel memory access instruction during the B-section pipeline stage when there is no global pause signal (Global_Stall). It is used to give each read memory access request entering the first station of the B-section pipeline its explicit memory access clock count label, and it is sent out along with the write-back data to the subsequent pipeline registers in the B-section pipeline until it is sent to the write-back data buffer and synchronization pipeline in the A-section pipeline.
5. The synchronization control circuit for the parallel memory access instruction pipeline according to claim 4, characterized in that, The write-back data synchronization buffer T consists of (M2+1) homogeneous registers T0-TM2. In addition to containing the data bit width required for the read instruction write-back, each register in the write-back data synchronization buffer T also adds an explicit memory access clock counter tag Count_Tag for each read memory access data. The write-back data synchronization buffer T is controlled by the read-write state machine WR_FSM of the write-back data buffer and the synchronization pipeline. WR_FSM performs read and write operations on the corresponding write-back data synchronization buffer T according to the Global_Stall status sampled by the write-back data buffer and the synchronization pipeline, the Count_Tag value of the memory access request data band, and the current explicit memory access clock counter CNT value.
6. The synchronization control circuit for the parallel memory access instruction pipeline according to claim 4, characterized in that, The explicit memory access clock counter CNT has a count register width of a positive integer L, where L is equal to log2(M2+1) rounded up. CNT starts counting from 0 and increments by 1. The maximum count output is M2. When reset or when the count reaches M2, the CNT count value is cleared to 0. If the CNT output is not equal to M2 and the Global_Stall sample is invalid, the clock increments by 1 until the count value reaches M2, at which point CNT is cleared to 0, and the same counting process begins again.