Switching control methods, devices, equipment and storage media

Abstract

This invention provides a switching control method, apparatus, device, and storage medium. The method includes: responding to user input in the BIOS settings interface, controlling the BIOS to enter a target mode; adjusting the BIOS token parameters according to the target mode; and controlling the BIOS to send a target notification to a CPLD according to the token parameters, so that the CPLD controls a first timer to stop the switching timing according to the target notification. This invention identifies situations where the BIOS is in certain special modes causing delayed startup under a normal dual-BIOS Flash mechanism by adjusting the BIOS token parameters. This avoids the CPLD waiting for timeouts in these special modes and performing forced switching, which would cause serious interference to the BIOS operation in these modes, thereby ensuring the normal operation of the device.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a switching control method, apparatus, device, and storage medium. Background Technology

[0002] With the continuous development of information technology, in order to improve the reliability of server startup, two Basic Input Output System flash (BIOS flash) chips are usually designed on the server motherboard to avoid the situation where the startup fails due to the damage of a single BIOS flash.

[0003] Existing BIOS flash switching schemes include: when the entire device is powered on, after the CPLD receives the power on signal, it powers on the CPU and starts a countdown. If a boot success signal is not received from the main BIOS before the countdown ends, it is considered a timeout and the system switches to the backup secondary BIOS for booting.

[0004] However, existing BIOS flash switching solutions have the following problems: Under normal circumstances, the BIOS can complete the boot and operating system boot process within 2 minutes. However, under certain specific circumstances, such as when debug mode is enabled, the BIOS will print detailed boot logs via serial port during the self-test phase. These logs are used by R&D and testing personnel for problem localization and analysis. The log output can take up to 30-40 minutes, which seriously slows down the boot time. Therefore, under the normal dual-Flash mechanism, the BIOS cannot complete the boot process and send a boot success signal to the CPLD in a timely manner. This causes the CPLD to wait for a timeout and force a switch to the backup secondary flash to restart, thereby interrupting the printout of the debug log and causing serious interference to debug-related tests. Therefore, the existing BIOS flash switching solution cannot cope with the timeout caused by certain specific circumstances under the normal dual-BIOS mechanism, which causes the CPLD to wait for a timeout and force a switch to the backup secondary BIOS to restart, resulting in serious interference to the operation of the main BIOS. Summary of the Invention

[0005] The purpose of this invention is to provide a switching control method, apparatus, device, and storage medium to solve the problem that existing BIOS flash switching schemes cannot cope with timeouts occurring under certain specific circumstances in a normal dual-BIOS mechanism, causing the CPLD to wait for timeout and forcibly switch to the backup secondary BIOS to restart, resulting in serious interference with the operation of the primary BIOS. The specific technical solution is as follows:

[0006] In a first aspect of the present invention, a switching control method is provided, characterized in that the method comprises:

[0007] In response to user input in the BIOS settings interface, the BIOS is controlled to enter the target mode;

[0008] Adjust the BIOS token parameters according to the target mode;

[0009] The BIOS is controlled to send a target notification to the CPLD based on the token parameter, so that the CPLD controls the first timer to stop switching timing based on the target notification.

[0010] Optionally, after adjusting the BIOS token parameters according to the target mode, the method further includes:

[0011] The first timer is started according to the power-on signal;

[0012] If the switching time of the first timer is detected to be less than a first preset time, the BIOS is controlled to create a boot preparation event;

[0013] The BIOS token parameter is obtained based on the prepared startup event.

[0014] Optionally, the boot preparation event is used to monitor the BIOS boot process.

[0015] Optionally, after controlling the BIOS to send the target notification to the CPLD according to the token parameter, the method further includes:

[0016] If the CPLD stops the switching timer, a second timer is started;

[0017] If the timing of the second timer is detected to be greater than the second preset time, a notification to continue the switching timing is sent to the CPLD, so that the CPLD controls the first timer to continue the switching timing.

[0018] Optionally, after sending a notification to the CPLD to continue executing the switching timer when the timing of the second timer is detected to be greater than a second preset time, the method further includes:

[0019] Obtain the switching timing of the first timer;

[0020] If the switching time of the first timer is detected to be greater than the first preset time, the BIOS is controlled to switch from the main BIOS to the secondary BIOS.

[0021] Optionally, after starting the second timer upon detecting that the CPLD has stopped the switching timer, the method further includes:

[0022] If the timing of the second timer is detected to be less than the second preset time, the BIOS boot information is obtained;

[0023] Once the BIOS boot process is confirmed to be complete, the CPLD register is adjusted so that the CPLD controls the first timer to end the switching timing.

[0024] Optionally, before controlling the BIOS to enter the target mode in response to user input at the BIOS setup interface, the method further includes:

[0025] Receive the power-on signal from the target device;

[0026] The CPLD is controlled to start the first timer according to the power-on signal.

[0027] In a second aspect of the invention, a switching control device is also provided, characterized in that it comprises:

[0028] The first control module is used to control the BIOS to enter the target mode in response to user input in the BIOS settings interface of the basic input / output system;

[0029] An adjustment module is used to adjust the token parameters of the BIOS according to the target mode;

[0030] The first sending module is used to control the BIOS to send a target notification to the CPLD according to the token parameter, so that the CPLD controls the first timer to stop switching timing according to the target notification.

[0031] In a third aspect of the present invention, a communication device is also provided, comprising: a transceiver, a memory, a processor, and a program stored in the memory and executable on the processor;

[0032] The processor is used to read the program in the memory to execute any of the switching control methods described above.

[0033] In a fourth aspect of the invention, a computer-readable storage medium is also provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform any of the switching control methods described above.

[0034] The switching control method provided in this invention responds to user input in the BIOS settings interface, controls the BIOS to enter a target mode, adjusts the BIOS token parameters according to the target mode, and controls the BIOS to send a target notification to the CPLD based on the token parameters. This causes the CPLD to control the first timer to stop the switching timer based on the target notification. This invention identifies situations where the BIOS is in certain special modes causing delayed startup under a normal dual-BIOS Flash mechanism by adjusting the BIOS token parameters. This avoids the CPLD waiting for timeouts in these special modes and performing forced switching, which would severely interfere with the main BIOS operation in these modes, thus ensuring the normal operation of the device. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0036] Figure 1 The step flow of the switching control method provided in the embodiments of the present invention Figure 1 ;

[0037] Figure 2 This is a flowchart of the switching control method provided in the embodiments of the present invention. Figure 2 ;

[0038] Figure 3 This is a flowchart of the switching control method provided in the embodiments of the present invention. Figure 3 ;

[0039] Figure 4 This is a schematic diagram of the structure of a switching control device provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of the structure of a communication device provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0042] Reference Figure 1The flowchart of the switching control method provided in the embodiment of the present invention is shown. Figure 1 The method may include:

[0043] Step 101: In response to user input in the BIOS setup interface of the Basic Input / Output System, control the BIOS to enter the target mode.

[0044] This invention addresses the problem of determining BIOS malfunction based on boot time, which can be disrupted by special circumstances that extend boot time. These special circumstances can be configured via BIOS settings, allowing the BIOS to enter a target mode in response to user input. For example, the user can enter the BIOS Setup interface, input information, and enable the target mode. This target mode can be Debug mode. In Debug mode, the BIOS prints detailed boot logs via serial port during the POST phase. These logs are used by R&D and testing personnel for problem localization and analysis. Log output can take 30-40 minutes, significantly slowing down boot time. Under normal dual-Flash mechanisms, the BIOS may fail to complete boot and send a BootOK signal to the CPLD, causing the CPLD to time out and force a switch to the backup Flash for restart, interrupting debug log printing and severely interfering with debug-related tests. This invention addresses this specific situation.

[0045] It should be noted that before the user inputs information in the BIOS setup interface, the BIOS startup process needs to be monitored and timed. Therefore, a first timer is started based on the power-on signal of the target device. Generally, the first timer is a countdown timer. By collecting historical startup information from the BIOS multiple times, a maximum estimated startup time is obtained, such as 1 minute. The countdown is then performed based on this time. Alternatively, it can be set as a normal timer with a threshold. When the countdown reaches 0 or the threshold is reached, a corresponding operation is performed. This invention does not specifically limit the timer. The specific steps for starting the timer via the power-on signal include:

[0046] Receive the power-on signal from the target device;

[0047] The CPLD is controlled to start the first timer based on the power-on signal.

[0048] The target device refers to any device that uses dual BIOS FLASH as a boot failure response mechanism, which can be a switch or a server; this invention does not specifically limit this. The BIOS is an immutable boot program etched onto the motherboard ROM chip. The BIOS is responsible for calculating the Power On Self Test (POST) and the system boot program, thus it is the first program after the switch system starts. Due to its immutability, the program is stored in the ROM chip and retains its original settings even after power failure. The main function of the BIOS is to control the basic programs after the switch or server device starts, including hard drive drivers (such as prioritizing hard drive boot, network boot, or USB boot disk during installation), serial port output settings, memory, and related devices. A CPLD is a device developed from Programmable Array Logic (PAL) and Generic Array Logic (GAL) devices. It is relatively large in scale and complex in structure, belonging to the category of large-scale integrated circuits. It is a type of digital integrated circuit where users construct their own logic functions according to their needs.

[0049] It should be noted that the CPLD interacts with the BIOS via I2C (Inter-Integrated Circuit, two-wire serial bus). I2C is a simple, bidirectional, two-wire synchronous serial bus that requires only two wires to transmit information between devices connected to the bus. The working principle of I2C is that the master device initiates the bus data transmission and generates a clock to enable the transmission. At this time, any addressed device is considered a slave device. The master-slave and transmit-receive relationships on the bus are not constant, but depend on the direction of data transmission at this time.

[0050] Step 102: Adjust the BIOS token parameters according to the target mode.

[0051] In this embodiment of the invention, after entering information in the BIOS settings interface, the system enters the target mode. During the operation of the target mode, the BIOS token parameter changes. For example, when the target mode is Debug mode, the BIOS token parameter is set to 1; when the target mode is POST mode, the BIOS token parameter is set to 2. By observing these token parameter values, the current operating information of the BIOS can be obtained.

[0052] The token is a string generated by the server to serve as a pass for client requests. Upon the first login, the server generates a token and returns it to the client. Subsequent requests only require this token, eliminating the need for the username and password. This reduces server load, minimizes database queries, and enhances server robustness. In this embodiment, it is used to uniquely identify a target pattern.

[0053] Step 103: Control the BIOS to send a target notification to the CPLD according to the token parameter, so that the CPLD controls the first timer to stop switching timing according to the target notification.

[0054] In this embodiment of the invention, upon detecting a change in the token parameter, the BIOS's current operating information is obtained based on the assigned value. When it is determined that the BIOS's boot time will change due to the target mode's operation, a target notification needs to be sent to the CPLD so that the CPLD can control the first timer to stop switching timings based on the target notification. Specifically, the target notification is a signal sent to the CPLD to stop the switching timings.

[0055] The first timer is controlled by a CPLD, but this first timer can be directly installed on the CPLD or it can be an intermediate device connected to the CPLD. This invention does not make any specific limitations here.

[0056] Furthermore, when the user does not input information in the BIOS interface, allowing the BIOS to run in normal mode, the CPLD starts the first timer when the target device is powered on. At the same time, the BIOS creates a boot preparation event to monitor the BIOS boot process. When the first timer's switching countdown reaches 0 or the threshold is reached, and a BIOS boot completion signal has not been received, the CPLD will be notified to switch the BIOS from the primary BIOS to the secondary BIOS. Simultaneously, a prompt message will be sent to the display screen to remind staff to troubleshoot the fault in a timely manner. If the BIOS boots up before the first timer's switching countdown reaches 0 or the threshold is reached, the boot completion event will be called, the CPLD register will be set, and the CPLD will be notified that the boot is complete.

[0057] The switching control method provided in this invention responds to user input in the BIOS settings interface, controls the BIOS to enter a target mode, adjusts the BIOS token parameters according to the target mode, and controls the BIOS to send a target notification to the CPLD based on the token parameters. This causes the CPLD to control the first timer to stop the switching timer based on the target notification. This invention identifies situations where the BIOS is in certain special modes causing delayed startup under a normal dual-BIOS Flash mechanism by adjusting the BIOS token parameters. This avoids the CPLD waiting for timeouts in these special modes and performing forced switching, which would severely interfere with the main BIOS operation in these modes, thus ensuring the normal operation of the device.

[0058] Reference Figure 2 The flowchart of the switching control method provided in the embodiment of the present invention is shown. Figure 2 The switching control method disclosed in this embodiment has the same steps as described above. Figure 1 The two methods are essentially the same, except that after step 102, the following may also be included:

[0059] Step 201: Start the first timer according to the power-on signal.

[0060] In this embodiment of the invention, when the target device is powered on, it sends a Power On signal to the CPLD, and the CPLD starts the first timer based on this signal. It should be noted that the CPLD starting the first timer and the BIOS entering the target mode are two processes that occur simultaneously.

[0061] Step 202: If the switching time of the first timer is detected to be less than the first preset time, control the BIOS to create a boot preparation event.

[0062] In this embodiment of the invention, the first preset time is the time for judging whether the BIOS startup is normal. If the BIOS completes startup within this time, it is considered that the BIOS startup is normal; if the BIOS fails to complete startup within this time, it is considered that the BIOS startup is abnormal. During the monitoring of BIOS completion, the BIOS creates a ReadyToBoot event to monitor whether the BIOS mode changes and to monitor the BIOS startup process. For example, the first preset time is set to 1 minute, and the first timer is a countdown timer. At this time, the countdown timer shows 50 seconds, and the switching time is calculated to be 10 seconds. Since 10 seconds is less than 1 minute, the CPLD has not yet judged the BIOS and performed any operation. At this time, the BIOS can be controlled to create a ReadyToBoot event to monitor and track the BIOS mode and startup status, thereby obtaining BIOS parameter information. When the countdown timer shows 0 seconds, the switching time is calculated to be 1 minute or more. At this time, the CPLD has already completed the operation of switching or not switching the BIOS based on the timing result, and further monitoring is meaningless.

[0063] Step 203: Obtain the BIOS token parameter based on the ready-to-boot event.

[0064] This invention monitors the BIOS boot process based on the boot preparation event and can also obtain various BIOS settings parameters, including token parameters.

[0065] It should be noted that the BIOS's ready-to-boot event will trigger different events depending on the token parameter. For example, when the obtained token parameter is 1, the BIOS's ready-to-boot event will determine that the BIOS is in Debug mode based on the token parameter 1, and will trigger an event to notify the CPLD to stop the switching timer. When the obtained token parameter is 2, the BIOS's ready-to-boot event will determine that the BIOS is in POST mode based on the token parameter 2, and will also trigger an event to notify the CPLD to stop the switching timer.

[0066] The switching control method provided in this invention responds to user input in the BIOS settings interface, controls the BIOS to enter a target mode, adjusts the BIOS token parameters according to the target mode, and controls the BIOS to send a target notification to the CPLD based on the token parameters. This causes the CPLD to control the first timer to stop the switching timer based on the target notification. This invention identifies situations where the BIOS is in certain special modes causing delayed startup under a normal dual-BIOS Flash mechanism by adjusting the BIOS token parameters. This avoids the CPLD waiting for timeouts in these special modes and performing forced switching, which would severely interfere with the main BIOS operation in these modes, thus ensuring the normal operation of the device.

[0067] Reference Figure 3 The flowchart of the switching control method provided in the embodiment of the present invention is shown. Figure 3 The switching control method disclosed in this embodiment has the same steps as described above. Figure 1 The two methods are essentially the same, except that after step 103, the following may also be included:

[0068] Step 301: If the CPLD stops switching timers, start the second timer.

[0069] In this embodiment of the invention, because the BIOS is in a special mode, the CPLD is controlled to stop timing. However, if the BIOS does malfunction, such as image corruption or link interruption, even if the BIOS boot event is prolonged due to the special mode, it will not be prolonged indefinitely. Therefore, after the CPLD controls the first timer to stop switching timing, the second timer is started to determine the end time of this special mode.

[0070] It should be noted that since the second timer is used to monitor the BIOS boot status in special modes, a countdown or time threshold can be set based on the maximum estimated boot time of the BIOS in that special mode. For example, if historical data shows that the maximum estimated boot time of the BIOS in a certain special mode is 25 minutes, then the second timer can be set to count down in 25 minutes, either as a countdown or a normal countdown.

[0071] In addition, this embodiment of the invention also divides the timing of the second timer. When the timing of the second timer is detected to be less than a second preset time, the BIOS boot information is obtained, and it is determined that the BIOS is normal. At this time, a boot success event is called back, the CPLD register is set, and the CPLD is informed of the BIOS boot completion based on the changes in the bits in the register, so that the CPLD controls the first timer to end the switching timing. The specific implementation steps include:

[0072] If the timing of the second timer is detected to be less than the second preset time, obtain the BI OS startup information;

[0073] Once the BIOS boot process is confirmed to be complete, adjust the CPLD register so that the CPLD controls the first timer to end the switching timer.

[0074] The aforementioned successful boot event and ready-to-boot event can both be invoked through the interface. A certain bit in the CPLD register is specified to mark the successful boot event of the BIOS. If the BIOS boots successfully, this bit in the CPLD register will be set to 1; if the BIOS boots fail, this bit in the CPLD register will be set to 0.

[0075] Step 302: If the timing of the second timer is detected to be greater than the second preset time, a notification to continue the switching timing is sent to the CPLD so that the CPLD controls the first timer to continue the switching timing.

[0076] In this embodiment of the invention, the second preset time is set according to the BIOS boot time in a special mode. The historical boot times of the BIOS in multiple special modes are collected, and the maximum estimated boot time of the BIOS is calculated based on these historical boot times as the second preset time.

[0077] If the second timer's countdown exceeds the second preset time and no BIOS boot success message is received, a BIOS malfunction is assumed, triggering an event that sends a "continue execution switching timer" notification to the CPLD. This allows the CPLD to control the first timer to continue executing the switching timer. If a timeout occurs while the CPLD continues executing the switching timer, it will notify the CPLD to switch the BIOS from the primary BIOS to the secondary BIOS. Simultaneously, a prompt message will be sent to the display screen to alert staff to troubleshoot the fault promptly.

[0078] It should be noted that if the BIOS boot completion information is obtained when the second timer's countdown time is less than the second preset time, the BIOS boot completion event will be invoked. Then, the CPLD register will be set, and the changes in the bits in the register will inform the CPLD that the BIOS boot is complete. This will cause the CPLD to control the first timer to stop switching. The specific implementation steps include:

[0079] If the timing of the second timer is detected to be less than the second preset time, obtain the BI OS startup information;

[0080] Once the BIOS boot process is confirmed to be complete, adjust the CPLD register so that the CPLD controls the first timer to end the switching timer.

[0081] The first and second timers include, but are not limited to, at least one of the following: an electromagnetic dot timer, a persistence timer, a reaction timer, and a server timer. After the timer completes, it needs to be reset to its initial state using a clear command for future operation.

[0082] The switching control method provided in this embodiment of the invention, in response to user input in the BIOS settings interface of the Basic Input / Output System (BIOS), controls the BIOS to enter a target mode, adjusts the BIOS token parameters according to the target mode, and controls the BIOS to send a target notification to the CPLD based on the token parameters. This causes the CPLD to control the first timer to stop the switching timer based on the target notification. This embodiment of the invention identifies situations where the BIOS is in certain special modes causing delayed startup under a normal dual-BIOS Flash mechanism by adjusting the BIOS token parameters. This avoids the CPLD waiting for timeouts in these special modes and performing forced switching, which would cause serious interference to the main BIOS operation in these modes, thus ensuring the normal operation of the device. Simultaneously, a second timer monitors the BIOS startup process in special modes to determine whether the delay in the main BIOS is due to a special mode or a malfunction, and then takes corresponding actions to ensure the normal operation of the device.

[0083] Reference Figure 4 The diagram shows a structural schematic of a switching control device provided in an embodiment of the present invention, such as... Figure 4 As shown, the device may include:

[0084] The first control module 401 is used to control the BIOS to enter the target mode in response to the user's input in the BIOS settings interface of the basic input / output system;

[0085] Adjustment module 402 is used to adjust the token parameters of the BIOS according to the target mode;

[0086] The first sending module 403 is used to control the BIOS to send a target notification to the CPLD according to the token parameter, so that the CPLD controls the first timer to stop switching timing according to the target notification.

[0087] Optionally, the switching control device further includes:

[0088] The first startup module is used to start the first timer according to the power-on signal;

[0089] The second control module is used to control the BIOS to create a boot preparation event when the switching time of the first timer is detected to be less than a first preset time.

[0090] The first acquisition module is used to acquire the token parameter of the BIOS based on the prepared startup event.

[0091] Optionally, the boot preparation event is used to monitor the BIOS boot process.

[0092] Optionally, the switching control device further includes:

[0093] The second startup module is used to start a second timer when the CPLD stops the switching timer.

[0094] The second sending module is used to send a notification to the CPLD to continue executing the switching timing when the timing time of the second timer is detected to be greater than the second preset time, so that the CPLD controls the first timer to continue executing the switching timing.

[0095] The second acquisition module is used to acquire the switching timing of the first timer;

[0096] The third control module is used to control the BIOS to switch from the main BIOS to the secondary BIOS when the switching time of the first timer is detected to be greater than a first preset time.

[0097] The third acquisition module is used to acquire the BIOS boot information when the timing time of the second timer is detected to be less than the second preset time.

[0098] The fourth control module is used to adjust the CPLD register when it is determined that the BIOS boot is complete, so that the CPLD controls the first timer to end the switching timing.

[0099] The receiving module is used to receive the power-on signal of the target device;

[0100] The fifth control module is used to control the CPLD to start the first timer according to the power-on signal.

[0101] The switching control method provided in this embodiment of the invention, in response to user input in the BIOS settings interface of the Basic Input / Output System (BIOS), controls the BIOS to enter a target mode, adjusts the BIOS token parameters according to the target mode, and controls the BIOS to send a target notification to the CPLD based on the token parameters. This causes the CPLD to control the first timer to stop the switching timer based on the target notification. This embodiment of the invention identifies situations where the BIOS is in certain special modes causing delayed startup under a normal dual-BIOS Flash mechanism by adjusting the BIOS token parameters. This avoids the CPLD waiting for timeouts in these special modes and performing forced switching, which would cause serious interference to the main BIOS operation in these modes, thus ensuring the normal operation of the device. Simultaneously, a second timer monitors the BIOS startup process in special modes to determine whether the delay in the main BIOS is due to a special mode or a malfunction, and then takes corresponding actions to ensure the normal operation of the device.

[0102] This invention also provides a communication device, such as... Figure 5 As shown, it includes a processor 501, a communication interface 502, a memory 503, and a communication bus 504, wherein the processor 501, the communication interface 502, and the memory 503 communicate with each other through the communication bus 504.

[0103] Memory 503 is used to store computer programs;

[0104] When processor 501 executes the program stored in memory 503, it performs the following steps:

[0105] In response to user input in the BIOS settings interface, the BIOS is controlled to enter the target mode;

[0106] Adjust the BIOS token parameters according to the target mode;

[0107] The BIOS is controlled to send a target notification to the CPLD based on the token parameter, so that the CPLD controls the first timer to stop switching timing based on the target notification.

[0108] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0109] The communication interface is used for communication between the aforementioned terminal and other devices.

[0110] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0111] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0112] The present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by the processor of an electronic device, the electronic device is able to perform the access control method of the foregoing embodiments.

[0113] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0114] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. The structure required to construct such a system is readily apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0115] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0116] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0117] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0118] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0119] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0120] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0121] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0122] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0123] It should be noted that the various data-related processes in the embodiments of this application are carried out in compliance with the relevant data protection laws and policies of the country where the location is located, and with the authorization granted by the owner of the corresponding device.

Claims

1. A switching control method, characterized in that, The method includes: In response to user input at the BIOS setup interface of the Basic Input / Output System, the BIOS is controlled to enter the target mode; The BIOS token parameters are adjusted according to the target mode; the BIOS token parameters change as the target mode is run. The BIOS is controlled to send a target notification to the CPLD according to the token parameter, so that the CPLD controls the first timer to stop switching timing according to the target notification; After controlling the BIOS to send the target notification to the CPLD according to the token parameter, the method further includes: If the CPLD stops the switching timer, a second timer is started; the second timer is used to monitor the boot status of the BIOS in the target mode. If the timing of the second timer is detected to be greater than the second preset time, a notification to continue the switching timing is sent to the CPLD, so that the CPLD controls the first timer to continue the switching timing.

2. The method according to claim 1, characterized in that, After adjusting the BIOS token parameters according to the target mode, the method further includes: The first timer is started according to the power-on signal; If the switching time of the first timer is detected to be less than a first preset time, the BIOS is controlled to create a boot preparation event; The BIOS token parameter is obtained based on the prepared startup event.

3. The method according to claim 2, characterized in that, The boot preparation event is used to monitor the BIOS boot process.

4. The method according to claim 1, characterized in that, After sending a notification to the CPLD to continue executing the switching timer when the second timer's timing duration is detected to be greater than a second preset time, the method further includes: Obtain the switching timing of the first timer; If the switching time of the first timer is detected to be greater than the first preset time, the BIOS is controlled to switch from the main BIOS to the secondary BIOS.

5. The method according to claim 1, characterized in that, After starting the second timer upon detecting that the CPLD has stopped the switching timer, the method further includes: If the timing of the second timer is detected to be less than the second preset time, the BIOS boot information is obtained; Once the BIOS boot process is confirmed to be complete, the CPLD register is adjusted so that the CPLD controls the first timer to end the switching timing.

6. The method according to claim 1, characterized in that, Before controlling the BIOS to enter the target mode in response to user input at the BIOS setup interface, the method further includes: Receive the power-on signal from the target device; The CPLD is controlled to start the first timer according to the power-on signal.

7. A switching control device, characterized in that, include: The first control module is used to control the BIOS to enter the target mode in response to user input in the BIOS settings interface of the basic input / output system; An adjustment module is used to adjust the token parameters of the BIOS according to the target mode; the token parameters of the BIOS change as the target mode is run. The first sending module is used to control the BIOS to send a target notification to the CPLD according to the token parameter, so that the CPLD controls the first timer to stop switching the timing according to the target notification; The switching control device further includes: The second startup module is used to start a second timer when the CPLD stops the switching timer; the second timer is used to monitor the startup status of the BIOS in the target mode. The second sending module is used to send a notification to the CPLD to continue executing the switching timing when it is detected that the timing of the second timer is greater than the second preset time, so that the CPLD controls the first timer to continue executing the switching timing.

8. A communication device, characterized in that, include: A transceiver, a memory, a processor, and a program stored in the memory and executable on the processor; The processor is used to read a program from the memory to implement the steps in the switching control method as described in any one of claims 1-6.

9. A readable storage medium for storing a program, characterized in that, When the program is executed by the processor, it implements the steps of the switching control method as described in any one of claims 1-6.

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