Thread priority adjustment method and apparatus, electronic device, and storage medium

Abstract

The present disclosure relates to a thread priority adjustment method and device, electronic equipment and storage medium. The method comprises. By using the embodiments of the present disclosure, the thread lock owner in the thread scheduling scene corresponding to the multi-thread lock can be quickly and accurately located. In the case that the second thread priority corresponding to the second thread is less than the first thread priority corresponding to the first thread, the thread priority of the second thread currently owning the target thread lock is increased, so that the second thread can quickly execute the task and release the lock. In turn, the blocking time of the high-priority first thread can be effectively reduced, the thread priority inversion problem can be quickly solved, and the program running performance can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a thread priority adjustment method, apparatus, electronic device, and storage medium. Background Technology

[0002] In the field of computing, during application operation, a large number of threads run simultaneously, and these threads share computing resources. Since the computing resources allocated to threads by each device at any given time are limited, related technologies assign a thread priority to each thread. Based on the thread priority, each thread receives different computing resources. Due to the sharing of resources among multiple threads, locking strategies are used to ensure the atomicity of data accessed by different threads in order to guarantee application stability. However, in this approach, if a low-priority thread is processing locked data, and a high-priority thread also wants to access this data, the high-priority thread will be blocked by the low-priority thread, resulting in thread priority inversion, the high-priority thread being blocked for a long time, and a decrease in program performance. Summary of the Invention

[0003] This disclosure provides a thread priority adjustment method, apparatus, electronic device, and storage medium to at least solve the problems in related technologies such as thread priority inversion, high-priority threads being blocked for extended periods, and degraded program performance. The technical solution of this disclosure is as follows:

[0004] According to one aspect of the embodiments of this disclosure, a thread priority adjustment method is provided, including:

[0005] During the execution of the target program, the thread state of the first thread corresponding to the target program is detected. The first thread is a thread with a thread priority greater than or equal to a preset priority.

[0006] If the thread is detected to be in a blocked state, the target lock type of the target thread lock corresponding to the first thread is determined;

[0007] Based on the target lock type, determine the second thread that owns the target thread lock;

[0008] If the priority of the second thread is lower than the priority of the first thread, the priority of the second thread is adjusted to the priority of the third thread; the priority of the third thread is higher than the priority of the second thread.

[0009] In an optional embodiment, the second thread that determines the target thread lock based on the target lock type includes:

[0010] When the target lock type is a single-owner lock type, the lock address information and the first address offset of the target thread lock are obtained, and the first address offset is a preset offset between the second thread's second thread identifier information and the lock address information;

[0011] Based on the lock address information and the first address offset, the second thread identification information is generated;

[0012] The second thread is determined based on the second thread identifier information.

[0013] In an optional embodiment, the second thread that determines the target thread lock based on the target lock type includes:

[0014] When the target lock type is a multi-owner lock type, the first owner identifier information of the first thread, the first thread identifier information of the first thread, the lock address information and the second address offset of the target thread lock are obtained, and the second address offset is a preset offset between the second owner identifier information of the second thread and the lock address information.

[0015] Based on the lock address information and the second address offset, the second owner identification information is generated;

[0016] Determine the identifier offset between the second owner identifier information and the first owner identifier information;

[0017] Based on the identifier offset and the first thread identifier information, the second thread identifier information of the second thread is generated;

[0018] The second thread is determined based on the second thread identifier information.

[0019] In an optional embodiment, the second thread that determines the target thread lock based on the target lock type includes:

[0020] When the target lock type is an ownerless lock type, first preset mapping information and lock address information of the target thread lock are obtained. The first preset mapping information is the correspondence between the lock address information and the second thread identifier information of the second thread when the second thread owns the target thread lock.

[0021] Based on the first preset mapping information and the lock address information, the second thread identification information is generated;

[0022] The second thread is determined based on the second thread identifier information.

[0023] In an optional embodiment, determining the target lock type of the target thread lock corresponding to the first thread includes:

[0024] Determine the target task identifier information of the target task executed by the first thread;

[0025] Based on the target task identification information, the target lock type is determined.

[0026] In an optional embodiment, the target task identification information for determining the target task executed by the first thread includes:

[0027] Obtain the target storage address information from the register corresponding to the first thread, wherein the target storage address information is the storage address information of the target task identifier information of the target task;

[0028] Based on the target storage address information, obtain the target task identifier information.

[0029] In an optional embodiment, determining the target lock type based on the target task identification information includes:

[0030] Obtain second preset mapping information, which represents the correspondence between lock identifier information corresponding to multiple thread locks and task identifier information corresponding to multiple tasks;

[0031] Based on the second preset mapping information, the target lock identifier information corresponding to the target task identifier information is determined from the lock identifier information of the various thread locks;

[0032] The thread lock corresponding to the target lock identifier information is taken as the target thread lock;

[0033] The lock type of the target thread lock is used as the target lock type.

[0034] In an optional embodiment, after adjusting the priority of the second thread to the priority of the third thread, the method further includes:

[0035] If the second thread releases the target thread lock, the priority of the third thread is adjusted to the priority of the second thread.

[0036] According to another aspect of the embodiments of this disclosure, a thread priority adjustment device is provided, comprising:

[0037] The thread state detection module is configured to detect the thread state of the first thread corresponding to the target program during the execution of the target program. The first thread is a thread with a thread priority greater than or equal to a preset priority.

[0038] The target lock type determination module is configured to determine the target lock type of the target thread lock corresponding to the first thread when the thread state is detected to be blocked.

[0039] The owner thread determination module is configured to execute a second thread that owns the target thread lock based on the target lock type.

[0040] The second thread priority adjustment module is configured to adjust the priority of the second thread to the priority of the third thread when the priority of the second thread is lower than the priority of the first thread; wherein the priority of the third thread is greater than the priority of the second thread.

[0041] In an optional embodiment, the owner thread determination module includes:

[0042] The first information acquisition unit is configured to acquire the lock address information and the first address offset of the target thread lock when the target lock type is a single owner lock type. The first address offset is a preset offset between the second thread identifier information of the second thread and the lock address information.

[0043] The first identification information generation unit is configured to generate the second thread identification information based on the lock address information and the first address offset;

[0044] The first thread determination unit is configured to determine the second thread based on the second thread identification information.

[0045] In an optional embodiment, the owner thread determination module includes:

[0046] The second information acquisition unit is configured to acquire, when the target lock type is a multi-owner lock type, the first owner identifier information of the first thread, the first thread identifier information of the first thread, the lock address information of the target thread lock, and the second address offset, wherein the second address offset is a preset offset between the second owner identifier information of the second thread and the lock address information.

[0047] The second identification information generation unit is configured to generate the second owner identification information based on the lock address information and the second address offset;

[0048] The identifier offset determination unit is configured to determine the identifier offset between the second owner identifier information and the first owner identifier information;

[0049] The third identification information generation unit is configured to generate second thread identification information for the second thread based on the identification offset and the first thread identification information.

[0050] The second thread determination unit is configured to determine the second thread based on the second thread identification information.

[0051] In an optional embodiment, the owner thread determination module includes:

[0052] The third information acquisition unit is configured to acquire first preset mapping information and lock address information of the target thread lock when the target lock type is an ownerless lock type. The first preset mapping information is the correspondence between the lock address information and the second thread identifier information of the second thread when the second thread owns the target thread lock.

[0053] The fourth identification information generation unit is configured to generate the second thread identification information based on the first preset mapping information and the lock address information;

[0054] The third thread determination unit is configured to determine the second thread based on the second thread identification information.

[0055] In an optional embodiment, the target lock type determination module includes:

[0056] The target task identification information determination unit is configured to determine the target task identification information of the target task executed by the first thread.

[0057] The target lock type determination unit is configured to determine the target lock type based on the target task identification information.

[0058] In an optional embodiment, the target task identification information determination unit includes:

[0059] The target storage address information acquisition unit is configured to acquire target storage address information from the register corresponding to the first thread, wherein the target storage address information is the storage address information of the target task identifier information of the target task;

[0060] The target task identification information acquisition unit is configured to acquire the target task identification information based on the target storage address information.

[0061] In an optional embodiment, the target lock type determination unit includes:

[0062] The second preset mapping information acquisition unit is configured to acquire the second preset mapping information, which represents the correspondence between lock identifier information corresponding to multiple thread locks and task identifier information corresponding to multiple tasks.

[0063] The target lock identifier information determination unit is configured to perform an operation based on the second preset mapping information to determine the target lock identifier information corresponding to the target task identifier information from the lock identifier information of the various thread locks;

[0064] The target thread lock determination unit is configured to execute the selection of the thread lock corresponding to the target lock identification information as the target thread lock;

[0065] The target lock type determination subunit is configured to execute the lock type of the target thread lock as the target lock type.

[0066] In an optional embodiment, the apparatus further includes:

[0067] The first thread priority adjustment module is configured to adjust the priority of the third thread to the priority of the second thread when the second thread releases the target thread lock.

[0068] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method as described in any one of the first aspects above.

[0069] According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform any one of the thread priority adjustment methods of the present disclosure.

[0070] According to another aspect of the present disclosure, a computer program product containing instructions is provided that, when run on a computer, causes the computer to perform any one of the thread priority adjustment methods described in the embodiments of the present disclosure.

[0071] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects:

[0072] During the execution of the target program, the blocking status of high-priority threads can be detected by monitoring the thread state of the first thread with a priority greater than or equal to a preset priority. Furthermore, when the blocking status of the high-priority first thread is detected, the thread lock owner in a multi-threaded lock scheduling scenario can be quickly and accurately located by first determining the target lock type of the first thread and then combining this with the target lock type to determine the second thread holding the target lock. This allows for the determination of the thread lock owner based on the lock type, effectively addressing multi-threaded lock scheduling scenarios. Moreover, if the priority of the second thread is lower than that of the first thread, increasing the priority of the second thread holding the target lock allows it to quickly complete its task and release the lock. This effectively reduces the blocking time of the high-priority first thread, quickly resolves the thread priority inversion problem, and enriches the thread scheduling scenarios while improving program performance.

[0073] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0074] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0075] Figure 1 This is a schematic diagram illustrating an application environment according to an exemplary embodiment;

[0076] Figure 2 This is a flowchart illustrating a thread priority adjustment method according to an exemplary embodiment;

[0077] Figure 3 This is a flowchart illustrating, according to an exemplary embodiment, a method for determining a target lock type based on target task identification information;

[0078] Figure 4 This is a flowchart illustrating a second thread that determines a target thread lock based on the target lock type, according to an exemplary embodiment.

[0079] Figure 5 This is a flowchart illustrating another method for determining a target thread lock based on the target lock type, according to an exemplary embodiment.

[0080] Figure 6 This is a flowchart illustrating another method for determining a target thread lock based on the target lock type, according to an exemplary embodiment.

[0081] Figure 7 This is a flowchart illustrating a thread priority adjustment method according to an exemplary embodiment;

[0082] Figure 8 This is a block diagram illustrating a thread priority adjustment device according to an exemplary embodiment;

[0083] Figure 9 This is a block diagram illustrating an electronic device for thread priority adjustment according to an exemplary embodiment;

[0084] Figure 10 This is a block diagram illustrating another electronic device for thread priority adjustment according to an exemplary embodiment. Detailed Implementation

[0085] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0086] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0087] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties.

[0088] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an application environment according to an exemplary embodiment, which may include a terminal 100 and a server 200.

[0089] In an optional embodiment, terminal 100 can be used to provide business services to any user, and in the process of providing business services, it can combine the thread priority adjustment method of this application to improve the program running performance during the business service process. Specifically, terminal 100 can be, but is not limited to, electronic devices such as smartphones, desktop computers, tablets, laptops, smart speakers, digital assistants, augmented reality (AR) / virtual reality (VR) devices, and smart wearable devices, or software running on the above-mentioned electronic devices, such as applications and mini-programs. Optionally, the operating system running on the electronic device can be, but is not limited to, Android, iOS, Linux, Windows, etc.

[0090] In an optional embodiment, server 200 can provide background services to terminal 100. Specifically, server 200 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server providing cloud computing services.

[0091] In addition, it should be noted that, Figure 1 The example shown is merely one application environment provided by this disclosure. In practical applications, other application environments may also be included. For example, the thread priority adjustment method of this application can also be applied to a server.

[0092] In the embodiments described in this specification, the terminal 100 and the server 200 can be directly or indirectly connected through wired or wireless communication, and this disclosure does not impose any restrictions.

[0093] Figure 2 This is a flowchart illustrating a thread priority adjustment method according to an exemplary embodiment, applicable to electronic devices such as terminals and servers. Figure 2 As shown, it may include the following steps;

[0094] In step S201, during the execution of the target program, the thread state of the first thread corresponding to the target program is detected.

[0095] In one specific embodiment, the target program can be any program currently running on the electronic device. Specifically, the first thread can be a thread with a thread priority greater than or equal to a preset priority; specifically, thread priority can represent the amount of computing resources (CPU time slices) allocated when a thread lock is held. Specifically, the higher the thread priority, the more computing resources are allocated.

[0096] In a specific embodiment, the preset priority can be a pre-set lower limit of thread priority; the preset priority can be set according to the needs of priority inversion control in actual applications; correspondingly, for threads with thread priorities greater than or equal to the preset priority, priority inversion can be detected and priority inversion can be adjusted in a timely manner.

[0097] In a specific embodiment, the thread state can include a ready state, a blocked state, and a running state. Specifically, the ready state can indicate that the corresponding thread is waiting to be selected by the thread scheduler to acquire computing resources; the blocked state can indicate that the corresponding thread is in a state of waiting for a thread lock and is temporarily stopped running; the running state can indicate that the corresponding thread has acquired the corresponding computing resources and is using the computing resources to execute the corresponding tasks.

[0098] In step S203, if the thread state is detected to be blocked, the target lock type of the target thread lock corresponding to the first thread is determined.

[0099] In one specific embodiment, the first running thread temporarily relinquishes computing resources before it finishes running, allowing other ready threads to preempt the target thread lock, occupy the corresponding computing resources, and then enter the running state. Conversely, when the first thread needs to re-preempt the target thread lock to run, it is blocked because the target thread lock has already been occupied.

[0100] In a specific embodiment, the target thread lock can be the thread lock that the first thread needs to preempt; the target lock type can be the lock type of the target thread lock. Specifically, during the execution of the target program, the thread locks that threads can preempt can include multiple thread locks, and correspondingly, multiple lock types. In a specific embodiment, the multiple lock types can include at least two of the following: single-owner lock type, multi-owner lock type, and no-owner lock type. Specifically, the single-owner lock type can be a lock type that can only be released by the locking thread (thread lock owner); the multi-owner lock type can be a lock type that can be released by multiple specified threads; and the no-owner lock type can be a lock type that can be released by any single thread.

[0101] In an optional embodiment, determining the target lock type corresponding to the target thread lock of the first thread may include:

[0102] Determine the target task identifier information for the target task executed by the first thread;

[0103] The target lock type is determined based on the target task identification information.

[0104] In one specific embodiment, the target task executed by the first thread can be an execution function of the first thread, and correspondingly, the target task identification information can be function identification information such as the function name of the execution function. Optionally, the target task identification information for determining the target task executed by the first thread includes:

[0105] Obtain the target storage address information from the register corresponding to the first thread. This target storage address information can be the storage address information of the target task identifier information. Based on the target storage address information, obtain the target task identifier information.

[0106] In practical applications, the register corresponding to each thread can store the memory address information corresponding to the function identifier information of the function currently being executed by that thread; correspondingly, the target memory address information can be obtained from the register corresponding to the first thread, and then the target task identifier information can be obtained by combining the target memory address information.

[0107] In a specific embodiment, the process of obtaining the target task identifier information by combining the target storage address information can be combined with a preset address resolution function (an address resolution function is a function used to obtain information by combining the storage address information of a certain information), such as the dladdr function.

[0108] In the above embodiments, by combining the target storage address information in the register corresponding to the first thread, the target task identifier information of the target task executed by the first thread can be obtained quickly and accurately, which makes it easier to accurately determine the target lock type of the target thread lock that the first thread needs to preempt.

[0109] In an optional embodiment, such as Figure 3 As shown, determining the target lock type based on the target task identification information may include the following steps:

[0110] In step S301, the second preset mapping information is obtained;

[0111] In step S303, based on the second preset mapping information, the target lock identifier information corresponding to the target task identifier information is determined from the lock identifier information of multiple thread locks;

[0112] In step S305, the thread lock corresponding to the target lock identifier information is taken as the target thread lock;

[0113] In step S307, the lock type of the target thread lock is used as the target lock type.

[0114] In a specific embodiment, the aforementioned second preset mapping information can characterize the correspondence between lock identifier information corresponding to multiple thread locks and task identifier information corresponding to multiple tasks. Lock identifier information can be used to identify different thread locks. Specifically, combining the second preset mapping information, the lock identifier information among the lock identifier information of multiple thread locks that corresponds to the target task identifier information can be used as the target lock identifier information. Correspondingly, the thread lock corresponding to this target lock identifier information can be the target thread lock; the lock type of the target thread lock can be the target lock type.

[0115] In the above embodiments, by combining the pre-set second preset mapping information that can characterize the correspondence between lock identifier information corresponding to multiple thread locks and task identifier information corresponding to multiple tasks, the lock identifier information of the thread lock that the first thread is waiting for can be quickly and accurately determined, thereby enabling fast and accurate lock type positioning. This not only enriches the types of thread locks in the thread scheduling scenario but also effectively ensures the efficiency and accuracy of thread lock positioning.

[0116] In the above embodiments, during the process of determining the thread lock that the first thread is waiting for, by determining the target task identifier information of the target task executed by the first thread, the target lock type of the thread lock that the first thread is waiting for can be quickly determined from multiple lock types. This not only enriches the types of thread locks in the thread scheduling scenario, but also effectively ensures the efficiency and accuracy of thread lock location.

[0117] In step S205, the second thread that owns the target thread lock is determined based on the target lock type;

[0118] In one specific embodiment, the second thread can be the thread that owns the target thread lock.

[0119] In the embodiments described in this specification, different strategies are used to determine the owning thread for different types of thread locks; in an optional embodiment, such as Figure 4 As shown, the second thread that determines the target thread lock based on the target lock type may include the following steps:

[0120] In step S401, if the target lock type is a single-owner lock type, the lock address information and the first address offset of the target thread lock are obtained;

[0121] In step S403, second thread identification information is generated based on the lock address information and the first address offset;

[0122] In step S405, the second thread is determined based on the second thread identifier information.

[0123] In one specific embodiment, the aforementioned first address offset can be a preset offset between the second thread's second thread identifier information and the lock address information. The lock address information can be the address information of the lock object; the second thread identifier information can be the thread identifier information of the second thread. The thread identifier information can be used to identify different threads.

[0124] In the embodiments of this specification, during the encoding of the owner thread identifier of a thread lock of a single-owner lock type, a preset offset (first address offset) corresponding to the single-owner lock type is added to the lock address information. Correspondingly, in determining the owner thread of a target thread lock, the first address offset is added to the lock address information of the target thread lock to obtain the thread identifier information (second thread identifier information) of the owner thread of the target thread lock. Furthermore, the thread corresponding to this second thread identifier information can be the owner thread of the target thread lock (second thread).

[0125] In the above embodiments, when the target lock type is a single-owner lock type, by combining the thread identification information encoding strategy corresponding to the single-owner lock type, the owner thread in the thread scheduling scenario corresponding to the single-owner lock type can be quickly and accurately determined by using the lock address information of the target thread lock and the offset between the preset thread identification information of the target thread lock's owner thread and the lock address information.

[0126] In an optional embodiment, such as Figure 5 As shown, the second thread that determines the target thread lock based on the target lock type may include the following steps:

[0127] In step S501, if the target lock type is a multi-owner lock type, the first owner identifier information of the first thread, the first thread identifier information of the first thread, the lock address information of the target thread lock, and the second address offset are obtained.

[0128] In step S503, a second owner identifier is generated based on the lock address information and the second address offset;

[0129] In step S505, the identifier offset between the second owner identifier information and the first owner identifier information is determined;

[0130] In step S507, based on the identifier offset and the first thread identifier information, the second thread identifier information of the second thread is generated;

[0131] In step S509, the second thread is determined based on the second thread identifier information.

[0132] In one specific embodiment, the first owner identifier information can be the owner identifier information of the first thread, which can be used to identify different thread owners; the lock address information can be the address information of the lock object; the first thread identifier information can be the thread identifier information of the first thread; and the second thread identifier information can be the thread identifier information of the second thread. The aforementioned second address offset can be a preset offset between the second owner identifier information of the second thread and the lock address information. The second owner identifier information is the owner identifier information of the second thread.

[0133] In the embodiments of this specification, in the thread scheduling scenario corresponding to a multi-owner lock type thread lock, the offset of the thread identification information between two threads is equal to the offset between the owner identification information of the two threads. Furthermore, the owner identification information of the thread owning the multi-owner lock type thread lock is encoded by adding a preset offset (second address offset) corresponding to the multi-owner lock type to the lock address information. Correspondingly, in determining the owner thread of the target thread lock, the lock address information of the target thread lock can be added to the second address offset to obtain the owner identification information (second owner identification information) of the target thread lock owner thread. Then, the offset between the second owner identification information and the first owner identification information is added to the first thread identification information to obtain the thread identification information (second thread identification information) of the target thread lock owner thread. Further, the thread corresponding to this second thread identification information can be the owner thread of the target thread lock (second thread).

[0134] In the above embodiments, when the target lock type is a multi-owner lock type, by combining the thread identification information encoding strategy corresponding to the multi-owner lock type, the owner identification information of the owner thread in the thread scheduling scenario corresponding to the multi-owner lock type can be quickly and accurately determined by using the lock address information of the target thread lock and the offset between the preset owner identification information of the target thread lock's owner thread and the lock address information. Furthermore, by combining the characteristic that the offset between the thread identification information of two threads is equal to the offset between the owner identification information of two threads, the owner thread in the thread scheduling scenario corresponding to the multi-owner lock type can be quickly and accurately determined by combining the identification offset between the second owner identification information and the first owner identification information with the first thread identification information.

[0135] In an optional embodiment, such as Figure 6 As shown, the second thread that determines the target thread lock based on the target lock type may include the following steps:

[0136] In step S601, if the target lock type is an ownerless lock type, the first preset mapping information and the lock address information of the target thread lock are obtained;

[0137] In step S603, second thread identification information is generated based on the first preset mapping information and lock address information;

[0138] In step S605, the second thread is determined based on the second thread identifier information.

[0139] In a specific embodiment, the aforementioned first preset mapping information can be the correspondence between the lock address information constructed when the second thread owns the target thread lock and the second thread identifier information of the second thread.

[0140] In the embodiments of this specification, when a thread lock of the ownerless lock type is occupied (owned) by a certain thread, a correspondence can be constructed between the lock address information of the ownerless lock type (target thread lock) and the thread identifier information of the thread that owns the target thread lock (i.e., the aforementioned first preset mapping information); accordingly, when it is determined that the lock type of the target thread lock that the first thread is waiting for is the ownerless lock type, the second thread identifier information can be determined by combining the first preset mapping information and the lock address information; furthermore, the thread corresponding to the second thread identifier information can be the owner thread of the target thread lock (second thread).

[0141] In the above embodiments, when the target lock type is an ownerless lock type, by combining the thread identification information encoding strategy corresponding to the ownerless lock type, and through the correspondence between the lock address information of the ownerless lock type thread lock (target thread lock) constructed when the second thread owns the target thread lock and the thread identification information of the thread owning the target thread lock, the owner thread in the thread scheduling scenario corresponding to the ownerless lock type can be quickly and accurately determined.

[0142] In step S207, if the priority of the second thread corresponding to the second thread is lower than the priority of the first thread corresponding to the first thread, the priority of the second thread is adjusted to the priority of the third thread.

[0143] In one specific embodiment, the first thread priority can be a pre-set thread priority for a first thread; the second thread priority can be a pre-set thread priority for a second thread; and the aforementioned third thread priority is greater than the second thread priority. The third thread priority can be the adjusted thread priority of the second thread.

[0144] In one specific embodiment, by adjusting the priority of the second thread to the priority of the third thread, the computing resources allocated to the second thread can be increased to speed up the execution of tasks by the second thread, thereby effectively reducing the blocking time of the high-priority first thread and quickly solving the problem of thread priority inversion.

[0145] In an optional embodiment, such as Figure 7 As shown, after adjusting the priority of the second thread to the priority of the third thread, the above method may further include the following steps:

[0146] In step S209, if the second thread releases the target thread lock, the priority of the third thread is adjusted to the priority of the second thread.

[0147] In one specific embodiment, after the second thread completes its corresponding task, the target thread lock can be released. Accordingly, the thread priority of the second thread can be restored from the third thread priority to the second thread priority. In addition, when the second thread releases the target thread lock, the first thread can acquire the target thread lock. Accordingly, the thread state of the first thread can be updated from blocked state to running state, and the target task corresponding to the first thread can be executed in combination with the corresponding computing resources.

[0148] In the above embodiments, when the second thread releases the target thread lock, the priority of the third thread is restored to the priority of the second thread in a timely manner, which can effectively ensure the rationality of the priority of threads executing different tasks, and thus better ensure the running performance of the program.

[0149] As can be seen from the technical solutions provided in the embodiments of this specification above, during the execution of the target program, the blocking of high-priority threads can be detected in a timely manner by detecting the thread state of the first thread whose thread priority is greater than or equal to a preset priority. Furthermore, when the blocking state of the high-priority first thread is detected, the thread lock owner in the thread scheduling scenario corresponding to the multi-threaded lock can be quickly and accurately located by first determining the target lock type of the target thread lock corresponding to the first thread, and then determining the second thread that owns the target thread lock based on the target lock type. This allows for the determination of the thread lock owner thread according to the lock type, thus effectively addressing thread scheduling scenarios corresponding to multi-threaded locks. Moreover, when the priority of the second thread is lower than that of the first thread, increasing the priority of the second thread currently owning the target thread lock allows the second thread to quickly complete its task and release the lock. This effectively reduces the blocking time of the high-priority first thread, quickly resolves the thread priority inversion problem, and effectively enriches the thread scheduling scenarios while improving program performance.

[0150] Figure 8 This is a block diagram illustrating a thread priority adjustment device according to an exemplary embodiment. (Refer to...) Figure 8 The device includes:

[0151] The thread state detection module 810 is configured to detect the thread state of the first thread corresponding to the target program during the execution of the target program. The first thread is a thread with a thread priority greater than or equal to a preset priority.

[0152] The target lock type determination module 820 is configured to determine the target lock type of the target thread lock corresponding to the first thread when the thread state is detected to be blocked.

[0153] The owner thread determination module 830 is configured to execute the determination of the second thread that owns the target thread lock based on the target lock type.

[0154] The second thread priority adjustment module 840 is configured to adjust the priority of the second thread to the priority of the third thread if the priority of the second thread is lower than the priority of the first thread; and the priority of the third thread is higher than the priority of the second thread.

[0155] In an optional embodiment, the owner thread determination module 830 includes:

[0156] The first information acquisition unit is configured to acquire the lock address information and the first address offset of the target thread lock when the target lock type is a single owner lock type. The first address offset is a preset offset between the second thread identifier information and the lock address information of the second thread.

[0157] The first identification information generation unit is configured to generate second thread identification information based on lock address information and first address offset;

[0158] The first thread determination unit is configured to determine the second thread based on the second thread identifier information.

[0159] In an optional embodiment, the owner thread determination module 830 includes:

[0160] The second information acquisition unit is configured to acquire the first owner identifier information of the first thread, the first thread identifier information of the first thread, the lock address information of the target thread lock and the second address offset when the target lock type is a multi-owner lock type. The second address offset is a preset offset between the second owner identifier information of the second thread and the lock address information.

[0161] The second identification information generation unit is configured to generate second owner identification information based on lock address information and second address offset.

[0162] The identifier offset determination unit is configured to determine the identifier offset between the second owner identifier information and the first owner identifier information;

[0163] The third identification information generation unit is configured to generate second thread identification information for the second thread based on the identification offset and the first thread identification information.

[0164] The second thread determination unit is configured to determine the second thread based on the second thread identifier information.

[0165] In an optional embodiment, the owner thread determination module 830 includes:

[0166] The third information acquisition unit is configured to acquire first preset mapping information and lock address information of the target thread lock when the target lock type is an ownerless lock type. The first preset mapping information is the correspondence between the lock address information constructed when the second thread owns the target thread lock and the second thread identifier information of the second thread.

[0167] The fourth identification information generation unit is configured to generate second thread identification information based on the first preset mapping information and lock address information;

[0168] The third thread determination unit is configured to determine the second thread based on the second thread identification information.

[0169] In an optional embodiment, the target lock type determination module 820 includes:

[0170] The target task identification information determination unit is configured to determine the target task identification information of the target task to be executed by the first thread.

[0171] The target lock type determination unit is configured to determine the target lock type based on the target task identification information.

[0172] In an optional embodiment, the target task identification information determination unit includes:

[0173] The target storage address information acquisition unit is configured to acquire target storage address information from the register corresponding to the first thread. The target storage address information is the storage address information of the target task identifier information of the target task.

[0174] The target task identification information acquisition unit is configured to acquire target task identification information based on target storage address information.

[0175] In an optional embodiment, the target lock type determination unit includes:

[0176] The second preset mapping information acquisition unit is configured to acquire the second preset mapping information, which represents the correspondence between lock identifier information corresponding to multiple thread locks and task identifier information corresponding to multiple tasks.

[0177] The target lock identifier information determination unit is configured to perform a process based on a second preset mapping information to determine the target lock identifier information corresponding to the target task identifier information from the lock identifier information of multiple thread locks;

[0178] The target thread lock determination unit is configured to execute the selection of the thread lock corresponding to the target lock identification information as the target thread lock;

[0179] The target lock type determination subunit is configured to execute the lock type of the target thread lock, which is used as the target lock type.

[0180] In an optional embodiment, the above-described apparatus further includes:

[0181] The first thread priority adjustment module is configured to adjust the priority of the third thread to the priority of the second thread when the second thread releases the target thread lock.

[0182] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0183] Figure 9 This is a block diagram illustrating an electronic device for thread priority adjustment according to an exemplary embodiment. The electronic device may be a terminal, and its internal structure diagram may be as follows: Figure 9 As shown, the electronic device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a thread priority adjustment method. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the device's casing, or an external keyboard, touchpad, or mouse.

[0184] Figure 10 This is a block diagram illustrating another electronic device for thread priority adjustment according to an exemplary embodiment. The electronic device may be a server, and its internal structure diagram may be as follows: Figure 10As shown, this electronic device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a thread priority adjustment method.

[0185] Those skilled in the art will understand that Figure 9 or Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the electronic device to which the present disclosure is applied. A specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0186] In an exemplary embodiment, an electronic device is also provided, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the thread priority adjustment method as described in the embodiments of this disclosure.

[0187] In an exemplary embodiment, a computer-readable storage medium is also provided, wherein when the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the thread priority adjustment method of the present disclosure embodiments.

[0188] In an exemplary embodiment, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the thread priority adjustment method of the present disclosure embodiments.

[0189] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0190] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0191] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A thread priority adjustment method, characterized in that, include: During the execution of the target program, the thread state of the first thread corresponding to the target program is detected. The first thread is a thread with a thread priority greater than or equal to a preset priority. If the thread state is detected to be blocked, the target lock type of the target thread lock corresponding to the first thread is determined. The target lock type is any one of the following: single owner lock type, multiple owner lock type, and no owner lock type. Based on the target lock type, the second thread that owns the target thread lock is determined. Different thread lock types correspond to different strategies for determining the owning thread. If the priority of the second thread is lower than the priority of the first thread, the priority of the second thread will be adjusted to the priority of the third thread. The priority of the third thread is higher than that of the second thread.

2. The thread priority adjustment method according to claim 1, characterized in that, The second thread that determines the target thread lock based on the target lock type includes: When the target lock type is the single owner lock type, the lock address information and the first address offset of the target thread lock are obtained, and the first address offset is a preset offset between the second thread's second thread identifier information and the lock address information; Based on the lock address information and the first address offset, the second thread identification information is generated; The second thread is determined based on the second thread identifier information.

3. The thread priority adjustment method according to claim 1, characterized in that, The second thread that determines the target thread lock based on the target lock type includes: When the target lock type is the multi-owner lock type, the first owner identifier information of the first thread, the first thread identifier information of the first thread, the lock address information and the second address offset of the target thread lock are obtained, and the second address offset is a preset offset between the second owner identifier information of the second thread and the lock address information. Based on the lock address information and the second address offset, the second owner identification information is generated; Determine the identifier offset between the second owner identifier information and the first owner identifier information; Based on the identifier offset and the first thread identifier information, the second thread identifier information of the second thread is generated; The second thread is determined based on the second thread identifier information.

4. The thread priority adjustment method according to claim 1, characterized in that, The second thread that determines the target thread lock based on the target lock type includes: When the target lock type is the ownerless lock type, first preset mapping information and lock address information of the target thread lock are obtained. The first preset mapping information is the correspondence between the lock address information and the second thread identifier information of the second thread when the second thread owns the target thread lock. Based on the first preset mapping information and the lock address information, the second thread identification information is generated; The second thread is determined based on the second thread identifier information.

5. The thread priority adjustment method according to any one of claims 1 to 4, characterized in that, The determination of the target lock type corresponding to the target thread lock of the first thread includes: Determine the target task identifier information of the target task executed by the first thread; Based on the target task identification information, the target lock type is determined.

6. The thread priority adjustment method according to claim 5, characterized in that, The target task identifier information for determining the target task executed by the first thread includes: Obtain the target storage address information from the register corresponding to the first thread, wherein the target storage address information is the storage address information of the target task identifier information of the target task; Based on the target storage address information, obtain the target task identifier information.

7. The thread priority adjustment method according to claim 5, characterized in that, Determining the target lock type based on the target task identifier information includes: Obtain second preset mapping information, which represents the correspondence between lock identifier information corresponding to multiple thread locks and task identifier information corresponding to multiple tasks; Based on the second preset mapping information, the target lock identifier information corresponding to the target task identifier information is determined from the lock identifier information of the various thread locks; The thread lock corresponding to the target lock identifier information is taken as the target thread lock; The lock type of the target thread lock is used as the target lock type.

8. The thread priority adjustment method according to any one of claims 1 to 4, characterized in that, After adjusting the priority of the second thread to the priority of the third thread, the method further includes: If the second thread releases the target thread lock, the priority of the third thread is adjusted to the priority of the second thread.

9. A thread priority adjustment device, characterized in that, include: The thread state detection module is configured to detect the thread state of the first thread corresponding to the target program during the execution of the target program. The first thread is a thread with a thread priority greater than or equal to a preset priority. The target lock type determination module is configured to determine the target lock type of the target thread lock corresponding to the first thread when the thread state is detected to be blocked. The target lock type is any one of the following: single owner lock type, multiple owner lock type, and no owner lock type. The owner thread determination module is configured to execute a second thread that determines the owner of the target thread lock based on the target lock type. Different types of thread locks correspond to different owner thread determination strategies. The second thread priority adjustment module is configured to adjust the priority of the second thread to the priority of the third thread when the priority of the second thread is lower than the priority of the first thread. The priority of the third thread is higher than that of the second thread.

10. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the thread priority adjustment method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the thread priority adjustment method as described in any one of claims 1 to 8.

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