An execution system for graph convolution acceleration

Abstract

The specification discloses an execution system for graph convolution acceleration, the system comprising: an aggregation engine, a combination engine, a cache area, the system can run the aggregation engine and the combination engine through a multi-core device, the aggregation engine and the combination engine process tasks in parallel, the aggregation engine obtains original graph data, divides the original graph data to obtain a plurality of subgraph data, selects at least part of the subgraph data from the plurality of subgraph data and stores the at least part of the subgraph data in the cache area, constructs each aggregation task according to the subgraph data in the cache area, and allocates each aggregation task to each core, different cores process each aggregation task in parallel, and the aggregation features corresponding to the nodes obtained after the aggregation task is completed are stored in the cache area; the combination engine can obtain the aggregation features of each node from the cache area, and execute a combination task according to the historical node features and the corresponding aggregation features of the node, so that the system can improve the efficiency of graph convolution to a certain extent.

Description

Technical Field

[0001] This specification relates to the field of neural network technology, and in particular to an execution system for accelerating graph convolution. Background Technology

[0002] Currently, graph data can be applied in various fields, such as information recommendation and link prediction. To effectively mine the characteristics of graph data, the industry has proposed graph convolutional neural networks. Graph convolutional neural networks transform graph data into a low-dimensional space while maximizing the preservation of structural and attribute information, providing an effective way to perform related business based on the features of graph data.

[0003] Graph convolution has two main execution phases: aggregation and combination. The aggregation phase relies on the inherently sparse graph structure. For each vertex, features need to be aggregated from all its source neighbors. The number and location of these source neighbors vary significantly between different vertices. The combination phase is more like a neural network; it uses a multilayer perceptron to transform the feature vector of each vertex into a new perceptron, typically represented using matrix-vector multiplication. In conventional graph convolution processing, the entire graph is usually stored on disk or in memory. When node aggregation is needed, the entire graph needs to be loaded, and the required nodes and related data need to be searched from the entire graph to begin aggregation and combination. However, this method requires loading the entire graph, which is inefficient.

[0004] Therefore, how to improve the efficiency of graph convolution is an urgent problem to be solved. Summary of the Invention

[0005] This specification provides an execution system for accelerating graph convolution, in order to partially solve the aforementioned problems existing in the prior art.

[0006] The following technical solution is adopted in this specification:

[0007] This specification provides an execution system for accelerating graph convolution, the system comprising: an aggregation engine, a combination engine, and a cache, wherein the system runs the aggregation engine and the combination engine on a multi-core device, and the aggregation engine and the combination engine process tasks in parallel;

[0008] The aggregation engine is used to: acquire original graph data; divide the original graph data into several subgraph data; select at least a portion of the subgraph data and store it in a cache; construct aggregation tasks for the nodes contained in the original graph data based on the subgraph data in the cache; assign each aggregation task to a core; process the aggregation tasks in parallel between different cores; and store the aggregation features corresponding to the nodes in the cache after the aggregation tasks are completed. For each node, the aggregation features corresponding to the node are obtained by aggregating the node features of nodes that have a preset adjacency relationship with the node.

[0009] The combination engine is used to obtain the aggregation features of each node from the cache area, and to perform a combination task based on the historical node features and the corresponding aggregation features of the node.

[0010] Optionally, the combination engine is used to determine whether this iteration is the last iteration after performing the combination task to obtain the node features of the node in this iteration. If not, the node features are stored in the cache so that the aggregation engine can continue to perform the aggregation task for the node.

[0011] Optionally, a subgraph data includes: a node interval and an edge interval. The node interval is used to represent the nodes contained in the subgraph corresponding to the subgraph data, and the edge interval is used to represent the edges corresponding to the nodes contained in the subgraph corresponding to the subgraph data. The node interval and the edge interval are respectively represented by compressed sparse columns.

[0012] Optionally, the system further includes: memory, which is used to store the plurality of subgraph data;

[0013] The aggregation engine is used to determine the degree of each node, select subgraph data corresponding to nodes with a degree value higher than a preset value from the subgraph data and store them in the cache; and construct each aggregation task based on the subgraph data in the cache and the subgraph data in memory.

[0014] If an aggregation task needs to be performed on a node, determine whether there is subgraph data related to that node in the cache. If so, construct the aggregation task corresponding to that node based on the subgraph data. If not, read the subgraph data related to that node from the memory to determine the aggregation elements related to that node, and construct the aggregation task for that node based on the aggregation elements related to that node.

[0015] Optionally, the aggregation engine is used to create a window of a preset size within each edge interval. The window slides down until there is an edge in the top row of the window, at which point the window stops, and the bottom row of the window shrinks upwards until there is an edge in the bottom row of the window. The edge interval is adjusted according to the top and bottom rows of the window to obtain the adjusted edge interval, and the adjusted edge interval is stored.

[0016] Optionally, the cache area includes a first cache area for storing subgraph data corresponding to nodes whose degree values ​​are higher than a preset value, and a second cache area for storing aggregation features.

[0017] Optionally, the combined engine includes several shrink arrays, and the combined engine includes an independent working mode and a cooperative working mode;

[0018] In the independent working mode, combined tasks of different nodes are executed in different shrink arrays in the combined engine;

[0019] In the cooperative working mode, the shrinking arrays in the combined engine jointly execute the combined tasks of the nodes.

[0020] Optionally, if the combination engine is in the independent working mode, after the aggregation engine completes less than a first set number of aggregation tasks, it stores less than a first set number of aggregation features in the cache area.

[0021] The combination engine detects that the cache contains fewer than a first set number of aggregated features, obtains the fewer than a first set number of aggregated features, and performs the combination task through the shrinking array according to the independent working mode.

[0022] Optionally, if the combination engine is in the combination working mode, after the aggregation engine completes no less than a second set number of aggregation tasks, it stores the resulting aggregation features (less than the second set number) into the cache area.

[0023] The combination engine detects that the cache contains no less than a second set number of aggregated features, obtains the no less than a second set number of aggregated features, and performs the combination task through the shrinking array according to the cooperative working mode.

[0024] Optionally, the system presets access priorities for the memory and cache.

[0025] This specification provides an execution method for accelerating graph convolution. The method is executed through a system including an aggregation engine, a combination engine, a cache, and memory. The system runs the aggregation engine and the combination engine on a multi-core device, and the aggregation engine and the combination engine process tasks in parallel. The method includes:

[0026] Obtain the original graph data;

[0027] The original graph data is divided by the aggregation engine to obtain several sub-graph data.

[0028] From the aforementioned subgraph data, at least a portion of the subgraph data is selected and stored in the cache area;

[0029] The aggregation engine constructs aggregation tasks for the nodes contained in the original graph data based on the subgraph data in the cache, and assigns each aggregation task to a core, with different cores processing each aggregation task in parallel.

[0030] After the aggregation task is completed, the aggregation features corresponding to the nodes are stored in the cache area. For each node, the aggregation feature corresponding to the node is obtained by aggregating the node features of nodes that have a preset adjacency relationship with the node.

[0031] The combination engine retrieves the aggregation features of each node from the cache and performs a combination task based on the node's historical node features and corresponding aggregation features.

[0032] This specification provides an execution apparatus for accelerating graph convolution, comprising an aggregation engine, a combination engine, and a cache. The apparatus runs the aggregation engine and the combination engine on a multi-core device, and the aggregation engine and the combination engine process tasks in parallel, including:

[0033] The acquisition module is used to acquire the raw graph data;

[0034] The partitioning module is used to partition the original graph data using the aggregation engine to obtain several sub-graph data.

[0035] The selection module is used to select at least a portion of the subgraph data from the plurality of subgraph data and store the data in the cache area;

[0036] The building module is used to construct each aggregation task for the nodes contained in the original graph data based on the subgraph data in the cache through the aggregation engine, and to allocate each aggregation task to each core, with different cores processing each aggregation task in parallel;

[0037] The storage module is used to store the aggregated features corresponding to the nodes obtained after the aggregation task is completed into the cache area. For each node, the aggregated features corresponding to the node are obtained by aggregating the node features of nodes that have a preset adjacency relationship with the node.

[0038] The execution module is used to obtain the aggregation features of each node from the cache through the combination engine, and to execute the combination task based on the historical node features and the corresponding aggregation features of the node.

[0039] This specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described execution method for accelerating graph convolution.

[0040] This specification provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-described execution method for accelerating graph convolution.

[0041] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects:

[0042] As can be seen from the above execution system for accelerating graph convolution, the system includes: an aggregation engine, a combination engine, and a cache. The system can run the aggregation engine and the combination engine on a multi-core device, processing tasks in parallel. The aggregation engine acquires the original graph data, divides it into several sub-graph data, selects at least a portion of the sub-graph data and stores it in the cache, constructs aggregation tasks for the nodes contained in the original graph data based on the sub-graph data in the cache, and assigns each aggregation task to a core. Different cores process the aggregation tasks in parallel. After the aggregation tasks are completed, the aggregation features corresponding to the nodes are stored in the cache. For each node, the aggregation feature is obtained by aggregating the node features of nodes with a preset adjacency relationship to that node. The combination engine acquires the aggregation features of each node from the cache and executes a combination task based on the node's historical node features and the corresponding aggregation features.

[0043] As can be seen from the above, the system provided in this specification can divide the original graph data to obtain multiple subgraph data. A portion of the subgraph data can be stored in the cache. When the aggregation engine and the combination engine execute tasks, the required data can be read from the cache first, thereby improving the cache hit rate. Furthermore, the aggregation engine and the combination engine can execute tasks in parallel. While the aggregation engine is executing the aggregation task, the combination engine reads the aggregation features stored in the cache and can start executing the combination task, thereby improving the efficiency of graph convolution to a certain extent. Attached Figure Description

[0044] The accompanying drawings, which are included to provide a further understanding of this specification and form part of this specification, illustrate exemplary embodiments and are used to explain this specification, but do not constitute an undue limitation thereof. In the drawings:

[0045] Figure 1 This is a schematic diagram of an execution system for accelerating graph convolution, as provided in this specification.

[0046] Figure 2 This is a flowchart illustrating the execution process of an aggregation engine provided in this specification;

[0047] Figure 3 This is a schematic diagram illustrating the execution flow of a combined engine provided in this specification;

[0048] Figure 4 This specification provides a schematic diagram of an execution device for accelerating graph convolution.

[0049] Figure 5 The corresponding information provided in this specification Figure 1 A schematic diagram of an electronic device. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0051] The technical solutions provided in the various embodiments of this specification are described in detail below with reference to the accompanying drawings.

[0052] Figure 1This is a schematic diagram of an execution system for accelerating graph convolution provided in this specification. The system may include: an aggregation engine, a combination engine, a cache, and memory, etc. The system can run the aggregation engine and the combination engine on a multi-core device, and the aggregation engine and the combination engine process tasks in parallel.

[0053] In graph convolution, the node feature extraction operation for graph data is performed iteratively. Each node in the graph data can have initial features. In one iteration, as aggregation and combination are carried out, the node's features will be updated once. That is, the node's features will be updated as many times as there are iterations, until the iteration stops.

[0054] The aggregation engine and composition engine in this specification can process tasks in parallel. As their names suggest, the aggregation engine primarily handles aggregation-related tasks, while the composition engine primarily handles composition-related tasks. A buffer (referred to as the "second buffer" below) can exist between the two engines. After the aggregation engine completes one or more aggregation tasks and obtains aggregation features for one or more nodes, it can pass these features into the buffer. The composition engine can then use the aggregation features in the buffer to begin performing composition operations on the nodes; that is, it updates the node features obtained in the previous iteration (or the node's initial features if this is the first iteration) using the aggregation features.

[0055] Because the aggregation engine and the combination engine are separate, and the aggregation and combination operations are decoupled, the aggregation engine can still perform aggregation tasks while the combination engine is executing combination tasks. The two are not completely sequential. That is, after the aggregation tasks of a small group of nodes are completed, the combination engine can start executing the combination tasks of that small group of nodes. At the same time, the aggregation engine can start executing the aggregation tasks of another group of nodes, and so on. In the entire graph convolution process, the processing tasks of the aggregation engine and the combination engine can be parallel, which can improve the efficiency of graph convolution to a certain extent.

[0056] In this system, in order to further improve efficiency, before the first iteration, the aggregation engine can obtain the original graph data, divide the original graph data, and obtain several sub-graph data.

[0057] Then, the aggregation engine can select at least a portion of the subgraph data from several subgraph data and store it in the cache. Based on the subgraph data in the cache, it constructs various aggregation tasks for the nodes contained in the original graph data and assigns each aggregation task to a core. Different cores process each aggregation task in parallel. After the aggregation task is completed, the aggregation features corresponding to the nodes are stored in the cache. For each node, the aggregation features corresponding to the node are obtained by aggregating the node features of nodes that have a preset adjacency relationship with the node.

[0058] The aggregation engine can retrieve the aggregation features of each node from the cache and perform an aggregation task based on the node's historical node features and corresponding aggregation features. After obtaining the node features for this iteration by performing the aggregation task, it can determine whether this iteration is the last iteration. If not, the node features can be stored in the cache so that the aggregation engine can continue to perform aggregation tasks for that node.

[0059] The subgraph data mentioned above can include node intervals and edge intervals. Node intervals and edge intervals can be represented by compressed sparse columns. A node interval can represent the nodes contained in the subgraph corresponding to the subgraph data, and an edge interval can be used to represent the edges corresponding to the nodes contained in the subgraph corresponding to the subgraph data.

[0060] To further reduce the space required to store subgraph data, each edge interval can be compressed to obtain the compressed edge interval for storage. Since graph connectivity is sparsely distributed, a method based on window sliding and shrinking is proposed to compress edge intervals, with the aim of removing unnecessary data from the edge intervals.

[0061] For each border interval, a window of a preset size can be created within that border interval. This window slides down until there is a border within the top row, at which point the window stops. Simultaneously, the bottom row of the window shrinks upwards until there is a border within the bottom row. The border interval is then adjusted according to the top and bottom rows of the window to obtain the adjusted border interval, which is then stored.

[0062] Adjust the edge interval according to the top and bottom rows of the window to obtain the adjusted edge interval. In other words, there is no row outside the adjusted edge interval that does not contain any edges.

[0063] The window is in matrix form, and the edge intervals are in adjacency matrix form. When storing adjusted edge intervals, they can be stored as sparse compressed columns, while when adjusting an edge interval, it can be in adjacency matrix form. When performing aggregation or combination tasks, the adjusted edge intervals can be directly used to obtain the required data.

[0064] When adjusting the aforementioned edge intervals, the adjustment can be made for the edge intervals corresponding to each node interval in the original adjacency matrix, and the window size can be the same as the original edge interval size.

[0065] The following example illustrates node intervals and edge intervals. For instance, there are four nodes [1, 2, 3, 4]. The edges between these four nodes can be represented by a 4×4 adjacency matrix. A node interval can include two nodes [1, 2] and two nodes [3, 4]. An edge interval can be a submatrix of the 4×4 adjacency matrix. For example, it can be divided into four 2×2 submatrixes, each submatrix representing the edges between two nodes. Alternatively, it can be divided into two 4×2 submatrixes, each submatrix containing all edges between nodes in a given node interval.

[0066] If the small matrix corresponding to the separated edge interval contains an extra row (i.e., this row does not contain an edge), then the extra row in the edge interval can be removed by compressing the edge interval using the above-mentioned window-based sliding and shrinking method.

[0067] In other words, this specification describes how the original graph data can be divided into multiple subgraph data. These subgraph data can be stored in memory or on disk, and a cache can store a portion of the subgraph data. When performing an aggregation task, the aggregation engine can first retrieve the required subgraph data from the cache to determine the data needed for node aggregation. Furthermore, since the graph is sparse, after splitting into subgraph data, each subgraph data may contain data that does not need to be stored. Adjustments can also be made to the edge intervals within the subgraph data to reduce the amount of data that needs to be stored.

[0068] It should be noted that the partial subgraph data stored in the cache can refer to the subgraph data corresponding to nodes whose degree values ​​are higher than a preset value. Therefore, all subgraph data can be stored in memory (or the remaining subgraph data besides the aforementioned partial subgraph data can also be stored). When an aggregation task needs to be performed, the data required for node aggregation can first be determined from the cache. If it is not found in the cache, the data required for node aggregation can then be determined from memory. Figure 2 As shown.

[0069] Figure 2 This is a flowchart illustrating the execution process of an aggregation engine provided in this specification.

[0070] from Figure 2 As can be seen, the aggregation engine can split the original graph data into multiple subgraph data. Furthermore, it can adjust the edge intervals in the subgraph data based on the sliding and shrinking of the window, thereby reducing the space required to store the edge intervals.

[0071] The cache area can also contain a dedicated cache area, which is used to store the subgraph data corresponding to nodes whose degree values ​​are higher than a set value. Here, the subgraph data corresponding to nodes whose degree values ​​are higher than the set value can refer to the data of a small portion of edges corresponding to the node in the subgraph data. The cache area can also store data related to the node, such as feature data.

[0072] After the original graph data is divided and the corresponding data is prepared in the cache, the aggregation engine can start to execute the aggregation task and store the obtained aggregation features in the cache after the aggregation task is completed.

[0073] One approach is to store a subgraph data in a cache (a third cache specifically for storing subgraph data). This allows the aggregation engine to first perform aggregation tasks on the nodes in the subgraph data. Once the aggregation engine has completed the aggregation tasks on the nodes in the subgraph data, it will then replace the subgraph data in the cache.

[0074] If an aggregation task needs to be performed on a node, it can be determined whether subgraph data related to that node exists in the cache. If so, the aggregation task corresponding to that node is constructed based on the subgraph data. If not, the subgraph data related to that node is read from memory to determine the aggregation elements related to that node, and the aggregation task for that node is constructed based on these aggregation elements. The aggregation elements mentioned here can refer to the data required to perform the aggregation task for that node.

[0075] Here, the degree can refer to the number of edges connected to a node. A dedicated cache area can be maintained: referred to here as the first cache area, it is used to store the subgraph data corresponding to nodes with a degree value higher than a preset value. The purpose of having this dedicated first cache area is that when performing aggregation tasks, if the required data exists in the first cache area, it does not need to be retrieved from memory, thereby improving the memory access hit rate and thus improving the efficiency of graph convolution.

[0076] It should also be noted that when the aggregation engine or the combination engine needs to look up data in memory or cache, it can first determine whether the data to be looked up is related to the node whose degree value is higher than the preset value. If so, the data to be looked up can be directly looked up in the cache. If not, the data to be looked up can be looked up in memory.

[0077] It should be noted that retrieving the required data from memory can be achieved by retrieving the edge interval where the required data is located from memory, storing the edge interval in the third cache, and then retrieving the required data through the edge interval in the third cache.

[0078] In this specification, the combination engine contains several shrink arrays. The combination engine can correspond to two working modes: independent working mode and cooperative working mode. When developers need the combination engine to complete combination tasks more efficiently, they can choose the independent working mode. When developers need the combination engine to complete combination tasks with lower energy consumption, they can choose the cooperative working mode.

[0079] In independent working mode, combined tasks from different nodes are executed in different shrink arrays within the combined engine; that is, one shrink array can execute one combined task. In cooperative working mode, the shrink arrays within the combined engine can jointly execute the combined tasks of the nodes; that is, the shrink arrays can cooperate to complete one or more combined tasks.

[0080] For the two working modes, the way the cache receives the aggregation engine, or in other words, the way the aggregation engine stores the aggregated features into the cache, can be different.

[0081] If the combination engine is in independent working mode, after the aggregation engine completes less than a first set number of aggregation tasks, it can store the less than a first set number of aggregation features in the cache. When the combination engine detects that less than a first set number of aggregation features are stored in the cache, it obtains less than a first set number of aggregation features and executes the combination task through the shrink array in independent working mode.

[0082] If the combination engine is in combination working mode, after the aggregation engine completes at least a second set number of aggregation tasks, it can store fewer than the second set number of aggregation features in the cache. The combination engine detects that the cache contains at least a second set number of aggregation features, acquires at least a second set number of aggregation features, and executes the combination task through a shrinking array according to the cooperative working mode. The first set number can be less than the second set number. Both the first and second set numbers can be manually set.

[0083] In other words, in independent working mode, once a small number of aggregated features are obtained, they can be stored in the cache, facilitating parallel execution of the combination tasks by the various shrinking arrays in the combination engine. In cooperative mode, however, a larger number of aggregated features can be obtained before storing them in the cache, allowing the shrinking arrays in the combination engine to cooperatively execute multiple combination tasks at once.

[0084] The following example illustrates the workflow of the composition engine. Figure 3 As shown.

[0085] Figure 3 This is a schematic diagram illustrating the execution process of a combined engine provided in this specification.

[0086] from Figure 3 As can be seen, the combination engine can first determine whether it is in independent working mode or combination working mode. If it is in independent working mode, it can read a small amount of aggregated features from the cache and start executing the combination task. If it is in combination working mode, it can read a larger amount of aggregated features from the cache and start executing the combination task.

[0087] After performing the combination task, the parameters of the graph convolution model can be updated according to the loss function, and it can be determined whether the current iteration is the last iteration. If not, the node features obtained by combination need to be sent back to the buffer. If it is the last iteration, the node features obtained by combination can be output, and the task ends after outputting the node features of the last node.

[0088] It should be noted that when setting the size of the aforementioned edge interval, the size of the edge interval can be related to the size of the buffer. The height of the edge interval is determined by the capacity of the first buffer, while the width of the edge interval is determined by the capacity of the second buffer. The size of the third buffer can affect the height and width of the edge interval, as it can accommodate every edge contained within the entire edge interval.

[0089] In this specification, the aggregation engine and the combination engine can share memory and a cache. Access priorities can be preset for memory and the cache, specifically: edge > aggregation feature > weight > node feature. For example, in a batch of access requests, high-priority access requests can be processed first, followed by low-priority requests. Low-priority accesses in the current batch can be processed before high-priority accesses in the next batch, rather than always prioritizing high-priority accesses. A batch of access requests can be requests accessing memory or the cache continuously within a certain time period, or it can be a continuous number of requests accessing memory or the cache.

[0090] As can be seen from the above, the execution system for accelerating graph convolution provided in this specification can improve the efficiency of graph convolution. By splitting the original graph data, the edge intervals in the split subgraph data can be compressed according to the sliding and shrinking method of the window, thereby removing redundant data in the edge intervals and eliminating graph sparsity to a certain extent.

[0091] Furthermore, storing the relevant data of nodes with height (nodes with a degree value higher than a preset value) in a separate cache area, and storing the split subgraph data one by one in the cache area, can improve the access hit speed to a certain extent.

[0092] Figure 4 This specification provides a schematic diagram of an execution device for accelerating graph convolution. The execution device includes an aggregation engine, a combination engine, and a cache. The execution device runs the aggregation engine and the combination engine on a multi-core device. The aggregation engine and the combination engine process tasks in parallel, including:

[0093] Module 401 is used to acquire raw image data;

[0094] The partitioning module 402 is used to partition the original graph data through the aggregation engine to obtain several sub-graph data.

[0095] The selection module 403 is used to select at least a portion of the subgraph data from the plurality of subgraph data and store the data in the cache area;

[0096] The construction module 404 is used to construct each aggregation task for the nodes contained in the original graph data based on the subgraph data in the cache through the aggregation engine, and to allocate each aggregation task to each core, with different cores processing each aggregation task in parallel.

[0097] The storage module 405 is used to store the aggregated features corresponding to the nodes obtained after the aggregation task is completed into the cache area. For each node, the aggregated features corresponding to the node are obtained by aggregating the node features of nodes that have a preset adjacency relationship with the node.

[0098] The execution module 406 is used to obtain the aggregation features of each node from the cache area through the combination engine, and to perform the combination task based on the historical node features and the corresponding aggregation features of the node.

[0099] Optionally, the execution module 406 is used to determine whether this iteration is the last iteration after obtaining the node features of the node in the current iteration by performing the combination task. If not, the node features are stored in the cache area so that the aggregation engine can continue to perform the aggregation task for the node.

[0100] Optionally, a subgraph data includes: a node interval and an edge interval. The node interval is used to represent the nodes contained in the subgraph corresponding to the subgraph data, and the edge interval is used to represent the edges corresponding to the nodes contained in the subgraph corresponding to the subgraph data. The node interval and the edge interval are respectively represented by compressed sparse columns.

[0101] Optionally, the execution device further includes: a memory for storing the plurality of subgraph data;

[0102] The construction module 404 is used to determine the degree of each node, select subgraph data corresponding to nodes with a degree value higher than a preset value from the plurality of subgraph data and store them in the cache area; and construct each aggregation task based on the subgraph data in the cache area and the subgraph data in the memory.

[0103] If an aggregation task needs to be performed on a node, determine whether there is subgraph data related to that node in the cache. If so, construct the aggregation task corresponding to that node based on the subgraph data. If not, read the subgraph data related to that node from the memory to determine the aggregation elements related to that node, and construct the aggregation task for that node based on the aggregation elements related to that node.

[0104] Optionally, the partitioning module 402 is further configured to, for each edge interval, create a window of a preset size within that edge interval, slide the window downwards until there is an edge within the top row of the window, then stop the window, and shrink the bottom row of the window upwards until there is an edge within the bottom row of the window. The edge interval is then adjusted according to the top and bottom rows of the window to obtain the adjusted edge interval, and the adjusted edge interval is stored.

[0105] Optionally, the cache area includes a first cache area for storing subgraph data corresponding to nodes whose degree values ​​are higher than a preset value, and a second cache area for storing aggregation features.

[0106] Optionally, the combination engine includes several shrink arrays, and the combination engine includes an independent working mode and a cooperative working mode; in the independent working mode, the combination tasks of different nodes are executed in different shrink arrays in the combination engine; in the cooperative working mode, each shrink array in the combination engine jointly executes the combination tasks of the nodes.

[0107] Optionally, the storage module 405 is further configured to, if the combination engine is in the independent working mode, store the fewer than the first set number of aggregated features obtained after the aggregation engine completes less than the first set number of aggregation tasks into the cache area.

[0108] The execution module 406 is specifically used to: when the combination engine detects that the cache contains fewer than a first set number of aggregated features, obtains the fewer than a first set number of aggregated features, and executes the combination task through the shrinking array according to the independent working mode.

[0109] Optionally, the storage module 405 is further configured to, if the combination engine is in the combination working mode, after the aggregation engine completes no less than a second set number of aggregation tasks, store the obtained aggregation features less than the second set number into the cache area.

[0110] The execution module 406 is specifically used to: when the combination engine detects that the cache contains no less than a second set number of aggregated features, obtain the no less than a second set number of aggregated features, and execute the combination task through the shrinking array according to the cooperative working mode.

[0111] Optionally, access priorities are preset for the memory and the cache.

[0112] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described execution method for accelerating graph convolution.

[0113] This instruction manual also provides Figure 5 The diagram shows a schematic structural representation of the electronic device. Figure 5 At the hardware level, the electronic device includes a processor, an internal bus, a network interface, memory, and non-volatile storage, and may also include other hardware required for the business logic. The processor reads the corresponding computer program from the non-volatile storage into memory and then runs it to implement the above-mentioned execution method for accelerating graph convolution.

[0114] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of hardware and software. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0115] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0116] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0117] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0118] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.

[0119] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0120] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0121] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0122] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0123] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0124] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0125] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0126] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0127] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] This specification can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This specification can also be practiced in distributed computing environments, where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0129] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0130] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. An execution system for accelerating graph convolution, characterized in that, The system includes: an aggregation engine, a combination engine, a cache, and memory. The system runs the aggregation engine and the combination engine on a multi-core device, and the aggregation engine and the combination engine process tasks in parallel. The aggregation engine is used to acquire original graph data, divide the original graph data into several subgraph data, determine the degree of each node contained in the original graph data, and select the subgraph data corresponding to the nodes whose degree values ​​are higher than a preset value from the several subgraph data as at least part of the subgraph data and store them in the cache area; wherein, the degree of the node refers to the number of edges connected to the node. The memory is used to store all of the plurality of subgraph data, or to store the remaining subgraph data excluding the at least some of the subgraph data; The aggregation engine is also used to construct aggregation tasks for nodes contained in the original graph data based on the subgraph data in the cache and the subgraph data in memory, and to allocate each aggregation task to each core. Different cores process each aggregation task in parallel. After the aggregation task is completed, the aggregation features corresponding to the obtained nodes are stored in the cache. For each node, the aggregation features corresponding to the node are obtained by aggregating the node features of nodes that have a preset adjacency relationship with the node. The combination engine is used to obtain the aggregation features of each node from the cache area, and to perform a combination task based on the historical node features and the corresponding aggregation features of the node.

2. The system as described in claim 1, characterized in that, The combination engine is used to determine whether this iteration is the last iteration after obtaining the node features of the node in the current iteration by performing a combination task. If not, the node features are stored in the cache area so that the aggregation engine can continue to perform aggregation tasks for the node.

3. The system as described in claim 1, characterized in that, A subgraph data includes: a node interval and an edge interval. The node interval is used to represent the nodes contained in the subgraph corresponding to the subgraph data, and the edge interval is used to represent the edges corresponding to the nodes contained in the subgraph corresponding to the subgraph data. The node interval and the edge interval are represented by compressed sparse columns.

4. The system as described in claim 1, characterized in that, If an aggregation task needs to be performed on a node, determine whether there is subgraph data related to that node in the cache. If so, construct the aggregation task corresponding to that node based on the subgraph data. If not, read the subgraph data related to that node from the memory to determine the aggregation elements related to that node, and construct the aggregation task for that node based on the aggregation elements related to that node.

5. The system as described in claim 3, characterized in that, The aggregation engine is used to create a window of a preset size within each edge interval, slide the window down until there is an edge in the top row of the window, stop the window, and shrink the bottom row of the window upwards until there is an edge in the bottom row of the window, adjust the edge interval according to the top row and the bottom row of the window to obtain the adjusted edge interval, and store the adjusted edge interval.

6. The system as described in claim 1, characterized in that, The cache area includes a first cache area for storing subgraph data corresponding to nodes whose degree values ​​are higher than a preset value, and a second cache area for storing aggregation features.

7. The system as described in claim 1, characterized in that, The combined engine includes several shrink arrays, and the combined engine includes an independent working mode and a cooperative working mode; In the independent working mode, combined tasks of different nodes are executed in different shrink arrays in the combined engine; In the cooperative working mode, the shrinking arrays in the combined engine jointly execute the combined tasks of the nodes.

8. The system as described in claim 7, characterized in that, If the combination engine is in the independent working mode, after the aggregation engine completes less than a first set number of aggregation tasks, it stores less than a first set number of aggregation features into the cache area. The combination engine detects that the cache contains fewer than a first set number of aggregated features, obtains the fewer than a first set number of aggregated features, and performs the combination task through the shrinking array according to the independent working mode.

9. The system as described in claim 7, characterized in that, If the combination engine is in the combination working mode, after the aggregation engine completes no less than a second set number of aggregation tasks, it stores the resulting aggregation features (less than the second set number) into the cache area. The combination engine detects that the cache contains no less than a second set number of aggregated features, obtains the no less than a second set number of aggregated features, and performs the combination task through the shrinking array according to the cooperative working mode.

10. The system as claimed in claim 1, characterized in that, The system has preset access priorities for the memory and the cache.

11. An execution method for accelerating graph convolution, characterized in that, The execution method is performed by a system including an aggregation engine, a combination engine, a cache, and memory. The system runs the aggregation engine and the combination engine on a multi-core device, and the aggregation engine and the combination engine process tasks in parallel, including: Obtain the original graph data; The original graph data is divided by the aggregation engine to obtain several sub-graph data. The degree of each node in the original graph data is determined, and from the plurality of subgraph data, the subgraph data corresponding to the nodes whose degree values ​​are higher than a preset value are selected as at least a portion of the subgraph data and stored in the cache area; wherein, the degree of the node refers to the number of edges connected to the node; The memory stores all of the plurality of subgraph data, or stores the remaining subgraph data excluding the at least some of the subgraph data; The aggregation engine constructs aggregation tasks for the nodes contained in the original graph data based on the subgraph data in the cache and the subgraph data in memory, and assigns each aggregation task to a core, with different cores processing each aggregation task in parallel. After the aggregation task is completed, the aggregation features corresponding to the nodes are stored in the cache area. For each node, the aggregation feature corresponding to the node is obtained by aggregating the node features of nodes that have a preset adjacency relationship with the node. The combination engine retrieves the aggregation features of each node from the cache and performs a combination task based on the node's historical node features and corresponding aggregation features.

12. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in claim 11.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method described in claim 11.

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