Memory-matched low-density parity-check decoding scheme

Abstract

Low density parity check (LDPC) decoding based on a charge voltage distribution (CVD) of memory cells in a data storage device. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

Description

Technical Field

[0001] This application generally relates to data storage devices, and more particularly to low-density parity-check (LDPC) decoding based on the voltage distribution (CVD) of memory cells in the data storage device. Background Technology

[0002] Memory devices can achieve increasingly higher memory capacities as memory density increases, through process scaling, 3D stacking, and storing more bits per memory cell. This increased memory density leads to essentially "noisier" media. Error correction codes (ECCs) also allocate space in memory, reducing the amount of space available for actual user data. Summary of the Invention

[0003] The technology disclosed herein optimizes ECC decoding to operate close to the theoretical limit (i.e., the Shannon limit). Specifically, when performing LDPC decoding, the decoding scheme of this disclosure takes into account the expected error rate for various programming states. As described in more detail below, the decoding scheme of this disclosure reduces memory over-provisioning, including the space allocated for ECC.

[0004] Advanced decoding schemes, such as LDPC, are typically not tailored to the memory device's memory error model. Specifically, the memory error protection level is not adjusted for each memory read threshold, but is determined globally. The memory error model is typically used only to set decoder initialization values. The technical proposals of this disclosure utilize a memory error model during ECC construction and design.

[0005] In one embodiment, this disclosure provides a memory controller including a memory interface and a controller. The memory interface is configured to interface with non-volatile memory. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

[0006] This disclosure also provides a method. In one embodiment, the method includes receiving a plurality of data pages to be stored in non-volatile memory, and transforming the plurality of data pages into a plurality of transformed data pages. The method further includes determining a plurality of parity bits based on the plurality of transformed data pages and storing the plurality of data pages and the plurality of parity bits in the non-volatile memory.

[0007] This disclosure also provides an apparatus. The apparatus includes components for interfacing with a non-volatile memory. The apparatus includes components for receiving a plurality of data pages to be stored in the non-volatile memory and components for transforming the plurality of data pages into a plurality of transformed data pages. The apparatus further includes components for determining a plurality of parity bits based on the plurality of transformed data pages and components for storing the plurality of data pages and the plurality of parity bits in the non-volatile memory.

[0008] Thus, various aspects of this disclosure provide improvements, at least in the technical field of data storage devices and their design and architecture. This disclosure can be embodied in various forms, including hardware or circuitry controlled by firmware (i.e., code executed on a processor), computer systems and networks; and hardware implementation methods, signal processing circuits, memory arrays, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc. The foregoing summary is intended only to give a general idea of ​​various aspects of this disclosure and does not limit the scope of this disclosure in any way. Attached Figure Description

[0009] Figure 1 The following is a block diagram of a system according to some embodiments of the present disclosure, the system including a data storage device with memory-matched LDPC decoding / decoding.

[0010] Figure 2 A graph illustrating the error rate of various cell voltage distribution levels of a four-level cell memory according to some embodiments of the present disclosure.

[0011] Figures 3A-3B Examples of memory matching transformations for a four-level cell (QLC) memory according to some embodiments of this disclosure.

[0012] Figure 4 A flowchart illustrating memory-matched LDPC encoding / decoding according to some embodiments of this disclosure is provided.

[0013] Figure 5 This is an exemplary memory-matched LDPC message passing process according to some embodiments of this disclosure.

[0014] Figure 6 A graph is provided to illustrate a QLC memory with a Gaussian memory level distribution according to some embodiments of the present disclosure.

[0015] Figure 7 A graph is shown to illustrate the decoder failure probability as a function of the unit error rate according to some embodiments of this disclosure.

[0016] Figure 8 Exemplary soft bit reads are provided according to some embodiments of this disclosure. Detailed Implementation

[0017] In the following description, numerous details, such as data storage device configuration and controller operation, are set forth in order to provide an understanding of one or more aspects of this disclosure. It will be apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of this application. Specifically, the functions associated with the memory device may be performed by hardware (e.g., analog or digital circuitry), a combination of hardware and software (e.g., program code or firmware stored in a non-transitory computer-readable medium and executed by processing or control circuitry), or any other suitable component. The following description is intended only to give a general idea of ​​the various aspects of this disclosure and does not limit the scope of this disclosure in any way.

[0018] Figure 1 This is a block diagram illustrating an example of a system 100 including a data storage device 102. In some specific implementations, the data storage device 102 is a flash memory device. For example, the data storage device 102 is a Secure Digital SD card. ® Card, microSD ® Card or another similar type of data storage device. Figure 1 The data storage device 102 shown includes non-volatile memory 104 and a controller 106. The data storage device 102 is coupled to a host device 108. The host device 108 is configured to provide data 110 (e.g., user data) to the data storage device 102 for storage, for example, in the non-volatile memory 104. For example, the host device 108 may be a smartphone, music player, video player, game console, e-book reader, personal digital assistant device, tablet computer, laptop computer, or another similar device.

[0019] The non-volatile memory 104 of the data storage device 102 is coupled to the controller 106. In some embodiments, the non-volatile memory 104 is a NAND flash memory. Figure 1 The non-volatile memory 104 shown includes a plurality of memory cells 112A-112N (e.g., flash memory cells). Each memory cell in the plurality of memory cells 112A-112N includes a plurality of storage elements. For example, in Figure 1In this embodiment, memory cell 112A includes representative memory element 114. In some embodiments, memory element 114 is a multilevel cell flash memory, such as a 2-level cell (“SLC”), 4-level cell (“MLC”), 8-level cell (“TLC”), 16-level cell (“QLC”), or a flash memory cell with a large number of bits per cell (e.g., five to ten bits per cell). In some embodiments, multiple memory cells 112A-112N are included in word lines or pages of the multilevel cell flash memory. In other embodiments, multiple memory cells 112A-112N are distributed across multiple word lines or pages of the multilevel cell flash memory.

[0020] Figure 1 The controller 106 shown includes a host interface 116, a memory interface 118, controller circuitry 120, and an ECC engine 122. The controller 106 in... Figure 1 The diagram is shown in a simplified form. Those skilled in the art will recognize that the controller for non-volatile memory will include, in addition to... Figure 1 Additional modules or components beyond those specifically shown in the diagram. Additionally, although data storage device 102 is... Figure 1 The device is shown as including a controller 106 and a module for performing, for example, ECC; however, in other implementations, the controller 106 is alternatively located within the host device 108 or otherwise separated from the data storage device 102. Therefore, ECC and other Flash Translation Layer (“FTL”) operations (e.g., wear leveling, bad block management, data scrambling, garbage collection, address mapping, etc.) typically performed by the controller 106 may be performed by the host device 108 or another device connected to the data storage device 102.

[0021] Controller 106 is configured to send data to and receive data and instructions from host device 108 via host interface 116. Host interface 116 enables host device 108 to read from and write to non-volatile memory 104, for example, using any suitable communication protocol. Suitable communication protocols include, for example, the Universal Flash Storage (“UFS”) Host Controller Interface Specification, Secure Digital (“SD”) Host Controller Specification, etc.

[0022] Controller 106 is also configured to send data and commands (e.g., memory operation 134) to non-volatile memory 104 and to receive data from non-volatile memory via memory interface 118. As an exemplary example, controller 106 is configured to send data and write commands to instruct non-volatile memory 104 to store data in a specific memory location within non-volatile memory 104. Controller 106 is also configured to send read commands to non-volatile memory 104 to read data from a specific memory location within non-volatile memory 104. In some examples, controller 106 is coupled to non-volatile memory 104 via bus 132 in conjunction with memory interface 118. For example, bus 132 may include multiple different channels to enable controller circuitry 120 to communicate with each of the one or more memory cells 112, in parallel with and independently of communication with other memory dies 103.

[0023] Figure 1 The controller circuitry 120 shown includes a processor 124 (e.g., a microprocessor, microcontroller, field-programmable gate array (“FPGA”) semiconductor, application-specific integrated circuit (“ASIC”) or other suitable programmable device) and a non-transitory computer-readable medium or memory 126 (e.g., including random access memory (“RAM”) and read-only memory (“ROM”)). The processor 124 is operatively connected to various modules within the controller circuitry 120, the controller 106, and the data storage device 102. For example, firmware is loaded into the ROM of the memory 126 as computer-executable instructions. These computer-executable instructions can be retrieved from the memory 126 and executed by the processor 124 to control the operation of the controller circuitry 120 and perform the processes described herein (e.g., data correction and ECC). In some embodiments, one or more modules of the controller circuitry 120 correspond to individual hardware components within the controller circuitry 120. In other embodiments, one or more modules of the controller circuitry 120 correspond to software stored in the memory 126 and executed by the processor 124. The memory 126 is configured to store data used by the controller circuit 120 during operation.

[0024] ECC engine 122 is configured to receive data to be stored in non-volatile memory 104. ECC engine 122 is configured to encode the data using an ECC encoding scheme. In some specific implementations, the ECC encoding scheme is the Reed Solomon encoding scheme, the Bose-Chaudhuri-Hocquenghem (“BCH”) encoding scheme, the Low-Density Parity-Check (“LDPC”) encoding scheme, or another suitable encoding scheme. Figure 1The ECC engine 122 shown includes a decoder 128 and an encoder 130. The decoder 128 is configured to decode data read from the non-volatile memory 104. For example, the decoder 128 is configured to decode codewords read from the non-volatile memory 104. A codeword may include, for example, 4*k data bits and 4*m parity bits, described in more detail below. The decoder 128 is configured to detect and correct bit errors present in the data read from the non-volatile memory 104. The decoder 128 corrects bit errors present in the data read from the non-volatile memory 104 depending on the error correction capability of the implemented ECC scheme. In some specific implementations, the ECC engine 122 is included in the controller circuitry 120.

[0025] As previously stated, the decoding scheme described herein uses the expected error rate of each programming state caused by the cell voltage distribution (CVD) in the memory device. Figure 2 A graph 200 illustrates an exemplary CVD of a QLC memory. Multiple memory cell states S0-S15 are shown by illustration 205. Graph 200 includes an x-axis 210 representing the gate voltage values ​​of the multiple memory cell states S0-S15. Graph 200 includes a y-axis 215 representing the bit distribution of each of the multiple memory cell states S0-S15. In some embodiments, one or more memory cell states S0-S15 may overlap with another memory cell state S0-S15 at a given gate voltage. Such overlaps result in a cell error rate (CER) for each overlap. Graph 200 includes fifteen CERs for fifteen overlaps among sixteen memory cell states S0-S15. Additionally, each memory cell state S0-S15 in graph 200 is asymmetrical and may have different ranges of gate voltages or bit distributions. In some ideal embodiments, each memory cell state S0-S15 is identical.

[0026] To customize LDPC to match CVD and its memory error model (defined by CER), the “memory matching transformation” (i.e., m) referred to in this paper will be used. 2 The transformation is applied to the memory model to ensure that errors introduced by each read threshold only affect a subset of the decoded bits. Figures 3A-3B An exemplary memory matching transformation for QLC memory is shown. For example... Figure 3A As shown, the QLC memory has multiple memory cell states 300, where each memory cell state 300 stores n = 4 user data bits, for a total of 2. n= 16 states (starting with state 0 and ending with state 15). Each memory cell state 300 has a next page 302, a middle page 304, a previous page 306, and a top page 308, and each page is configured as a storage bit. Figure 3A In the example, only one bit changes when moving through states from left to right. For example, state 0 stores bit [1 1 1 1], while state 1 stores bit [1 1 1 0], where only the bit in the top page 308 has changed. State 2 stores bit [1 01 0], where only the bit in the middle page 304 has changed.

[0027] To read the state 300 of each memory cell, t = 2 is required. n -1 = 15 read thresholds (i.e., CER). Therefore, the memory match transformation converts every n = 4 user data pages into t = 15 transformed pages 320. From Figures 3A to 3B The transformation occurs vertically. For example, although state 0 stores bits [1 1 1 1], transformed page 0 stores bits [1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]. State 1 stores bits [1 1 1 0], while transformed page 1 stores bits [0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]. In the case of transformed page 320, any cell error introduced by the j-th read threshold will only introduce a bit error at the j-th transformed page 320. Each transformed page has a CER value of 340.

[0028] For example, consider a cell programmed into the first memory cell state (i.e., state 0) of a plurality of memory cell states 300 such that the value of the transformed page corresponding to this particular cell is [1 1 1 1 1 1 1 1 1 1 1 1 1 1 11]. However, during a read, a cell error is introduced through a first read threshold, resulting in the read of the cell state at the second plurality of cell states 200 (i.e., state 1) and thus the read value of the corresponding transformed page being [0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]. Therefore, a bit error is introduced only in the first page of the 15 transformed pages.

[0029] In another example, consider a cell programmed into the fourth memory cell state (i.e., state 3) of a plurality of memory cell states such that the value of the transformed page corresponding to this particular cell is [0 0 0 1 1 1 1 1 1 1 1 1 1 1 11 1]. However, during a read, a cell error is introduced via a third read threshold, resulting in the read of the cell state at the third plurality of cell states 200 (i.e., state 2) and thus the read value of the corresponding transformed page being [0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1]. Therefore, a bit error is introduced only in the third page out of 15 transformed pages.

[0030] Therefore, due to the memory match transformation, the bit error rate introduced into each page of the transformed page 320 corresponds to the cell error rate associated with the corresponding read threshold. Additionally, an appropriate protection level can be assigned to each transformed page corresponding to the expected CER of the corresponding read threshold. Alternatively, a different memory match transformation can be used instead. Figures 3A-3B The transformations shown. For example, page-level matching transformations can be used.

[0031] The total bit error rate (BER) of the original n = 4 pages (i.e., next page 302, middle page 304, previous page 306, and top page 308) is the same as the total BER of the transformed page 320. Specifically:

[0032]

[0033] On average, the BER observed for each transformed page 320 is n / t = 4 / 15 of that of the original page. Therefore, the total ECC redundancy required to protect the transformed page 320 is the same as the ECC redundancy required to protect n = 4 original data pages.

[0034] Using an LDPC encoder (i.e., a memory-matched LDPC encoder, m) 2An LDPC encoder encodes the transformed page 320, taking into account the error rate of the transformed page 320. A certain number of parity bits are allocated to each of the transformed pages 320 according to its expected BER. Therefore, if each transformed page 320 has the same expected BER, the parity bits can be allocated symmetrically. In some examples, parity bits can be allocated asymmetrically when the transformed pages 320 have varying BERs. In other examples, a single LDPC code can be used, where different degree spectra (i.e., different allocations of parity equations for each bit) are used for each of the transformed pages 320 in the underlying bipartite graph representing the LDPC code. The degree spectra then correspond to the expected BER of the respective transformed page. For example, a subset of bits expected to exhibit a higher BER, such as those affected by a more error-prone read threshold, participates in more parity equations compared to a subset of bits expected to exhibit a lower contrast BER.

[0035] Figure 4 An exemplary process 400 for LDPC encoding and decoding methods for memory matching is shown. Process 400 can be executed by ECC engine 122. Figure 4 In the example, n = 4 user data pages (i.e., next page 302, middle page 304, previous page 306, and top page 308) are provided as input data, each page comprising k bits. The 4*k bits of input data are provided to the memory-matched transform coding block 405. The memory-matched transform coding block 405 transforms the input data into t = 15 transformed pages (e.g., transformed page 320) with k bits. The transformed 15*k bits are encoded by the memory-matched LDPC encoder 410, which produces n*m = 4*m parity bits. In parallel with the memory-matched transform coding block 405 and the memory-matched LDPC encoder 410, the 4*k raw user bits are stored together with the 4*m parity bits in non-volatile memory 104 (i.e., QLC data pages) such that k+m bits exist per page.

[0036] The transformed pages are not directly stored in non-volatile memory 104 because the memory cell can only store n pages and cannot directly store t = 2 pages. n -1 page. Conversely, during a read operation, the transformed page is inferred from the read cell voltage (Vt) via an inverse memory matching transformation. For example, the cell state, the value of the logical page (e.g., next page 302, middle page 304, previous page 306, and top page 308), and the value of the transformed page 320 can be inferred from the Vt of the read cell. The read operation retrieves a quantized version of the cell's Vt at any desired resolution (in Figure 5 The designation is Y). In one implementation, with Figure 2The nominal read threshold shown in the diagram performs reads to retrieve hard bit (HB) pages and infer the cell's state. In another embodiment, in addition to the hard bits, a higher read resolution (more finely determining the cell's Vt) used to retrieve soft bits (SB) is used to assign reliability to the read values.

[0037] Each hard bit corresponds to a logical page (e.g., next page 302, middle page 304, previous page 306, and top page 308) read from non-volatile memory 104. Each soft bit indicates how close the cell's Vt is to the read threshold, such as... Figure 8 As shown in the diagram. Therefore, the soft bit indicates the probability of an incorrect hard bit (e.g., the probability of a read error). The combination of the hard and soft bits read by a cell is denoted as Y and corresponds to the quantized version of the cell's Vt. The cell read value Y can be used to determine if the cell is programmed into different states s = 0, 1, ..., 2. n The probability of -1. The probability of reading a specific value Y from a cell programmed as state s can be calculated based on a CVD model, denoted as Pr(Y|s).

[0038] During the read operation, for m 2 The read unit value Y in the LDPC decoder 415 performs decoding to correct errors introduced by the non-volatile memory 104 and recover user data stored in the non-volatile memory 104. 2 LDPC decoding operations employ a unique iterative message-passing decoding algorithm. Under appropriate message computation rules, m 2 The LDPC messaging algorithm can be viewed as operating on a tripartite graph with "cell nodes," "bit nodes," and "check nodes" (as opposed to regular LDPC messaging decoding, which operates on a bipartite graph). Message delivery estimates of codeword bits are exchanged at the edges of the tripartite graph, which iteratively improves upon this. A common metric for delivering bit estimates is the log-likelihood ratio (LLR). The LLR of bit b given an observation V is defined by equation (1):

[0039] (1)

[0040] The calculations described in this paper assume a base of 2 for the logarithm, but other base values ​​can be used. Figure 5 An exemplary tripartite diagram 500 is shown. The tripartite diagram 500 includes cell nodes 505, bit nodes 510, and check nodes 515.

[0041] Cell node 505 includes k information cells ("stores" the original n*k = 4*k information bits) and m parity cells ("stores" n*m = 4*m parity bits). Each cell node 505 is connected to t = 15 bit nodes, corresponding to t = 15 transformed information bits stored indirectly by the cell. Each parity cell node is connected to n = 4 bit nodes, corresponding to n = 4 parity bits stored directly by the cell. The operation performed between the information cell node 505 and its corresponding bit node 510 is an "expansion" operation from n = 4 read bits to t = 15 transformed bits. The expansion operation corresponds to a memory matching transformation at the log-likelihood ratio (LLR) level. The memory matching transformation performed between cell node 505 and bit node 510 calculates the LLR estimate of the transformed bits, denoted as message T. The LLR message from information cell node f to bit node v is calculated according to the following expression (2a):

[0042] (2a)

[0043] The LLR messages from parity unit node f to node v are calculated according to the following expression (2b):

[0044]

[0045] Where s(v) is the value of bit v in state s.

[0046] Calculate the LLR message from bit node v to cell node f according to expression (3):

[0047] (3)

[0048] Regular LDPC message passing decoding is performed between bit node 510 and check node 515 by exchanging bit-to-check messages (denoted as Q messages) and check-to-bit messages (denoted as R messages). The check node imposes parity constraints on the bit nodes connected to it (as guaranteed by the encoding operation that generates parity bits, ensuring that the parity constraints are met). The LLR message (transmitting the current bit estimate) from bit node v to check node c is calculated according to expression (4):

[0049] (4)

[0050] The LLR message from check node c to node v is calculated according to expression (5) (based on the fact that the bits connected to the check node should satisfy the parity constraint and the updated bit estimate is transmitted):

[0051] (5)

[0052] in .

[0053] exist Figure 5 In one example, each check node 515 is connected to four bit nodes 510. In other examples, each check node is connected to more or fewer than four bit nodes 510. The four bit nodes 510 connected to a given check node 515 are added to 0 (mod 2). If an error exists, the check node 515 is instead added to 1 (mod 2). Errors can then be detected and corrected when the check node 515 is added to 1. In some examples, the memory match transformation is also based on the current bit estimate delivered by the Q message.

[0054] return Figure 4 Four * (k+m) "hard bits" and four * (k+m) "soft bits" are input into the memory-matched LDPC decoder 415. The "soft" memory-matched transform decoding block 420 decodes the provided hard and soft bits (indicating the Vt value Y of the quantized read cell) and outputs 15 * k transformed pages and 4 * m parity bits in LLR form (hence this is a "soft" transform, delivering a soft estimate of the transformed information bits and parity bits). The soft memory-matched transform corresponds to an iterative message-passing operation performed between the cell node and the bit node. The LDPC decoder block 425 updates the LLR estimate of the bits by utilizing the fact that the 15 * k transformed bits and 4 * m parity bits should satisfy a set of parity constraints. This corresponds to a message-passing operation performed between the bit node and the parity node. Several iterations can be performed between the memory-matched transform decoding block 420 and the LDPC decoder block 425 until the bit estimates of the 15*k transformed bits and 4*m parity bits satisfy all parity constraints, indicating that the decoding operation has converged to a valid codeword. Once the decoding operation has converged to a valid codeword (indicating that the LDPC decoder block 425 has corrected all errors within the 15*k transformed pages), the LDPC decoder block 425 retrieves the original 4*k bits from the 15*k transformed pages (by applying the inverse hard memory matched transform) to output the corrected input data.

[0055] Figure 6 A QLC memory with multiple memory cell states 600 is shown. The multiple memory cell states 600 have a Gaussian distribution, where the standard deviation (σ) of state 0 (i.e., Er state) is a value that is α times larger than the values ​​of the other states. Figure 7 The text shows the results for various α values. Figure 6 The LDPC correction capability of the QLC memory. Figure 7A graph 700 is provided showing the decoder failure probability as a function of CER. The first curve 705 and the third curve 715 correspond to conventional LDPC decoding methods. The second curve 710 and the fourth curve 720 correspond to memory-matched LDPC decoding (also known as "m...)" as described herein. 2 (LDPC). Additionally, the first curve 705 and the second curve 710 correspond to α=4, while the third curve 715 and the fourth curve 720 correspond to α=1. As α increases and the memory model becomes more asymmetric (i.e., the variance between error rates at different read thresholds increases), the effectiveness of memory-matched LDPC decoding increases.

[0056] In addition to the benefits of improved correction capabilities, using the proposed memory-matched LDPC decoding offers several additional advantages. When using m 2 When LDPC is encoded, the error introduced by each read threshold affects a unique subset of bits (i.e., the specific transformed page associated with said read threshold). The error rate associated with each read threshold can be estimated by estimating the bit error rate (BER) of each transformed page. Assuming the decoder has converged, the error rate of the transformed page can be estimated by comparing the initial read bit value of the transformed page with the decoded, corrected bit value of the transformed page. Alternatively, the number of unsatisfied parity equations associated with the initial read bits of the transformed page can be used for BER estimation. The higher the number of unsatisfied parity constraints (aka checker weights), the higher the expected BER. This method can be applied even if decoding fails (because it is based solely on the initial read bit value). Estimating the BER of each read threshold can be used to estimate a potential memory error model or CVD associated with the read memory word line of non-volatile memory 104. This can, in turn, be used for access memory health. It can also be used to calculate the accurate LLR value of the decoder based on a more accurate estimate of P(Y|s).

[0057] Another application of the ability to estimate the BER per read threshold is adjusting and tuning the read threshold. An optimal read threshold can be found as the read threshold that minimizes its associated BER estimate. The directional BER per read threshold, indicating how many bits have been flipped from 0 to 1, can also be estimated by comparing the initial transformed page bit value before decoding with its decoded value. 0→1 And how many bits have been flipped from 1 to 0 (BER) 1→0 Directional BER can provide information on which direction the read threshold needs to be adjusted to minimize and balance BER. 0→1 and BER 1→0 Instructions.

[0058] The implementation described so far is based on LDPC decoding with iterative message passing decoding. However, the memory-matching decoding concept can also be applied to other decoding schemes. A memory-matching transformation can be applied to user data, and then any given decoding scheme (BCH, RS, or other suitable decoding scheme) can be applied to each transformed page in the transformed page. During the read operation, an inverse memory-matching transformation can be applied. The inverse memory-matching transformation can be a hard transformation (on the read bits) or a soft transformation (outputting the LLR of the soft decoder). After the inverse memory-matching transformation, decoding can be applied to correct errors on the transformed pages.

[0059] Regarding the processes, systems, methods, heuristics, etc., described herein, it should be understood that although the steps of such processes are described as being performed according to an ordered sequence, such processes can be practiced with the steps performed in a sequence other than that described herein. It should also be understood that some steps may be performed simultaneously, other steps may be added, or some steps described herein may be omitted. In other words, the description of processes herein is provided for the purpose of illustrating certain embodiments and should in no way be construed as limiting the claims.

[0060] Therefore, it should be understood that the above description is intended to be exemplary and not restrictive. Many embodiments and applications beyond the examples provided will be apparent upon reading the above description. The scope should not be determined by reference to the above description, but rather by reference to the full scope of the appended claims together with the equivalents to which such claims are entitled. It is anticipated and intended that the technology discussed herein will be further developed in the future, and the disclosed systems and methods will be incorporated into such future embodiments. In conclusion, it should be understood that modifications and variations are possible with this application.

[0061] All terms used in the claims are intended to be given their broadest reasonable construction and their common meaning as understood by one skilled in the art described herein, unless expressly indicated otherwise herein. Specifically, the use of singular articles such as “a,” “the,” “the,” etc., should be understood to mean one or more of the elements indicated in the statement, unless expressly limited to the contrary by the statement of the claims.

[0062] A summary of the specification is provided to allow readers to quickly determine the nature of the technical disclosure. It should be understood that the submitted content is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

Claims

1. A memory controller, comprising: A memory interface configured to connect to non-volatile memory; and The controller is configured to: Receive multiple data pages associated with a write command, said multiple data pages will be stored in the non-volatile memory, wherein said multiple data pages are N data pages. The plurality of data pages associated with the write command are transformed into a plurality of transformed data pages, wherein the plurality of transformed data pages is 2. N -1 data page, Multiple parity bits are determined based on the multiple transformed data pages, and The plurality of data pages and the plurality of parity bits are stored in the non-volatile memory; and Each of the plurality of transformed data pages is affected by an error in the associated read threshold of the non-volatile memory, such that the error introduces a bit error at each of the plurality of transformed data pages.

2. The memory controller of claim 1, wherein the bit error rate of the plurality of data pages is equal to the bit error rate of the plurality of transformed data pages.

3. The memory controller of claim 1, wherein the non-volatile memory comprises a plurality of memory cell states, and wherein the number of the plurality of transformed data pages is a number based on read thresholds of the plurality of memory cell states.

4. The memory controller of claim 1, wherein the controller is further configured to: Retrieve stored data pages and stored parity bits from the non-volatile memory. The stored data pages include multiple hard data bits and multiple soft data bits, and the stored parity bits include multiple hard parity bits and multiple soft parity bits.

5. The memory controller of claim 4, wherein the controller is further configured to: Transform the stored multiple data pages into a second set of transformed data pages, and Determine the log-likelihood ratio estimate of the second plurality of transformed data pages and the plurality of parity bits.

6. The memory controller of claim 5, wherein the controller is further configured to: Based on the log-likelihood ratio estimates of the second plurality of transformed data pages and the log-likelihood ratio estimates of the plurality of parity bits, a plurality of corrected data pages are generated.

7. The memory controller of claim 4, wherein the controller is further configured to: The stored multiple data pages are transformed into a second set of transformed data pages. Determine whether the second plurality of transformed data pages and the plurality of parity bits satisfy a set of parity constraints, and In response to the failure of the second plurality of transformed data pages and the plurality of parity bits to satisfy the set of parity constraints, the value of at least one of the second plurality of transformed data pages is adjusted.

8. The memory controller of claim 7, wherein the controller is further configured to: Determine whether the second plurality of transformed data pages and the plurality of parity bits satisfy the set of parity constraints, and Adjust the value of at least one of the second plurality of transformed data pages until the second plurality of transformed data pages and the plurality of parity bits satisfy the set of parity constraints.

9. The memory controller of claim 1, wherein the bit error distribution caused by the non-volatile memory on the plurality of transformed data pages is different from the error distribution on the plurality of data pages.

10. The memory controller of claim 1, wherein the controller is further configured to: The memory error model of the non-volatile memory is determined based on the estimated bit error rate of the multiple transformed data pages, and The health of the non-volatile memory is determined based on the memory error model.

11. The memory controller of claim 1, wherein the controller is further configured to: The read threshold of the non-volatile memory is adjusted based on the estimated bit error rate of the plurality of transformed data pages.

12. A method for operating a memory controller, the method comprising: Receive multiple data pages associated with a write command, which will be stored in non-volatile memory, wherein the multiple data pages are N data pages. The plurality of data pages associated with the write command are transformed into a plurality of transformed data pages, wherein the plurality of transformed data pages is 2. N -1 data page, Multiple parity bits are determined based on the multiple transformed data pages, and The plurality of data pages and the plurality of parity bits are stored in the non-volatile memory; and Each of the plurality of transformed data pages is affected by an error in the associated read threshold of the non-volatile memory, such that the error introduces a bit error at each of the plurality of transformed data pages.

13. The method of claim 12, wherein N is four, and wherein M is thirteen.

14. The method of claim 12, wherein the bit error rate of the plurality of data pages is equal to the bit error rate of the plurality of transformed data pages.

15. The method of claim 12, wherein the non-volatile memory comprises a plurality of memory cell states, and wherein the number of the plurality of transformed data pages is based on the number of the plurality of memory cell states.

16. The method of claim 12, further comprising: Retrieve stored data pages and stored parity bits from the non-volatile memory. The stored data pages include multiple hard data bits and multiple soft data bits, and the stored parity bits include multiple hard parity bits and multiple soft parity bits.

17. The method of claim 16, further comprising: Transform the stored multiple data pages into a second set of transformed data pages, and Determine the log-likelihood ratio estimate of the second plurality of transformed data pages and the plurality of parity bits.

18. The method of claim 17, further comprising: Based on the log-likelihood ratio estimates of the second plurality of transformed data pages and the log-likelihood ratio estimates of the plurality of parity bits, a plurality of corrected data pages are generated.

19. A memory device, comprising: Components for connecting to non-volatile memory; A component for receiving multiple data pages associated with a write command, the multiple data pages being stored in the non-volatile memory, wherein the multiple data pages are N data pages. A component for transforming the plurality of data pages associated with the write command into a plurality of transformed data pages, wherein the plurality of transformed data pages is 2 N -1 data page, A component for determining multiple parity bits based on the multiple transformed data pages, and Components for storing the plurality of data pages and the plurality of parity bits in the non-volatile memory; and Each of the plurality of transformed data pages is affected by an error in the associated read threshold of the non-volatile memory, such that the error introduces a bit error at each of the plurality of transformed data pages.

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