Memory chip test rack and memory chip test system

Abstract

The application discloses a storage chip test rack, which comprises a storage chip test seat, a main control module, a protocol conversion module, a peripheral circuit, a shunt power supply module, a total power supply, a current detection module and an MCU. The storage chip test seat is used for installing storage chips; the main control module is connected to the storage chip test seat and connected to a test computer through the protocol conversion module; the shunt power supply module is connected to the main control module and the storage chip test seat; the shunt power supply module converts the power output by the total power supply into shunt power and provides the shunt power for the storage chip test seat; the current detection module is connected between the total power supply and the shunt power supply module, the current detection module detects the current of the shunt power supply module and outputs a current detection signal; and the MCU outputs a power disconnect signal according to the current detection signal and a preset threshold value to control the shunt power supply module to turn off the power output. The application can reduce damage to the test seat and prolong the service life of the storage chip test rack.

Description

Technical Field

[0001] This application relates to the field of chip packaging testing, and more particularly to a test fixture and test system for testing memory chips. Background Technology

[0002] Solid-state drives (SSDs) are now one of the mainstream storage devices used in computers and other devices. Most SSDs consist of three main components: a controller, Dynamic Random Access Memory (DRAM), and NAND flash memory chips. NAND flash is composed of multiple blocks of non-volatile memory chips and is the primary data storage component. DRAM is volatile memory, requiring a continuous power supply to store data; some SSDs may not include DRAM. In the semiconductor storage industry, common flash memory chip packages include TSOP, BGA, and COB. BGA stands for Ball Grid Array. Common BGA package models for flash memory chips include BGA316, BGA272, BGA152, and BGA132. BGA152 and BGA132 have identical functional pins, differing only in their external dimensions. BGA316 and BGA272 also have identical functional pins, differing only in their external dimensions. For the consumer market, in order to minimize the decline in SSD yield caused by flash memory chip quality issues during the production of solid-state drives and other storage devices, the industry standard method is to perform testing and sorting (BGA Sorting) after the flash memory chips are BGA packaged.

[0003] In the testing and sorting process, memory chips need to be placed in a BGA test socket and test rack to form a solid-state drive (SSD) model, which is then connected to a test computer for testing. The test rack includes a power supply branch that powers the SSD model, converting the system power supply to the voltage required by the SSD model. However, when the power supply branch short-circuits due to a memory chip, the test computer connected to the SSD model cannot detect the short circuit, and the system power supply fails to automatically shut down to protect the circuit. Additionally, some memory chips, due to variations in the location of the damage, may not affect the firmware burning process for testing, but may cause high current and heat generation during testing. These short circuits or high currents can easily lead to overheating and damage to the BGA test socket, and prolonged exposure to this condition can severely impact the lifespan of the test rack. Summary of the Invention

[0004] The purpose of this application is to provide a memory chip test fixture that reduces or avoids damage to the test fixture due to memory chip quality issues and improves the service life of the test fixture.

[0005] A memory chip test fixture, connected to a test computer for testing memory chips, includes: a memory chip test socket, a main control module, a protocol conversion module, peripheral circuits, branch power supply modules, a main power supply, a current detection module, and an MCU. The memory chip test socket is used to mount memory chips to electrically connect them to the test fixture. The main control module is connected to the memory chip test socket and connected to the test computer via the protocol conversion module. The peripheral circuits are connected to both the main control module and the memory chip test socket. The branch power supply modules are connected to both the main control module and the memory chip test socket. The main power supply is connected to both the protocol conversion module and the branch power supply modules, and the branch power supply modules convert the power output from the main power supply into branch power supplies for the main control module and the memory chip test socket. The current detection module is connected between the main power supply and the branch power supply modules, and detects the current in the branch power supply modules and outputs a current detection signal. The MCU is connected to both the current detection module and the branch power supply modules, receives the current detection signal, and outputs a power disconnect signal based on the current detection signal and a preset threshold. The branch power supply modules shut off their power output based on the power disconnect signal.

[0006] Optionally, the memory chip test fixture also includes an alarm output module, which is connected to the MCU. The MCU outputs an alarm control signal based on the current detection signal and the preset threshold, and the alarm output module outputs an alarm presentation signal based on the alarm control signal.

[0007] Optionally, the alarm output module includes LEDs, a buzzer, and / or a display.

[0008] Optionally, the MCU may further output the alarm control signal to the test computer.

[0009] Optionally, the shunt power module includes a DC-DC converter, and the MCU shuts off the power output of the shunt power module by outputting a power disconnect signal to the enable pin of the DC-DC converter.

[0010] Optionally, the memory chip is a BGA-packaged flash memory chip, and the memory chip test socket is a BGA test socket.

[0011] Optionally, the BGA test socket is compatible with various types of BGA packaged memory chips.

[0012] Optionally, the preset threshold includes a first threshold and a second threshold. When the current detection signal reaches or exceeds the first threshold, and the duration of the current detection signal reaching or exceeding the first threshold exceeds the second threshold, the MCU outputs the power disconnect signal.

[0013] Optionally, the protocol conversion module includes a SATA to USB conversion module, and the main control module is a SATA main control module.

[0014] A memory chip testing system includes a test computer and a memory chip test rack connected to the test computer. The memory chip test rack includes: a memory chip test socket, a main control module, a protocol conversion module, peripheral circuits, branch power supply modules, a main power supply, a current detection module, and an MCU. The memory chip test socket is used to mount memory chips for electrical connection to the test rack. The main control module is connected to the memory chip test socket and connected to the test computer via the protocol conversion module. The peripheral circuits are connected to the main control module and the memory chip test socket. The branch power supply modules are connected to the main control module and the memory chip test socket. The main power supply is connected to the protocol conversion module and the branch power supply modules, and the branch power supply modules convert the power output from the main power supply into branch power supplies for the main control module and the memory chip test socket. The current detection module is connected between the main power supply and the branch power supply modules, and detects the current of the branch power supply modules and outputs a current detection signal. The MCU is connected to the current detection module and the branch power supply modules, receives the current detection signal, and outputs a power disconnect signal based on the current detection signal and a preset threshold. The branch power supply modules shut off their power output based on the power disconnect signal.

[0015] According to the memory chip test fixture and system of the present invention, a current detection module connected between the main power supply and the branch power supply modules in the test fixture detects the current between the main power supply and the branch power supply modules and generates a current detection signal. The MCU monitors the current in the circuit based on the current detection signal. When the internal circuit of the memory chip is damaged, causing a large current or abnormal current to be generated in the test socket and the connected branch power supply module, the MCU can output a corresponding alarm control signal in a timely manner according to the current detection signal and a preset threshold to control the branch power supply module to shut down the power output, reduce the damage of the large current to the components in the branch power supply module and the test socket, and improve the service life of the memory chip test fixture. Attached Figure Description

[0016] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A block diagram of a memory chip testing system according to an embodiment of the present invention is shown;

[0018] Figure 2 A schematic diagram illustrating the process of testing memory chips using the memory chip test fixture of an embodiment of the present invention is shown. Detailed Implementation

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0020] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0021] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0022] like Figure 1The diagram shows a schematic of a memory chip testing system according to an embodiment of the present invention. The testing system 1 includes a test computer 10 and a test rack 20. The test rack 20 is connected to the test computer 10 via a USB interface. The test computer 10 controls the test rack 20 to test the memory chips according to a predetermined test program. Specifically, the test computer 10 is pre-installed with software tools for BGA sorting and provides a visual test interface through a display screen. The test rack 20 is used to install the memory chips to be tested, such as NAND Flash chips, and to test the memory chips according to the test program to screen out qualified chips.

[0023] The test fixture 20 includes a memory chip test socket 200, a SATA host control module 201, peripheral circuitry 202, a protocol conversion module 203, a branch power supply module 204, a main power supply 205, a current detection module 206, an MCU 207, and an alarm output module 208. A single test fixture 20 may include multiple memory chip test sockets 200, each of which can be a compatible design, accommodating memory chips in various package sizes. For example, in an embodiment where the memory chip test socket 200 is a BGA test socket, the socket can be compatible with flash memory chips in BGA152 and BGA132 packages, or with BGA316 and BGA272 packages. Memory chips (not shown) can be connected to and positioned within the test fixture 20 via the memory chip test socket 200. The storage chip test socket 200 is interconnected with the SATA main control module 201 and peripheral circuits 202. After the storage chip is installed in the storage chip test socket 200, the storage chip, storage chip test socket 200, SATA main control module 201, and peripheral circuits 202 combine to form a SATA solid-state drive model, where the SATA main control module serves as the main control module for this solid-state drive. Because the solid-state drive interface uses a SATA interface, a protocol conversion module 203 is provided between the test computer 10 and the SATA main control module 201 to enable data transmission between devices with different interfaces. The protocol conversion module 203 can be a SATA to USB protocol conversion chip. Of course, the SATA main control module can also be a main control module for other types of solid-state drive interfaces. The branch power module 204 is used to convert the power from the main power supply 205 into the power required by the SATA main control module 201 and the storage chip test socket 200. The branch power module 204 can be a DC-DC converter. The main power supply 205 can also be used to power the protocol conversion module 203. The test computer 10 has a separate power supply line and does not share the main power supply 205 with the test rack 20. Although not shown in the diagram, it should be understood that the MCU207 and alarm output module 208 can be powered by the main power supply 205, or via one or more branch power supplies connected to the main power supply 205.

[0024] A current detection module 206 is connected between the main power supply 205 and the branch power supply module 204. It detects the current in the branch power supply module 204 and outputs a current detection signal. This signal can be a current signal or a voltage signal corresponding to the current magnitude. An MCU 207 is connected to both the power detection module 206 and the branch power supply module 204. The MCU 207 monitors the test fixture current based on the received current detection signal. Specifically, it can control whether the branch power supply module 204 is turned off based on the current detection signal. If the current detection signal representing the current in the branch power supply module 204 reaches or exceeds a first threshold, and the duration of reaching or exceeding the first threshold exceeds a second threshold, the MCU 207 outputs a power disconnect signal to control the branch power supply module 204 to turn off its power output. This effectively disconnects the power supply to the memory chip test socket 200, effectively breaking the electrical connection with the memory chip test socket 200. This allows for timely disconnection of the test socket's power supply when a short circuit occurs in the power supply module 204 due to damage to certain circuits within the memory chip, preventing the memory chip test socket 200 connected to the power supply module 204 from being damaged by a large current. In one example, the MCU 207 can control the enable pin (EN pin) of the DC-DC converter to shut down the output of the power supply module, thereby protecting the circuit and the BGA test socket.

[0025] Optionally, the MCU207 can also output an alarm control signal to the connected alarm output module 208 based on the monitored abnormal current, such as based on the current detection signal and a preset threshold. The alarm output module 208 then outputs an alarm presentation signal based on the alarm control signal. The preset threshold may include the aforementioned first threshold or a combination of the first and second thresholds. The alarm presentation signal may be a light signal, a sound signal, or other signals used to present alarm information, or a combination of multiple signals. The alarm output module 208 may be an LED light, a buzzer, and / or other signal output components in the test system, such as the monitor of the test computer 10, an external communication alarm module, etc. The alarm notification mechanism can promptly remind the operator that there is a damaged memory chip on the test rack 20, so that the damaged memory chip can be removed from the test rack in time, reducing wear and tear on the memory chip test rack 20 and thus increasing its service life, and also improving the overall efficiency of chip testing. The MCU207 can also feed back the alarm control signal to the test computer 10 so that the test computer 10 can promptly stop the test of the memory chip with the current short circuit problem based on the alarm control signal.

[0026] The method for testing memory chips using the aforementioned memory chip test fixture mainly includes: reading the original manufacturer's bad block identifier; determining whether the memory chip meets the requirements based on the original manufacturer's bad block identifier; if it meets the requirements, burning the RDT test firmware and performing RDT testing; marking read / write test bad blocks (RDT test bad blocks) and generating RDT test data during the RDT test; and re-evaluating the memory chip's qualification based on the RDT test bad block data. For detailed procedures, please refer to [reference needed]. Figure 2 And the corresponding description.

[0027] Please refer to Figure 2 This is a schematic diagram of the process of testing memory chips using the memory chip test fixture of this embodiment of the invention.

[0028] S01: Read the original bad block identifier.

[0029] The initial step of the test involves reading the original manufacturer's bad block identifier. This identifier determines whether the memory chip on the test socket meets the company's or customer's requirements. If it does not, further testing is deemed unnecessary. This step follows the firmware tool K1 process.

[0030] S02: Determine whether the memory chip meets the requirements based on the original manufacturer's bad block markings.

[0031] Based on the read original manufacturer bad block identifier, it can be determined whether the memory chip meets the requirements. A judgment threshold can be set or read during the testing process; for example, the threshold can be set as the number of bad blocks. Once the number of bad blocks exceeds the threshold, it is determined that the chip does not meet the requirements, and step S08 is executed to classify the memory chip as a defective product. If the chip meets the requirements, step S03 is executed.

[0032] S03: Burn the RDT test firmware.

[0033] S04: Perform RDT testing, mark RDT test bad blocks, and generate RDT test bad block data.

[0034] Based on the burned RDT test firmware, the test computer 10 performs read and write tests on the storage chips in the hard disk model, and marks RDT test bad blocks according to the read and write test results, generating RDT test bad block data. Bad block data is automatically marked during the RDT test.

[0035] S05: Read RDT test bad block data.

[0036] This step, often referred to as the Firmware Tool K2 process, involves reading the RDT test bad block data obtained during the RDT test. RDT test bad blocks are those discovered during the RDT test and differ from the bad blocks marked by the manufacturer.

[0037] S06: Determine whether the memory chip is qualified based on the bad block data from the RDT test.

[0038] Based on the bad block data read from the RDT test, the memory chips that were deemed qualified in the K1 stage are re-evaluated to determine whether they are qualified or not.

[0039] S07: Determined to be a qualified memory chip.

[0040] S08: Determined to be a defective memory chip.

[0041] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0042] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0043] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environmental and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document.

[0044] The foregoing specific descriptions have been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, considerations for this disclosure are to be illustrative rather than restrictive, and all such modifications are to be included within its scope. Similarly, advantages, other advantages, and solutions to problems with respect to various embodiments have been described above. However, benefits, advantages, solutions to problems, and any elements that produce these, or make them more explicit, should not be construed as critical, essential, or necessary. The term “comprising” and any other variations thereof as used herein are non-exclusive inclusion, meaning that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or not part of the process, method, system, article, or apparatus. Furthermore, the term “coupled” and any other variations thereof as used herein refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and / or any other connections.

[0045] Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the basic principles of the invention. Therefore, the scope of the invention should be determined according to the foregoing claims.

Claims

1. A memory chip test fixture for connecting to a test computer to test memory chips, characterized in that, include: A memory chip test socket is used to mount the memory chip to electrically connect the memory chip to the memory chip test fixture; The main control module is connected to the memory chip test socket; A protocol conversion module is provided, through which the main control module is connected to the test computer. Peripheral circuitry is connected to the main control module and the memory chip test socket; A branch power supply module is connected to the main control module and the memory chip test socket; The main power supply is connected to the protocol conversion module and the branch power supply module. The branch power supply module converts the power output from the main power supply into branch power to provide to the main control module and the memory chip test socket. A current detection module is connected between the main power supply and the branch power supply module. The current detection module detects the current of the branch power supply module and outputs a current detection signal. and The MCU is connected to the current detection module and the branch power supply module. The MCU receives the current detection signal and outputs a power disconnect signal based on the current detection signal and a preset threshold. The branch power supply module shuts off the power output based on the power disconnect signal. The power supply module includes a DC-DC converter. The MCU shuts off the power output of the power supply module by outputting a power disconnect signal to the enable pin of the DC-DC converter. The preset threshold includes a first threshold and a second threshold. When the current detection signal reaches or exceeds the first threshold, and the duration of the current detection signal reaching or exceeding the first threshold exceeds the second threshold, the MCU outputs the power-off signal. The memory chip test fixture also includes an alarm output module connected to the MCU. The MCU outputs an alarm control signal based on the current detection signal and the preset threshold. The alarm output module outputs an alarm presentation signal based on the alarm control signal. The alarm output module includes an LED, a buzzer, and / or a display. The MCU outputs the alarm control signal to the test computer. The protocol conversion module includes a SATA to USB conversion module, and the main control module is a SATA main control module.

2. The memory chip test fixture as described in claim 1, characterized in that, The memory chip is a BGA-packaged flash memory chip, and the memory chip test socket is a BGA test socket.

3. The memory chip test fixture as described in claim 2, characterized in that, The BGA test socket is compatible with various models of BGA packaged memory chips.

4. A memory chip testing system, characterized in that, include: The memory chip test fixture according to any one of claims 1-3; The test computer is connected to the memory chip test fixture.

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