A memory detection method and a detection device, and a storage medium

Abstract

The embodiment of the application discloses a storage fault detection method and detection equipment, and a storage medium, comprising: an operation type register, used for obtaining a storage address corresponding to a first operation value and first data from a data register in the case of receiving the first operation value transmitted by a processor; writing the first data in a target storage corresponding to the storage address; the data in the data register is data written by the processor; a detection result register, used for obtaining second data from a target storage corresponding to a second operation value in the case of the value in the operation type register being the second operation value; determining a detection result of a storage detection process of the target storage according to the first data and the second data; and reading the detection result from the detection result register and transmitting the detection result to the processor in the case of receiving a detection result acquisition instruction transmitted by the processor.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a memory detection method, detection equipment, and storage medium. Background Technology

[0002] In server systems, multiple Double Data Rate (DDR) chips are typically connected alongside the Central Processing Unit (CPU) as the CPU's main memory, storing the CPU's code and data. The correct read / write functionality of the DDR chips is fundamental to ensuring the normal operation of the server system. To guarantee DDR chip read / write functionality, servers usually undergo self-testing tests on the DDR chips used during manufacturing to ensure reliable delivery.

[0003] In related technologies, the hardware provides the basic read and write channels and functions for DDR chips. The CPU implements the above-mentioned DDR self-test process through software instructions. First, special data is written, and then it is read out for verification. If the data is correct, it passes; if the data does not meet expectations, it fails. Since DDR self-test usually requires reading and writing all addresses of the DDR chip, large-capacity DDR chips need to be read and written hundreds of millions of times. Moreover, the latency of each CPU read from the DDR chip is large, which reduces the speed of memory detection. Summary of the Invention

[0004] To address the aforementioned technical problems, this application aims to provide a storage fault detection method, detection device, and storage medium that can improve the detection speed of the memory.

[0005] The technical solution of this application is implemented as follows:

[0006] This application provides a detection device, the detection device comprising:

[0007] An operation type register is used to obtain the memory address and first data corresponding to the first operation value from the data register when a first operation value is received from the processor; and to write the first data into the target memory corresponding to the memory address; the data in the data register is the data written by the processor.

[0008] The detection result register is used to: acquire second data from the target memory corresponding to the second operation value when the value in the operation type register is the second operation value; determine the detection result of the storage detection process of the target memory based on the first data and the second data; and read the detection result from the detection result register and transmit the detection result to the processor when a detection result acquisition instruction is received from the processor.

[0009] This application provides a storage fault detection method, the method comprising:

[0010] Upon receiving a first operation value transmitted by the processor, the memory address and first data corresponding to the first operation value are obtained; the memory address and the first data are the data transmitted by the processor.

[0011] The first data is stored in the target memory corresponding to the memory address;

[0012] Upon receiving the second operation value transmitted by the processor, the second data is retrieved from the target memory;

[0013] The detection result of the storage detection process of the target memory is determined based on the first data and the second data;

[0014] Upon receiving a detection result acquisition instruction transmitted by the processor, the detection result is transmitted to the processor.

[0015] This application provides a storage medium storing a computer program for use in a testing device. The computer program, when executed by a processor in the testing device, implements the storage fault detection method described above.

[0016] This application provides a storage fault detection method, detection device, and storage medium. The detection device includes: an operation type register, used to, upon receiving a first operation value transmitted by a processor, obtain a memory address and first data corresponding to the first operation value from a data register; write the first data into a target memory corresponding to the memory address; the data in the data register is the data written by the processor; and a detection result register, used to, when the value in the operation type register is a second operation value, obtain second data from the target memory corresponding to the second operation value; determine the detection result of the storage detection process of the target memory based on the first data and the second data; and, upon receiving a detection result acquisition instruction transmitted by the processor, read the detection result from the detection result register and transmit the detection result to the processor. The above-described scheme utilizes the operation value in the operation type register to identify the data reading task of the target memory indicated by the processor. It obtains the memory address and first data corresponding to the first operation value from the data register. The first data is written into the target memory corresponding to the memory address. If the value in the operation type register is detected as the second operation value, the second data is directly read from the target memory corresponding to the second operation value using the detection result register. The second data and the first data are then compared to obtain the detection result. In other words, the hardware compares and verifies the second data read from the target memory with the first data, eliminating the need for software (processor, i.e., CPU) to verify the second data read from the target memory. This saves CPU (processor) register reading time and thus improves the speed of memory detection. Attached Figure Description

[0017] Figure 1 A schematic diagram of the composition structure of a detection device provided in this application embodiment. Figure 1 ;

[0018] Figure 2 A schematic diagram of the composition structure of an exemplary detection device provided in this application embodiment. Figure 2 ;

[0019] Figure 3 This is a flowchart of a storage fault detection method provided in an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0021] This application provides a detection device, such as... Figure 1 As shown, the testing device 1 may include:

[0022] Operation type register 11 is used to obtain the memory address and first data corresponding to the first operation value from data register 12 when a first operation value is received from the processor; and to write the first data into the target memory corresponding to the memory address; the data in the data register is the data written by the processor.

[0023] The detection result register 13 is used to: acquire second data from the target memory corresponding to the second operation value when the value in the operation type register is the second operation value; determine the detection result of the storage detection process of the target memory based on the first data and the second data; and read the detection result from the detection result register and transmit the detection result to the processor when a detection result acquisition instruction is received from the processor.

[0024] The detection device provided in this application embodiment is suitable for scenarios involving fault detection of target memory.

[0025] In the embodiments of this application, the detection device can be implemented in various forms. For example, the detection device described in this application may include devices such as mobile phones, cameras, tablet computers, laptops, handheld computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., as well as devices such as digital TVs, desktop computers, servers, etc.

[0026] In this embodiment of the application, the data register includes an address register and a write data register.

[0027] It should be noted that the address register is used to store the address of the target memory, that is, to store the memory address. The write data register is used to store the data to be written to the target memory, that is, to store the first data.

[0028] It should be noted that the number of the first data can be determined according to the actual situation, and this application embodiment does not limit it.

[0029] In the embodiments of this application, the target memory can be DDR, or it can be other types of memory. The specific target memory can be determined according to the actual situation, and this application does not limit it.

[0030] It should be noted that the number of target memories can be determined according to the actual situation, and this application embodiment does not limit this. The address register is used to store the address of each target memory.

[0031] In this embodiment of the application, the operation type register is the operation identifier (second operation value) corresponding to the read access operation of the storage DDR, or the operation identifier (first operation value) corresponding to the write access operation of the storage DDR.

[0032] It should be noted that the first operation value indicates a write operation access to the DDR, and the second operation value indicates a read operation access to the DDR.

[0033] In this embodiment, the detection device further includes a data expected value register 14 for storing values ​​written into the target memory, i.e., storing first data. After obtaining second data from the target memory corresponding to the second operation value, the first data can be obtained from the data expected value register, and then the detection result of the storage detection process of the target memory can be determined based on the first data and the second data.

[0034] Optionally, data register 12 includes address register 121 and write data register 122:

[0035] The operation type register 11 is used to obtain the storage address corresponding to the first operation value from the address register 121 and obtain the first data corresponding to the first operation value from the write data register 122 when the first operation value is received from the processor.

[0036] In this embodiment, the value in the operation type register is data written by the processor (CPU). The data in the data memory (including the memory address and the first data) is data written by the processor.

[0037] In this embodiment, when the detection device receives the memory address to be processed and transmitted, it writes the memory address into the address register. When the detection device receives the first data transmitted by the processor, it writes the first data into the data register.

[0038] It should be noted that the processor can be a central processing unit (CPU) or other processor devices, and the specific type can be determined according to the actual situation. This application does not limit this.

[0039] Optionally, the operation type register 11 is used to store the first operation value when the first operation value is received;

[0040] The address register 121 is used to store the memory address when a memory address is received;

[0041] The write data register 122 is used to store the first data upon receiving the first data.

[0042] It should be noted that there can be multiple memory addresses, and the specific number of memory addresses can be determined according to the actual situation. This application does not limit this.

[0043] It should also be noted that the number of memory addresses corresponds one-to-one with the number of target memories, meaning one memory address corresponds to one target memory. In other words, there can be multiple target memories, and the specific number can be determined based on actual circumstances; this application does not limit this.

[0044] In this embodiment of the application, the first operation value can be 1, 110, or other values; the specific first operation value can be determined according to the actual situation, and this embodiment of the application does not limit it.

[0045] In the embodiments of this application, the first data can be 0x5a5a5a5a, the first data can also be 0xa5a5a5a5, or other values. The specific first data can be determined according to the actual situation, and the embodiments of this application do not limit it.

[0046] It should be noted that this application does not limit the length of the first data.

[0047] Optionally, the detection result register 13 is used to obtain the memory address corresponding to the second operation value from the address register, and to obtain the second data from the target memory corresponding to the memory address.

[0048] In this embodiment, the memory address is the address of the device whose data read operation corresponds to the second operation value, and is associated with the second operation value. The specific correspondence between the second operation value and the memory address can be any data correspondence method, and this embodiment does not limit this.

[0049] Optionally, the detection result register 13 is used to transmit an instruction to the scheduler to read the second data from the target memory, so that the scheduler 14 can obtain the second data from the target memory.

[0050] In this embodiment, the scheduler is used to schedule multiple requests for simultaneous access to the target memory by the detection device and other modules (e.g., other modules accessing the target memory) and to distribute read return data.

[0051] It should be noted that the scheduler can be any scheduler in the prior art, or other devices that can implement multi-request scheduling; the specific scheduler can be determined according to the actual situation, and this application embodiment does not limit it in this regard.

[0052] Optionally, the operation type register 11 is used to store the second operation value when the second operation value is received.

[0053] In the embodiments of this application, the second operation value can be 0, 001, or other values; the specific second operation value can be determined according to the actual situation, and the embodiments of this application do not limit it.

[0054] In this embodiment of the application, the data length of the second operation value can be determined according to the actual situation, and this embodiment of the application does not limit it.

[0055] Optionally, the operation type register 11 is used to transmit an instruction to the scheduler to write the first data to the target memory, so that the scheduler can write the first data to the target memory.

[0056] Optionally, operation type register 11 is used to group multiple memory addresses to obtain at least two sets of addresses; group multiple target memories according to the at least two sets of addresses to obtain at least two sets of target memories; and write at least two first data items into the at least two sets of target memories.

[0057] It should be noted that the number of the first data is at least two, the number of the memory addresses is multiple, and the number of target memories is multiple.

[0058] In this embodiment, the method of grouping multiple memory addresses to obtain at least two sets of addresses can be: grouping multiple memory addresses according to the parity of the address data to obtain two sets of addresses; or grouping multiple memory addresses according to a preset number of addresses to obtain at least two sets of addresses; or grouping multiple memory addresses according to other grouping methods to obtain at least two sets of addresses. The specific method of grouping multiple memory addresses to obtain at least two sets of addresses can be determined according to the actual situation, and this embodiment does not limit it.

[0059] In this embodiment of the application, the method of grouping multiple target memories according to the at least two sets of addresses to obtain at least two sets of target memories can be: obtaining each set of target memories corresponding to each set of addresses in the at least two sets of addresses, thereby obtaining at least two sets of target memories.

[0060] Optionally, a detection result register is used to obtain the at least two sets of second data from the at least two sets of target memories; compare the at least two sets of first data with the at least two sets of second data to obtain the detection result; and store the detection result.

[0061] It should be noted that the at least two sets of target memories correspond one-to-one with the at least two sets of second data. Specifically, one set of target memories corresponds to one set of second data.

[0062] It should be noted that the second set of data consists of at least two sets.

[0063] In this embodiment, the detection result includes detection success and detection failure. Detection success means there is no storage fault, while detection failure means there is a storage fault.

[0064] It should be noted that after the detection result is determined, the corresponding identifier value is written into the detection result register.

[0065] It should be noted that the detection result identifier corresponding to a successful detection can be 1, or it can be other identifier values. The specific detection result identifier value corresponding to a successful detection can be determined according to the actual situation, and this application embodiment does not limit it in this way.

[0066] It should be noted that the detection result identifier corresponding to the detection failure can be 0, or it can be other identifier values. The specific detection result identifier value corresponding to the detection failure can be determined according to the actual situation, and this application embodiment does not limit it.

[0067] For example, the CPU first selects several test data (first data), such as 0x5a5a5a5a and 0xa5a5a5a5. Then, it divides the addresses (memory addresses) into several groups, writing the same data to each group of addresses; for example, odd-numbered addresses are written to 0x5a5a5a5a, and even-numbered addresses are written to 0xa5a5a5a5. The CPU then writes the test data to the expected value register and initiates a read request for the corresponding address space. The self-test module (detection device) checks whether the data returned by these reads matches the value in the expected register. If they differ, the data verification result register is set to 1. If there are several groups of address spaces with different expected values, the above operation is performed the same number of times. In this way, the CPU performs a large number of register write operations and a final register read operation in the entire self-test process, thus completing the write operations to all addresses of the DDR chip (target memory), the read operations to all addresses, and the data verification. In this way, the data checking function required for self-testing is realized, while the hardware uses as few hardware resources as possible to realize the dedicated self-testing function, and the self-testing time is greatly saved compared with the pure software solution.

[0068] Understandably, this application designs a new hardware self-test register interface, through which our designed hardware and software co-operation self-test process can be implemented. This application pre-writes the expected data value into the hardware register, transforming the original step of the CPU determining whether the DDR chip read return data matches the expectation into a hardware comparison between the read return data and the hardware expected value register, avoiding CPU register read operations and saving significant register read time. This application divides the address space of the DDR chip (target memory) into multiple groups, with each group containing the same data. All read return data comparisons can use the same expected data register, further reducing the configuration time of the expected data register.

[0069] In this application embodiment, an exemplary storage fault detection block diagram is shown as follows: Figure 2The diagram shows a system comprising a CPU module (processor), a self-test module (detection device), other modules for accessing DDR chips, a DDR scheduler module (scheduler), and a DDR chip module (target memory). The CPU module executes software instructions and controls the entire self-test process by reading and writing registers in the self-test module. The self-test module is the core module of this solution, internally divided into a DDR request processing module and a DDR read return processing module. This module handles all the hardware registers required for DDR self-testing. The software controls the self-test module's operation by reading and writing these registers. After receiving register read / write requests, the self-test module performs write operations, read operations, and read return data verification on the DDR chip according to the process. The DDR request module receives write register operations from the CPU and converts them into write and read requests for the DDR chip. The DDR read return processing module receives read return data from the DDR chip in response to previous DDR read requests, verifies the read return data, and records the verification results. Finally, the CPU reads the verification result register in the DDR read return processing module to determine whether the self-test process has passed. DDR Scheduler: Used to schedule multiple requests from the self-test module and other modules (e.g., other modules accessing DDR chips) to simultaneously access the DDR chip, and to distribute read return data; DDR Chip: The DDR chip to be tested in this self-test process; Other Modules Accessing DDR Chips: As the name suggests, these are modules not involved in this solution. Specifically, when the testing device receives a first operation value, it writes the first operation value to the operation type register; when it receives a memory address and first data, it writes the memory address and first data to the data register. If the value in the operation type register is the first operation value, it retrieves the memory address corresponding to the first operation value from the address register; it retrieves the first data corresponding to the first operation value from the write data register; it transmits an instruction to the scheduler to write the first data to the target memory, so that the scheduler can write the first data to the target memory; when a second operation value is received, it writes the second operation value to the operation type register. If the value in the operation type register is the second operation value, the memory address corresponding to the second operation value is obtained from the address memory; an instruction to read the second data from the target memory is transmitted to the scheduler, so that the second data can be obtained from the target memory through the scheduler; the detection result of the target memory is determined according to the first data and the second data, and the detection result is written into the detection result register; if the detection result acquisition instruction is received from the processor, the detection result is read from the detection result register and transmitted to the processor.

[0070] Understandably, the detection device uses the operation value in the operation type register to identify the data reading task of the target memory indicated by the processor, obtains the memory address and first data corresponding to the first operation value from the data register, writes the first data into the target memory corresponding to the memory address, and if the value in the operation type register is detected as the second operation value, it directly reads the second data from the target memory corresponding to the second operation value using the detection result register, and compares the second data with the first data to obtain the detection result. That is, the hardware compares and verifies the second data read from the target memory with the first data, without the need for software (processor, i.e., CPU) to verify the second data read from the target memory, saving the CPU (processor) register reading time and thus improving the speed of memory detection.

[0071] This application provides a storage fault detection method, which is applied to a detection device. Figure 3 A flowchart of a storage fault detection method provided in an embodiment of this application is shown below. Figure 3 As shown, storage fault detection methods may include:

[0072] S101. Upon receiving a first operation value transmitted by the processor, obtain the memory address and first data corresponding to the first operation value; the memory address and first data are the data transmitted by the processor.

[0073] The storage fault detection method provided in this application embodiment is applicable to scenarios where fault detection is performed on the target memory.

[0074] In the embodiments of this application, the detection device can be implemented in various forms. For example, the detection device described in this application may include devices such as mobile phones, cameras, tablet computers, laptops, handheld computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., as well as devices such as digital TVs, desktop computers, servers, etc.

[0075] In this embodiment of the application, the memory address and first data corresponding to the first operation value can be obtained from the data register, which includes an address register and a write data register.

[0076] It should be noted that the address register is used to store the address of the target memory, that is, to store the memory address. The write data register is used to store the data to be written to the target memory, that is, to store the first data.

[0077] It should be noted that the number of the first data can be determined according to the actual situation, and this application embodiment does not limit it.

[0078] In the embodiments of this application, the target memory can be DDR, or it can be other types of memory. The specific target memory can be determined according to the actual situation, and this application does not limit it.

[0079] It should be noted that the number of target memories can be determined according to the actual situation, and this application embodiment does not limit this. The address register is used to store the address of each target memory.

[0080] In this embodiment of the application, the operation type register is the operation identifier (second operation value) corresponding to the read access operation of the storage DDR, or the operation identifier (first operation value) corresponding to the write access operation of the storage DDR.

[0081] It should be noted that the first operation value indicates a write operation access to the DDR, and the second operation value indicates a read operation access to the DDR.

[0082] In this embodiment, the value in the operation type register is data written by the processor (CPU). The data in the data memory (including the memory address and the first data) can be data written by the processor.

[0083] In this embodiment, when the detection device receives the memory address to be processed and transmitted, it writes the memory address into the address register. When the detection device receives the first data transmitted by the processor, it writes the first data into the data register.

[0084] S102. Store the first data in the target memory corresponding to the memory address.

[0085] In this embodiment of the application, after the detection device obtains the memory address and the first data corresponding to the first operation value, it uses the target memory corresponding to the memory address to store the first data.

[0086] In this embodiment of the application, the detection device can transmit an instruction to the scheduler to write the first data to the target memory, so that the scheduler can write the first data to the target memory.

[0087] In this embodiment, the scheduler is used to schedule multiple requests for simultaneous access to the target memory by the detection device and other modules (e.g., other modules accessing the target memory) and to distribute read return data.

[0088] It should be noted that the scheduler can be any scheduler in the prior art, or other devices that can implement multi-request scheduling; the specific scheduler can be determined according to the actual situation, and this application embodiment does not limit it in this regard.

[0089] In this embodiment of the application, the number of first data is at least two, the number of memory addresses is multiple, and the number of target memories is multiple. The process by which the detection device stores the first data using the target memories corresponding to the memory addresses includes: grouping the multiple memory addresses to obtain at least two groups of addresses; grouping the multiple target memories according to the at least two groups of addresses to obtain at least two groups of target memories; and writing at least two first data into the at least two groups of target memories.

[0090] It should be noted that the number of first data items is at least two, the number of memory addresses is multiple, and the number of target memories is multiple.

[0091] In this embodiment, the method of grouping multiple memory addresses to obtain at least two sets of addresses can be: grouping multiple memory addresses according to the parity of the address data to obtain two sets of addresses; or grouping multiple memory addresses according to a preset number of addresses to obtain at least two sets of addresses; or grouping multiple memory addresses according to other grouping methods to obtain at least two sets of addresses. The specific method of grouping multiple memory addresses to obtain at least two sets of addresses can be determined according to the actual situation, and this embodiment does not limit it.

[0092] In this embodiment of the application, the method of grouping multiple target memories according to at least two sets of addresses to obtain at least two sets of target memories can be: obtaining each set of target memories corresponding to each set of addresses in at least two sets of addresses, thereby obtaining at least two sets of target memories.

[0093] In this embodiment of the application, the number of second data is at least two sets; the process by which the detection device determines the detection result of the storage detection process of the target memory based on the first data and the second data includes: obtaining at least two sets of second data from at least two sets of target memories; comparing at least two sets of first data with at least two sets of second data to obtain the detection result.

[0094] It should be noted that at least two sets of target memories correspond one-to-one with at least two sets of second data. Specifically, one set of target memories corresponds to one set of second data.

[0095] It should be noted that the second set of data consists of at least two sets.

[0096] In this embodiment, the detection result includes detection success and detection failure. Detection success means there is no storage fault, while detection failure means there is a storage fault.

[0097] It should be noted that after the detection result is determined, the corresponding identifier value is written into the detection result register.

[0098] It should be noted that the detection result identifier corresponding to a successful detection can be 1, or it can be other identifier values. The specific detection result identifier value corresponding to a successful detection can be determined according to the actual situation, and this application embodiment does not limit it in this way.

[0099] It should be noted that the detection result identifier corresponding to the detection failure can be 0, or it can be other identifier values. The specific detection result identifier value corresponding to the detection failure can be determined according to the actual situation, and this application embodiment does not limit it.

[0100] In this embodiment of the application, the detection device can transmit an instruction to the scheduler to read second data from the target memory, so as to obtain at least two sets of second data from at least two sets of target memories through the scheduler.

[0101] S103. Upon receiving the second operation value transmitted by the processor, retrieve the second data from the target memory.

[0102] In this embodiment of the application, after the detection device stores the first data in the target memory corresponding to the memory address, it retrieves the second data from the target memory upon receiving the second operation value transmitted by the processor.

[0103] In this embodiment of the application, the process of the detection device obtaining second data from the target memory includes: obtaining the memory address corresponding to the second operation value; and obtaining the second data from the target memory corresponding to the memory address.

[0104] In this embodiment, the memory address is the address of the device whose data read operation corresponds to the second operation value, and is associated with the second operation value. The specific correspondence between the second operation value and the memory address can be any data correspondence method, and this embodiment does not limit this.

[0105] S104. Determine the detection result of the storage detection process of the target memory based on the first data and the second data.

[0106] In this embodiment of the application, after the detection device obtains the second data from the target memory, it determines the detection result of the storage detection process of the target memory based on the first data and the second data.

[0107] S105. Upon receiving the detection result acquisition instruction transmitted by the processor, transmit the detection result to the processor.

[0108] In this embodiment of the application, after the detection device determines the detection result of the storage detection process of the target memory based on the first data and the second data, it transmits the detection result to the processor upon receiving the detection result acquisition instruction transmitted by the processor.

[0109] In this embodiment, upon receiving a detection instruction from the target memory, the processor (central processing unit) generates a first operation value, first data, and the memory address of the target memory; transmits the first operation value, first data, and memory address to the detection device so that the detection device can configure the first operation value in the operation type register and the first data and memory address in the data register; when a preset time arrives, it generates a second operation value; transmits the second operation value to the detection device so that the detection device can configure the second operation value in the operation type register, and performs a storage detection process on the target memory based on the first operation value, the second operation value, the first data, and the memory address.

[0110] This application provides a computer-readable storage medium having a computer program thereon, which, when executed by a processor, implements the storage fault detection method described above.

[0111] Understandably, the detection device uses the operation value in the operation type register to identify the data reading task of the target memory indicated by the processor, obtains the memory address and first data corresponding to the first operation value from the data register, writes the first data into the target memory corresponding to the memory address, and if the value in the operation type register is detected as the second operation value, it directly reads the second data from the target memory corresponding to the second operation value using the detection result register, and compares the second data with the first data to obtain the detection result. That is, the hardware compares and verifies the second data read from the target memory with the first data, without the need for software (processor, i.e., CPU) to verify the second data read from the target memory, saving the CPU (processor) register reading time and thus improving the speed of memory detection.

[0112] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0113] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0114] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0115] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0116] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A testing device, characterized in that, The detection equipment includes: An operation type register is used to obtain the memory address and first data corresponding to the first operation value from the data register when a first operation value is received from the processor; and to write the first data into the target memory corresponding to the memory address; the data in the data register is the data written by the processor; the first operation value is the operation identifier corresponding to a read access operation; The detection result register is used to retrieve second data from the target memory corresponding to the second operation value when the value in the operation type register is the second operation value; determine the detection result of the storage detection process of the target memory based on the first data and the second data; and read the detection result from the detection result register and transmit the detection result to the processor when a detection result retrieval instruction is received from the processor. The second operation value is the operation identifier corresponding to the write access operation.

2. The detection device according to claim 1, characterized in that, The data register includes an address register and a write data register: The operation type register is used to obtain the storage address corresponding to the first operation value from the address register when the first operation value is received from the processor. Obtain the first data corresponding to the first operation value from the write data register.

3. The detection device according to claim 2, characterized in that, The operation type register is used to store the first operation value when the first operation value is received; The address register is used to store the memory address when a memory address is received; The write data register is used to store the first data upon receiving the first data.

4. The detection device according to claim 1, characterized in that, The detection result register is used to obtain the memory address corresponding to the second operation value from the address register, and to obtain the second data from the target memory corresponding to the memory address.

5. The detection device according to claim 4, characterized in that, The detection result register is used to transmit an instruction to the scheduler to read the second data from the target memory, so that the scheduler can obtain the second data from the target memory.

6. The detection device according to claim 1, characterized in that, The operation type register is used to store the second operation value when the second operation value is received.

7. The detection device according to claim 1, characterized in that, The operation type register is used to transmit an instruction to the scheduler to write the first data to the target memory, so that the scheduler can write the first data to the target memory.

8. The detection device according to claim 1, characterized in that, The number of the first data is at least two, the number of the memory addresses is multiple, and the number of target memories is multiple; An operation type register is used to group multiple memory addresses to obtain at least two groups of addresses; and to group multiple target memories according to the at least two groups of addresses to obtain at least two groups of target memories. Write at least two sets of first data into the at least two sets of target memories.

9. The detection device according to claim 8, characterized in that, The second set of data consists of at least two sets; A detection result register is used to obtain the at least two sets of second data from the at least two sets of target memories; compare the at least two sets of first data with the at least two sets of second data to obtain the detection result; and store the detection result; the at least two sets of target memories correspond one-to-one with the at least two sets of second data.

10. A storage fault detection method, characterized in that, Applied to a testing device, the method includes: Upon receiving a first operation value transmitted by the processor, the memory address and first data corresponding to the first operation value are obtained; the memory address and the first data are data transmitted by the processor; the first operation value is an operation identifier corresponding to a read access operation. The first data is stored in the target memory corresponding to the memory address; Upon receiving a second operation value transmitted by the processor, second data is retrieved from the target memory; the second operation value is an operation identifier corresponding to a write access operation. The detection result of the storage detection process of the target memory is determined based on the first data and the second data; Upon receiving a detection result acquisition instruction transmitted by the processor, the detection result is transmitted to the processor.

11. The method according to claim 10, characterized in that, The step of obtaining the second data from the target memory includes: Obtain the memory address corresponding to the second operation value; The second data is obtained from the target memory corresponding to the memory address.

12. The method according to claim 10, characterized in that, The first data has at least two elements, the memory addresses have multiple elements, and the target memories have multiple elements; storing the first data using the target memories corresponding to the memory addresses includes: Group the multiple memory addresses to obtain at least two groups of addresses; According to the at least two sets of addresses, the multiple target memories are grouped to obtain at least two sets of target memories; Write at least two sets of first data into the at least two sets of target memories.

13. The method according to claim 12, characterized in that, The second data consists of at least two sets; the determination of the detection result of the storage detection process of the target memory based on the first data and the second data includes: Obtain the at least two sets of second data from the at least two sets of target memories; The detection result is obtained by comparing the at least two first data with the at least two sets of second data; the at least two sets of target memory correspond one-to-one with the at least two sets of second data.

14. A storage medium having a computer program stored thereon, used in a testing device, characterized in that, When the computer program is executed by the processor in the detection device, it implements the method according to any one of claims 10 to 13.

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