Memory management system, method, apparatus, and storage medium

Abstract

The application discloses a memory management system, method and device and a storage medium. The system comprises a released memory resource space used for storing returned memory spaces, an applied memory resource space used for storing the memory spaces to be requested, and a memory resource space queue used for buffering the memory spaces called from the released memory resource space and sending the memory spaces to the applied memory resource space when the memory resource space queue meets a first preset condition. The application solves the technical problem of low efficiency of memory management in the related art.

Description

Technical Field

[0001] This invention relates to the field of big data, and more specifically, to a memory management system, method, apparatus, and storage medium. Background Technology

[0002] In a System on Chip (SOC) system that implements soft forwarding of routing access by superimposing a central processing unit (CPU Core) on a switch core, the switch core is responsible for sending received packets to the CPU Core and sending packets received from the CPU Core out through the destination network interface. It also provides backplane switching between high-density network interfaces and Quality of Service (QoS) functionality. The CPU Core is responsible for software forwarding of service packets. Data exchange between the switch core and the CPU Core is completed through Direct Memory Access (DMA). The CPU and DMA controller use descriptors to control the transmission of interactive information and record the memory space addresses where the information is stored. The data storage addresses bound in the descriptors can be continuous or discrete, but they are all maintained and allocated by the CPU. Under high-bandwidth soft forwarding performance requirements, this method of software-allocated buffer addresses can lead to excessive CPU consumption.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This invention provides a memory management system, method, apparatus, and storage medium to at least solve the technical problem of low efficiency in memory management in related technologies.

[0005] According to one aspect of the present invention, a memory management system is provided, the memory management system including a memory manager, the memory manager including: releasing memory resource space for storing returned memory space; requesting memory resource space for storing memory space to be requested; and a memory resource space queue for caching memory space retrieved from the released memory resource space, and sending the memory space to the requested memory resource space when the memory resource space queue meets a first preset condition.

[0006] Optionally, releasing memory resource space includes: a first temporary memory space, used to temporarily store returned memory space, and when the first temporary memory space meets a second preset condition, transferring the memory space to a first local memory space queue; and a first local memory space queue, used to transfer all stored memory space to the memory resource space queue when the number of stored memory spaces is greater than or equal to a first preset number.

[0007] Optionally, the requested memory resource space includes: a second temporary memory space, used to temporarily store the requested memory space, and, if the second temporary memory space meets a third preset condition, memory space is retrieved from the second local memory space queue; the second local memory space queue is used to retrieve memory space from the memory resource space queue if the number of stored memory spaces is less than or equal to a second preset number.

[0008] Optionally, the memory management system further includes: a switch for receiving a first data packet and sending the first data packet to a direct memory accessor; a direct memory accessor for generating a first memory space request instruction based on the first data packet and sending the first memory space request instruction to a memory manager; a memory manager for generating a first memory address based on the first memory space request instruction and sending the first memory address to the direct memory accessor; the direct memory accessor is also used to store the first data packet in a first memory space in the memory storage according to the first memory address, wherein the first memory address is the memory address of the first memory space; a processor for obtaining the first memory address, retrieving the first data packet from the first memory space of the memory manager based on the first memory address, processing the first data packet, and obtaining a first processing result; and a memory storage for storing the first data packet in the first memory space.

[0009] Optionally, the processor is also used to obtain a second memory address and send the second memory address to the direct memory accessor, wherein the second memory address is the address of the second memory space; the direct memory accessor is also used to send a second data packet to the switch according to the second memory address; the switch is also used to output the second data packet; after the direct memory accessor outputs the second data packet, it returns the second memory address to the memory manager.

[0010] According to one aspect of the present invention, a memory management method is provided, comprising: in response to a memory manager receiving a memory space return instruction, determining a return interface based on the quantity of memory space to be returned in the memory space return instruction and the device type that generated the memory space return instruction, wherein the device type includes one of the following: the type of processor, the type of direct memory accessor; and returning the memory space to be returned using the return interface.

[0011] Optionally, the return interface includes: a first return interface and a second return interface. The return interface is determined based on the number of memory spaces to be returned in the memory space return request and the type of device that generates the memory space return instruction. The determination includes: in response to the memory space to be returned being a single memory space, determining the first return interface as the return interface, wherein the first return interface is used to directly return the single memory space; in response to the memory space to be returned being multiple memory spaces, determining the second return interface as the return interface, wherein the second return interface is used to return the multiple memory spaces in batches.

[0012] Optionally, the method further includes: in response to the memory manager receiving a memory space request instruction, determining a request interface based on the amount of memory space to be requested in the memory space request instruction and the device type that generated the memory space request instruction, wherein the device type includes one of the following: the type of processor, the type of direct memory accessor; and using the request interface to obtain the memory space to be requested.

[0013] Optionally, the request interface includes: a first request interface and a second request interface. The request interface is determined based on the number of memory spaces to be requested in the memory space request instruction and the device type that generated the memory space request instruction. The determination includes: in response to the memory space to be requested being a single memory space, determining the first request interface as the request interface according to the device type of the memory space request instruction, wherein the first request interface is used to directly obtain a single memory space; in response to the memory space to be requested being multiple memory spaces, determining the second request interface as the request interface according to the device type of the memory space request instruction, wherein the second request interface is used to obtain multiple memory spaces in batches.

[0014] Optionally, the method further includes: acquiring a first data packet received by the switch; acquiring a first memory space request instruction from the direct memory accessor based on the first data packet; generating a first memory address using the memory manager according to the first memory space request instruction; storing the first data packet into the first memory space of the memory storage based on the first memory address, wherein the first memory address is the memory address of the first memory space; and processing the first data packet from the first memory space based on the first memory address by the processor to obtain a first processing result.

[0015] Optionally, the method further includes: acquiring a second data packet from the processor; acquiring a second space allocation instruction from the direct memory accessor based on the second data packet; generating a second memory address using the memory manager according to the second space allocation instruction; storing the second data packet into a second memory space in the memory storage according to the second memory address; retrieving the second data packet from the second memory space through the direct memory accessor and sending the second data packet to the switch, wherein the switch is used to output the second data packet; and returning the second memory address to the memory manager in response to the switch outputting the second data packet.

[0016] According to one aspect of the present invention, a memory management apparatus is provided, comprising: a generation module, configured to, in response to a memory manager receiving a memory space return instruction, determine a return interface based on the quantity of memory space to be returned in the memory space return instruction and the device type that generated the memory space return instruction, wherein the device type includes one of the following: a processor type, a direct memory accessor type; and a return module, configured to return the memory space to be returned using the return interface.

[0017] According to one aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to perform any of the methods described above.

[0018] In this embodiment of the invention, the memory management system includes a memory manager, which includes: a released memory resource space for storing returned memory space; a requested memory resource space for storing requested memory space; and a memory resource space queue for caching memory space retrieved from the released memory resource space. When the memory resource space queue meets a first preset condition, the memory space is sent to the requested memory resource space. This allows for efficient retrieval of memory space, thereby improving memory management efficiency and solving the technical problem of low memory management efficiency in related technologies. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a memory management system according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a memory manager according to an embodiment of the present invention; Figure 3 This is a schematic diagram of memory resource management according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a BP return according to an embodiment of the present invention; Figure 5 This is a flowchart of a memory management method according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a memory management device according to an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] According to an embodiment of the present invention, a method embodiment for memory management is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0023] First, some terms in this invention will be explained. Table 1 below is a list of English abbreviations, full English names, and Chinese explanations for some terms in this invention.

[0024] Table 1

[0025] Example 1

[0026] Figure 1 This is a schematic diagram of a memory management system according to an embodiment of the present invention, such as... Figure 1 As shown, the memory management system 100 includes a memory manager, which comprises the following components: Release memory resource space 102, used to store returned memory space; request memory resource space 104, used to store memory space to be requested; memory resource space queue 106, used to cache memory space retrieved from the released memory resource space, and send the memory space to the requested memory resource space when the memory resource space queue meets the first preset condition.

[0027] The freed memory resources mentioned above can be used to store the returned memory space.

[0028] The first preset condition mentioned above can be the case where the memory resource space queue is full.

[0029] The memory resource space requested above can be used to store the memory space to be requested.

[0030] It should be noted that the resources in the memory resource space queue mentioned above, that is, the FIFO, can be returned by the release interface or actively read from DDR. The resources in the FIFO can be allocated to the CPU request interface or the DMA request interface according to the request.

[0031] Figure 2 This is a schematic diagram of a memory manager according to an embodiment of the present invention, such as... Figure 2 As shown, when each data packet arrives at the memory access data receiving interface (also known as DMA RX RING), it will select a BPP to request a BP based on the current BPP configuration and status. According to the message length, subsequent new message segments may continue to request one or more BPs, corresponding to one or more buffer cells on the DDR, until the end of the message, that is, the entire message is received.

[0032] Each DMA ring has a cache queue, also known as a local FIFO, such as... Figure 2As shown, when each message's initial segment arrives at the DMA RX RING, it selects a BPP to request a BP based on the current BPP configuration and status. A BP is requested at the start of the current period (SOP). Depending on the message length, non-SOP entries may continue to request one or more BPs, corresponding to one or more buffer cells on the DDR, until the end of the current period (EOP). Each DMA RING has a local FIFO and a temporary BP space that can store three temporary BPs. If there are BPs in the temporary BP space, they are used directly. If the temporary BP space is empty, one local buffer entry (also called a FIFO Entry) is popped, resulting in four BPs. One BP is considered a successful request, and the three BPs are written to the temporary BP space. When the local FIFO Entry is not full, it requests FIFO Entry from the BPP FIFO. Each FIFO Entry contains four BPs. When the number of BPP FIFO Entry is less than a set threshold, the BPP hardware FIFO reads addresses from the DDR. After obtaining the BP, the corresponding message data is written to the corresponding DDR buffer cell according to the BP. Simultaneously, the selected BPP ID and the obtained BP are written to the DMA RX descriptor for later use by DMA TX to read data from DDR and return the BP to the BPP FIFO corresponding to the BPPID. When hardware BP management is enabled, each BPP FIFO, when not full, requests BPs from the Buffer Management module on a FIFO Entry basis. The Buffer Manager module maintains the overall state of BPPs. If the BPs of a certain BPP are nearing exhaustion, it will notify the DMA RX. The Buffer Management module is the memory manager 106. If a shared BPP (also called a Global BPP) is enabled, the DMA RX RING will decide whether to select a Global BPP based on the exhaustion status of the preferred BPP. If all used BPPs are unavailable, the DMA RX RING will send a pause signal (also called a stall signal) back to switch 102, instructing it to stop sending packets to this DMA RX RING. The DMA RX RING needs to ensure that the BPs used by the same message all come from the same BPP; the BPPID is written to the descriptor.

[0033] Optionally, releasing memory resource space includes: a first temporary memory space, used to temporarily store returned memory space, and when the first temporary memory space meets a second preset condition, transferring the memory space to a first local memory space queue; and a first local memory space queue, used to transfer all stored memory space to the memory resource space queue when the number of stored memory spaces is greater than or equal to a first preset number.

[0034] The aforementioned second space request instruction can be issued by the direct memory accessor 104 to cause the memory manager 106 to generate a second memory address.

[0035] The second data packet mentioned above can be a data packet that the processor 108 needs to transmit to the switch 102. Optionally, the second data packet can be data such as web browsing information and video playback records stored in the processor 108.

[0036] The aforementioned second memory address can be the address of the second memory space where the second data packet is located. The second memory space exists in the memory storage 110. Optionally, the second memory address can be obtained by the processor 108.

[0037] In an optional embodiment, the processor 108 can transmit the second data packet to the switch 102. Optionally, when the processor 108 needs to transmit the second data packet to the switch 102, it can first request an access address, that is, request the address of the second memory space where the second data packet is located. During data transmission, the processor 108 only needs to call the second memory address to call the second data packet according to the second memory address and send it to the switch 102.

[0038] The aforementioned first temporary memory space can be used to temporarily store returned memory space.

[0039] The second preset condition mentioned above can be the case that the first temporary memory space is full.

[0040] The first local memory space queue mentioned above can be used to cache returned memory space.

[0041] The aforementioned first preset quantity can be set by those skilled in the art.

[0042] In one optional embodiment, the temporarily returned memory space can be stored in the first temporary memory space. If the number of stored memory spaces is greater than or equal to a first preset number, all stored memory spaces can be transferred to the memory resource space queue. If the first temporary memory space meets the second preset condition, the memory space can be transferred to the first local memory space queue.

[0043] Figure 3 This is a schematic diagram of memory resource management according to an embodiment of the present invention, such as... Figure 3The diagram shows 9 BPPs, including 8 guaranteed BPPs (also known as Guarantee BPPs) and 1 global BPP. The DDR / SRAM memory resources on the far left of the diagram correspond to the management of 9 DDR BPPs, which can be understood as software-level BPP management. The diagram shows 32 DMA RXRINGs and 32 DMA TXRINGs. Each RING is independently selectable, including whether to enable hardware BPP management, with 8 RINGs bound to one BPP, and the option to enable or disable global BPP. The diagram shows that independent BP request and BP return interfaces are provided to the processor in units of BPPs. The BP request interface is divided into a single request interface 1 for the CPU, multiple request interfaces 2, and a single request interface 3 for direct access to memory. The BP return interface is also divided into a single return interface 1 for the CPU, multiple return interfaces 2, and a single return interface 3 for direct access to memory.

[0044] This invention provides a variable processor core-independent Buffer Pointer Pool (BPP) for multi-processor cores, which is based on BPP resource isolation (Per CPU Core Guarantee Buffer). Different CPU cores enjoy exclusive buffer resources. Of course, it can also be refined to bind independent BPPs per DMA ring. At the same time, it supports global shared buffer resources to deal with burst traffic (Global Share Buffer). That is, when the Guarantee Buffer is exhausted, the Global Buffer can be used.

[0045] For each BPP: a large number of BPs are stored in DDR, and the chip maintains a large FIFO for each BPP, namely the BPP FIFO, such as... Figure 3 3; Supports requesting DDR read interfaces from DDR BPP to BPP FIFO, such as... Figure 3 10; Supports DDR write interfaces for writing back BP from BPP FIFO to DDR, such as... Figure 3 The chip, based on the depth of the large FIFO, controls the BP movement between the BPP FIFO and the DDR BPP using a configurable Threshold; the chip supports DMA RX RING request interfaces and CPU Request I / O request interfaces; the chip supports DMA TX RING return interfaces and CPU Release I / O return interfaces; the chip sets up a small BP FIFO, also called a local FIFO, for each type of requester and returner, such as... Figure 3 Temporary cache space for 2 and 3 BP, such as Figure 31. Ensures the timeliness of BP acquisition and return; FIFO Entry for large and small FIFOs is based on 4 BPs; DDR relocation is based on 4 FIFOEntries (16 BPs).

[0046] Figure 4 This is a schematic diagram of a BP return according to an embodiment of the present invention, as shown below. Figure 4 As shown, after each Direct Memory Access (DMA TX RING) descriptor completes the corresponding data transmission, the BP (Backup Component) needs to be returned according to the BP and BPPID in the DMA descriptor. Each DMA TX RING has a local FIFO and three temporary BP spaces in the Buffer Manager: if there are empty spaces in the temporary BP spaces, data is written directly to the temporary BP spaces; if the temporary BP spaces are full, one FIFO Entry is created, i.e., four BPs, and the local FIFO corresponding to the DMA TX RING is pushed forward, and the temporary BP spaces are emptyed; when the number of local FIFO Entry reaches the configured threshold, the FIFO Entry is returned to the BPP hardware FIFO in batches; when the number of BPP hardware FIFO Entry reaches the configured threshold, the BPP hardware FIFO writes addresses to the DDR in batches.

[0047] Optionally, the requested memory resource space includes: a second temporary memory space, used to temporarily store the requested memory space, and, if the second temporary memory space meets a third preset condition, memory space is retrieved from the second local memory space queue; the second local memory space queue is used to retrieve memory space from the memory resource space queue if the number of stored memory spaces is less than or equal to a second preset number.

[0048] The aforementioned second preset quantity can be set by those skilled in the art.

[0049] like Figure 3 The CPU BP Request section provides two request interfaces: direct request from a single BP and indirect request from multiple BPs. In terms of implementation, it also sets up temporary space for 3 BPs and a small FIFO for the variable type (also known as Local) on the CPU side.

[0050] Single BP Request: A single BP request implements the read-allocate function by directly reading the address, meaning each read operation triggers a hardware BP allocation. Each read address supporting read-allocate corresponds to a specific BPP ID. The CPU request retrieves BP from the non-empty temporary space; or, when the temporary space is empty, it pops the local FIFO to obtain BP while simultaneously filling the temporary BP space. The local FIFO typically requests addresses from the BPP FIFO when it is not full or in a configurable state.

[0051] Multiple BP Requests: The multiple BP indirect request interface is used for batch requesting BPs, supporting multiple BP requests at once. If there are enough BPs in the temporary space, the BPs in the temporary space are taken; if there are not enough BPs in the temporary space, the local FIFO is popped until the request is completed or there are enough BPs in the temporary space. When hardware BP management is enabled, if each LocalFIFO is not full, it will request BPs from the BPP large FIFO in units of FIFO Entry. When the number of entries in the BPP large FIFO is less than the configured Threshold, it is similar to DMA RX processing, where the BPP hardware FIFO reads the address from DDR. Regardless of whether it is DMA or CPU request, the large FIFO per BPP is the same.

[0052] Optionally, the memory management system further includes: a switch for receiving a first data packet and sending the first data packet to a direct memory accessor; a direct memory accessor for generating a first memory space request instruction based on the first data packet and sending the first memory space request instruction to a memory manager; a memory manager for generating a first memory address based on the first memory space request instruction and sending the first memory address to the direct memory accessor; the direct memory accessor is also used to store the first data packet in a first memory space in the memory storage according to the first memory address, wherein the first memory address is the memory address of the first memory space; a processor for obtaining the first memory address, retrieving the first data packet from the first memory space of the memory manager based on the first memory address, processing the first data packet, and obtaining a first processing result; and a memory storage for storing the first data packet in the first memory space.

[0053] The aforementioned switch can be a network device that can connect multiple devices and enable the devices to communicate with each other on the network. It can forward data to multiple devices through packet switching.

[0054] The first data packet mentioned above can be a data packet that the switch needs to transmit to the processor. Optionally, the first data packet can include data from browsing web pages, chat logs, data generated from watching videos, etc. Furthermore, the first data packet can be multiple different data packets.

[0055] The aforementioned direct memory accessor 104 can be used to transfer data.

[0056] In one optional embodiment, when the switch needs to transmit the first data packet to the processor, the switch can first transmit the first data packet to the direct memory accessor (DMI) and determine the memory address of the first data packet. The descriptor can be the identification information of the first data packet used to determine its memory address. Optionally, the memory address can be stored in the DMI. When the first data packet needs to be retrieved, the data can be retrieved simply by using the relevant functions or programs in the DMI based on the memory address, greatly improving the efficiency of memory management.

[0057] The aforementioned descriptor is a set of control information for direct memory access controllers to control data movement. It includes the memory address where the data packet is stored. This memory address is requested from the memory manager when the data packet triggers DMA to accept the data packet and write it to memory. After obtaining the memory address, the data packet is written to the corresponding address space while the memory address is written to the descriptor.

[0058] The direct memory accessor is used to generate a first memory space request instruction based on the first data packet and send the first memory space request instruction to the memory manager.

[0059] The aforementioned first memory space request instruction is issued by the direct memory accessor and can be represented by a program or text.

[0060] The aforementioned first memory space can be the storage space for the first data packet. This first memory space resides within the memory manager.

[0061] In one optional embodiment, after obtaining the first data packet, the first data packet can be analyzed and processed to generate a corresponding first memory space request instruction. Optionally, the direct memory accessor 104 can send the first memory space request instruction to the memory manager 106, thereby allowing access to the processor 106 through the direct memory accessor 104, and further processing of the first data packet.

[0062] Optionally, the processor is further configured to obtain a second memory address and send the second memory address to a direct memory accessor (DMI). The DMI stores the second data packet into a second memory space in the memory storage based on the second memory address, where the second memory address is the address of the second memory space. The DMI is also configured to send the second data packet to a switch based on the second memory address. The switch is further configured to output the second data packet. After the switch outputs the second data packet, the processor is further configured to return the second memory address to the memory manager.

[0063] The memory manager 106 is used to generate a first memory address according to the first memory space request instruction and send the first memory address to the direct memory accessor 104.

[0064] The aforementioned first memory address can be the storage address of the first data packet.

[0065] The memory manager 106 described above may contain a first memory space.

[0066] In an optional embodiment, after determining the storage address (i.e., the first memory address) of the first data packet to be transmitted from switch 102 to processor 108, the first data packet can be stored in the corresponding first memory space in memory manager 106 based on the first memory address. Optionally, after storing the first data packet in the first memory space, when transmitting the first data packet, it is only necessary to determine the first memory address corresponding to the first data packet in direct memory accessor 104, and retrieve the first data packet stored in the first memory space corresponding to the first memory address from memory manager 106 using switch 102 based on the first memory address, thereby improving the efficiency of memory management.

[0067] The processor 108 is configured to retrieve a first data packet from the first memory space of the memory manager 106 according to a first memory address, process the first data packet, and obtain a first processing result; The first processing result mentioned above can be the result obtained by processing the first data packet using the processor 108.

[0068] In an optional embodiment, the processor 108 may include multiple scheduling centers, which can use different scheduling centers to obtain the first memory space where the first data packet is stored from the direct memory accessor 104, and call the first data packet based on the first memory space. Furthermore, after calling the first data packet, the first data packet can be processed to obtain a first processing result.

[0069] The memory storage 110 is used to store the first data packet into the first memory space.

[0070] In an optional embodiment, after the first memory space is determined, the first data packet can be stored in the first memory space in the memory manager 106 using the memory storage 110. If the first data packet is needed, it can be retrieved from the first memory space, avoiding the need to retrieve the data again, thereby greatly improving the efficiency of memory management.

[0071] In this embodiment of the invention, the system employs a switch 102, which receives a first data packet and sends it to a direct memory accessor 104; the direct memory accessor 104 generates a first memory space request instruction based on the first data packet and sends it to a memory manager 106; the memory manager 106 generates a first memory address based on the first memory space request instruction and sends it to the direct memory accessor 104; the direct memory accessor 104 further stores the first data packet in a first memory space in a memory storage 110 based on the first memory address and sends the first memory address to a processor 108, wherein the first memory address is the memory address of the first memory space; the processor 108 retrieves the first data packet from the first memory space of the memory manager 106 based on the first memory address and processes the first data packet to obtain a first processing result; and the memory storage 110 stores the first data packet in the first memory space. It is easy to note that the memory manager 106 can generate a first memory address according to the first memory space request instruction and send the first memory address to the direct memory accessor 104. The direct memory accessor 104 then stores the first data packet into the first memory space of the memory according to the first memory address and sends the first memory address to the processor 108. This can improve the efficiency of memory management and solve the technical problem of low efficiency of memory management in related technologies.

[0072] Example 2

[0073] According to another aspect of the present invention, a memory management method is also provided. Figure 5 This is a flowchart of a memory management method according to an embodiment of the present invention, such as... Figure 5 As shown, the method consists of the following steps: Step S502: In response to the memory manager receiving a memory space return instruction, the return interface is determined based on the amount of memory space to be returned in the memory space return instruction and the device type that generated the memory space return instruction.

[0074] The device type includes one of the following: processor type, direct memory accessor type.

[0075] Step S504: Use the return interface to return the memory space to be returned.

[0076] Optionally, the return interface includes: a first return interface and a second return interface. The return interface is determined based on the number of memory spaces to be returned in the memory space return request and the type of device that generates the memory space return instruction. The determination includes: in response to the memory space to be returned being a single memory space, determining the first return interface as the return interface, wherein the first return interface is used to directly return the single memory space; in response to the memory space to be returned being multiple memory spaces, determining the second return interface as the return interface, wherein the second return interface is used to return the multiple memory spaces in batches.

[0077] like Figure 4 As shown, after each DMA TX descriptor completes the corresponding data transmission, the BP needs to be returned according to the BP and BPPID in the DMA descriptor. Each BPP sets up a local FIFO and 3 temporary BP spaces in the Buffer Manager for the DMA TX: if there are empty spaces in the temporary BP spaces, the data is directly written to the temporary BP spaces; if the temporary BP spaces are full, one FIFO Entry is created, i.e., 4 BPs, and pushed into the local FIFO corresponding to the DMA TX, and the temporary BP spaces are empty; when the number of local FIFO Entry reaches the configured Threshold, for example, when it is not empty, the FIFO Entry is returned to the BPP hardware FIFO in batches; when the number of BPP hardware FIFO Entry reaches the configured Threshold, the BPP hardware FIFO writes addresses to the DDR in batches.

[0078] Optionally, the method further includes: in response to the memory manager receiving a memory space request instruction, determining a request interface based on the amount of memory space to be requested in the memory space request instruction and the device type that generated the memory space request instruction, wherein the device type includes one of the following: the type of processor, the type of direct memory accessor; and using the request interface to obtain the memory space to be requested.

[0079] Optionally, the request interface includes: a first request interface and a second request interface. The request interface is determined based on the number of memory spaces to be requested in the memory space request instruction and the device type that generated the memory space request instruction. The determination includes: in response to the memory space to be requested being a single memory space, determining the first request interface as the request interface according to the device type of the memory space request instruction, wherein the first request interface is used to directly obtain a single memory space; in response to the memory space to be requested being multiple memory spaces, determining the second request interface as the request interface according to the device type of the memory space request instruction, wherein the second request interface is used to obtain multiple memory spaces in batches.

[0080] Optionally, the method further includes: acquiring a first data packet received by the switch; acquiring a first memory space request instruction from the direct memory accessor based on the first data packet; generating a first memory address using the memory manager according to the first memory space request instruction; storing the first data packet into the first memory space of the memory storage based on the first memory address, wherein the first memory address is the memory address of the first memory space; and processing the first data packet from the first memory space based on the first memory address by the processor to obtain a first processing result.

[0081] Optionally, the method further includes: acquiring a second data packet from the processor; acquiring a second space allocation instruction from the direct memory accessor based on the second data packet; generating a second memory address using the memory manager according to the second space allocation instruction; storing the second data packet into a second memory space in the memory storage according to the second memory address; retrieving the second data packet from the second memory space through the direct memory accessor and sending the second data packet to the switch, wherein the switch is used to output the second data packet; and returning the second memory address to the memory manager in response to the switch outputting the second data packet.

[0082] In one optional embodiment, when the processor needs to send a second data packet to the switch, the processor's scheduling center can send a request to the direct memory accessor to apply for the access address of the second data packet, and retrieve the second data packet from the second memory space through the direct memory accessor.

[0083] The aforementioned memory space return instruction can be issued from the memory space itself.

[0084] The aforementioned return interface is used to return memory space.

[0085] The aforementioned device types are primarily used to determine whether the memory space return instruction is generated by the processor or the memory accessor.

[0086] like Figure 3 In the CPU BP Release section, CPU return also provides two return interfaces: direct return for a single BP; and indirect return for multiple BPs.

[0087] First, let's introduce single BP direct return: Single BP return achieves write-release functionality by directly writing to the address, meaning each write operation triggers a hardware BP return. Under normal chip conditions, the release operation should succeed. Each write address supporting write-release corresponds to a specific BPPID. If there is space in the temporary BP space corresponding to CPU Release, it is written directly into the temporary BP space; if the temporary BP space is full, one FIFOEntry (i.e., four BPs) is created, pushed into the local FIFO corresponding to CPU Release, and the temporary BP space is emptyed; whenever the local FIFO is not empty, the FIFO Entry is returned in batches to the BPP hardware FIFO; when the number of BPP hardware FIFO Entry reaches the configured Threshold, the BPP hardware FIFO writes the address to DDR.

[0088] Next, we introduce the multi-BP indirect return interface: This interface is used for batch BP return, supporting the return of multiple BPs at once. The chip must guarantee that the return operation will succeed. The release process is similar to a single BP direct return, continuing until all BPs in the batch have been returned. At this point, the entire hardware management mechanism for BPs has been fully demonstrated. This significantly reduces the CPU's workload in managing BPs, decreasing CPU buffer allocation and release operations, reducing CPU DDR I / O reads and writes, and improving CPU message transmission and reception performance.

[0089] like Figure 3 The diagram shows 9 BPPs (Browser Builders), including 8 Guarantee BPPs and 1 Global BPP. The DDR / SRAM memory resources on the far left correspond to the management of 9 DDR BPPs, which can be understood as software-level BPP management. The diagram also shows 32 DMA RX Rings and 32 DMA TX Rings. Each ring is independently selectable, including whether to enable hardware BPP management, with 8 rings bound to one BPP, and the option to enable Global BPP. The diagram illustrates the independent BP request and BP return interfaces provided to the CPU on a BPP basis.

[0090] This invention provides a hardware-managed memory resource device, responsible for memory resource allocation, release, and other maintenance functions. The use of buffer resources includes, but is not limited to, CPU and DMA; that is, software-allocated memory resources are completely handed over to hardware management. Even when the CPU actively sends packets, it needs to request a BufferPointer from the hardware BPP. Figure 3The document showcases the core of buffer management, primarily including components for the DMA RX Ring to request BPs from the BPP, the DMA TX Ring to release BPs from the BPP, the CPU to request BPs from the BPP, the CPU to release BPs from the BPP, and the FIFO of each bufferPointer. DDR memory resources for storing interactive data can be allocated to multiple BPPs. The memory resources within each BPP can be configured with a configurable byte length, which can be a multiple of the bus width. Further subdivision is possible, with each subdivided unit called a BufferCell, corresponding to a unique BufferPointer. Each BPP manages its own resources. For objects using buffer resources, GuaranteeBuffer can be used first, followed by optional GlobalBuffer, supporting optional buffer resource isolation management. This significantly reduces the CPU's workload in managing BPs, decreases CPU buffer allocation and release operations, reduces CPU DDR I / O, and improves CPU message transmission and reception performance.

[0091] Example 3

[0092] According to another aspect of the present invention, a memory management device is also provided. Figure 6 This is a schematic diagram of a memory management device according to an embodiment of the present invention, such as... Figure 6 As shown, the device includes the following components: The generation module 602 is used to respond to the memory manager receiving a memory space return instruction, and determine the return interface based on the amount of memory space to be returned in the memory space return instruction and the device type that generated the memory space return instruction, wherein the device type includes one of the following: the type of processor and the type of direct memory accessor.

[0093] The return module 604 is used to return the memory space to be returned using the return interface.

[0094] Optionally, the return interface includes: a first return interface and a second return interface. The generation module is further configured to determine the first return interface as the return interface in response to the memory space to be returned being a single memory space, wherein the first return interface is used to directly return the single memory space; and to determine the second return interface as the return interface in response to the memory space to be returned being multiple memory spaces, wherein the second return interface is used to return the multiple memory spaces in batches.

[0095] Optionally, the generation module is also configured to, in response to the memory manager receiving a memory space request instruction, determine the request interface based on the amount of memory space to be requested in the memory space request instruction and the device type that generates the memory space return instruction, wherein the device type includes one of the following: the type of processor, the type of direct memory accessor; and obtain the memory space to be requested using the request interface.

[0096] Optionally, the request interface includes: a first request interface and a second request interface. The generation module is further configured to, in response to the memory space to be requested being a single memory space, determine the first request interface as the request interface according to the device type of the memory space return instruction, wherein the first request interface is used to directly obtain a single memory space; and in response to the memory space to be requested being multiple memory spaces, determine the second request interface as the request interface according to the device type of the memory space return instruction, wherein the second request interface is used to obtain multiple memory spaces in batches.

[0097] Optionally, the device is further configured to acquire a first data packet received by the switch; acquire a first memory space request instruction from the direct memory accessor based on the first data packet; generate a first memory address using the memory manager according to the first memory space request instruction; store the first data packet in the first memory space of the memory storage based on the first memory address, wherein the first memory address is the memory address of the first memory space; and process the first data packet from the first memory space based on the first memory address to obtain a first processing result.

[0098] Optionally, the device is further configured to acquire a second data packet from the processor; acquire a second space request instruction from the direct memory accessor based on the second data packet; generate a second memory address using the memory manager according to the second space request instruction; store the second data packet in the second memory space in the memory storage according to the second memory address; retrieve the second data packet from the second memory space through the direct memory accessor and send the second data packet to the switch, wherein the switch is used to output the second data packet; and return the second memory address to the memory manager in response to the switch outputting the second data packet.

[0099] Example 4

[0100] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to perform the memory management method described above.

[0101] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0102] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0103] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0106] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0107] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A memory management system, characterized in that, The memory management system includes a memory manager, and the memory manager includes: Release memory resources to store returned memory space; Allocate memory resources to store the requested memory space; A memory resource space queue is used to cache memory space requested from the released memory resource space, and when the memory resource space queue meets a first preset condition, the memory space cached in the memory resource space queue is sent to the requested memory resource space. The memory management system further includes: a switch, configured to receive a first data packet and send the first data packet to a direct memory accessor; the direct memory accessor, configured to generate a first memory space request instruction based on the first data packet and send the first memory space request instruction to a memory manager; the memory manager, configured to generate a first memory address based on the first memory space request instruction and send the first memory address to the direct memory accessor; the direct memory accessor is further configured to store the first data packet in a first memory space in a memory storage device based on the first memory address, wherein the first memory address is the memory address of the first memory space; and a processor, configured to obtain the first memory address, retrieve the first data packet from the first memory space of the memory manager based on the first memory address, process the first data packet, and obtain a first processing result. The processor is further configured to obtain a second memory address and send the second memory address to the direct memory accessor; the direct memory accessor is further configured to store the second data packet into a second memory space in the memory storage according to the second memory address, wherein the second memory address is the address of the second memory space; the direct memory accessor is further configured to send the second data packet to the switch according to the second memory address; the switch is further configured to output the second data packet; the processor is further configured to return the second memory address to the memory manager after the switch outputs the second data packet.

2. The memory management system according to claim 1, characterized in that, The release of memory resource space includes: a first temporary memory space for temporarily storing the returned memory space; when the first temporary memory space meets a second preset condition, the memory space temporarily stored in the released memory resource space is transferred to a first local memory space queue; and a first local memory space queue for transferring all the memory space stored in the first local memory space queue to the memory resource space queue when the number of memory spaces stored in the first local memory space queue is greater than or equal to a first preset number.

3. The memory management system according to claim 2, characterized in that, The requested memory resource space includes: The second temporary memory space is used to temporarily store the requested memory space. When the second temporary memory space meets the third preset condition, the memory space is retrieved from the second local memory space queue. The second local memory space queue is used to retrieve memory space from the memory resource space queue when the number of memory spaces stored in the second local memory space queue is less than or equal to a second preset number.

4. A memory management method, characterized in that, include: In response to the memory manager receiving a memory space return instruction, a return interface is determined based on the amount of memory space to be returned in the memory space return instruction and the device type that generated the memory space return instruction, wherein the device type includes one of the following: the type of processor, the type of direct memory accessor; the memory space to be returned is returned using the return interface; The method further includes: acquiring a first data packet received by the switch; acquiring a first memory space request instruction from the direct memory accessor based on the first data packet; generating a first memory address using a memory manager according to the first memory space request instruction; storing the first data packet into a first memory space of the memory storage based on the first memory address, wherein the first memory address is the memory address of the first memory space; and processing the first data packet from the first memory space using a processor based on the first memory address to obtain a first processing result. The method further includes: acquiring a second data packet from the processor; acquiring a second space allocation instruction from the direct memory accessor based on the second data packet; generating a second memory address using the memory manager according to the second space allocation instruction; storing the second data packet in a second memory space in the memory storage according to the second memory address; retrieving the second data packet from the second memory space through the direct memory accessor and sending the second data packet to the switch, wherein the switch is used to output the second data packet; and returning the second memory address to the memory manager in response to the switch outputting the second data packet.

5. The method according to claim 4, characterized in that, The return interface includes: a first return interface and a second return interface. The return interface is determined based on the amount of memory space to be returned in the memory space return instruction and the type of device that generated the memory space return instruction, including: In response to the fact that the memory space to be returned is a single memory space, the first return interface is determined to be the return interface, wherein the first return interface is used to directly return the single memory space; In response to the fact that the memory space to be returned is multiple memory spaces, the second return interface is determined to be the return interface, wherein the second return interface is used to return the multiple memory spaces in batches.

6. The method according to claim 5, characterized in that, The method further includes: In response to the memory manager receiving a memory space request instruction, a request interface is determined based on the amount of memory space to be requested in the memory space request instruction and the device type that generated the memory space request instruction, wherein the device type includes one of the following: the type of processor, the type of direct memory accessor; and the request interface is used to obtain the memory space to be requested.

7. The method according to claim 6, characterized in that, The request interface includes: a first request interface and a second request interface. The request interface is determined based on the amount of memory space to be requested in the memory space request instruction and the type of device that generated the memory space request instruction, including: In response to the fact that the requested memory space is a single memory space, the first request interface is determined to be the request interface according to the device type of the memory space request instruction, wherein the first request interface is used to directly obtain the single memory space; In response to the fact that the requested memory space is multiple memory spaces, the second request interface is determined as the request interface according to the device type of the memory space request instruction, wherein the second request interface is used to obtain the multiple memory spaces in batches.

8. A memory management device, characterized in that, include: A generation module is configured to, in response to a memory manager receiving a memory space return instruction, determine a return interface based on the quantity of memory space to be returned in the memory space return instruction and the device type that generated the memory space return instruction, wherein the device type includes one of the following: the type of processor, the type of direct memory accessor; A return module is used to return the memory space to be returned using the return interface; The apparatus is further configured to: acquire a first data packet received by the switch; acquire a first memory space request instruction from the direct memory accessor based on the first data packet; generate a first memory address using a memory manager according to the first memory space request instruction; store the first data packet in the first memory space of the memory storage based on the first memory address, wherein the first memory address is the memory address of the first memory space; and process the first data packet from the first memory space using a processor based on the first memory address to obtain a first processing result. The apparatus is further configured to: acquire a second data packet from the processor; acquire a second space request instruction from the direct memory accessor based on the second data packet; generate a second memory address using the memory manager according to the second space request instruction; store the second data packet in a second memory space in the memory storage according to the second memory address; retrieve the second data packet from the second memory space through the direct memory accessor and send the second data packet to the switch, wherein the switch is configured to output the second data packet; and return the second memory address to the memory manager in response to the switch outputting the second data packet.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform the method of any one of claims 4 to 7.

Images