DDR4 access control method, apparatus and network device

Abstract

The application provides a DDR4 access control method and device and network equipment, and relates to the technical field of network processors. The method comprises the following steps: performing reordering processing on an access instruction according to bank order preservation information in the access instruction sent by a service module, so as to map the access instruction to a first cache corresponding to the bank order preservation information; polling and serially reading a to-be-processed access instruction from each first cache, so as to perform an access operation corresponding to the to-be-processed access instruction on a corresponding DDR4, wherein the to-be-processed access instruction is one of the access instructions sent by a previous stage module; when reading read data from the DDR4, writing the read data into a corresponding second cache according to bank order preservation information in an access instruction corresponding to the read data; and performing order preservation processing on the read data read from the second cache according to user order preservation information before reordering, so as to feed back the read data to the corresponding service module according to the user order preservation information.

Description

Technical Field

[0001] This application relates to the field of network processor technology, and in particular to a DDR4 access control method, apparatus and network device. Background Technology

[0002] Currently, in network security devices, filtering firewalls can be used to achieve fast forwarding of IP packets. For example, in an internal LAN, a filtering firewall can accelerate user terminals' access to work-related websites such as online meetings and online office applications. Filtering firewalls are typically deployed between the client and server to quickly forward IP packets between them. Most filtering firewalls employ an architecture combining FPGA and CPU. The FPGA primarily handles packet parsing, session creation, session matching / writeback, session aging, and packet encapsulation and forwarding; the CPU mainly manages the FPGA's internal parameter configuration, various tables (including the session table), and log maintenance.

[0003] Due to limited internal storage resources within an FPGA, external DDR4 memory is typically used to store a large number of session tables. During packet aging, modules such as session creation (writing to DDR4), session matching / writeback (reading / writing to DDR4), and session aging (reading / writing to DDR4) all randomly access this DDR4 storage device. However, in actual testing, especially with a high number of session writebacks, DDR4 memory access performance degrades significantly, leading to a sharp decline in the firewall's packet aging performance. Currently, increasing the number of DDR4 modules can improve DDR4 memory access performance, but this increases hardware costs, physical size, and product weight.

[0004] Therefore, how to solve the problem of network device speed degradation caused by DDR4 memory access performance degradation in existing technologies without adding additional DDR4 is one of the technical problems worth considering. Summary of the Invention

[0005] In view of this, this application provides a DDR4 access control method, apparatus, and network device to solve the problem of decreased network device speed performance caused by the degraded DDR4 memory access performance in the prior art without adding additional DDR4.

[0006] Specifically, this application is implemented through the following technical solution:

[0007] According to a first aspect of this application, a DDR4 access control method is provided, applied in an FPGA, the method comprising:

[0008] Based on the Bank ordering information in the access instruction sent by the business module, the access instruction is reordered so as to map the access instruction to the first cache corresponding to the Bank ordering information;

[0009] The system polls and reads access instructions to be processed serially from each first cache to perform the access operation corresponding to the access instruction to be processed on the corresponding DDR4, wherein the access instruction to be processed is one of the access instructions sent by the previous module.

[0010] When read data from DDR4, the read data is written into the corresponding second cache according to the Bank order information in the access instruction corresponding to the read data.

[0011] Based on the user order information before reordering, the read data read from the second cache is processed to preserve the order, so that the read data is fed back to the corresponding business module according to the user order information.

[0012] According to a second aspect of this application, a DDR4 access control device is provided, disposed in an FPGA, the device comprising:

[0013] The reordering processing module is used to reorder the access instruction according to the Bank ordering information in the access instruction sent by the business module, so as to map the access instruction to the first cache corresponding to the Bank ordering information;

[0014] The instruction processing module is used to poll and serially read the access instructions to be processed from each first cache, so as to execute the access operation corresponding to the access instruction to be processed on the corresponding DDR4, wherein the access instruction to be processed is one of the access instructions sent by the previous module.

[0015] The first order preservation processing module is used to write the read data into the corresponding second cache according to the Bank order preservation information in the access instruction corresponding to the read data when read data is read from DDR4;

[0016] The second order preservation processing module is used to perform order preservation processing on the read data read from the second cache according to the user order preservation information before reordering, so as to feed the read data back to the corresponding business module according to the user order preservation information.

[0017] According to a third aspect of this application, a network device is provided, including an FPGA and a plurality of DDR4 modules, wherein the FPGA is used to execute the method provided in the first aspect of the embodiments of this application.

[0018] According to a fourth aspect of this application, a machine-readable storage medium is provided, which stores a computer program that, when invoked and executed by an FPGA, causes the FPGA to perform the method provided in the first aspect of the embodiments of this application.

[0019] The beneficial effects of the embodiments of this application are as follows:

[0020] In the DDR4 access control method and apparatus provided in this application embodiment, the FPGA reorders the access instructions according to the Bank ordering information in the access instructions sent by the service module, so as to map the access instructions to the first cache corresponding to the Bank ordering information; it polls and serially reads the access instructions to be processed from each of the first caches, so as to execute the access operation corresponding to the access instructions to be processed on the corresponding DDR4, wherein the access instructions to be processed are one of the access instructions sent by the previous level module; when read data is read from DDR4, the read data is written into the corresponding second cache according to the Bank ordering information in the access instruction corresponding to the read data; according to the user ordering information before reordering, the read data read from the second cache is processed to maintain the order, so as to feed the read data back to the corresponding service module according to the user ordering information. By adopting the aforementioned method, the received access instructions are first mapped to the first cache. This avoids the large number of access instructions generated by the business module from not being processed by the FPGA in a timely manner, thus improving the speed of access instructions. On the other hand, by performing reordering and instruction order preservation processing, interleaved access to DDR4 is well realized, that is, the same DDR4 is avoided in a short period of time, thus improving the random access performance of DDR4. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating a DDR4 access control method provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram illustrating the mapping relationship between regions in a Bank, FIFO, and RAM, provided in an embodiment of this application.

[0023] Figure 3 This is a schematic diagram of the structure of a DDR4 access control device provided in an embodiment of this application;

[0024] Figure 4a This is a schematic diagram of another DDR4 access control device provided in an embodiment of this application;

[0025] Figure 4b This is a schematic diagram illustrating an application scenario of the DDR4 access control device provided in this application embodiment;

[0026] Figure 5 This is a schematic diagram of the hardware structure of a network device implementing a DDR4 access control method, provided in an embodiment of this application. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0028] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the corresponding listed items.

[0029] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0030] The DDR4 access control method provided in this application will be described in detail below.

[0031] See Figure 1 , Figure 1 This is a flowchart of a DDR4 access control method provided in this application. This method can be applied to an FPGA, which can be, but is not limited to, installed in a network device. When implementing this method, the FPGA may include the following steps:

[0032] S101. Based on the Bank ordering information in the access instruction sent by the business module, the access instruction is reordered to map the access instruction to the first cache corresponding to the Bank ordering information.

[0033] In this step, to ensure fast access to DDR4, thereby improving the network device's switching performance and avoiding access latency caused by short-term access to the same DDR4, this embodiment proposes setting up multiple first caches. Thus, upon receiving an access command from a service module, the access command is temporarily stored in the corresponding first cache. This ensures timely response processing for subsequent access commands from service modules, thereby improving the network device's switching performance. When caching access commands, this embodiment proposes cache mapping based on the Bank ordering information in the access command to cache the access command in the corresponding first cache.

[0034] For example, if access commands 0, 1, 2, 15, etc., are received sequentially, multiple first caches can be set up, denoted as First Cache 1 to First Cache n, where the value of n can be configured according to actual needs. This allows different access commands to be mapped to their corresponding first caches based on the Bank ordering information within each access command. Furthermore, to avoid access latency caused by short-term access to the same DDR4 memory, the access commands are reordered during cache mapping. Access commands are processed intermittently based on the Bank ordering information within each command; specifically, a bankgroup-interleaved DDR4 access mapping method can be used.

[0035] Specifically, step S101 can be performed as follows: the access instruction is cache-mapped according to Bank_num in the Bank sequence information and written into the first cache corresponding to Bank_num.

[0036] Furthermore, access instructions can be cached in the corresponding first cache according to the set Bank_num interval.

[0037] Specifically, the Bank ordering information for each access instruction includes bank_num. In practical applications, this bank_num can be used for cache mapping. For example, every 4 bank_num intervals (as mentioned above), the corresponding cached instructions are cached in consecutive first caches. When the first cache can, but is not limited to, use FIFO, assuming there are currently 0 to 15 first caches, and each access instruction corresponds to bank_num from 0 to 15, then during cache mapping, access instruction 0 corresponding to bank_num 0 can be written to first cache 0, access instruction 4 corresponding to bank_num 4 can be cached to first cache 1, access instruction 8 corresponding to bank_num 8 can be cached to first cache 2, and so on. For details, please refer to the cache mapping method shown in Table 1, where fifo_num is the cache number of each first cache.

[0038] Table 1

[0039] 0 0 4 1 8 2 12 3 1 4 5 5 9 6 13 7 2 8 6 9 10 10 14 11 3 12 7 13 11 14 15 15

[0040] By employing the aforementioned cache mapping method, access commands are cached in the first cache. This prevents access command congestion even if the service module continuously generates access commands. Furthermore, access commands are not continuously stored in the first cache; after the current access command successfully accesses DDR4 from the first cache, the next access command is read from the first cache. Therefore, a large number of access commands do not accumulate in the first cache. In addition, by performing reordering and command order preservation processing, interleaved access to DDR4 is effectively achieved, avoiding short-term access to the same DDR4, thereby improving DDR4 access performance and preventing the degradation of network device speed switching performance.

[0041] Optionally, the above-mentioned business modules may include, but are not limited to, a session aging module, a session creation module, a session matching / writing module, etc.

[0042] S102. Poll and serially read the access instructions to be processed from each first cache to perform the access operation corresponding to the DDR4 to be processed, wherein the access instruction to be processed is one of the access instructions sent by the previous module.

[0043] In this step, each access instruction is only temporarily stored in its respective first cache. Since the FPGA still needs to process each access instruction, it needs to read the access instructions from the first cache. This embodiment proposes using a polling method to read the access instruction to be processed from each first cache. This access instruction to be processed is one of the access instructions written in step S101. Then, the read access instructions to be processed are converted from parallel to serial processing so that each access instruction to be processed is processed serially. Finally, the corresponding access operation is executed based on the DDR4 indicated by the access instruction to be processed.

[0044] Optionally, the aforementioned access instruction can be, but is not limited to, a read access instruction, a write access instruction, etc. If the currently processed access instruction is a write access instruction, the write data corresponding to the write access instruction is directly written into the DDR4. When the access instruction is a read access instruction, the read data indicated by the read access instruction needs to be read from the corresponding DDR4 when executing the read access instruction. After the read data is read, since it needs to be fed back to the corresponding business module, this embodiment provides a read data return process in step S103.

[0045] S103. When read data is read from DDR4, the read data is written into the corresponding second cache according to the Bank order information in the access instruction corresponding to the read data.

[0046] In this step, after reading data from DDR4 in response to a read access command, there may be a significant latency issue during the read data reading process. Furthermore, previously read data may still be being fed back to the service module. To prevent delays in the feedback of the next read access command due to the newly read data waiting for feedback from the previous read data, this embodiment proposes setting up multiple second caches during read data feedback, and then caching the read data from DDR4 into the corresponding second caches. Therefore, since the read access command includes Bank ordering information, this embodiment can also utilize the Bank ordering information in the read access command to map the read data cache to the corresponding second cache.

[0047] It should be noted that when performing cache mapping, the cache mapping method used can be based on bank_num in the Bank order information. For details, please refer to Table 2, where fifo_num is the cache number of the second cache.

[0048] Table 2

[0049]

[0050]

[0051] S104. Based on the user order information before reordering, the read data read from the second cache is processed to preserve the order, so that the read data is fed back to the corresponding business module according to the user order information.

[0052] In this step, after the read data is cached in the second cache, since the read data is to be fed back to the business module, after the previous read data is fed back to the business module, the read data can be read serially from the second cache. Then, according to the user order information of the previous access instructions, the read data is fed back to the corresponding business module, thus realizing the accurate and fast feedback of read data to the corresponding business module.

[0053] It should be noted that when reading data from the second cache, the reading can be performed based on the Bank ordering information of the read access instruction.

[0054] In the DDR4 access control method provided in this application, the FPGA reorders the access instructions based on the Bank ordering information in the access instructions sent by the service module, mapping the access instructions to the first cache corresponding to the Bank ordering information. It then polls and serially reads the access instructions to be processed from each of the first caches to execute the access operation corresponding to the access instruction on the corresponding DDR4, wherein the access instruction to be processed is one of the access instructions sent by the previous module. When read data is read from the DDR4, the read data is written to the corresponding second cache according to the Bank ordering information in the access instruction corresponding to the read data. Based on the user ordering information before reordering, the read data read from the second cache is processed to maintain its order, and then fed back to the corresponding service module according to the user ordering information. By adopting the aforementioned method, on the one hand, it avoids a large number of access instructions generated by the service module not being processed by the FPGA in a timely manner, thus improving the speed of access instruction processing; on the other hand, by performing reordering and ordering processing of instructions, it effectively achieves interleaved access to DDR4, avoiding access to the same DDR4 in a short period of time, thereby improving the random access performance of DDR4.

[0055] Optionally, based on any of the above embodiments, this embodiment may perform step S102 according to the following method: perform interface protocol conversion processing on the read access instruction to be processed, so as to convert it into a target access instruction that matches the interface protocol supported by the DDR4 controller; send the target access instruction to the corresponding DDR4 controller, so that the DDR4 controller performs the corresponding access operation on the DDR4 based on the target access instruction.

[0056] Specifically, since the protocol used by the access command triggered by the service module may differ from the protocol that DDR4 can recognize, this embodiment proposes to perform interface protocol conversion processing on the access command in order to enable DDR4 to recognize the operation indicated by the access command. That is, the interface protocol is converted according to the protocol specified by DDR4. The converted target access command is then sent to the DDR4 controller. Thus, after receiving the target access command with a protocol consistent with the DDR4 protocol, the DDR4 controller can execute the corresponding access operation. For example, when the access command is a read access command, the interface protocol conversion yields the target read access command. After sending this target read access command to the DDR4 controller, the DDR4 controller can read the corresponding data from the corresponding DDR4 based on the target read access command. Conversely, when the access command is a write access command, after receiving the target write access command after interface protocol conversion, the DDR4 can write the write data indicated by the target write access command into the corresponding DDR4. This not only ensures that the access command correctly reaches the DDR4, thus guaranteeing normal DDR4 access, but also enables normal processing of multiple commands through protocol conversion.

[0057] Furthermore, after the FPGA performs interface protocol conversion, it connects to multiple DDR4 controllers through multiple interfaces. In this way, during interface protocol conversion, the target write access command and / or target read access command can be mapped to the corresponding interface of the DDR4 controller, thereby realizing fast and parallel processing of access commands.

[0058] Accordingly, before sending write data to the DDR4 controller, the FPGA also needs to perform interface protocol conversion processing on the write data to convert it into write data that the DDR4 controller and DDR4 can recognize and store. Then, the write processing is performed on the converted write data. Similarly, after the DDR4 controller reads read data from the DDR4 and sends it back to the FPGA, the FPGA also needs to perform interface protocol conversion processing on the read data to convert it into read data that the FPGA can recognize. Then, the read data is processed according to the steps S103 and S104 described above.

[0059] Furthermore, when both the first and second buffers within the FPGA are FIFOs, read access instructions, write access instructions, data writing, data reading triggered by the service module, as well as data transmission between other modules within the FPGA, are all implemented based on the FIFO interface protocol. The data transmission format and functions followed by the FIFO interface protocol can be found in Table 3.

[0060] Table 3

[0061]

[0062] Optionally, based on any of the above embodiments, this embodiment may further include the following process before executing step S101: polling the received multiple access instructions to convert the parallel multiple access instructions into serial and adjacent access instructions for different business modules.

[0063] Specifically, since different service modules may generate different access instructions, and multiple modules may generate access instructions simultaneously, multiple accesses to DDR4 may be required. Therefore, to achieve efficient and accurate access to DDR4, this embodiment proposes that after receiving access instructions from multiple service modules, these access instructions are polled and scheduled to convert the parallel-received access instructions into serial access instructions. Furthermore, to ensure that the access instructions from each service module are processed, this embodiment also proposes that after converting the access instructions in parallel to serial order, adjacent access instructions are from different service modules. This can be understood as including access instructions from each service module within each instruction processing cycle.

[0064] For example, consider business module 1, business module 2, and business module 3. Business module 1 generates access commands 1, 2, and 3; business module 2 generates access commands 4 and 5; and business module 3 generates access commands 6, 7, and 8, and so on. These eight access commands can be converted from parallel to string. When polling the access commands from each business module, the processing order is: access command 1, access command 4, access command 6, access command 2, access command 5, access command 7, access command 3, and access command 8.

[0065] It should be noted that when performing parallel-to-serial conversion and write polling sorting, the processing can be carried out according to the time order of the received access instructions. If each business module has a processing priority, when access instructions sent by each business module are received at the same time, this embodiment can process them according to the processing priority of each business module. Of course, other sorting methods can also be used, and the specific method can be configured according to the actual situation.

[0066] Optionally, during polling scheduling, there can be two polling processes: one dedicated to handling write access commands and the other dedicated to handling read access commands. Each polling process processes the access commands it receives in parallel and serial processing, and then aggregates them to the scheduling process. To ensure balanced processing of access commands from various business modules, the scheduling process will perform polling processing on the serial access commands according to the above processing method, so as to ensure that adjacent access commands processed belong to different business modules.

[0067] Optionally, based on any of the above embodiments, before executing step S101, or after polling the received multiple access instructions, before executing step S101, this embodiment may also perform the following process: when the multiple access instructions received simultaneously include a write access instruction, the write access instruction is processed first.

[0068] Specifically, in practical applications, each business module may generate read access instructions and / or write access instructions. Read access instructions and write access instructions have different priorities. Generally, write access instructions are given priority by default. Therefore, after parallel-to-serial conversion, when two access instructions sent by two polling processes are received at the same time, the write access instructions are processed first. That is, the access instructions are reordered according to the Bank ordering information in the write access instructions.

[0069] When the scheduling process receives multiple access instructions simultaneously, including write access instructions, the write access instructions can be processed first. That is, the access instructions are reordered based on the Bank ordering information within them. For example, if the currently received access instructions are: Access Instruction 1, Access Instruction 4, and Access Instruction 6, and Access Instruction 4 is a write access instruction, the scheduling process can process these three instructions in the following order: Access Instruction 4, Access Instruction 1, and Access Instruction 6. Then, the access instructions are reordered based on the Bank ordering information within Access Instruction 4. After processing Access Instruction 4, Access Instructions 1 and 6 are processed sequentially.

[0070] Optionally, based on any of the above embodiments, in this embodiment, when the access instruction includes a write access instruction, the write data corresponding to the write access instruction is cached in the random access memory (RAM).

[0071] Specifically, this embodiment uses a caching mechanism based on FIFO and RAM architecture to cache access instructions and write data respectively in setting up the first and second caches. For DDR64, the instruction bit width requirement is not large (32 bits), but the data bit width is large (DDR4 IP Core data bit width is 512 bits, burst length is 8). If both instructions and data are cached in a general FIFO, it will consume a large amount of logic resources inside the FPGA. In view of this, this embodiment proposes to use FIFO as the first and second caches to cache access instructions; at the same time, RAM is used to cache the write data corresponding to the write access instructions. Specifically, the FIFO is used to store a small amount of pointer information (corresponding to RAM addresses) and bank order information, while a large amount of data is stored in one RAM, which can be composed of URAM, each URAM having a capacity of 4K*72 bits. Moreover, this RAM is divided into areas with the same number and specifications as the FIFOs, corresponding one-to-one with the FIFOs. By using the FPGA's internal storage resources to replace some logic resources, the consumption of FPGA's internal logic resources is reduced.

[0072] Specifically, DDR4 has 16 banks, designated Bank0 to Bank15. Correspondingly, the FPGA internally sets up either a first cache or a second cache corresponding to the number of banks, i.e., 16 first caches and 16 second caches respectively. The RAM corresponding to the first cache can be divided into 16 regions, with each region corresponding to one first cache. When the first cache is a FIFO, the mapping relationship between banks, FIFOs, and regions in RAM can be referenced... Figure 2As shown, this application employs a cross-bankgroup interleaved access method for DDR4 during reordering, which offers the highest DDR4 access efficiency. Therefore, in this embodiment, Bank0 to Bank3 are designated as bankgroup0, Bank4 to Bank7 as bankgroup1, Bank8 to Bank11 as bankgroup2, and Bank12 to Bank15 as bankgroup3. Based on this, during reordering, bank0 corresponds to FIFO0, bank1 to FIFO4, bank2 to FIFO8, bank3 to FIFO12, bank4 to FIFO1, bank5 to FIFO5, bank6 to FIFO9, bank7 to FIFO13, bank8 to FIFO2, bank9 to FIFO6, bank10 to FIFO10, bank11 to FIFO14, bank12 to FIFO3, bank13 to FIFO7, bank14 to FIFO11, and bank15 to FIFO15. In other words, access instructions with bank_num=bank0 are cached in the first cache with fifo_num=FIFO0, access instructions with bank_num=bank1 are cached in the first cache with fifo_num=FIFO4, access instructions with bank_num=bank2 are cached in the first cache with fifo_num=FIFO8, and so on.

[0073] Based on this, the data format definition for read / write access instructions is as follows:

[0074]

[0075] Similarly, the data format for reading / writing data can be as follows:

[0076] typedef struct packed{

[0077] reg[511:0]burst_data; / / 511:0

[0078] DRAM_DAT_S;

[0079] Based on this, the format of the information stored in the first buffer FIFO is defined as follows:

[0080]

[0081] Similarly, the data format for write data stored in RAM is defined as follows:

[0082]

[0083] For read data from DDR4, this read data is shared with the write data to be written to DDR4. The data members are different, but the data bit width is the same, and the format is as follows:

[0084] typedef struct packed{

[0085] reg [543-32-n:0]rsv; / / Reserved

[0086] reg [n-1:0] user_num; / / User order information, generated during polling and parallel-to-serial transformation processing;

[0087] reg[31:0]cmd; / / Contains Bank order preservation information;

[0088] }IG_RAM_DAT_S;

[0089] Similarly, when performing order-preserving processing, the data format stored in the second buffer FIFO can be defined as follows:

[0090] typedef struct packed{

[0091] reg[6:0]ram_addr; / / This value represents the RAM region address

[0092] }EG_RAM_CMD_S;

[0093] Furthermore, the data format for read data stored in RAM can be defined as follows:

[0094]

[0095] At this point, the format of the order-preserving information corresponding to the data read from the second buffer FIFO is as follows:

[0096]

[0097] Furthermore, the target access commands (target read access command, target write access command, target write data) on the DDR4 controller side can be based on the DDR4 User Interface protocol, as shown in Table 4:

[0098] Table 4

[0099]

[0100]

[0101] Thus, by providing the DDR4 access control method in any embodiment of this application, the received access instructions are reordered and cached, which to a certain extent ensures that DDR4 is accessed in a bankgroup interleaving manner, effectively improving efficiency; and to a certain extent avoids frequent read-write switching memory access, thereby solving the problem of low DDR4 random memory access performance.

[0102] Based on the same inventive concept, this application also provides a DDR4 access control device corresponding to the above-described DDR4 access control method. Specific implementation details of this DDR4 access control device can be found in the above description of the DDR4 access control method, and will not be elaborated upon here.

[0103] See Figure 3 , Figure 3 This application provides an exemplary embodiment of a DDR4 access control device, disposed in an FPGA, the device comprising:

[0104] The reordering processing module 301 is used to reorder the access instructions according to the Bank order information in the access instructions sent by the service module, so as to map the access instructions to the first cache corresponding to the Bank order information; and to poll and serially read the access instructions to be processed from each first cache, so as to execute the access operation corresponding to the access instructions to be processed on the corresponding DDR4, wherein the access instructions to be processed are one of the access instructions sent by the previous module.

[0105] The first order preservation processing module 302 is used to write the read data into the corresponding second cache according to the Bank order preservation information in the access instruction corresponding to the read data when read data is read from DDR4;

[0106] The second order preservation processing module 303 is used to perform order preservation processing on the read data read from the second cache according to the user order preservation information before reordering, so as to feed the read data back to the corresponding business module according to the user order preservation information.

[0107] Optionally, based on the above embodiments, the DDR4 access control device provided in this embodiment may further include: an interface protocol conversion module, which can be referred to in detail. Figure 4a As shown, where:

[0108] The reordering processing module 301 is used to send the read access instruction to be processed to the interface protocol conversion module;

[0109] The aforementioned interface protocol conversion module is used to perform interface protocol conversion processing on the received access instruction to be processed, so as to convert it into a target access instruction that matches the interface protocol supported by the DDR4 controller; and send the target access instruction to the corresponding DDR4 controller, so that the DDR4 controller can perform the corresponding access operation on the DDR4 based on the target access instruction.

[0110] Optionally, based on any of the above embodiments, the DDR4 access control device provided in this embodiment may further include a polling processing module, which can also be referred to in detail. Figure 4a As shown, where:

[0111] The aforementioned polling processing module is used to poll multiple received access instructions before the reordering processing module 301 reorders the access instructions according to the Bank order information in the access instructions sent by the service modules, so as to convert the multiple parallel access instructions into serial and adjacent access instructions for different service modules.

[0112] Specifically, the aforementioned polling processing module may include two n-in-1 processing modules, combined with Figure 4a To illustrate, one n-in-1 processing module is used for polling write access commands. Specifically, it receives write access commands `user_wr[n-1:0]` from the service module and performs polling to convert the parallel write access commands into serial write access commands `user_wr[0:0]`, which are then sent to the next-level module. Similarly, another n-in-1 processing module is used for polling read access commands. It receives read access commands `user_rd[n-1:0]` from the service module and performs polling to convert the parallel read access commands into serial read access commands `user_rd[0:0]`, which are then sent to the next-level module.

[0113] Optionally, based on any of the above embodiments, the DDR4 access control device provided in this embodiment may further include: a scheduling module, please also refer to Figure 4a As shown, where:

[0114] The scheduling module (not shown in the figure) is used to prioritize sending the write access instruction to the reordering processing module when multiple access instructions received at the same time include a write access instruction.

[0115] Based on this, the reordering module 301 is specifically used to reorder the write access instruction according to the Bank order preservation information in the write access instruction after receiving the write access instruction.

[0116] Specifically, when the aforementioned scheduling module is a sub-module of the polling scheduling module, after receiving the serial access instructions sent by the n-to-1 processing module in the polling processing module, if the received access instructions include both read and write access instructions, the scheduling module will perform priority scheduling. Generally, the priority of write access instructions is higher than that of read access instructions. Therefore, the scheduling module will prioritize processing write access instructions, that is, prioritize sending write access instructions to the reordering processing module 301. After receiving the serial access instructions (write access instructions and / or read access instructions), in order to achieve fast forwarding of access instructions and avoid accessing the same DDR4 in a short period of time, thereby improving the random access performance of DDR4, the reordering processing module 301 can execute the following process: Taking a DDR4 with 16 banks as an example, the reordering processing module 301 can set up a first cache with the same number of banks, that is, set up 16 first caches. Based on this, a 1-to-16 processing module can be set in the reordering processing module. This 1-to-16 processing module can perform parallel conversion processing on the received serial access instructions, and then perform reordering processing according to the Bank order preservation information in each access instruction, thereby mapping each access instruction to different first caches.

[0117] Based on this, since the access instructions in the first cache still need to be read and access DDR4, the reordering processing module 301 mentioned above also includes a 16-in-1 processing module. Please refer to [the relevant documentation]. Figure 4a As shown. This 16-in-1 processing module can each read access instructions from the first cache, such as... Figure 4a The system reads user[15:0] from the DDR4 controller, and then performs serial conversion processing on the access instructions read in parallel. This means processing each access instruction sequentially, sending each access instruction user[0:0] to the interface protocol conversion module in order. Upon receiving the access instruction, the interface protocol conversion module can convert it into a target access instruction ddr4_app_intf that the DDR4 controller can recognize. Then, upon receiving this target access instruction, the DDR4 controller can perform the corresponding access operation on the DDR4 based on the target access instruction.

[0118] It should be noted that when the 16-in-1 processing module in the reordering processing module reads a read access instruction, since this read access instruction requires reading the corresponding read data from the corresponding DDR4, the 16-in-1 processing module can send the Bank sequence information of the read access instruction to the first sequence keeping processing module 302 after reading the read access instruction. The first sequence keeping processing module 302 will wait for the read data returned by the interface protocol conversion module. This read data is recorded as the read data corresponding to the received Bank sequence information, thus ensuring that the read data is correctly fed back to the service module. Specifically, the first sequence keeping processing module 302 is equipped with a second cache, and it should be noted that the number of the second cache is consistent with the number of Banks. The first sequence keeping processing module 302 is also equipped with a 1-to-16 processing module. When the interface protocol conversion module receives the read data ddr4_app_intf read from the DDR4 by the DDR4 controller, it will perform interface protocol conversion processing on the read data to convert it into read data that can be recognized by the various modules inside the FPGA, and record it as the target read data. In this way, after receiving the target read data, the 1-to-16 processing module in the first order preservation processing module 302 can perform mapping processing on the target read data based on the Bank order preservation information fed back by the 16-to-1 processing module in the reordering processing module 301, so as to map the target read data to the corresponding second cache. This avoids the situation where the read data returned from DDR4 is slow due to the lack of a second cache. That is, by setting the second cache, the read data corresponding to the read access instructions continuously sent to the DDR4 controller by the 16-to-1 processing module in the reordering processing module can be continuously cached.

[0119] Based on this, since the data cached in the second cache needs to be fed back to the business module, the first order-keeping processing module 302 is also equipped with a 16-in-1 processing module. After reading one piece of read data from the second cache, the 16-in-1 processing module will continue to read the next piece of read data from the second cache and then send it serially to the second order-keeping processing module 303.

[0120] It is worth noting that since access commands are sent by various business modules, and these commands are ordered, this embodiment proposes that, in order to ensure that the read data corresponding to the read access command is correctly fed back to the corresponding business module, the n-in-1 processing module in the polling processing module, after performing parallel-to-serial transformation on the read access command, generates user order preservation information to indicate the business module corresponding to the read access command. To achieve order preservation, this user order preservation information is transmitted to various modules. For example, the n-in-1 processing module will transmit the user order preservation information along with the read access command to the reordering processing module 301. Figure 4aThe order preservation information in the reordering processing module 301 includes both Bank order preservation information and User order preservation information. The reordering processing module 301 then transmits the order preservation information to the first order preservation processing module 302. In addition, the polling processing module handles both read access instructions and write access instructions. Since only read access instructions involve reading data from DDR4, to ensure fast processing of the read data returned by the read access instructions, the n-in-1 processing module in the polling processing module, after receiving a read access instruction, will sequentially send the Bank ordering information from each read access instruction to the 16-in-1 processing module in the first ordering processing module 302, so that the 16-in-1 processing module can read the corresponding read data from the corresponding second cache according to the received Bank ordering information. In addition, in order to accurately feed the read data back to the corresponding business module, since the ordering information returned by the 16-in-1 processing module in the reordering processing module 301 to the first ordering processing module 302 includes both Bank ordering information and User ordering information, the 1-in-16 processing module in the first ordering processing module 302 will transmit the User ordering information to the 16-in-1 processing module in the first ordering processing module 302 after receiving it. In this way, the 16-in-1 processing module can send the read data user_dat[0:0] and the corresponding User sequence information to the second sequence processing module 303.

[0121] The second sequence preservation processing module 303 can be a 1-to-n processing module. Since the read data received from the first sequence preservation processing module 302 is serially transmitted, in order to quickly feed back each read data to the corresponding business module, the 1-to-n processing module can perform parallel conversion processing on the serially received read data, and then forward the read data to the corresponding business modules in parallel according to the User sequence preservation information.

[0122] Optionally, based on any of the above embodiments, in this embodiment, the reordering processing module 301 is specifically used to perform cache mapping processing on the access instruction according to the Bank_num in the Bank ordering information, so as to write it into the first cache corresponding to the Bank_num.

[0123] Furthermore, the aforementioned reordering processing module 301 is specifically used to cache access instructions into the corresponding first cache according to the set Bank_num interval.

[0124] Optionally, based on any of the above embodiments, in this embodiment, when the access instruction includes a write access instruction, the write data corresponding to the write access instruction is cached in the random access memory (RAM).

[0125] Thus, by providing the aforementioned DDR4 access control device, not only is the performance of DDR4 random access memory improved, but the speed performance of network devices is also enhanced.

[0126] To better understand the DDR4 access control device provided in this embodiment, an application scenario diagram of the device is provided. The FPGA internally includes a session aging module, a session creation module, a packet parsing module, a session matching / write-back module, a packet encapsulation module, and a DDR4 controller. The processing flow of each module is roughly as follows:

[0127] After a message enters the message parsing module, it extracts the message features (generally composed of quintuples, etc.) and then transmits these features to the session matching / write-back module for session matching. During session matching, the module identifies the corresponding session entries. Since these session entries are stored in DDR4, the session matching / write-back module sends a read access command to the DDR4 access control module provided in this application to perform message feature matching based on the read session entries. If the message requires write-back processing, the session matching / write-back module can send a write access command to the DDR4 access control device to update the entries in DDR4. Finally, the message enters the message encapsulation module to complete message exit routing, etc.

[0128] If no match is found within the FPGA, it indicates that the message may be the first message. The FPGA will then send the first message to the CPU. The CPU will perform session table flushing control based on the message characteristics and complete session creation through the session creation module inside the FPGA. That is, the session creation module will send the table entry processing instruction to the DDR4 access control device. The DDR4 access control device can then write the table entry into the corresponding DDR4 according to the method described in any embodiment of this application to complete the flushing of the session table entry.

[0129] The session aging module periodically scans session entries according to parameters set by the CPU. Since it needs to read DDR4 to obtain session entries, the session aging module sends a read access command to the DDR4 access control device. The DDR4 access control device can then read the session entries according to the method described in any embodiment of this application and return the information to the session aging module. The session aging module determines whether aging processing is required based on the entry content. If a session entry needs to be deleted, the session aging module sends a write access command to the DDR4 access control device, so that the DDR4 controller can delete the session entry from DDR4. In addition, the CPU can also directly read / write DDR4 to complete specific debugging functions, such as querying the content of a certain entry or clearing the content of a certain entry through the DDR4 access control device provided in any embodiment of this application.

[0130] By providing the aforementioned DDR4 access control device, not only is the performance of DDR4 random access memory improved, but the speed performance of the network device where the FPGA is located is also improved.

[0131] Based on the same inventive concept, embodiments of this application provide a network device, such as... Figure 5 As shown, the network device includes a central processing unit 500, an FPGA 501, several DDR4 memory modules, and a machine-readable storage medium 502. The machine-readable storage medium 502 stores a computer program executable by the FPGA 501. The FPGA 501 is prompted by the computer program to execute the DDR4 access control method provided in any embodiment of this application. Furthermore, the network device also includes a communication interface 503 and a communication bus 504, wherein the processor 501, the communication interface 503, and the machine-readable storage medium 502 communicate with each other via the communication bus 504.

[0132] The communication bus mentioned in the above network devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0133] The communication interface is used for communication between the aforementioned network devices and other devices.

[0134] The machine-readable storage medium 502 described above can be a memory, which may include random access memory (RAM), DDR SRAM (Double Data Rate Synchronous Dynamic Random Access Memory), or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0135] For network devices and machine-readable storage media embodiments, since the methods involved are basically similar to those described in the foregoing method embodiments, the description is relatively simple, and relevant details can be found in the descriptions of the method embodiments.

[0136] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0137] The specific implementation process of the functions and roles of each unit / module in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0138] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units / modules described as separate components may or may not be physically separate. The components shown as units / modules may or may not be physical units / modules, that is, they may be located in one place or distributed across multiple network units / modules. Some or all of the units / modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0139] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A DDR4 access control method, characterized in that, When applied to an FPGA, the method includes: Based on the Bank ordering information in the access instruction sent by the business module, the access instruction is reordered so as to map the access instruction to the first cache corresponding to the Bank ordering information; The system polls and reads access instructions to be processed serially from each first cache to perform the access operation corresponding to the access instruction to be processed on the corresponding DDR4, wherein the access instruction to be processed is one of the access instructions sent by the previous module. When read data from DDR4, the read data is written into the corresponding second cache according to the Bank order information in the access instruction corresponding to the read data. Based on the user order information before reordering, the read data read from the second cache is processed to preserve the order, so that the read data is fed back to the corresponding business module according to the user order information.

2. The method according to claim 1, characterized in that, Polling and serially reading pending access instructions from each of the first caches, and executing the access operation corresponding to the pending access instruction on the corresponding DDR4, including: The read access instructions to be processed are converted into target access instructions that match the interface protocol supported by the DDR4 controller. The target access instruction is sent to the corresponding DDR4 controller, so that the DDR4 controller can perform the corresponding access operation on the DDR4 based on the target access instruction.

3. The method according to claim 1, characterized in that, Before reordering the access instruction based on the Bank ordering information in the access instruction sent by the business module, the process further includes: The received multiple access commands are polled to convert the parallel access commands into serial and adjacent access commands for different business modules.

4. The method according to any one of claims 1 to 3, characterized in that, Before reordering the access instruction based on the Bank ordering information in the access instruction sent by the business module, the process further includes: When multiple access commands received simultaneously include a write access command, the write access command is processed first.

5. The method according to claim 1, characterized in that, Based on the Bank ordering information in the access command sent by the business module, the access command is reordered to map the access command to the first cache corresponding to the Bank ordering information, including: The access instruction is cache-mapped according to the Bank_num in the Bank sequence information and written into the first cache corresponding to the Bank_num.

6. The method according to claim 1, characterized in that, When the access instruction includes a write access instruction, the write data corresponding to the write access instruction is cached in the random access memory (RAM).

7. The method according to claim 5, characterized in that, The access instruction is cache-mapped according to the Bank_num in the Bank ordering information and written to the first cache corresponding to the Bank_num, including: Access instructions are cached in the corresponding first cache according to the set Bank_num interval.

8. A DDR4 access control device, characterized in that, The device, configured in an FPGA, includes: The reordering processing module is used to reorder the access instructions according to the Bank ordering information in the access instructions sent by the service module, so as to map the access instructions to the first cache corresponding to the Bank ordering information; and to poll and serially read the access instructions to be processed from each first cache, so as to execute the access operation corresponding to the access instructions to be processed on the corresponding DDR4, wherein the access instructions to be processed are one of the access instructions sent by the previous module. The first order preservation processing module is used to write the read data into the corresponding second cache according to the Bank order preservation information in the access instruction corresponding to the read data when read data is read from DDR4; The second order preservation processing module is used to perform order preservation processing on the read data read from the second cache according to the user order preservation information before reordering, so as to feed the read data back to the corresponding business module according to the user order preservation information.

9. The apparatus according to claim 8, characterized in that, Also includes: The interface protocol conversion module includes: The reordering processing module is specifically used to send the read access instructions to be processed to the interface protocol conversion module; The interface protocol conversion module is used to perform interface protocol conversion processing on the received access instruction to be processed, so as to convert it into a target access instruction that matches the interface protocol supported by the DDR4 controller; and send the target access instruction to the corresponding DDR4 controller, so that the DDR4 controller can perform the corresponding access operation on the DDR4 based on the target access instruction.

10. The apparatus according to claim 8, characterized in that, Also includes: The polling processing module is used to poll multiple received access instructions before the reordering processing module reorders the access instructions according to the Bank order information in the access instructions sent by the service modules, so as to convert the multiple parallel access instructions into serial and adjacent access instructions for different service modules.

11. The apparatus according to any one of claims 8 to 10, characterized in that, Also includes: The scheduling module is used to prioritize sending the write access instruction to the reordering processing module when multiple access instructions received simultaneously include a write access instruction. The reordering module is specifically used to reorder the write access instruction according to the Bank order preservation information in the write access instruction after receiving the write access instruction.

12. The apparatus according to claim 8, characterized in that, The reordering processing module is specifically used to perform cache mapping processing on the access instruction according to the Bank_num in the Bank ordering information, so as to write it into the first cache corresponding to the Bank_num.

13. The apparatus according to claim 11, characterized in that, The reordering processing module is specifically used to cache access instructions into the corresponding first cache according to the set Bank_num interval.

14. A network device, characterized in that, It includes an FPGA and several DDR4 modules, wherein the FPGA is used to execute the DDR4 access control method according to any one of claims 1 to 7.

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