Dma control apparatus and method and chip

Abstract

The application provides a DMA control device and method and a chip. The device comprises: a plurality of logical channels respectively configured to receive a transmission request; a plurality of physical channels respectively configured to perform data transmission based on the transmission request; a channel selection module electrically coupled between the plurality of logical channels and the plurality of physical channels and configured to bind a selected logical channel in the plurality of logical channels to an idle physical channel in the plurality of physical channels; and a bus selection module electrically coupled between the plurality of physical channels and a bus and configured to enable a selected physical channel in the plurality of physical channels to access the bus to perform the data transmission. The application provides a multi-channel, time-multiplexed DMA controller structure, which can reduce the area of the DMA controller and facilitate the expansion of the number of channels.

Description

Technical Field

[0001] This application belongs to the technical field of DMA control, and relates to a control device, and more particularly to a DMA control device, method and chip. Background Technology

[0002] Generally, in a SoC (System on Chip), low-speed peripherals transmit data through a DMA (Direct Memory Access) controller. For example... Figure 1 As shown, high-speed modules such as the processor, memory, and DMA controller are connected to the high-speed system bus, while low-speed peripherals are connected to the low-speed local bus. The local bus interacts with the system bus through a bus bridge. The DMA controller can read and write to memory and low-speed peripherals via the bus, thereby enabling data transfer between memory and memory, memory and peripherals, and peripherals and memory. Each peripheral occupies one DMA channel and initiates a transfer request to the DMA channel via a DMA request signal. The software first configures the peripheral and the DMA controller, then the peripheral initiates a DMA request to the DMA channel, the DMA channel executes the data transfer, and finally the DMA channel returns a DMA acknowledgment to the peripheral.

[0003] Traditional DMA channels consist of a data processing module and a data buffer, both of which occupy a large area. Furthermore, current SoC systems contain numerous low-speed peripherals, requiring a large number of DMA channels. The data processing modules and data buffers for multiple DMA channels also occupy a significant area, resulting in substantial hardware overhead for the DMA controller. Therefore, traditional DMA controllers have a limited number of channels, each with a large area, hindering channel expansion. To meet these demands, multiple DMA controllers must be used, which undoubtedly increases chip area, power consumption, and software / hardware complexity. Summary of the Invention

[0004] The purpose of this application is to provide a DMA control device, method, and chip to solve the problem of the inability to simultaneously increase the number of channels and reduce the channel area.

[0005] A first aspect of this application provides a DMA control apparatus. The apparatus includes: a plurality of logical channels, each configured to receive a transmission request; a plurality of physical channels, each configured to perform data transmission based on the transmission request; a channel selection module electrically coupled between the plurality of logical channels and the plurality of physical channels, and configured to bind a selected logical channel from the plurality of logical channels to an idle physical channel among the plurality of physical channels; and a bus selection module electrically coupled between the plurality of physical channels and a bus, and configured to cause a selected physical channel from the plurality of physical channels to access the bus to perform the data transmission.

[0006] In this application, the DMA channel is divided into two parts: a logical channel and a physical channel. The logical channel has a small area, and the number of logical channels can be configured according to the number of low-speed peripherals; the physical channel has a large area, and the number of physical channels can be configured according to performance requirements.

[0007] In one implementation of the first aspect, the plurality of logical channels are further configured to send a channel allocation request to the channel selection module based on the transmission request, and the channel selection module is configured to select one logical channel from the plurality of logical channels at a certain time based on the channel allocation request, and allocate an idle physical channel from the plurality of physical channels to the selected logical channel.

[0008] In one implementation of the first aspect, the plurality of physical channels are further configured to send a bus read / write request to the bus selection module based on the transmission request, and the bus selection module is configured to select one physical channel from the plurality of physical channels at a certain time based on the bus read / write request, so as to allow the selected physical channel to perform data reading or data writing for the bus.

[0009] In one implementation of the first aspect, the number of the plurality of logical channels and the number of the plurality of physical channels are set independently of each other.

[0010] In one implementation of the first aspect, the apparatus further includes: a bus interface module electrically coupled between the bus selection module and the bus, and configured to electrically couple the selected physical channel to the bus via a bus read interface or a bus write interface.

[0011] In one implementation of the first aspect, the channel selection module includes: a channel arbitrator configured to allocate the idle physical channel to the at least one logical channel in response to a channel allocation request initiated by at least one of the plurality of logical channels, according to a first allocation principle, the first allocation principle including a polling or priority principle; and a channel multiplexer configured to electrically couple a logical channel selected from the at least one logical channel to the idle physical channel.

[0012] In one implementation of the first aspect, the bus selection module includes: a bus arbiter configured to, in response to a bus read / write request initiated by a bound physical channel among the plurality of physical channels, authorize the selected physical channel to access the bus according to a second allocation principle, the second allocation principle including a polling or priority principle; and a bus multiplexer configured to electrically couple the authorized selected physical channel to the bus.

[0013] In one implementation of the first aspect, each of the plurality of logical channels includes a first configuration register, a first control module, and a DMA request interface; the first configuration register includes configuration units for channel enable / reset, binding status and priority, descriptor address, transfer command, and interrupt status; the first control module includes a DMA transfer progress control unit and a first DMA error handling unit.

[0014] In this implementation, the logical channel removes the data transmission function and no longer directly accesses the bus interface module; the bus interface module is accessed by a smaller number of physical channels, thereby reducing the size of the bus arbiter and bus multiplexer.

[0015] In one implementation of the first aspect, each of the plurality of physical channels includes a second configuration register, a second control module, a data buffer, a data processing module, and a bus request interface; the second configuration register includes configuration units for channel enable / reset, binding status, descriptor address, and data transmission parameters; the second control module includes a descriptor and data transmission control unit and a second DMA error handling unit; the data buffer is configured for temporary data storage; the data processing module is configured for data packing and unpacking operations; and the bus request interface is configured to generate bus read / write requests for the physical channels.

[0016] In one implementation of the first aspect, the plurality of physical channels are further configured to: in response to the selected physical channel interacting with the bus to complete the data transmission, initiate a channel release for the selected physical channel to enter an idle state.

[0017] In one implementation of the first aspect, the plurality of logical channels are further configured such that, in response to the selected physical channel interacting with the bus to complete the data transmission, the selected logical channel receives another transmission request.

[0018] In one implementation of the first aspect, the bus interface module is configured to cache read / write request information, read / write data information, and read / write response information through a data buffer.

[0019] In one implementation of the first aspect, the channel selection module is configured to bind the selected logical channel to the idle physical channel through dynamic binding or static binding. Dynamic binding refers to applying for and allocating a corresponding physical channel according to the received transmission request, while static binding refers to binding a physical channel to a logical channel through a software register. Transmission requests received on the logical channel are immediately executed through the statically bound physical channel.

[0020] In this implementation, dynamic binding and static binding are used to balance the requirements of increasing the number of channels and limiting the channel area, while also taking into account data transmission scenarios with high real-time requirements.

[0021] A second aspect of this application provides a DMA control method. The method includes: receiving a DMA request from a logical channel; initiating a channel allocation request to a channel selection module from the logical channel to request a physical channel; binding the physical channel to the logical channel that initiated the channel allocation request from the channel selection module; initiating a bus read / write request to a bus selection module from the bound physical channel to access the bus; and authorizing the access to the bus from the physical channel that initiated the bus read / write request from the bus selection module, such that the authorized physical channel performs data transmission based on the DMA request.

[0022] A third aspect of this application provides a chip. The chip includes the DMA control device described above.

[0023] In the DMA control device, method, and chip described in this application, the logical channel area is reduced, and its number can be configured according to the number of low-speed peripherals. Furthermore, the physical channels are performance-dependent, and their number can be configured according to performance requirements. There is no constraint on the number of either, allowing for flexible configuration to adapt to systems with a large number of low-speed peripherals and high performance requirements, while simultaneously reducing chip area and power consumption, and lowering software and hardware complexity. In this application, the logical channels have removed data transmission functionality and no longer directly access the bus interface module. The bus interface module is accessed by a smaller number of physical channels, thereby reducing the size of the bus arbiter and bus multiplexer. Through dynamic and static binding, the requirements of increasing the number of channels and limiting channel area are balanced, while also considering data transmission scenarios with high real-time requirements. Attached Figure Description

[0024] Figure 1 This diagram shows the interconnection structure between DMA and peripherals in a SoC system.

[0025] Figure 2 The diagram shown is a schematic diagram of the DMA control device described in an embodiment of this application.

[0026] Figure 3 The diagram shown is a control structure diagram of the DMA control device described in the embodiments of this application.

[0027] Figure 4 The diagram shown is a schematic diagram illustrating the channel splitting principle of the DMA control device described in the embodiments of this application.

[0028] Figure 5The diagram shown is a structural diagram of the channel selection module of the DMA control device described in the embodiments of this application.

[0029] Figure 6 The diagram shown is a structural diagram of the bus selection module based on a read operation in the DMA control device described in this application embodiment.

[0030] Figure 7 The diagram shown is a structural diagram of the bus selection module based on write operation of the DMA control device described in the embodiments of this application.

[0031] Figure 8 This is a flowchart illustrating the operation of the DMA control device described in an embodiment of this application.

[0032] Figure 9 The diagram shown is a timing diagram of the DMA control device described in the embodiments of this application.

[0033] Figure 10 The diagram shown is a flowchart illustrating the principle of the DMA control method described in the embodiments of this application.

[0034] Figure 11 The diagram shown is a schematic representation of the structure and principle of the chip described in the embodiments of this application. Detailed Implementation

[0035] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] A DMA channel can include configuration registers, a DMA request interface, a control module, a data processing module, a data buffer, and a bus request interface. The configuration registers include descriptor addresses, transfer commands, interrupt status, and data transfer parameters. The DMA request interface handles peripheral DMA requests. The control module controls descriptor and data transfer, and handles DMA errors. The data processing module performs format conversion based on the bus data format and the data width of the internal buffer, and reads and writes to the data buffer. The data buffer temporarily stores source address data returned by the bus. The bus request interface generates channel bus read / write requests.

[0038] The data transfer process of a DMA channel can be divided into two stages: instruction fetch and data transfer. The instruction fetch process involves reading a memory descriptor to obtain the source address, destination address, data length, and transfer mode. The DMA channel then updates its internal registers and control module to initiate the data transfer process. The data transfer process involves the DMA channel reading data from the source address in the specified transfer mode, processing it in the data processing module, and temporarily storing it in the data buffer. The data is then output from the data buffer, processed by the data processing module, and written to the destination address in the specified transfer mode. If there are still descriptors to process, the above process is repeated.

[0039] In the DMA control device of this application, the DMA channel is divided into two parts: a logical channel and a physical channel. These two parts interact indirectly through a channel arbitrator and a channel multiplexer. The logical channel is responsible for receiving low-speed peripheral transmission requests and software transmission requests, and after a transmission request is valid, it requests the allocation of a physical channel from the channel arbitrator. After authorization, the physical channel binds to the logical channel, and the physical channel begins data transmission. The physical channel initiates read / write requests to the bus arbitrator and interacts with the bus interface module to complete the data transmission. Afterward, the physical channel initiates channel release and enters an idle state. If the low-speed peripheral or software still has transmission needs, the above process is repeated. If multiple logical channels initiate transmission requests simultaneously, the channel arbitrator allocates physical channels sequentially according to the allocation principle. If multiple physical channels initiate bus read / write requests simultaneously, the bus arbitrator authorizes the physical channels to access the bus interface module sequentially according to the allocation principle.

[0040] The terms "logical channel" and "physical channel" in this application are not merely literal terms. In existing technologies, logical channels and physical channels can respectively respond to software-scheduled transfer requests and internal engine transfer requests. The use of the terms "logical" and "physical" is to distinguish the origin of the transfer request, or in other words, whether software scheduling is involved. Furthermore, in existing technologies, both logical and physical channels are complete DMA channels, meaning they both include configuration registers, DMA request interfaces, control modules, data processing modules, data buffers, and bus request interfaces. In contrast, this application splits the complete DMA channel into logical channels and physical channels, each containing some functional modules of the original DMA channel. The specific structures of both will be described below.

[0041] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] Figure 2 The diagram shown is a schematic diagram of the DMA control device described in an embodiment of this application. Figure 2 As shown, this embodiment provides a DMA control device 2, which includes: multiple logical channels 21, a channel selection module 22, multiple physical channels 23 and a bus selection module 24.

[0043] The plurality of logical channels 21 are each configured to receive transmission requests. In some embodiments, the transmission requests include low-speed peripheral transmission requests and software transmission requests.

[0044] In some embodiments, a portion of the logical channels are used for dynamic binding. In this case, these logical channels are configured to receive transmission requests and are flexibly bound to physical channels. Additionally, another portion of the logical channels are used for static binding, primarily for data transmission requests with high real-time requirements. This involves pre-binding a logical channel to a physical channel to execute such data transmission requests at any time.

[0045] The channel selection module 22 is electrically coupled between the plurality of logical channels and the plurality of physical channels, and is configured to bind a logical channel selected from the plurality of logical channels to an idle physical channel among the plurality of physical channels.

[0046] The plurality of physical channels 23 are respectively configured to perform data transmission based on the transmission request.

[0047] The bus selection module 24 is electrically coupled between the plurality of physical channels and the bus, and is configured to allow a selected physical channel from the plurality of physical channels to access the bus to perform the data transmission.

[0048] In one embodiment, the plurality of logical channels 21 are further configured to send a channel allocation request to the channel selection module 22 based on the transmission request. The channel selection module 22 is configured to select a logical channel from the plurality of logical channels 21 at a certain time based on the channel allocation request, and allocate any idle physical channels from the plurality of physical channels 23 to the selected logical channel.

[0049] In one embodiment, the plurality of physical channels 23 are further configured to send bus read / write requests to the bus selection module 24 based on the transmission request. The bus selection module 24 is configured to select one physical channel from the plurality of physical channels 23 at a certain time based on the bus read / write request, so as to allow the selected physical channel to perform data reading or data writing on the bus.

[0050] In one embodiment, the number of the plurality of logical channels 21 and the number of the plurality of physical channels 23 are set independently of each other.

[0051] According to embodiments of this application, by separately setting logical channels and physical channels, the area of ​​the logical channels is reduced, allowing their number to be configured according to the number of low-speed peripherals. Furthermore, the number of physical channels is performance-dependent and can be configured according to performance requirements. This approach adapts to systems with a large number of low-speed peripherals and high performance requirements, while simultaneously reducing chip area and power consumption, and lowering software and hardware complexity. In addition, data transmission functionality is removed from the logical channels, eliminating bus access; the bus is accessed by a smaller number of physical channels, thus reducing the size of the bus arbiter and bus multiplexer. Moreover, through dynamic and static binding, the requirements of increasing the number of channels and limiting channel area are balanced, while also considering data transmission scenarios with high real-time requirements.

[0052] Figure 3 The diagram shown is a control structure diagram of the DMA control device described in an embodiment of this application. Figure 3 As shown, in one embodiment, the DMA control device further includes a bus interface module 25. The bus interface module 25 is electrically coupled between the bus selection module 24 and the bus, and is configured to electrically couple the selected physical channel to the bus via a bus read interface or a bus write interface.

[0053] In one embodiment, the bus interface module 25 is configured to cache read / write request information, read / write data information, and read / write response information using a data buffer. Specifically, the bus interface module 25 interfaces with multiple physical channels on one side and with the system bus on the other, for accessing low-speed peripherals and memory. Internally, the bus interface module 25 uses a FIFO (First In First Out) data buffer to cache read / write request information, read / write data information, and read / write response information. Data is first read from the source address into the internal read data FIFO of the bus interface module, then temporarily stored in the physical channel data buffer, then output from the buffer to the internal write data FIFO of the bus interface module, and finally transmitted to the destination address.

[0054] In some embodiments, the channel selection module 22 includes a channel arbitrator 221 and a channel multiplexer 222.

[0055] The channel arbitrator 221 is configured to allocate the idle physical channel to the at least one logical channel in response to a channel allocation request initiated by at least one of the plurality of logical channels 21, according to a first allocation principle, the first allocation principle including a round-robin or priority principle.

[0056] The channel multiplexer 222 is configured to electrically couple a selected logical channel from the at least one logical channel to the idle physical channel.

[0057] In the embodiments of this application, the channel arbitrator 221 is responsible for allocating physical channels to logical channels based on logical channel request information. The allocation principle can be based on round-robin or priority. The channel arbitrator 221 selects one from multiple logical channel requests and one from multiple idle physical channels, and binds the two together. Which physical channel a logical channel is specifically bound to is determined by the logical channel priority and the hardware. When there are no idle physical channels, the channel arbitrator 221 stops the allocation work.

[0058] Therefore, the channel arbiter 221 and the channel multiplexer 222 separate multiple logical channels 21 from multiple physical channels 23. The number of the two is no longer dependent. The number of logical channels can be configured according to the number of low-speed peripherals, and the number of physical channels can be configured according to performance requirements, so that both chip area and performance can be guaranteed.

[0059] Please continue reading. Figure 3 In some embodiments, the bus selection module 24 includes a bus arbiter 241 and a bus multiplexer 242. Operation requests may include bus read / write requests.

[0060] The bus arbiter 241 is configured to, in response to a bus read / write request initiated by a bound physical channel among the plurality of physical channels, authorize the selected physical channel to access the bus according to a second allocation principle, which includes a polling or priority principle.

[0061] The bus multiplexer 242 is configured to electrically couple the authorized selected physical channel to the bus.

[0062] In this embodiment, the logical channel descriptor address is sent to the physical channel during the channel binding phase. The physical channel reads, parses, and writes back the descriptor, avoiding the implementation method of multiplexing transmission request information from all logical channels, thus reducing the size of the channel multiplexer. Here, the logical channel descriptor address can be aligned to a larger address boundary to reduce the descriptor address width. The transmission request information of the logical channel includes the data transmission source address, destination address, data length, and transmission mode, resulting in a relatively large total signal bit width.

[0063] Furthermore, in one embodiment, the plurality of physical channels are further configured to: in response to the selected physical channel completing the data transmission through interaction with the bus, initiate a channel release for the selected physical channel to enter an idle state. Additionally, in another embodiment, the plurality of logical channels are further configured to: in response to the selected physical channel completing the data transmission through interaction with the bus, the selected logical channel receives another transmission request.

[0064] Figure 4 This diagram illustrates the channel splitting principle of the DMA control device described in an embodiment of this application. Figure 4 As shown, in one embodiment, the plurality of logical channels 21 include a first configuration register 211, a DMA request interface 212, and a first control module 213.

[0065] The first configuration register 211 includes configuration units for channel enable reset, binding status and priority, descriptor address, transmission command and interrupt status.

[0066] Therefore, compared to traditional DMA channels, the logical channel in this application eliminates the data transmission parameter register, thus no longer accessing the bus interface module; the bus interface module is accessed by a smaller number of physical channels, reducing the size of the bus arbiter and bus multiplexer. The data transmission parameter register specifically includes the data source address, data destination address, data length, and data transfer mode.

[0067] The first control module 213 includes a DMA transfer progress control unit and a first DMA error handling unit. Therefore, compared to a conventional DMA channel, the first control module of this application eliminates the need for descriptors and data transfer control.

[0068] Please continue reading. Figure 4 In one embodiment, the physical channel 23 includes a second configuration register 231, a second control module 232, a data processing module 233, a data buffer 234, and a bus request interface 235.

[0069] The second configuration register 231 includes configuration units for channel enable reset, binding status, descriptor address, and data transmission parameters.

[0070] Specifically, the configuration unit for data transmission parameters refers to the parameter register for data transmission, which includes the data source address, data destination address, data length, and data transmission mode. Compared with traditional DMA channels, the second configuration register in this application removes the transmission command, priority, and interrupt status registers.

[0071] The second control module 232 includes a descriptor and data transmission control unit and a second DMA error handling unit. Therefore, compared to a conventional DMA channel, the second control module of this application eliminates DMA transfer progress control.

[0072] The data buffer 234 is configured for temporary data storage. Specifically, the physical channel's bus request interface initiates a read request, and after the data is returned, it is processed by the data processing module and stored in the data buffer. Then, the data is output from the data buffer, processed by the data processing module, and written to the destination address via the bus. Here, the data width of the data buffer can be different from the data width of the read / write request, and the format conversion is handled by the data processing module.

[0073] The data processing module 233 is configured to perform data packing and unpacking operations. Specifically, data packing is responsible for converting the format of the data returned from the bus according to the bus format of the data read and the data width of the data buffer, and storing it in the internal buffer as a continuous byte stream; data unpacking is responsible for reading data from the internal buffer and converting the format according to the data width of the internal buffer and the bus format of the data output.

[0074] The bus request interface 235 is configured to generate a physical channel operation request, which is sent to the bus interface module via the bus selection module.

[0075] Therefore, the traditional DMA channel is split into two parts: a logical channel and a physical channel. The logical channel is responsible for handling DMA requests, DMA transfer progress control, and DMA error handling, while the physical channel is responsible for descriptor and data transfer control, data processing and data temporary storage, and DMA error handling. The former has a small area and its number can be configured according to the number of low-speed peripherals; the latter has a large area and its number can be configured according to performance requirements.

[0076] Figure 5 This diagram shows the channel selection module structure of the DMA control device described in an embodiment of this application. Figure 5 As shown, the input signals include m logical channel request information and n physical channel idle status signals, and the output signals include m logical channel authorization signals, n physical channel authorization signals, logical channel index signals, and physical channel index signals. Here, the logical channel request information includes channel binding request signals, peripheral request types, and descriptor addresses.

[0077] Figure 6 The diagram shown is a structural diagram of the bus selection module based on a read operation in the DMA control device described in an embodiment of this application. Figure 6 As shown, for a read request, the bus arbiter selects one from multiple physical channel read request messages, generates a selection signal for the bus multiplexer, and instructs it to access the bus read interface. The physical channel read request message includes the read request, read address, and read mode.

[0078] Figure 7 The diagram shown is a structural diagram of the bus selection module based on a write operation in the DMA control device described in an embodiment of this application. Figure 7 As shown, for a write request, the bus arbiter selects one from multiple physical channel write request messages, generates a selection signal for the bus multiplexer, and instructs it to access the bus write interface. The physical channel write request message includes the write request, write address, and write mode.

[0079] Figure 8 This diagram illustrates the workflow of the DMA control device described in an embodiment of this application. Specifically, the DMA control device refers to a DMA controller having the device structure described in this application. Figure 8 As shown, the working process of the DMA control device is as follows.

[0080] In step S81, the software configures the low-speed peripherals and DMA controller.

[0081] In step S82, the low-speed peripheral or software initiates a DMA request to the DMA controller.

[0082] In step S83, the logical channel requests a physical channel from the channel arbitrator.

[0083] In step S84, the logical channel is bound to the physical channel.

[0084] In step S85, the physical channel performs data transmission.

[0085] In step S86, after data transmission is complete, the physical channel initiates channel release and enters an idle state.

[0086] In step S87, it is determined whether the low-speed peripheral or software still has data transmission requirements, i.e., a DMA request. If yes, return to step S82; otherwise, complete the DMA control process.

[0087] Figure 9 The diagram shown is a timing diagram of the DMA control device described in an embodiment of this application. Figure 9 As shown, a timing diagram is presented using four logical channels and two physical channels as an example.

[0088] The four logical channels are: LCH_REQ[0] - logical channel 0, LCH_REQ[1] - logical channel 1, LCH_REQ[2] - logical channel 2, and LCH_REQ[3] - logical channel 3.

[0089] The authorization signals corresponding to the four logical channels are: LCH_GNT[0] - authorization signal for logical channel 0, LCH_GNT[1] - authorization signal for logical channel 1, LCH_GNT[2] - authorization signal for logical channel 2, and LCH_GNT[3] - authorization signal for logical channel 3.

[0090] The logical channel index is LCH_IDX_GNT.

[0091] The two physical channels include PCH_AVAIL[0] - physical channel 0 and PCH_AVAIL[1] - physical channel 1.

[0092] The authorization signals corresponding to the two physical channels include PCH_GNT[0] - authorization signal for physical channel 0 and PCH_GNT[1] - authorization signal for physical channel 1. The physical channel index is PCH_IDX_GNT.

[0093] The status of each channel at different times is as follows:

[0094] T0: No requests have been initiated for any logical channels, and all physical channels are in an idle state;

[0095] T1: Logical channel 0 initiates an application;

[0096] T2: Physical channel 0 is assigned to logical channel 0 and is no longer idle; at the same time, the authorization signals for logical channel 0 and physical channel 0 become valid, and the logical channel and physical channel indices are 0 and 0, respectively.

[0097] T3: Logical channel 1 initiates a request;

[0098] T4: Physical channel 1 is assigned to logical channel 1 and is no longer idle; at the same time, the authorization signals for logical channel 1 and physical channel 1 become valid, and the logical channel and physical channel indices are 1 and 1 respectively; all physical channels are in a busy state.

[0099] T5: Logical channel 2 initiates a request. At this time, there is no free physical channel, and the request signal remains valid.

[0100] T6: There is still no free physical channel, and the request signal for logical channel 2 remains valid.

[0101] T7: Logical channel 3 initiates a request. At this time, there is no free physical channel, and the request signal remains valid.

[0102] T10: Physical channel 0 enters idle state;

[0103] T11: Physical channel 0 is assigned to logical channel 2 and is no longer idle; at the same time, the authorization signals for logical channel 2 and physical channel 0 become valid, and the logical channel and physical channel indices are 2 and 0 respectively; all physical channels are in a busy state.

[0104] T12: Physical channel 1 enters idle state;

[0105] T13: Physical channel 1 is assigned to logical channel 3 and is no longer idle; at the same time, the authorization signals for logical channel 3 and physical channel 1 become valid, and the logical channel and physical channel indices are 3 and 1 respectively; all physical channels are in a busy state.

[0106] T16: Physical channel 0 enters idle state;

[0107] T18: Physical channel 1 enters idle state;

[0108] T19: No requests have been initiated for any logical channels, and all physical channels are idle.

[0109] In some embodiments, when there are few physical channels, some logical channels cannot immediately request physical channels, and their data transmission requests cannot be executed immediately, affecting real-time performance. Therefore, in addition to dynamic binding, this application can also implement static binding.

[0110] In one embodiment, the channel selection module is configured to bind the selected logical channel to the idle physical channel via dynamic binding or static binding. Dynamic binding refers to requesting and allocating a corresponding physical channel based on a received transmission request. Static binding refers to binding a physical channel to a logical channel via a software register, whereby transmission requests received on the logical channel are immediately executed through the statically bound physical channel.

[0111] Furthermore, physical and logical channels involved in static binding no longer participate in dynamic hardware binding. Static-bound logical channels do not need to request a physical channel from the channel arbitrator; their data transmission requests can be immediately executed by the statically bound physical channel. This is suitable for data transmission scenarios with high real-time requirements.

[0112] Figure 10 The diagram shown illustrates the principle flowchart of the DMA control method described in this application embodiment. Figure 10 As shown, the DMA control method provided in this embodiment specifically includes the following steps S11 to S15.

[0113] In step S11, a DMA request is received by the logical channel.

[0114] In step S12, the logical channel initiates a channel allocation request to the channel selection module to apply for a physical channel.

[0115] In step S13, the channel selection module binds the physical channel to the logical channel that initiated the channel allocation request.

[0116] In step S14, the bound physical channel initiates a bus read / write request to the bus selection module to access the bus.

[0117] In step S15, the bus selection module authorizes access to the bus for the physical channel that initiated the bus read / write request, so that the authorized physical channel performs data transmission based on the DMA request.

[0118] The scope of protection of the DMA control method described in this application is not limited to the execution order of the steps listed in this application. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the scope of protection of this application.

[0119] The DMA control device described in the embodiments of this application can implement the DMA control method described in this application. However, the implementation device of the DMA control method described in this application includes, but is not limited to, the structure of the DMA control device listed in this embodiment. All structural modifications and substitutions of the prior art made based on the principles of this application are included within the protection scope of this application.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed apparatus or method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0121] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0122] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0123] Figure 11 The diagram shown is a schematic representation of the structure and principle of the chip described in an embodiment of this application. Figure 11 As shown, the chip described in this embodiment includes the DMA control device described above.

[0124] In the chip, multiple logical channels are configured to receive transmission requests; multiple physical channels are configured to perform data transmission based on the transmission requests; a channel selection module is electrically coupled between the multiple logical channels and the multiple physical channels, and is configured to bind a selected logical channel among the multiple logical channels to an idle physical channel among the multiple physical channels; a bus selection module is electrically coupled between the multiple physical channels and a bus, and is configured to enable a selected physical channel among the multiple physical channels to access the bus to perform the data transmission.

[0125] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0126] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A DMA control device, characterized in that, include: Multiple logical channels are configured to receive transmission requests. Each logical channel includes a first configuration register, a first control module, and a DMA request interface. The number of logical channels is configured according to the number of low-speed peripherals. The parameter register for data transmission is removed from the logical channels. The first control module is free of descriptors and data transmission control. The logical channels are responsible for handling DMA requests, DMA transmission progress control, and DMA error handling. Multiple physical channels are configured to perform data transmission based on the transmission request. Each physical channel includes a second configuration register, a second control module, a data buffer, a data processing module, and a bus request interface. The number of physical channels is configured according to performance requirements. The second control module removes DMA transmission progress control. The physical channels are responsible for descriptor and data transmission control, data processing, data temporary storage, and DMA error handling. A channel selection module is electrically coupled between the plurality of logical channels and the plurality of physical channels, and is configured to dynamically or statically bind a logical channel selected from the plurality of logical channels to an idle physical channel among the plurality of physical channels. The descriptor address of the logical channel is sent to the physical channel during the channel binding phase, and the physical channel reads, parses, and writes the descriptor back. as well as A bus selection module is electrically coupled between the plurality of physical channels and the bus, and is configured to cause a physical channel selected from the plurality of physical channels to access the bus to perform the data transmission; The channel selection module includes: A channel arbitrator is configured to, in response to a channel allocation request initiated by at least one of the plurality of logical channels, allocate the idle physical channel to the at least one logical channel according to a first allocation principle, the first allocation principle including a round-robin or priority principle; and A channel multiplexer is configured to electrically couple a selected logical channel from the at least one logical channel to the idle physical channel.

2. The apparatus according to claim 1, characterized in that, The plurality of logical channels are further configured to send a channel allocation request to the channel selection module based on the transmission request. The channel selection module is configured to select a logical channel from the plurality of logical channels at a certain time based on the channel allocation request, and allocate an idle physical channel from the plurality of physical channels to the selected logical channel.

3. The apparatus according to claim 1, characterized in that, The plurality of physical channels are further configured to send bus read / write requests to the bus selection module based on the transmission request. The bus selection module is configured to select a physical channel from the plurality of physical channels at a certain time based on the bus read / write request, so as to allow the selected physical channel to perform data read or data write for the bus.

4. The apparatus according to claim 1, characterized in that, The number of the plurality of logical channels and the number of the plurality of physical channels are set independently of each other.

5. The apparatus according to claim 1, characterized in that, Also includes: A bus interface module is electrically coupled between the bus selection module and the bus, and is configured to electrically couple the selected physical channel to the bus via a bus read interface or a bus write interface.

6. The apparatus according to claim 1, characterized in that, The bus selection module includes: A bus arbiter, configured to, in response to a bus read / write request initiated by a bound physical channel among the plurality of physical channels, authorize access to the bus by the selected physical channel according to a second allocation principle, the second allocation principle including a round-robin or priority principle; and A bus multiplexer is configured to electrically couple the authorized selected physical channel to the bus.

7. The apparatus according to claim 1, characterized in that, The first configuration register includes configuration units for channel enable reset, binding status and priority, descriptor address, transmission command and interrupt status; The first control module includes a DMA transfer progress control unit and a first DMA error handling unit.

8. The apparatus according to claim 1, characterized in that, The second configuration register includes configuration units for channel enable reset, binding status, descriptor address, and data transfer parameters; The second control module includes a descriptor and data transmission control unit and a second DMA error handling unit; The data buffer is configured to temporarily store data. The data processing module is configured to perform data packaging and unpacking operations; The bus request interface is configured to generate bus read / write requests for physical channels.

9. The apparatus according to claim 1, characterized in that, The plurality of physical channels are further configured as follows: In response to the selected physical channel interacting with the bus to complete the data transmission, a channel release is initiated for the selected physical channel to enter an idle state.

10. The apparatus according to claim 1, characterized in that, The plurality of logical channels are further configured as follows: In response to the selected physical channel interacting with the bus to complete the data transmission, the selected logical channel receives another transmission request.

11. The apparatus according to claim 5, characterized in that, The bus interface module is configured as follows: The read / write request information, read / write data information, and read / write response information are cached using a data buffer.

12. The apparatus according to claim 1, characterized in that: The dynamic binding refers to requesting and allocating the corresponding physical channel based on the received transmission request; The static binding refers to binding a physical channel to a logical channel through a software register, so that the transmission request received on the logical channel is immediately executed through the statically bound physical channel.

13. A DMA control method, characterized in that, The DMA control device according to any one of claims 1 to 12; comprising: DMA requests are received via a logical channel; The logical channel initiates a channel allocation request to the channel selection module to apply for a physical channel; The channel selection module binds the physical channel to the logical channel that initiated the channel allocation request; The bound physical channel initiates a bus read / write request to the bus selection module to access the bus; and The bus selection module authorizes access to the bus for the physical channel that initiates the bus read / write request, so that the authorized physical channel performs data transmission based on the DMA request.

14. A chip, characterized in that, include: The DMA control device according to any one of claims 1 to 12.

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