An apparatus for implementing direct memory access quick transfer and a method thereof
By introducing a request arbitration module, a transfer control module, and an interrupt control module into the DMA controller, the process of reading and writing data and sending acknowledgment signals is optimized, solving the problem of low efficiency of the DMA controller and realizing fast memory access and efficient transfer.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN MEGA HUNT ELECTRONICS TECH CO LTD
- Filing Date
- 2022-12-16
- Publication Date
- 2026-07-31
AI Technical Summary
Existing DMA controllers require waiting for data transfer to complete before issuing a termination signal in the clearing method requested by external devices, resulting in low efficiency. Furthermore, existing DMA data transfer methods are complex to implement and have high hardware development costs.
By employing a request arbitration module, a transmission control module, a configuration register, and an interrupt control module, and by independently performing request priority arbitration, data reading, and data writing within the same time sequence, the process of sending confirmation signals and writing data is optimized, thereby achieving fast transmission of direct memory access.
It improves the speed of request and arbitration processing, realizes fast transmission of direct memory access, and achieves a transmission efficiency of 100% of the bus transmission efficiency. It is suitable for source address to destination address transmission of clocks with the same frequency or divided frequency.
Smart Images
Figure CN116303174B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an apparatus for achieving fast transfer of data via direct memory access, and also to a method for achieving fast transfer of data via direct memory access, belonging to the field of memory management technology. Background Technology
[0002] Direct Memory Access (DMA) is primarily used to reduce the dependence of external devices on the CPU in a System-on-Chip (SoC) system, thereby improving the internal data transfer efficiency of the computer system. By using a DMA controller, data can be automatically transferred between memory and external devices, between external devices, and between memory and memory. As SoC systems continue to upgrade and their operating frequencies increase, the internal transfer speeds achieved by DMA technology must also continue to improve.
[0003] Chinese patent application CN114168504A discloses a multi-channel DMA controller based on the AHB-Lite bus. This multi-channel DMA controller includes a Master module, a channel control module, an arbitration module, a response module, a Slave module, a channel request module, and a handshake module. The Master module generates control signals for the corresponding AHB-Lite protocol and simultaneously reads data from an external source device or writes data to a destination device. However, in its method of clearing requests from external devices, this multi-channel DMA controller clears the request only after the data transfer is complete. That is, it needs to wait until the entire external device-memory module or memory-external device module data transfer is finished before issuing a termination signal, thus there is still room for improvement in terms of efficiency.
[0004] Furthermore, Chinese patent application CN114328320A discloses a DMA data transfer method. Based on DMA data send commands, it alternately writes data from a first device to a pre-divided first buffer and a second buffer to send the data from the first device to a second device; based on DMA data receive commands, it alternately reads the data from the pre-divided first and second buffers to receive the data from the second device. This DMA data transfer method utilizes two buffers to improve DMA efficiency, but its implementation is complex and its hardware development costs are high. Summary of the Invention
[0005] The primary technical problem to be solved by this invention is to provide a device for realizing fast transfer of direct memory access.
[0006] Another technical problem to be solved by the present invention is to provide a method for achieving fast transfer of data via direct memory access.
[0007] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:
[0008] According to a first aspect of the present invention, an apparatus for implementing fast transfer of direct memory access is provided, comprising an arbitration request module, a transfer control module, a configuration register, and an interrupt control module; wherein,
[0009] The request arbitration module receives a request signal sent to it by an external device, an arbitration enable signal and an acknowledgment enable signal sent to it by the transmission control module, and a configuration signal sent to it by the configuration register. It sends channel configuration information and a transmission end signal to the transmission control module, sends a transmission completion signal or a transmission half signal to the interrupt control module, and sends an acknowledgment signal to the external device.
[0010] The transmission control module receives the transmission status signal sent by the Advanced High Performance Bus (AHHBO) and sends read / write signals to the AHHBO.
[0011] The configuration register receives read / write signals from the high-performance bus sent by the CPU, and sends interrupt enable and clear signals to the interrupt control module.
[0012] The interrupt control module sends status signals to external devices.
[0013] Preferably, the request arbitration module includes a request priority arbitration unit, a timing control unit, a response control unit, a multiplexer, and a transmission counter; wherein, the request priority arbitration unit receives a request signal sent by an external device and an arbitration enable signal sent by the timing control unit, sends the arbitration result to the multiplexer, and sends the level state of the request signal to the response control unit; the timing control unit receives an arbitration enable signal and a response enable signal sent by the read / write control state machine, and sends a response enable signal to the response control unit; the response control unit receives the idle / busy status signal of the high-performance bus and sends an acknowledgment signal to the external device.
[0014] Preferably, the multiplexer sends the selected channel configuration information to the read / write control state machine and the transmission quantity information to the transmission counter; the transmission counter sends a transmission end signal to the read / write state machine and a transmission completion signal or a transmission half signal to the interrupt control module.
[0015] Preferably, the transmission control module includes an advanced high-performance bus control unit, a read / write control state machine, and an error handling unit; wherein the read / write control state machine sends a read / write enable signal to the advanced high-performance bus control unit and a read / write status signal to the error handling unit.
[0016] Preferably, the error handling unit receives the transmission status information and arbitration result information of the high-performance bus and sends an error alarm signal to the interrupt control module.
[0017] According to a second aspect of the present invention, a method for implementing fast transfer via direct memory access is provided, comprising the following steps:
[0018] S1: In the timing control unit of the arbitration request module, set its working timing so that when the timing is for reading data, the arbitration enable signal is enabled to the priority arbitration request unit; when the timing is for writing data, the response enable signal is enabled to the response control unit.
[0019] S2: Configure the registers of the DMA controller channel where the external device is located;
[0020] S3: Enables access to external devices;
[0021] S4: The external device sends a request signal to the arbitration request module;
[0022] S5: The request priority arbitration unit in the request arbitration module receives the request signal and performs arbitration;
[0023] S6: The priority arbitration unit requests the transmission control module to send channel configuration information based on the arbitration result;
[0024] S7: After receiving the channel configuration information, the read / write control state machine in the transmission control module enables read / write to the high-performance bus control, reads and writes data, and at the same time enables the arbitration enable signal and the response enable signal to the timing control unit in the request arbitration module.
[0025] S8: The timing control unit sends an arbitration enable signal or a response enable signal to the request priority arbitration unit or the response control unit according to the current timing.
[0026] S9: The external device receives the confirmation signal sent by the request arbitration module and clears the request signal that has been executed in step S5;
[0027] S10: Determine whether the external device should continue sending request signals. If yes, the transmission control module continues to read and write data to the external device; if no, proceed to step S11.
[0028] S11: End data transmission and send an end signal to the CPU.
[0029] Preferably, in step S1, the priority arbitration request is performed in the priority arbitration request unit, and the data reading is performed in the read / write control state machine in the transmission control module. The two tasks are performed independently within the same time sequence.
[0030] Preferably, in step S1, the sending of the confirmation signal is carried out in the response control unit, and the writing of data is carried out in the read / write control state machine in the transmission control module. The two tasks are performed independently within the same time sequence.
[0031] Preferably, in step S8, when the timing is for reading data, the timing control unit enables the arbitration signal to the request priority arbitration unit; when the timing is for writing data, the timing control unit enables the response signal to the response control unit.
[0032] Preferably, in step S10, after the external device module waits for a predetermined period of confirmation signal from the request arbitration module, it determines whether it needs to continue sending request signals to the request arbitration module based on the continued sending request signals from the external device. If the external device's sending request signal is high, it continues to send request signals to the request arbitration module, and the transmission control module continues to read and write data to the external device. If the external device's sending request signal is low, it no longer sends request signals to the request arbitration module and proceeds to step S11.
[0033] Compared with the prior art, the apparatus and method for realizing fast transmission of direct memory access provided by the present invention optimizes the work that needs to be run in different time sequences in the prior art, such as request priority arbitration and data reading, confirmation signal sending and data writing, into independent operations in the same time sequence, thereby effectively improving the processing speed of requests and arbitration, and realizing fast transmission of direct memory access. Attached Figure Description
[0034] Figure 1(a) is a simplified structural diagram of the device for implementing fast transfer of direct memory access provided in an embodiment of the present invention;
[0035] Figure 1(b) is a detailed internal structure diagram of the request arbitration module and configuration register in the apparatus for implementing fast transfer of direct memory access provided in an embodiment of the present invention;
[0036] Figure 1(c) is a detailed internal structure diagram of the transmission control module and the interrupt control module in the apparatus for implementing fast transmission of direct memory access provided in an embodiment of the present invention.
[0037] Figure 2 A flowchart illustrating a method for implementing fast transfer via direct memory access, provided in an embodiment of the present invention.
[0038] Figure 3 This is a timing diagram illustrating the operation of fast transfer via direct memory access in an embodiment of the present invention. Detailed Implementation
[0039] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0040] like Figures 1(a) to 1(c) As shown in Figure 1(b), this invention first discloses a device (DMA controller) for implementing fast direct memory access transfer. This device includes at least a request arbitration module, a transfer control module, a configuration register, and an interrupt control module. As shown in Figure 1(b), the request arbitration module receives request (REQ) signals from external devices, receives arbitration enable and acknowledgment enable signals from the transfer control module, receives configuration signals from the configuration register, sends channel configuration information and a transfer end signal to the transfer control module, sends a transfer completion signal or a transfer half-finish signal to the interrupt control module, and sends an acknowledgment (ACK) signal to the external device. The transfer control module receives transfer status signals from the Advanced High Performance Bus (AHB), sends read / write signals to the AHB, and sends error alarm signals to the interrupt control module. The configuration register receives read / write signals from the AHB sent by the CPU and sends interrupt enable and clear signals to the interrupt control module. The interrupt control module sends status signals to external devices.
[0041] In one embodiment of the present invention, the request arbitration module includes a request priority arbitration unit, a timing control unit, a response control unit, a multiplexer, and a transmission counter. The request priority arbitration unit receives a request signal from an external device and an arbitration enable signal from the timing control unit, sends the arbitration result to the multiplexer, and sends the level status of the request signal to the response control unit. The timing control unit receives the arbitration enable signal and the response enable signal from the read / write control state machine, and sends the response enable signal to the response control unit. The response control unit receives the idle / busy status signal from the high-performance bus and sends an acknowledgment signal to the external device; the multiplexer sends the selected channel configuration information to the read / write control state machine and the transmission quantity information to the transmission counter; the transmission counter sends a transmission end signal to the read / write state machine and a transmission completion signal or a transmission half-finish signal to the interrupt control module.
[0042] In one embodiment of the present invention, the transmission control module includes an Advanced High Performance Bus (AHS) control unit, a read / write control state machine, and an error handling unit. The read / write control state machine sends read / write enable signals to the AHS control unit and read / write status signals to the error handling unit. The AHS sends read / write signals to memory or external devices via a bus matrix. The error handling unit receives transmission status information and arbitration result information from the AHS and sends an error alarm signal to the interrupt control module.
[0043] In one embodiment of the present invention, the information stored in the configuration register includes, but is not limited to, channel enable, loop mode, channel priority, number of transmissions, source address, destination address, interrupt enable, data width, and other data for each channel.
[0044] In one embodiment of the present invention, the interrupt control module is used to send status signals to external devices. It should be noted that this interrupt control module can be set up separately or implemented using the interrupt control module within the CPU. Regardless of the implementation method, these are conventional techniques commonly known to those skilled in the art, and will not be elaborated upon here.
[0045] Building upon the aforementioned apparatus (DMA controller) for implementing fast direct memory access transfers, this invention further provides a method for implementing fast direct memory access transfers, used to enable the transfer of data from various external devices (e.g., timers, Serial Peripheral Interface (SPI), I2C serial bus, Universal Asynchronous Receiver / Transmitter (UART), Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC), etc.) to memory. In one embodiment of this invention, the Serial Peripheral Interface (SPI) and I2C serial bus are used as examples for illustration.
[0046] like Figure 2 As shown in the figure, this embodiment of the invention further discloses a method for implementing fast transfer via direct memory access, comprising the following steps:
[0047] S1: In the timing control unit of the arbitration request module, set its working timing so that when the timing is for reading data, the arbitration enable signal is enabled to the priority arbitration request unit; when the timing is for writing data, the response enable signal is enabled to the response control unit.
[0048] like Figure 3 As shown, since priority arbitration is performed in the priority arbitration unit and data reading is performed in the read / write control state machine in the transmission control module, the two tasks are independent of each other and do not affect each other, so the two tasks can be performed in the same time sequence.
[0049] Similarly, since the sending of the confirmation signal is carried out in the response control unit and the writing of data is carried out in the read / write control state machine in the transmission control module, the two tasks are independent of each other and do not affect each other, so these two tasks can be carried out in the same time sequence.
[0050] Through the above technical measures, the reading and writing of data and the processing of requests during direct memory access can be synchronized, thereby greatly accelerating the efficiency of processing the next request from the external device and significantly shortening the transmission response time.
[0051] S2: Configuration register.
[0052] Configure the registers of the DMA controller channels where the first external device (e.g., an SPI interface device) and the second external device (e.g., an I2C interface device) reside.
[0053] For example, if the first external device is on channel 1 of the DMA controller and the second external device is on channel 2 of the DMA controller, then the channel 1 register and channel 2 register of the DMA controller should be configured respectively.
[0054] The configuration information includes, but is not limited to: channel enable, loop mode, channel priority, number of transmissions, source address, destination address, interrupt enable, and data width.
[0055] S3: Enable access signals for the first and second external devices.
[0056] S4: The first external device and the second external device send a request (REQ) signal to the request arbitration module.
[0057] S5: The request priority arbitration unit in the request arbitration module receives the request (REQ) signal and performs arbitration.
[0058] When the request signal is low, it is assumed that no request signal exists; when the request signal is high, it is assumed that a request signal exists.
[0059] The request priority arbitration unit arbitrates the received request signals based on the configuration information sent by the configuration register. For example, if the first external device has a higher priority than the second external device, the request signal of the first external device will be processed first.
[0060] In one embodiment of the present invention, the following steps are described with the example of prioritizing the processing of the first external device and then processing the second external device.
[0061] S6: The priority arbitration unit requests that the channel configuration information be sent to the transmission control module based on the arbitration result.
[0062] S7: After receiving the channel configuration information, the read / write control state machine in the transmission control module enables read / write to the high-performance bus control, reads and writes data, and at the same time enables arbitration and response enable signals to the timing control unit in the request arbitration module.
[0063] S8: The timing control unit enables the arbitration enable signal or the response enable signal to the request priority arbitration unit or the response control unit according to the current timing.
[0064] Among them, such as Figure 3As shown, when the timing is for reading data, the timing control unit enables the arbitration signal to the request priority arbitration unit; when the timing is for writing data, the timing control unit enables the response signal to the response control unit.
[0065] S9: The first external device receives the confirmation signal sent by the request arbitration module and clears the request signal that has been executed in step S5.
[0066] Specifically, when the Advanced High Performance Bus is busy and read / write operations require waiting, the acknowledgment signal remains high, meaning the acknowledgment signal remains valid; when the Advanced High Performance Bus is idle and the request signal is low, meaning the request signal has been cleared, the acknowledgment signal is low, meaning the acknowledgment signal has been cleared.
[0067] S10: Determine whether the first external device and / or the second external device continue to send request signals. If yes, the transmission control module continues to read and write data to the external device; if no, proceed to step S11.
[0068] After the first external device and / or the second external device module waits for the confirmation signal from the arbitration request module for two PCLK cycles, it determines whether it needs to continue sending request signals to the arbitration request module based on the Continuing Transmission Request (TXE) signal from the first external device and / or the second external device. If the TXE signal from the first external device and / or the second external device is high, it continues to send request signals to the arbitration request module, and the transmission control module continues to read and write data to the first external device and / or the second external device; if the TXE signal from the first external device and / or the second external device is low, it no longer sends request signals to the arbitration request module, and proceeds to step S11.
[0069] S11: End data transmission and send an end signal to the CPU.
[0070] Compared with existing technologies, the apparatus and method for achieving fast direct memory access provided by this invention optimizes the operations that need to run in different time sequences in existing technologies, such as request priority arbitration and data reading, confirmation signal sending and data writing, into independent operations within the same time sequence. This effectively improves the processing speed of requests and arbitration, achieving fast direct memory access. The inventors have experimentally verified that when PCLK and HCLK are at the same frequency, the direct memory access efficiency achieved using this invention can reach 100% of the bus transmission efficiency, and it is applicable to any source address to destination address clock with the same or divided frequency.
[0071] The apparatus and method for implementing fast transfer via direct memory access provided by the present invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of the present invention will constitute an infringement of the patent rights of the present invention and will incur corresponding legal liability.
Claims
1. An apparatus for implementing fast transfer via direct memory access, characterized in that... This includes an arbitration request module, a transmission control module, a configuration register, and an interrupt control module; among which, The request arbitration module receives a request signal sent to it by an external device, an arbitration enable signal and an acknowledgment enable signal sent to it by the transmission control module, and a configuration signal sent to it by the configuration register. It sends channel configuration information and a transmission end signal to the transmission control module, sends a transmission completion signal or a transmission half signal to the interrupt control module, and sends an acknowledgment signal to the external device. The request arbitration module includes a request priority arbitration unit, a timing control unit, a response control unit, a multiplexer, and a transmission counter. The request priority arbitration unit receives a request signal from an external device and an arbitration enable signal from the timing control unit, sends the arbitration result to the multiplexer, and sends the level status of the request signal to the response control unit. The timing control unit receives an arbitration enable signal and a response enable signal from the read / write control state machine, and sends a response enable signal to the response control unit. The response control unit receives the idle / busy status signal from the high-performance bus and sends an acknowledgment signal to the external device. The timing control unit's operating timing is set as follows: when the timing is for reading data, it enables the arbitration enable signal to the request priority arbitration unit; when the timing is for writing data, it enables the response enable signal to the response control unit. The transmission control module receives the transmission status signal sent by the Advanced High Performance Bus (AHPC) and sends read / write signals to the AHPC. The transmission control module includes an advanced high-performance bus control unit, a read / write control state machine, and an error handling unit; wherein, the read / write control state machine sends read / write enable signals to the advanced high-performance bus control unit and read / write status signals to the error handling unit; the advanced high-performance bus sends read / write signals to memory or peripherals through a bus matrix; The configuration register receives read / write signals from the high-performance bus sent by the CPU, and sends interrupt enable and clear signals to the interrupt control module. The interrupt control module sends status signals to external devices.
2. The apparatus as described in claim 1, characterized in that: The multiplexer sends the selected channel configuration information to the read / write control state machine and the transmission quantity information to the transmission counter; the transmission counter sends a transmission end signal to the read / write state machine and a transmission completion signal or a transmission half signal to the interrupt control module.
3. The apparatus as described in claim 1, characterized in that: The error handling unit receives the transmission status information and arbitration result information of the high-performance bus and sends an error alarm signal to the interrupt control module.
4. A method for achieving fast transfer via direct memory access, implemented using the apparatus described in any one of claims 1 to 3, characterized in that... Includes the following steps: S1: In the timing control unit of the arbitration request module, set its working timing so that when the timing is for reading data, the arbitration enable signal is enabled to the priority arbitration request unit; when the timing is for writing data, the response enable signal is enabled to the response control unit. S2: Configure the registers of the DMA controller channel where the external device is located; S3: Enables access to external devices; S4: The external device sends a request signal to the arbitration request module; S5: The request priority arbitration unit in the request arbitration module receives the request signal and performs arbitration; S6: The priority arbitration unit requests the transmission control module to send channel configuration information based on the arbitration result; S7: After receiving the channel configuration information, the read / write control state machine in the transmission control module enables read / write to the high-performance bus control, reads and writes data, and at the same time enables the arbitration enable signal and the response enable signal to the timing control unit in the request arbitration module. S8: The timing control unit sends an arbitration enable signal or a response enable signal to the request priority arbitration unit or the response control unit according to the current timing. S9: The external device receives the confirmation signal sent by the request arbitration module and clears the request signal that has been executed in step S5; S10: Determine whether the external device should continue sending request signals, and the transmission control module should continue reading and writing data to the external device; S11: End data transmission and send an end signal to the CPU.
5. The method as described in claim 4, characterized in that: In step S1, priority arbitration is performed in the priority arbitration unit, and data reading is performed in the read / write control state machine in the transmission control module. The two tasks are performed independently within the same time sequence.
6. The method as described in claim 4, characterized in that: In step S1, the sending of the confirmation signal is carried out in the response control unit, and the writing of data is carried out in the read / write control state machine in the transmission control module. The two tasks are performed independently within the same time sequence.
7. The method as described in claim 4, characterized in that: In step S8, when the timing is for reading data, the timing control unit enables the arbitration signal to the request priority arbitration unit; when the timing is for writing data, the timing control unit enables the response signal to the response control unit.
8. The method as described in claim 4, characterized in that: In step S10, after waiting for a predetermined period of confirmation signal from the request arbitration module, the external device determines whether to continue sending a request signal to the request arbitration module based on the request signal it needs to continue sending. If the request signal to continue sending is high, the external device sends a request signal to the request arbitration module and repeats steps S5 to S10. If the request signal to continue sending is low, the external device does not send a request signal and proceeds to step S11.