Data processing method and device, electronic equipment, readable storage medium and chip

Abstract

The application discloses a data processing method and device, electronic equipment, readable storage medium and chip, and belongs to the technical field of data processing. The data processing method comprises the following steps: acquiring a first data set and a second data set, and a processing number M of matching processing of data in the first data set and the second data set, wherein M is a positive integer; acquiring P target data subsets in the second data set, wherein P is a positive integer; and performing matching processing on each target data subset in the P target data subsets and the first data set through N computing units.

Description

Technical Field

[0001] This application belongs to the field of data processing technology, and specifically relates to a data processing method, apparatus, electronic device, readable storage medium, and chip. Background Technology

[0002] In the fields of data image processing and neural network processing, there are processing methods that match and calculate data of a smaller size with data of a larger size.

[0003] The matching process in related technologies requires multiple rounds of repeated matching calculations on two data points. Each round of matching calculations requires rereading the data, resulting in a long matching process and high power consumption. Summary of the Invention

[0004] The purpose of this application is to provide a data processing method, apparatus, electronic device, readable storage medium, and chip that reduces the number of data reads during the matching process and improves work efficiency.

[0005] In a first aspect, embodiments of this application provide a data processing method executed by an electronic device, the electronic device comprising N computing units, where N is an integer greater than 1, the data processing method comprising: acquiring a first dataset and a second dataset, and performing matching processing on data in the first dataset and the second dataset a number of times M, where M is a positive integer; acquiring P target data subsets from the second dataset, wherein... P is a positive integer; each of the P target data subsets is matched with the first dataset through N computing units.

[0006] Secondly, embodiments of this application provide a data processing apparatus applied to an electronic device. The electronic device includes N computing units, where N is an integer greater than 1. The data processing apparatus includes: an acquisition module, configured to acquire a first dataset and a second dataset, and to perform matching processing on the data in the first dataset and the second dataset a number of times M, where M is a positive integer; and an acquisition module, configured to acquire P target data subsets from the second dataset, wherein... P is a positive integer; the processing module is used to match each of the P target data subsets with the first dataset through N computing units.

[0007] Thirdly, embodiments of this application provide an electronic device, including: a processor and a memory, wherein the memory stores a program or instructions that can run on the processor, and when the program or instructions are executed by the processor, they implement the steps of the data processing method as described in the first aspect.

[0008] Fourthly, embodiments of this application provide a readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the data processing method as described in the first aspect.

[0009] Fifthly, embodiments of this application provide a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the steps of the data processing method as described in the first aspect.

[0010] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the steps of the data processing method as described in the first aspect.

[0011] In this embodiment, the electronic device is configured with N computing units to acquire a first dataset, a second dataset, and M number of matching operations performed on the data in the first and second datasets. It then acquires P target data subsets from the second dataset and performs matching operations between each of the P target data subsets and the first dataset using the N computing units, where N is an integer greater than 1. The above solution eliminates the need to reread data during each matching process, reducing the number of data reads during the matching process and improving work efficiency. Attached Figure Description

[0012] Figure 1 A flowchart of a data processing method according to some embodiments of this application is shown;

[0013] Figure 2 A schematic diagram of N registers and N computing units provided in some embodiments of this application is shown;

[0014] Figure 3 This illustration shows a schematic diagram of the flow of second data in a register provided by some embodiments of this application;

[0015] Figure 4 A structural block diagram of a data processing apparatus according to an embodiment of this application is shown;

[0016] Figure 5 A structural block diagram of an electronic device according to an embodiment of this application is shown;

[0017] Figure 6 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0019] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] The following is combined Figures 1 to 6 The data processing methods, apparatus, electronic devices, and storage media provided in this application will be described in detail through specific embodiments and application scenarios.

[0021] In some embodiments of this application, a data processing method is provided, executed by an electronic device, which includes N computing units, each computing unit, Figure 1 A flowchart of a data processing method according to some embodiments of this application is shown, such as... Figure 1 As shown, the data processing methods include:

[0022] Step 102: Obtain the first dataset and the second dataset, and the number of times M is used to match the data in the first dataset and the second dataset, where M is a positive integer;

[0023] In this embodiment, the first dataset and the second dataset are two datasets that need to be matched. The number of processing iterations M is the number of repeated computation rounds required to match the first dataset and the second dataset, i.e., the computational field of view. The number of processing iterations M can be a pre-set number and is related to the processing of the first dataset and the second dataset. The number of processing iterations M can be obtained from image algorithms and determined according to the required matching accuracy.

[0024] For example, the data in the first dataset is smaller-sized data (kernel data), and the data in the second dataset is larger-sized data (data).

[0025] Step 104: Obtain P target data subsets from the second dataset, where...

[0026] In this embodiment of the application, when the number of computing units N is greater than or equal to the number of processing times M, according to Dividing the number of processing steps M by the number of computing units N and rounding up, we get the result that only one subset of the target data needs to be obtained, i.e., the second dataset is used as the subset of the target data. When the number of computing units N is less than the number of processing steps M, according to... That is, the number of processing times M divided by the number of computing units N, and then rounded up, gives the number of target data P obtained. Optionally, the number of second data in the target data subset is greater than or equal to N.

[0027] The number of processing operations, M, represents the number of times the first data in the first dataset is matched with the second data in M ​​different sets of second datasets. The number of computing units, N, represents the parallelism of the electronic device in matching the target data subset with the data in the first dataset. That is, reading data once can match the first data in the first dataset with the second data in N different sets of second datasets. Therefore, the number of target data subsets, P, is the integer part of M divided by N.

[0028] For example, the number of processing steps is 7, the number of computing units is 4, so P is 2, which means that two subsets of the target data can be obtained.

[0029] For example, if the number of processing steps is 4 and the number of computing units is 4, then P is 1, meaning that a subset of the target data can be obtained.

[0030] It should be noted that the number of computing units N can be configured according to the algorithm to be executed by the electronic device. Taking into account factors such as power consumption requirements, performance requirements, number of calculations, and resource overhead of each group of computing units, a suitable parallelism N can be determined, thereby configuring a suitable number of computing units.

[0031] In this embodiment, based on the parallelism N of the matching process performed by the electronic device and the number of matching processes M required by the electronic device for the first dataset, the number P of target data subsets to be acquired can be determined. This reduces the number of times the electronic device reads the second dataset from memory, thereby reducing the power consumption required for the entire matching process and improving the efficiency of the matching process.

[0032] Step 106: Match each of the P target data subsets with the first dataset using N computing units.

[0033] In this embodiment, each of the P target data subsets contains data from the second dataset. N computing units are used to match each target data subset with the first dataset. That is, only one target data subset is matched with the first dataset at any given time. After one target data subset is matched with the first dataset, the next target data subset is matched with the first dataset. The number of second data items in the target data subsets is greater than the number of first data items in the first dataset. N computing units perform multi-channel matching calculations on the target data subsets and the first dataset, ensuring that each second data item in the target data subset is matched with each first data item in the first dataset.

[0034] Specifically, during the matching process, N computing units are used to match the target data subset with the data in the first dataset. The N computing units can process the data synchronously at the same time.

[0035] For example, there are four computing units. At the same time, the four first data points in the first dataset are input into the four computing units respectively, and the four second data points in the target data subset are input into the four computing units respectively. The four computing units can perform matching calculations on the four first data points and the four second data points simultaneously, reducing the time required for matching processing.

[0036] For example, matching the first and second datasets is equivalent to performing 3D noise reduction on the images, that is, matching two frames of image data that are different in the temporal domain. Matching can also be performed on two frames of image data that are different in the spatial domain.

[0037] In this embodiment, the electronic device is configured with N computing units to acquire a first dataset, a second dataset, and M number of matching operations performed on the data in the first and second datasets. It then acquires P target data subsets from the second dataset and performs matching operations between each of the P target data subsets and the first dataset using the N computing units, where N is an integer greater than 1. The above solution eliminates the need to reread data during each matching process, reducing the number of data reads during the matching process and improving work efficiency.

[0038] In some embodiments of this application, each of the P target data subsets is matched with a first dataset using N computing units. This includes: inputting N second data items from the target data subsets into the N computing units in the order they are arranged during Q clock cycles. The N second data items include the (X-N+1)th to the Xth data item from the target data subsets, where Q and X are positive integers, Q = X, and Q ≥ N; and inputting the first data item from the first dataset into the N computing units. The first data item is the data extracted during the Qth clock cycle from the first dataset. The N computing units then perform matching processing on the Q first data items and the second data items. Optionally, inputting the first data item from the first dataset into the N computing units includes inputting a single copy of the first data item from the first dataset into each of the N computing units, meaning that the N computing units have the same first data item.

[0039] In this embodiment of the application, at each moment during the process of matching the target data subset with the first dataset, N computing units are used to calculate the second data in the target data subset and the first data in the first dataset.

[0040] Specifically, at clock Q, the (X-N+1)th to the Xth second data points in the target data subset are input to N computing units, and the Xth first data point in the first dataset is also input to N computing units. Both the Xth second and Xth first data points are data extracted at clock Q. At this time, each computing unit receives the Xth first data point and different second data points, enabling N computing units to synchronously match N different second data points with the same first data point in the target data subset. At clock Q+1, the (X-N+2)th to the (N+1)th second data points in the target data subset are input to N computing units, and the (X+1)th first data point in the first dataset is also input to N computing units. The first data points input to the N computing units change with the computing clock, and the second data points in each of the N computing units also change with the computing clock during the calculation process, thus achieving sliding computation on the data in the first dataset and the target data subset. For example, there are 4 computing units. In the 4th clock cycle, the first to fourth second data points from the target data subset are input into the computing unit and matched with the first data points in the first dataset. In the 5th clock cycle, the second to fifth second data points from the target data subset are input into the computing unit and matched with the first data points in the first dataset.

[0041] For example, there are four computing units: AU1, AU2, AU3, and AU4. The first data in the first dataset is kernel data, and the second data in the target data subset is data. Each clock cycle corresponds to a moment, and the same kernel data is input to the four computing units in each clock cycle. In the first clock cycle, AU1 writes data1, AU2 writes data2, AU3 writes data3, and AU4 writes data4. AU1, AU2, AU3, and AU4 are simultaneously written to kernel1. In the second clock cycle, AU1 writes data2, AU2 writes data3, AU3 writes data4, and AU4 writes data5. AU1, AU2, AU3, and AU4 are simultaneously written to kernel2. This process continues in subsequent clock cycles, allowing the data in the second dataset to slide through the N computing units until each piece of first data in the first dataset has been input to a computing unit once, at which point the current round of computation stops. By sliding the second data through four computing units in sequence, and simultaneously computing the first data in the first dataset with four different sets of second data columns through N computing units, and after matching the target data subset with the first dataset through four computing units, four matching processes for the first dataset are completed. If the number of calculations is 8, then obtaining the target data subset once more will complete the matching process for the first and second datasets.

[0042] In this embodiment, by sequentially inputting the second data in the target data subset into N computing units according to the calculation time, and synchronously inputting the first data in the first dataset into N computing units for calculation, different computing units can perform matching processing on different second data with the same first data. After all the first data in the first dataset has been input into the computing units once, N matching processes are completed. This achieves N matching processes on the first dataset by reading the target data subset once, improving the efficiency of matching processing and reducing the number of times data in the second dataset is obtained.

[0043] In some embodiments of this application, the electronic device further includes N registers, each corresponding to one of the N computing units.

[0044] In this embodiment, the electronic device is further configured with the same number of registers as the computing units, and the N registers are connected sequentially to enable data transfer between them. Each of the N registers corresponds one-to-one with one of the N computing units. During the process of inputting N second data points into the N computing units in a pre-arranged order, each of the N computing units reads data from its corresponding N registers.

[0045] Specifically, N registers are connected sequentially. Data in the target data subset is transferred through the N registers according to the calculation time, ensuring that each second data point in the target data subset flows through the N registers sequentially. In this embodiment, by setting up N levels of registers and N computing units corresponding one-to-one with the N levels of registers in the electronic device, during data reading, the data stored in the N levels of registers can be read by the N computing units respectively, allowing the data in the target data subset to flow through the N levels of registers. This enables the data in the target data subset to enter the computing units for calculation sequentially, reducing the number of times the target data subset needs to be retrieved from the local memory, thereby reducing the power consumption caused by reading data and improving the processing speed.

[0046] In some embodiments of this application, before matching each of the P target data subsets with the first dataset through N computing units, the process further includes:

[0047] The N second data points in the target data subset are transferred to N registers respectively, so that the second data in the N registers can be input to the corresponding computing unit at each clock cycle.

[0048] In the embodiments of this application, by transmitting the second data in the target data subset to N registers respectively, the corresponding N computing units can read the second data in the corresponding register at each clock cycle. As the clock changes, the second data in the target data subset is sequentially transmitted to the N registers.

[0049] Specifically, the number of registers is the same as the number of computing units, and the registers are matched with the computing units to ensure that the second data in each register can be input into the corresponding computing unit.

[0050] In this embodiment of the application, by setting an N-level register in the electronic device and inputting the second data in the target data subset into the N-level register, the second data in the target dataset is transmitted in the N-level register. This enables N matching processes to be performed once the target dataset is acquired, reducing the number of times the target dataset needs to be acquired from the local memory, thereby reducing the power consumption caused by reading data and improving the processing speed.

[0051] In some embodiments of this application, N registers are connected sequentially;

[0052] The N second data points in the target data subset are transferred to N registers respectively, including: at the Y-th clock, the Z-th second data point in the target data subset is input to the first register of the N registers, where Y and Z are positive integers, Y = Z; wherein, at each clock, the second data points input to the N registers in the previous clock flow to the next register according to the order of the N registers, until they flow out of the N registers.

[0053] In this embodiment, N registers are connected sequentially, allowing the second data in the target data subset to flow through these N registers. Specifically, the second data is input into the first register of the N registers, and after each clock cycle, the second data flows to the next register until it exits all N registers. During the process of inputting data from the target data subset into the N registers, it is only necessary to input the corresponding second data into the first register at each clock cycle. At each clock cycle, the second data in each register can flow to the next register, ensuring that each piece of second data passes through all N registers sequentially, thus enabling the corresponding second data to be read by each clock calculation unit.

[0054] For example, taking N=4 as an example: In the first clock cycle, the first second data is input to the first register; in the second clock cycle, the second second data is input to the first register, and the first second data input in the first clock cycle flows to the second register connected to the first register; in the third clock cycle, the third second data is input to the first register, the second second data flows to the second register, and the first second data flows to the third register; in the fourth clock cycle, the fourth second data is input to the first register, the third second data flows to the second register, the second second data flows to the third register, and the first second data flows to the last register; in the fifth clock cycle, the fifth second data is input to the first register, the fourth second data flows to the second register, the third second data flows to the third register, the second second data flows to the last register, and the first second data flows out of the last register.

[0055] Figure 2 The diagram illustrates N registers and N computing units provided in some embodiments of this application, such as... Figure 2As shown, there are four registers: reg0, reg1, reg2, and reg3, and four computation units: AU0, AU1, AU2, and AU3. Each computation unit corresponds one-to-one with each register. The second data (data) of the target data subset is input into the four registers and flows sequentially through the four computation units. The first data (kernel) of the first dataset is synchronously input into the four computation units and computed with four different second data (data).

[0056] For example, each register level can store one second data. At clock 1, data0 from the target data subset is registered in reg0. At clock 2, dota0 is transferred from reg0 to reg1, and data1 is registered in reg0. At clock 3, dota0 is transferred from reg1 to reg2, data1 is transferred from reg0 to reg1, and data2 is registered in reg0. At clock 4, dota0 is transferred from reg2 to reg3, data1 is transferred from reg1 to reg2, data2 is transferred from reg0 to reg1, and data3 is registered in reg0. At clock 5, dota0 is transferred from reg3 to the outside, data1 is transferred from reg2 to reg3, data2 is transferred from reg1 to reg2, data3 is transferred from reg0 to reg1, and data4 is registered in reg0. It can be seen that reg1 to reg4 are connected sequentially, and the second data in the target data subset flows sequentially through the four registers. Therefore, at clock 1, computation unit AU0 reads data0, and at clock 2, computation unit AU0 reads data1, and AU1 reads data0. Clock 3 calculation unit AU0 reads data2, AU1 reads data1, AU2 reads data0. Clock 4 calculation unit AU0 reads data3, AU1 reads data2, AU2 reads data1, AU3 reads data0. Clock 5 calculation unit AU0 reads data4, AU1 reads data3, AU2 reads data2, AU3 reads data1.

[0057] Figure 3 This application provides schematic diagrams illustrating the flow of second data in registers according to some embodiments, such as... Figure 3As shown. The first dataset includes 12 first data points, namely kernelA, kernelB to kernelL, with 7 computations and 4 computation units and registers, designated reg0, reg1, reg2, and reg3. At each time step (CLK), the 4 computation units perform matching processing on the first and second data points within their respective datasets. There are 2 target datasets: a first target dataset and a second target dataset, each containing 15 second data points. The second data points in the first target dataset are data0, data2 to data14, and the second data points in the second target dataset are data4, data5 to data18. During the calculations from clk3 to clk14, the data in register reg3 completed the matching process between data0 to data11 and kernelA to kernelL; the data in register reg2 completed the matching process between data1 to data12 and kernelA to kernelL; the data in register reg1 completed the matching process between data2 to data13 and kernelA to kernelL; and the data in register reg0 completed the matching process between data3 to data14 and kernelA to kernelL. At this point, the first target dataset has completed its matching process with the first dataset, and the process of matching the second target dataset with the first dataset begins, which is the same as the matching process between the first target dataset and the first dataset. After the second target dataset completes its matching process with the first dataset, the first dataset has completed seven matching processes with the second dataset.

[0058] In this embodiment, by sequentially connecting N registers, the second data can flow through the N registers, ensuring that each piece of second data can flow through the N registers sequentially. This enables the acquisition of a target data subset to be matched with the first dataset N times, reducing the number of times data is retrieved from the local storage area, improving processing speed while reducing power consumption.

[0059] The data processing method provided in this application can be executed by a data processing device. This application uses an example of a data processing device executing a data processing method to illustrate the data processing apparatus provided in this application.

[0060] In some embodiments of this application, a data processing apparatus is provided, applied to an electronic device, the electronic device including N computing units, where N is an integer greater than 1. Figure 4 A structural block diagram of a data processing apparatus according to an embodiment of this application is shown, such as... Figure 4 As shown, the data processing device 400 includes:

[0061] The acquisition module 402 is used to acquire the first dataset and the second dataset, and the number of times M, where M is a positive integer, is used to perform matching processing on the data in the first dataset and the second dataset.

[0062] Module 402 is used to obtain P target data subsets from the second dataset, where, P is a positive integer;

[0063] Processing module 404 is used to match each of the P target data subsets with the first dataset through N computing units.

[0064] In this embodiment, the electronic device is configured with N computing units to acquire a first dataset, a second dataset, and M number of matching operations performed on the data in the first and second datasets. It then acquires P target data subsets from the second dataset and performs matching operations between each of the P target data subsets and the first dataset using the N computing units, where N is an integer greater than 1. The above solution eliminates the need to reread data during each matching process, reducing the number of data reads during the matching process and improving work efficiency.

[0065] In some embodiments of this application, the processing module 404 is used to input N second data in the target data subset into N computing units in the order of arrangement at the Q-th clock cycle. The N second data include the data from the (X-N+1)th to the Xth data in the target data subset, where Q and X are positive integers, Q = X, and Q ≥ N.

[0066] Processing module 404 is used to input the first data in the first data set to N computing units. The first data is the data collected in the first data set at the Qth clock cycle.

[0067] The processing module 404 is used to perform matching processing on the first data and N second data respectively through N calculation units.

[0068] In this embodiment, by sequentially inputting the second data in the target data subset into N computing units according to the calculation time, and synchronously inputting the first data in the first dataset into N computing units for calculation, different computing units can perform matching processing on different second data with the same first data. After all the first data in the first dataset has been input into the computing units once, N matching processes are completed. This achieves N matching processes on the first dataset by reading the target data subset once, improving the efficiency of matching processing and reducing the number of times data in the second dataset is obtained.

[0069] In some embodiments of this application, the electronic device further includes N registers, each corresponding to one of the N computing units.

[0070] In this embodiment, by setting up an N-level register and N computing units corresponding to the N-level register in the electronic device, during the data reading process, the data stored in the N-level register can be read by the N computing units respectively, and the data in the target data subset can flow in the N-level register, so that the data in the target data subset can enter the computing units for calculation in sequence. This reduces the number of times the target data subset needs to be obtained from the local memory, thereby reducing the power consumption caused by reading data and improving the processing speed.

[0071] In some embodiments of this application, the processing module 404 is used to transfer the second data in the target data subset to N registers respectively, so that the second data in the N registers can be input to the corresponding computing unit at each clock cycle.

[0072] In this embodiment, by setting an N-level register in the electronic device and inputting the second data in the target data subset into the N-level register, the second data in the target data set is transmitted in the N-level register. This enables N matching processes to be performed once a target data subset is obtained, reducing the number of times the target data subset needs to be obtained from the local memory, thereby reducing the power consumption caused by reading data and improving the processing speed.

[0073] In some embodiments of this application, N registers are connected sequentially;

[0074] The processing module is also used to input the Zth second data in the target data subset into the first register of N registers in the Y-th clock cycle, where Y and Z are positive integers, Y = Z; wherein, in each clock cycle, the second data input into the N registers in the previous clock cycle flows to the next register in the order of the N registers, until it flows out of the N registers.

[0075] In this embodiment, N registers are connected sequentially, with the output data of one register serving as the input data of the next. Therefore, the second data in the target data subset can flow through the N registers. Specifically, the second data is input into the first register of the N registers, and after each clock cycle, the second data flows to the next register until it exits all N registers. In the process of inputting data from the target data subset into the N registers, it is only necessary to input the corresponding second data into the first register at each clock cycle. At each clock cycle, the second data in each register can flow to the next register, ensuring that each piece of second data passes through all N registers sequentially. This allows the corresponding second data to be read by the computation unit at each clock cycle. This reduces the number of times data is retrieved from local storage, improving processing speed while reducing power consumption.

[0076] The data processing device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0077] The data processing device in this application embodiment can be a device with an operating system. The operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system.

[0078] The data processing apparatus provided in this application embodiment can implement the various processes implemented in the above method embodiments, and will not be described again here to avoid repetition.

[0079] Optionally, embodiments of this application also provide an electronic device. Figure 5A structural block diagram of an electronic device according to an embodiment of this application is shown, such as... Figure 5 As shown, the electronic device 500 includes a processor 502, a memory 504, and a program or instructions stored in the memory 504 and executable on the processor 502. When the program or instructions are executed by the processor 502, they implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0080] It should be noted that the electronic devices in the embodiments of this application include the aforementioned mobile electronic devices and non-mobile electronic devices.

[0081] Figure 6 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0082] The electronic device 600 includes, but is not limited to, components such as: radio frequency unit 601, network module 602, audio output unit 603, input unit 604, sensor 605, display unit 606, user input unit 607, interface unit 608, memory 609, and processor 610.

[0083] Those skilled in the art will understand that the electronic device 600 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 610 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 6 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0084] The processor 610 is used to acquire the first dataset and the second dataset, and to perform matching processing on the data in the first dataset and the second dataset a number of times M, where M is a positive integer.

[0085] Processor 610 is used to acquire P target data subsets from the second dataset, where, P is a positive integer;

[0086] Processor 610 is used to match each of the P target data subsets with the first dataset through N computing units.

[0087] In this embodiment, the electronic device is configured with N computing units to acquire a first dataset, a second dataset, and M number of matching operations performed on the data in the first and second datasets. It then acquires P target data subsets from the second dataset and performs matching operations between each of the P target data subsets and the first dataset using the N computing units, where N is an integer greater than 1.

[0088] The above solution eliminates the need to reread data during each matching process, reducing the number of data reads during the matching process and improving work efficiency.

[0089] Furthermore, the processor 610 is used to input N second data points from the target data subset into N computing units in the order of arrangement during the Q-th clock cycle. The N second data points include the (X-N+1)th to the Xth data points in the target data subset, where Q and X are positive integers, Q = X, and Q ≥ N.

[0090] Processor 610 is used to input the first data in the first data set to N computing units. The first data is the data collected in the first data set at the Q-th clock cycle.

[0091] The processor 610 is used to perform matching processing on the first data and N second data respectively through N computing units.

[0092] In this embodiment, by sequentially inputting the second data in the target data subset into N computing units according to the calculation time, and synchronously inputting the first data in the first dataset into N computing units for calculation, different computing units can perform matching processing on different second data with the same first data. After all the first data in the first dataset has been input into the computing units once, N matching processes are completed. This achieves N matching processes on the first dataset by reading the target data subset once, improving the efficiency of matching processing and reducing the number of times data in the second dataset is obtained.

[0093] Furthermore, the electronic device also includes N registers, each corresponding to one of the N computing units.

[0094] In this embodiment, by setting up an N-level register and N computing units corresponding to the N-level register in the electronic device, during the data reading process, the data stored in the N-level register can be read by the N computing units respectively, and the data in the target data subset can flow in the N-level register, so that the data in the target data subset can enter the computing units for calculation in sequence. This reduces the number of times the target data subset needs to be obtained from the local memory, thereby reducing the power consumption caused by reading data and improving the processing speed.

[0095] Furthermore, the processor 610 is used to transfer N second data from the target data subset to N registers respectively, so that the second data in the N registers can be input to the corresponding computing unit at each clock cycle.

[0096] In this embodiment, by setting an N-level register in the electronic device and inputting the second data in the target data subset into the N-level register, the second data in the target data set is transmitted in the N-level register. This enables N matching processes to be performed once a target data subset is obtained, reducing the number of times the target data subset needs to be obtained from the local memory, thereby reducing the power consumption caused by reading data and improving the processing speed.

[0097] Furthermore, the N registers are connected sequentially;

[0098] The processing module is also used to input the Zth second data in the target data subset into the first register of N registers in the Y-th clock cycle, where Y and Z are positive integers, Y = Z; wherein, in each clock cycle, the second data input into the N registers in the previous clock cycle flows to the next register in the order of the N registers, until it flows out of the N registers.

[0099] In this embodiment, N registers are connected sequentially, allowing the second data in the target data subset to flow through these N registers. Specifically, the second data is input into the first register of the N registers, and after each clock cycle, the second data flows to the next register until it exits all N registers. During the input of data from the target data subset into the N registers, only the corresponding second data needs to be input into the first register at each clock cycle. At each clock cycle, the second data in each register can flow to the next register, ensuring that each piece of second data passes through all N registers sequentially. This ensures that the corresponding second data can be read by the computation unit at each clock cycle. This reduces the number of times data is retrieved from local storage, improving processing speed while reducing power consumption.

[0100] It should be understood that, in this embodiment, the input unit 604 may include a graphics processing unit (GPU) 6041 and a microphone 6042. The GPU 6041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 606 may include a display panel 6061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 607 includes at least one of a touch panel 6071 and other input devices 6072. The touch panel 6071 is also called a touch screen. The touch panel 6071 may include two parts: a touch detection device and a touch controller. Other input devices 6072 may include, but are not limited to, a physical keyboard, function keys (such as volume control buttons, power buttons, etc.), a trackball, a mouse, and a joystick, which will not be described in detail here.

[0101] The memory 609 can be used to store software programs and various data. The memory 609 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 609 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 609 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0102] Processor 610 may include one or more processing units; optionally, processor 610 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 610.

[0103] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0104] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0105] This application also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0106] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0107] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0108] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0110] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A data processing method, executed by an electronic device, characterized in that, The electronic device includes N computing units, where N is an integer greater than 1, and the data processing method includes: Obtain the first dataset and the second dataset, and the number of times M, where M is a positive integer, is used to perform matching processing on the data in the first dataset and the second dataset; Obtain P target data subsets from the second dataset, where, P is a positive integer; Each of the P target data subsets is matched with the first dataset using the N computing units; The step of matching each of the P target data subsets with the first dataset through the N computing units includes: at the Q-th clock cycle, inputting the N second data from the target data subsets into the N computing units in the order of arrangement, wherein the N second data include the data from the (X-N+1)th to the Xth data in the target data subsets, where Q and X are positive integers, Q = X, and Q ≥ N; And inputting the first data from the first dataset into the N computing units, wherein the first data is the data extracted from the first dataset at the Q-th clock cycle; The first data is matched with the N second data using the N computing units.

2. The data processing method according to claim 1, characterized in that, The electronic device also includes N registers, each of which corresponds to one of the N computing units.

3. The data processing method according to claim 2, characterized in that, Before matching each of the P target data subsets with the first dataset through the N computing units, the process further includes: The N second data points in the target data subset are respectively transferred to the N registers.

4. The data processing method according to claim 3, characterized in that, The N registers are connected sequentially; The step of transmitting N second data points from the target data subset to the N registers respectively includes: At the Y-th clock cycle, the Z-th second data in the target data subset is input into the first register of the N registers, where Y and Z are positive integers, and Y = Z; In each clock cycle, the second data input to the N registers from the previous clock cycle flows to the next register in the order of the N registers, until it flows out of the N registers.

5. A data processing device, applied to electronic equipment, characterized in that, The electronic device includes N computing units, where N is an integer greater than 1, and the data processing device includes: The acquisition module is used to acquire a first dataset and a second dataset, and to perform matching processing on the data in the first dataset and the second dataset a number of times, M, where M is a positive integer; The acquisition module is used to acquire P target data subsets in the second dataset, where P = ⌈M / N⌉ and P is a positive integer; The processing module is used to match each of the P target data subsets with the first dataset through the N computing units; The processing module is used to input N second data points from the target data subset into the N computing units in the order of arrangement at the Q-th clock cycle. The N second data points include the (X-N+1)th data point to the Xth data point in the target data subset, where Q and X are positive integers, Q = X, and Q ≥ N. The processing module is used to input the first data in the first dataset to the N computing units, wherein the first data is the data collected in the first dataset at the Q-th clock cycle; The processing module is used to perform matching processing on the first data and the N second data respectively through the N calculation units.

6. The data processing apparatus according to claim 5, characterized in that, The electronic device also includes N registers, each of which corresponds to one of the N computing units.

7. The data processing apparatus according to claim 6, characterized in that, The processing module is used to transmit the second data in the target data subset to the N registers respectively.

8. The data processing apparatus according to claim 7, characterized in that, The N registers are connected sequentially; The processing module is used to input the Zth second data in the target data subset into the first register of the N registers at the Yth clock cycle, where Y and Z are positive integers, and Y = Z; In each clock cycle, the second data input to the N registers from the previous clock cycle flows to the next register in the order of the N registers, until it flows out of the N registers.

9. An electronic device, characterized in that, include: A processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the data processing method as described in any one of claims 1 to 4.

10. A readable storage medium having a program or instructions stored thereon, characterized in that, When the program or instructions are executed by the processor, they implement the steps of the data processing method as described in any one of claims 1 to 4.

11. A chip, characterized in that, The chip includes a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the steps of the data processing method as described in any one of claims 1 to 4.

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