Chip test data analysis method and device

Abstract

The application provides a chip test data analysis method and device, chips are located on wafers, the method comprises the following steps: acquiring test data of the chips on multiple wafers, performing quality partitioning on the test data to obtain a two-dimensional quality matrix of each wafer, scanning the quality matrix by using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence, sorting multiple wafer-Hilbert scan sequences to obtain a quality sequence matrix of the multiple wafers, and analyzing the test data of the chips on the multiple wafers according to the quality sequence matrix, that is, the information in the quality matrix is compressed into a two-dimensional quality sequence matrix by performing Hilbert curve scanning on the quality matrix corresponding to the wafer comprising the multiple chips, the analysis difficulty of the test data of the chips is greatly reduced, and the analysis efficiency of the wafer-level chip test data is improved.

Description

Technical Field

[0001] This invention relates to the field of data analysis, and in particular to a method and apparatus for analyzing chip test data. Background Technology

[0002] With the technological advancements in related fields, the semiconductor industry has also experienced tremendous growth, especially in the chip sector. Current chip mass production is based on wafers, and testing engineering batches or mass-produced chip wafers generates a large amount of multi-dimensional test data.

[0003] Analyzing test data can provide information about chip quality. However, in actual analysis, the efficiency of chip test data analysis is low because the types of chip test data are numerous and the quantity increases exponentially with the number of chips and wafers.

[0004] Therefore, there is an urgent need for a highly efficient method for analyzing chip test data. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a chip test data analysis method and apparatus that can improve the analysis efficiency of chip test data.

[0006] This application provides a chip test data analysis method, wherein the chip is located on a wafer, and the method includes:

[0007] Test data of multiple chips on multiple wafers are acquired, and the test data is partitioned by quality to obtain a two-dimensional quality matrix for each wafer;

[0008] The quality matrix is ​​scanned using Hilbert curves to obtain a one-dimensional wafer-Hilbert scan sequence;

[0009] Arrange the multiple wafer-Hilbert scan sequences in rows to construct a mass sequence matrix of multiple wafers;

[0010] The test data of multiple chips on the multiple wafers are analyzed based on the quality sequence matrix.

[0011] Optionally, the step of acquiring test data from multiple chips on multiple wafers, and performing quality partitioning on the test data to obtain a two-dimensional quality matrix for each wafer includes:

[0012] A test dataset of multiple chips on multiple wafers is obtained. The test dataset includes multiple test data. According to the chip quality classification rules, the test data in the test dataset are divided into quality categories to obtain the quality value corresponding to each test data. A quality matrix for each wafer is formed based on the quality values.

[0013] Optionally, forming a quality matrix for each wafer based on the quality value includes:

[0014] By combining the chip location information of each wafer, a mass matrix is ​​formed for each wafer based on the mass value corresponding to each chip on each wafer.

[0015] Optionally, the test data includes various chip parameters;

[0016] The process of acquiring test data from multiple chips on multiple wafers, and partitioning the test data by quality to obtain a two-dimensional quality matrix for each wafer includes:

[0017] Multiple chip parameters are obtained for each chip among multiple chips on multiple wafers. Each chip parameter among the multiple chip parameters is divided into quality partitions to obtain the quality matrix of each chip parameter in each wafer.

[0018] Optionally, the step of scanning the quality matrix using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence includes:

[0019] The scanning path of the Hilbert curve is determined based on the size of the quality matrix, and the scanning path carries chip location information for each wafer;

[0020] The quality matrix of each wafer is scanned according to the scan path to obtain a one-dimensional wafer-Hilbert scan sequence for each wafer.

[0021] Optionally, the test data includes various chip parameters, and the quality sequence matrix includes a first target quality sequence matrix;

[0022] The step of arranging the multiple wafer-Hilbert scan sequences in rows to construct a multiple wafer quality sequence matrix includes:

[0023] Using a wafer as a sub-module, the wafer-Hilbert scan sequences corresponding to multiple chip parameters under the same wafer are extracted and sorted by row to obtain the first target quality sequence matrix. The number of rows in the first target quality sequence matrix is ​​the product of the number of wafers and the number of chip parameters.

[0024] Optionally, the test data includes various chip parameters, and the quality sequence matrix includes a second target quality sequence matrix;

[0025] The step of arranging the multiple wafer-Hilbert scan sequences in rows to construct a multiple wafer quality sequence matrix includes:

[0026] Using chip parameters as a submodule, the wafer-Hilbert scan sequences corresponding to multiple wafers under the same chip parameters are extracted and sorted by row to obtain the second target quality sequence matrix. The number of rows in the second target quality sequence matrix is ​​the product of the number of chip parameters and the number of wafers.

[0027] Optionally, the analysis of test data of multiple chips on the multiple wafers based on the quality sequence matrix includes:

[0028] The quality sequence matrix is ​​visualized to obtain a visualization spectrum corresponding to the quality sequence matrix, and the test data of multiple chips on multiple wafers are analyzed based on the visualization spectrum.

[0029] Optionally, the quality sequence matrix includes the quality value corresponding to each test data, and the visualization spectrum includes a color quality feature spectrum;

[0030] The step of visualizing the quality sequence matrix to obtain a visual spectrum corresponding to the quality sequence matrix, and analyzing the test data of multiple chips on multiple wafers based on the visual spectrum, includes:

[0031] According to the coloring rules, the quality value corresponding to each test data in the quality sequence matrix is ​​colored to obtain a color quality feature spectrum. The test data of multiple chips on multiple wafers are analyzed based on the color quality feature spectrum.

[0032] This application provides a chip test data analysis device, wherein the chip is located on a wafer, and the device includes:

[0033] The acquisition unit is used to acquire test data of multiple chips on multiple wafers, perform quality partitioning on the test data, and obtain a two-dimensional quality matrix for each wafer.

[0034] A scanning unit is used to scan the quality matrix using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence;

[0035] An arrangement unit is used to arrange multiple wafer-Hilbert scan sequences in rows to construct a mass sequence matrix of multiple wafers;

[0036] An analysis unit is used to analyze test data of multiple chips on multiple wafers based on the quality sequence matrix.

[0037] This application provides a chip test data analysis method. The chip is located on a wafer. The method includes: acquiring test data of multiple chips on multiple wafers; dividing the test data into quality partitions to obtain a two-dimensional quality matrix for each wafer; scanning the quality matrix using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence; arranging the multiple wafer-Hilbert scan sequences in rows to construct a quality sequence matrix for multiple wafers; and analyzing the test data of multiple chips on multiple wafers based on the quality sequence matrix. In other words, by scanning the quality matrix corresponding to the wafers containing multiple chips using Hilbert curves, the information in the quality matrix is ​​compressed into a two-dimensional quality sequence matrix, which greatly reduces the difficulty of analyzing chip test data and improves the efficiency of wafer-level chip test data analysis. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A schematic flowchart of a chip test data analysis method provided in an embodiment of this application is shown;

[0040] Figure 2 This illustration shows a schematic diagram of a wafer quality matrix distribution provided in an embodiment of this application;

[0041] Figure 3 This illustration shows a path diagram of a third-order Hilbert curve scanning a square matrix according to an embodiment of this application;

[0042] Figure 4 This illustration shows a wafer quality grade distribution diagram with chip parameters as sub-modules, provided by an embodiment of this application.

[0043] Figure 5 This illustration shows a wafer quality grade distribution diagram with wafers as sub-modules, provided by an embodiment of this application.

[0044] Figure 6 This illustration shows the quality distribution of chip parameters provided in an embodiment of this application;

[0045] Figure 7 A schematic diagram of the structure of a chip test data analysis device provided in an embodiment of this application is shown. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] With the technological advancements in related fields, the semiconductor industry has also experienced tremendous growth, especially in the chip sector. Current chip mass production is based on wafers, and testing engineering batches or mass-produced chip wafers generates a large amount of multi-dimensional test data.

[0049] Analyzing test data can reveal chip quality information, such as extracting chip quality information from the test dataset and visualizing the corresponding data matrix in two-dimensional space to generate wafer maps, thus obtaining the distribution of chip quality and chip parameter quality. However, in actual analysis, the large variety and exponentially increasing quantity of chip test data with the number of chips and wafers lead to a significant increase in the number of wafer maps, resulting in low efficiency in chip test data analysis.

[0050] Therefore, there is an urgent need for a highly efficient method for analyzing chip test data.

[0051] Based on this, embodiments of this application provide a chip test data analysis method, wherein the chip is located on a wafer. The method includes: acquiring test data of multiple chips on multiple wafers; dividing the test data into quality partitions to obtain a two-dimensional quality matrix for each wafer; scanning the quality matrix using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence; arranging multiple wafer-Hilbert scan sequences in rows to construct a quality sequence matrix for multiple wafers; and analyzing the test data of multiple chips on multiple wafers based on the quality sequence matrix. In other words, by performing Hilbert curve scanning on the quality matrix corresponding to wafers containing multiple chips, the information in the quality matrix is ​​compressed into a two-dimensional quality sequence matrix, which greatly reduces the difficulty of analyzing chip test data and improves the efficiency of wafer-level chip test data analysis.

[0052] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0053] See Figure 1 The figure is a flowchart illustrating a chip test data analysis method provided in an embodiment of this application.

[0054] In the embodiments of this application, the chip is disposed on a wafer, that is, a wafer includes multiple chips, and multiple chips in multiple wafers can be tested subsequently.

[0055] The chip test data analysis method provided in this embodiment includes the following steps:

[0056] S101: Acquire test data from multiple chips on multiple wafers, partition the test data by quality, and obtain a two-dimensional quality matrix for each wafer.

[0057] In the embodiments of this application, after testing multiple chips on multiple wafers, test data of multiple chips on multiple wafers can be obtained. This test data is wafer-level test data, which has the characteristics of large data volume, high dimensionality, and contains spatial location information of the chips.

[0058] Specifically, test data can include various chip parameters; that is, test data can include multiple types, each corresponding to a specific chip parameter.

[0059] One possible implementation is to convert the test data of all chips on the wafer into a matrix form, forming a parameter matrix. The feature matrix consists of n chip parameters, and the parameter matrix is ​​defined according to the positional relationship of the chip parameters.

[0060] As an example, the parameter matrix formula (1) is shown:

[0061]

[0062] Where m represents the number of test chips, n represents the number of chip parameters, n is the key parameter for evaluating chip performance, and chip's ID is the wafer number.

[0063] Test data from all wafers in the same batch can be expressed using a parameter matrix, forming a wafer-level chip dataset `date_set`. In other words, test data from multiple chips on multiple wafers can form a test dataset, as shown below:

[0064]

[0065] As shown above, the wafer-level chip dataset `date_set` consists of N wafers. The dataset can be organized according to the order in which the wafers were tested, and can be represented using the following formula:

[0066] data_set = {X i ,i=1,2,...,N} (2)

[0067] The date_set contains N wafers, X i,j,k This represents the test value of parameter k for chip numbered j on the i-th wafer.

[0068] Therefore, any test value in the dataset is a point in three-dimensional space, i.e., x = x(i,j,k). Here, i represents the wafer number, j represents the chip number, and k represents the chip parameter type.

[0069] In the embodiments of this application, after obtaining test data of multiple chips on multiple wafers, the test data can be partitioned by quality to obtain a two-dimensional quality matrix for each wafer.

[0070] Specifically, the test data in the test dataset can be divided into quality categories according to chip quality classification rules, and the quality value corresponding to each test data can be obtained. A quality matrix for each wafer can then be formed based on the quality values.

[0071] As one possible implementation, classification criteria can be determined based on the chip's test data. The classification criteria may include a chip quality partitioning baseline, which can effectively classify the chip's quality. The classification criteria are shown in formula (3):

[0072] line = [l1,l2,l3,…,l k ] 1×k (3)

[0073] In other words, for k partition vectors, the chip quality can be divided into k+1 blocks, meaning the quality values ​​include 1, 2, ..., k, k+1.

[0074] The chip quality classification rules can be shown in formula (4):

[0075]

[0076] According to the chip quality classification rules in formula (4), the chip test dataset date_set is divided into quality categories to generate the corresponding quality matrix set Q_set. The quality matrix set Q_set is a collection of multiple wafer quality matrices Q. As shown in formula (5), the quality matrix set Q_set includes the result of quality partitioning of test data of multiple chips on each wafer.

[0077] Q_set={Q i ,i=1,2,...,N} (5)

[0078] Q i This indicates the result of the test data of the i-th wafer chip being classified according to the chip quality classification rules in (4).

[0079] In the embodiments of this application, when converting the test data of all chips on the wafer into a matrix form to form a parameter matrix, the order of chip numbers is unrelated. When forming the quality matrix Q of each wafer and the quality matrix set Q_set of multiple wafers, the chip position information of each wafer can be combined to form the quality matrix of each wafer based on the quality value corresponding to each chip on each wafer.

[0080] As one possible implementation, each chip has fixed location information on the wafer. The chip location information WaferTable_ID can be defined as shown in formula (6):

[0081]

[0082] Based on the chip location information provided by formula (6), the quality matrix set Q_set of formula (5) is mapped to the location.

[0083] In practical applications, because the data distribution on the chips on the wafer is circular, some IDs... ij Since there is no actual chip at the location, the chip number at the missing position is filled by adding a constant 'a'. Generate a two-dimensional quality matrix Q_wafer for each wafer, as shown in Equation (7).

[0084]

[0085] Q_wafer ij This represents the quality value of the j-th chip parameter of each chip on the i-th wafer. id_xlabel represents the horizontal coordinate of each chip, and id_ylabel represents the vertical coordinate of each chip. The quality value of each chip can be located through (id_xlabel, id_ylabel).

[0086] In the embodiments of this application, since the test data includes multiple chip parameters, quality partitioning is performed for each chip parameter to obtain a quality matrix for each chip parameter in each wafer.

[0087] In the embodiments of this application, the quality matrix Q_wafer for each chip parameter in each obtained wafer can be... ijVisualization processing, such as coloring, is performed to obtain the quality matrix distribution map of the j-th chip parameter for each chip on the i-th wafer, as shown in the reference. Figure 2 As shown, Figure 2 The midpoint value a = 0, and the color bar value from 1 to 7 represents the chip quality from excellent to poor. Figure 2 It can intuitively reflect the quality distribution pattern of the chip.

[0088] S102, the quality matrix is ​​scanned using the Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence.

[0089] In the embodiments of this application, after obtaining the two-dimensional quality matrix of each wafer, the quality matrix can be scanned using Hilbert curves to obtain a one-dimensional wafer-Hilbert scan sequence. This can compress the information in the quality matrix into a one-dimensional wafer-Hilbert scan sequence, greatly reducing the difficulty of analyzing chip test data and improving the efficiency of wafer-level chip test data analysis.

[0090] In fractal theory, the Hilbert curve, due to its unique recursive method and trajectory, can effectively fill a two-dimensional plane. Furthermore, the path planned by the Hilbert curve ensures the positional correlation between image pixels; that is, the curve can effectively cover each value of the quality matrix and take into account the spatial distribution, texture, shape, and other features of the quality values. The Hilbert scan matrix algorithm is shown in formula (8):

[0091]

[0092] Where E represents the identity matrix of the corresponding order. 2 k The scan matrix representing the Hilbert curve is: Where, A, The transformation of the matrix is ​​defined by the following formulas (9) to (11). Formula (10) represents the left-right reversal of matrix A, and formula (11) represents the top-bottom reversal of matrix A.

[0093]

[0094]

[0095]

[0096] Formula (8) constructs a k-order Hilbert curve recursive scanning matrix, which is the Hilbert curve scanning matrix. The Hilbert curve scanning algorithm shown in Formula (8) can be used to scan the quality matrix Q, transforming the two-dimensional discrete signal in the quality matrix Q into a one-dimensional discrete signal.

[0097] In the embodiments of this application, the scanning path of the Hilbert curve can be determined according to the size of the quality matrix. The scanning path carries the chip position information of each wafer. The quality matrix of each wafer is scanned according to the scanning path to obtain a one-dimensional wafer-Hilbert scan sequence for each wafer. That is, the scanning path of the Hilbert curve can be changed according to the size of the quality matrix. When scanning the quality matrix of each wafer using the Hilbert curve, the chip position information of each wafer can be carried. It can also ensure that the positional correlation of adjacent chips on the wafer remains unchanged while performing dimensionality reduction. In other words, the Hilbert curve can maximize the guarantee that adjacent points in two-dimensional space are also together in one-dimensional space. That is, using the Hilbert curve for dimensionality reduction can greatly facilitate subsequent chip quality analysis.

[0098] In practical applications, the scan paths of Hilbert curves of the same size can also be different. The specific path can be varied depending on the actual quality matrix. (Refer to...) Figure 3 As shown, Figure 3 A schematic diagram of the path for a third-order Hilbert curve to scan a square matrix is ​​shown.

[0099] As one possible implementation, the scanning path H of the Hilbert curve can be determined based on the size of the obtained quality matrix, as shown in formula (12):

[0100] H = [h1 h2 … h] m*n ] 1×(m*n) (12)

[0101] Where H is a one-dimensional matrix with a length equal to the number of scan points of the Hilbert curve on the quality matrix Q. The Hilbert curve scan matrix elements ensure the correlation of adjacent elements in spatial position, and the correspondence between the curve scan path and the points on the quality matrix is ​​shown in formula (13).

[0102]

[0103] In practical applications, the quality matrix of each wafer is derived from the original wafer position map, and its size has no fixed standard. Hilbert curves can handle square matrices well. For the quality matrix of wafers with irregular dimensions, a point-filling operation can be performed to adjust the Q_wafer with dimensions x×y.ij The matrix is ​​expanded into a square matrix of size r × r, where r = 2. k ;2 k-1 ≤x, y≤2 k The expansion points outside the mass matrix of each wafer are defined as a constant a. Define the expanded mass matrix as the wafer mass expansion matrix Q_wafer′. ij , as in formula (14).

[0104]

[0105] Use Hilbert curves to scan the wafer quality extension matrix Q_wafer′ ij The scan path H_Hilbert is obtained, and the Hilbert value for each wafer Q_Hilbert can be obtained based on the scan path. ij Scan sequence, length 2 2k .

[0106] S103, arrange multiple wafer-Hilbert scan sequences in rows to construct a quality sequence matrix for multiple wafers.

[0107] In the embodiments of this application, after obtaining the wafer-Hilbert scan sequence corresponding to a single chip parameter for each wafer, multiple wafer-Hilbert scan sequences can be arranged row-wise to construct a quality sequence matrix for multiple wafers, so as to uniformly analyze the quality information of multiple wafers subsequently. Since the test data of each wafer includes multiple chip parameters, when arranging, the wafer-Hilbert scan sequences corresponding to multiple chip parameters under the same wafer can be arranged as a sub-module, or the wafer-Hilbert scan sequences corresponding to multiple wafers under the same chip parameter can be arranged as a sub-module.

[0108] The first possible implementation is to use wafers as sub-modules, extract wafer-Hilbert scan sequences corresponding to multiple chip parameters under the same wafer, arrange them in rows, and construct a first target quality sequence matrix. The number of rows in the first target quality sequence matrix is ​​the product of the number of wafers and the number of chip parameters. In other words, the characteristic of the first target quality sequence matrix is ​​that it is a quality sequence matrix composed of wafers as sub-modules.

[0109] As an example, in formula (15), a wafer is used as a sub-module, and the wafer-Hilbert Q_Hilbert is a sub-module of n chip parameters of a wafer. ij The scan sequence is arranged in rows, and N wafers can be assembled into an N×n row Hilbert_wafer quality sequence matrix.

[0110]

[0111] The second possible implementation is to use chip parameters as sub-modules, extract wafer-Hilbert scan sequences corresponding to multiple wafers under the same chip parameters, arrange them in rows, and construct a second target quality sequence matrix. The number of rows in the second target quality sequence matrix is ​​the product of the number of chip parameters and the number of wafers. In other words, the characteristic of the second target quality sequence matrix is ​​that it is a quality sequence matrix composed of chip parameters as sub-modules.

[0112] As an example, in formula (16), the chip parameters are used as sub-modules, and the wafer-Hilbert Q of N wafers is used. ij The scan sequence is arranged in rows, and n chip parameters can be assembled into an n×N row Hilbert_para quality sequence matrix.

[0113] In practical applications, there are many methods for arranging multiple wafer-Hilbert scan sequences. The embodiments of this application list the above two row arrangement methods. Those skilled in the art can also perform column arrangement or other arrangements.

[0114] Specifically, the number of multiple wafers can be the number of wafers in the entire batch, and constructing the quality sequence matrix of multiple wafers can be the same as constructing the quality sequence matrix of the entire batch of wafers.

[0115] In practical applications, since the Hilbert_wafer quality sequence matrix or the Hilbert_para quality sequence matrix has multiple extended columns of length N×n, the extended points at these positions can be deleted to generate a wafer quality sequence matrix without extended points. This allows chips with the same number or chips at the same position on different wafers to be placed in the same column, which facilitates the subsequent unified quality analysis of chips at the same position on different wafers. The wafer quality sequence matrix without extended points can be referred to formulas (17) and (18), where L represents the sequence length after deleting extended point a.

[0116]

[0117]

[0118] S104 analyzes test data of multiple chips on multiple wafers based on the quality sequence matrix.

[0119] In the embodiments of this application, after obtaining multiple wafer-Hilbert scan sequences by scanning the quality matrix of multiple wafers using Hilbert curves, and arranging the multiple wafer-Hilbert scan sequences to obtain multiple wafer quality sequence matrices, a unified quality analysis can be performed on the test data of multiple chips on multiple wafers based on the multiple wafer quality sequence matrices.

[0120] Specifically, the quality sequence matrix can be visualized to obtain a visual spectrum corresponding to the quality sequence matrix, and the test data of multiple chips on multiple wafers can be analyzed based on the visual spectrum.

[0121] Visualized spectra can be those that can be displayed intuitively, such as three-dimensional peak images or color quality feature spectra. The following explanation uses color quality feature spectra as an example:

[0122] According to the coloring rules, the quality value corresponding to each test data in the quality sequence matrix is ​​colored to obtain a color quality feature spectrum. The test data of multiple chips on multiple wafers are then analyzed based on the color quality feature spectrum.

[0123] The quality sequence matrix can be colored by defining coloring rules. The coloring rules are referenced in formula (19):

[0124]

[0125] In the color quality feature spectrum obtained by coloring the quality sequence matrix, white is defined as the best quality level and black represents the worst quality level. According to formula (19), the change of color from white, green, ..., red to black in the color quality feature spectrum represents the transition from the best quality level to the fault level. Coloring formulas (17) and (18) generates a color quality feature spectrum. The distribution of chip quality can be observed through visualization. Since the Hilbert scan curve ensures the positional relationship of adjacent chips on the wafer, the quality consistency of adjacent chips can be observed. The visualization results are as follows: Figure 4 and Figure 5 As shown, Figure 4 This diagram shows the wafer quality grade distribution with chip parameters as sub-modules. Figure 5 The diagram shows the wafer quality grade distribution with wafers as sub-modules.

[0126] Figure 4 and Figure 5 This image shows the distribution of chip quality grades across all wafers in a batch. Numbers 1-7 represent a transition from excellent to defective quality, with smaller quality grade values ​​indicating better chip quality. The results show that quality values ​​deviating from grade 1 are effectively clustered. The best quality grade (white) occupies the largest area of ​​the image, while the second-best quality grade (green) is clustered within the image. Notably, other color distributions (quality grades other than white and green) are distributed within the green stripes, indicating that the quality at the clustered green stripes is a key factor affecting overall quality instability. Furthermore, the black line from top to bottom in the image indicates that chips at the same location within this batch of wafers exhibit complete defects.

[0127] In the embodiments of this application, in addition to visually displaying the quality of multiple chips in multiple wafers using color quality feature spectra, quantitative analysis of chip quality can also be performed, providing a basis for quantitative analysis. Figure 4 and Figure 5 The quality distribution of all chip parameters on a batch of wafers is statistically analyzed for different quality levels, as shown in formula (20).

[0128]

[0129] The calculation results of formula (20) are visualized, and the results are referenced. Figure 6 , Figure 6 The number of chip parameters for each quality value from 1 to 7 is shown.

[0130] Therefore, this application's embodiments introduce Hilbert curves from fractal theory into the field of chip data analysis, reducing the dimensionality of the four-dimensional wafer chip test dataset (including the number of wafers, the two-dimensional positions of the chips, and the number of chip parameters) to a two-dimensional quality sequence matrix and visualization spectrum, thus improving the analysis efficiency of wafer-level chip test data. In the process of using Hilbert curves to process the quality matrix formed from chip test data, the coupling characteristics between chip positions in the two-dimensional space of the test dataset are preserved. By scanning the wafer map corresponding to the chip quality matrix with Hilbert curves, all information in the wafer map is compressed into a two-dimensional quality sequence matrix. Subsequent visualization processing can be performed, such as defining coloring rules to color the data in the compressed quality sequence matrix, constructing a color quality feature spectrum for this batch of test data, and intuitively displaying the quality distribution pattern of a batch of wafer-level chips through color changes. The quality sequence matrix and color quality feature spectrum can be analyzed, facilitating the convenient and efficient extraction of the required chip quality information.

[0131] This application provides a chip test data analysis method. The chip is located on a wafer. The method includes: acquiring test data of multiple chips on multiple wafers; dividing the test data into quality partitions to obtain a two-dimensional quality matrix for each wafer; scanning the quality matrix using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence; arranging the multiple wafer-Hilbert scan sequences in rows to construct a quality sequence matrix for multiple wafers; and analyzing the test data of multiple chips on multiple wafers based on the quality sequence matrix. In other words, by scanning the quality matrix corresponding to the wafers containing multiple chips using Hilbert curves, the information in the quality matrix is ​​compressed into a two-dimensional quality sequence matrix, which greatly reduces the difficulty of analyzing chip test data and improves the efficiency of wafer-level chip test data analysis.

[0132] Based on the chip test data analysis method provided in the above embodiments, this application also provides a chip test data analysis device, the working principle of which will be described in detail below with reference to the accompanying drawings.

[0133] See Figure 7 The figure is a schematic diagram of the structure of a chip test data analysis device provided in an embodiment of this application.

[0134] The chip test data analysis device 700 provided in this application embodiment includes:

[0135] The acquisition unit 710 is used to acquire test data of multiple chips on multiple wafers, perform quality partitioning on the test data, and obtain a two-dimensional quality matrix for each wafer.

[0136] The scanning unit 720 is used to scan the quality matrix using the Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence.

[0137] Arrangement unit 730 is used to arrange multiple wafer-Hilbert scan sequences in rows to construct a mass sequence matrix of multiple wafers;

[0138] Analysis unit 740 is used to analyze test data of multiple chips on multiple wafers based on the quality sequence matrix.

[0139] Optionally, the acquisition unit 710 is configured to:

[0140] A test dataset of multiple chips on multiple wafers is obtained. The test dataset includes multiple test data. According to the chip quality classification rules, the test data in the test dataset are divided into quality categories to obtain the quality value corresponding to each test data. A quality matrix for each wafer is formed based on the quality values.

[0141] Optionally, the acquisition unit 710 is configured to:

[0142] By combining the chip location information of each wafer, a mass matrix is ​​formed for each wafer based on the mass value corresponding to each chip on each wafer.

[0143] Optionally, the test data includes various chip parameters;

[0144] The acquisition unit 710 is used for:

[0145] Multiple chip parameters are obtained for each chip among multiple chips on multiple wafers. Each chip parameter among the multiple chip parameters is divided into quality partitions to obtain the quality matrix of each chip parameter in each wafer.

[0146] Optionally, the scanning unit 720 is used for:

[0147] The scanning path of the Hilbert curve is determined based on the size of the quality matrix, and the scanning path carries chip location information for each wafer;

[0148] The quality matrix of each wafer is scanned according to the scan path to obtain a one-dimensional wafer-Hilbert scan sequence for each wafer.

[0149] Optionally, the test data includes various chip parameters;

[0150] The arrangement unit 730 is used for:

[0151] Using a wafer as a sub-module, extract wafer-Hilbert scan sequences corresponding to multiple chip parameters under the same wafer and arrange them in rows to construct a quality sequence matrix for the first target row. The number of rows in the first target row is the product of the number of wafers and the number of chip parameters.

[0152] Optionally, the test data includes various chip parameters;

[0153] The arrangement unit 730 is used for:

[0154] Using chip parameters as a sub-module, the wafer-Hilbert scan sequences corresponding to multiple wafers under the same chip parameters are extracted and arranged in rows to construct a quality sequence matrix for the second target row. The number of rows in the second target row is the product of the number of chip parameters and the number of wafers.

[0155] Optionally, the analysis unit 740 is used for:

[0156] The quality sequence matrix is ​​visualized to obtain a visualization spectrum corresponding to the quality sequence matrix, and the test data of multiple chips on multiple wafers are analyzed based on the visualization spectrum.

[0157] Optionally, the quality sequence matrix includes the quality value corresponding to each test data, and the visualization spectrum includes a color quality feature spectrum;

[0158] The analysis unit 740 is used for:

[0159] According to the coloring rules, the quality value corresponding to each test data in the quality sequence matrix is ​​colored to obtain a color quality feature spectrum. The test data of multiple chips on multiple wafers are analyzed based on the color quality feature spectrum.

[0160] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device embodiments described above are merely illustrative. The units and modules described as separate components may or may not be physically separate. Furthermore, some or all of the units and modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0161] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A chip test data analysis method, characterized in that, The chip is located on a wafer, and the method includes: Test data of multiple chips on multiple wafers are acquired, and the test data is partitioned by quality to obtain a two-dimensional quality matrix for each wafer; The quality matrix is ​​scanned using Hilbert curves to obtain a one-dimensional wafer-Hilbert scan sequence; Multiple wafer-Hilbert scan sequences are arranged in rows to construct multiple wafer quality sequence matrices; chips with the same number or the same position on different wafers are located in the same column in the quality sequence matrix; The test data of multiple chips on the multiple wafers are analyzed based on the quality sequence matrix; The step of scanning the quality matrix using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence includes: The scanning path of the Hilbert curve is determined based on the size of the quality matrix, and the scanning path carries chip location information for each wafer; The quality matrix of each wafer is scanned according to the scan path to obtain a one-dimensional wafer-Hilbert scan sequence for each wafer.

2. The method according to claim 1, characterized in that, The process of acquiring test data from multiple chips on multiple wafers, and partitioning the test data by quality to obtain a two-dimensional quality matrix for each wafer includes: A test dataset of multiple chips on multiple wafers is obtained. The test dataset includes multiple test data. According to the chip quality classification rules, the test data in the test dataset are divided into quality categories to obtain the quality value corresponding to each test data. A quality matrix for each wafer is formed based on the quality values.

3. The method according to claim 2, characterized in that, The process of forming a quality matrix for each wafer based on the quality value includes: By combining the chip location information of each wafer, a mass matrix is ​​formed for each wafer based on the mass value corresponding to each chip on each wafer.

4. The method according to claim 1, characterized in that, The test data includes various chip parameters; The process of acquiring test data from multiple chips on multiple wafers, and partitioning the test data by quality to obtain a two-dimensional quality matrix for each wafer includes: Multiple chip parameters are obtained for each chip among multiple chips on multiple wafers. Each chip parameter among the multiple chip parameters is divided into quality partitions to obtain the quality matrix of each chip parameter in each wafer.

5. The method according to claim 1, characterized in that, The test data includes various chip parameters, and the quality sequence matrix includes a first target quality sequence matrix. The step of arranging the multiple wafer-Hilbert scan sequences in rows to construct a multiple wafer quality sequence matrix includes: Using a wafer as a sub-module, extract wafer-Hilbert scan sequences corresponding to multiple chip parameters under the same wafer and arrange them in rows to construct the first target quality sequence matrix. The number of rows in the first target quality sequence matrix is ​​the product of the number of wafers and the number of chip parameters.

6. The method according to claim 1, characterized in that, The test data includes various chip parameters, and the quality sequence matrix includes a second target quality sequence matrix. The step of arranging the multiple wafer-Hilbert scan sequences in rows to construct a multiple wafer quality sequence matrix includes: Using chip parameters as a sub-module, the wafer-Hilbert scan sequences corresponding to multiple wafers under the same chip parameters are extracted and arranged in rows to construct a second target quality sequence matrix. The number of rows in the second target quality sequence matrix is ​​the product of the number of chip parameters and the number of wafers.

7. The method according to claim 1, characterized in that, The analysis of test data of multiple chips on multiple wafers based on the quality sequence matrix includes: The quality sequence matrix is ​​visualized to obtain a visualization spectrum corresponding to the quality sequence matrix, and the test data of multiple chips on multiple wafers are analyzed based on the visualization spectrum.

8. The method according to claim 7, characterized in that, The quality sequence matrix includes the quality value corresponding to each test data, and the visualization spectrum includes a color quality feature spectrum. The step of visualizing the quality sequence matrix to obtain a visual spectrum corresponding to the quality sequence matrix, and analyzing the test data of multiple chips on multiple wafers based on the visual spectrum, includes: According to the coloring rules, the quality value corresponding to each test data in the quality sequence matrix is ​​colored to obtain a color quality feature spectrum. The test data of multiple chips on multiple wafers are analyzed based on the color quality feature spectrum.

9. A chip test data analysis device, characterized in that, The chip is located on a wafer, and the device includes: The acquisition unit is used to acquire test data of multiple chips on multiple wafers, perform quality partitioning on the test data, and obtain a two-dimensional quality matrix for each wafer. A scanning unit is used to scan the quality matrix using a Hilbert curve to obtain a one-dimensional wafer-Hilbert scan sequence; An arrangement unit is used to arrange multiple wafer-Hilbert scan sequences in rows to construct a quality sequence matrix of multiple wafers; chips with the same number or chips at the same position on different wafers are located in the same column in the quality sequence matrix; An analysis unit is used to analyze test data of multiple chips on multiple wafers based on the quality sequence matrix; The scanning unit is used to determine the scanning path of the Hilbert curve according to the size of the quality matrix, the scanning path carrying chip position information of each wafer; and to scan the quality matrix of each wafer according to the scanning path to obtain a one-dimensional wafer-Hilbert scan sequence for each wafer.

Images